KR20160093411A - Gate Driver - Google Patents

Abstract

The present invention aims to provide a gate driver, comprising: a free charge output unit; and a normal output unit, which improves the rising or falling speed of a scan pulse by using the free charge output unit to increase the rising/falling speed of the scan pulse supplied to a pixel far-distanced from the gate driver and to have a high driving speed. According to the present invention, the gate driver, when the scan pulse rises/falls, drives the free charge output unit to output a higher gate high voltage than before and a low gate low voltage, and when the scan pulse is maintained at a certain level, drives the normal output unit to output the same gate high voltage as before and a low gate low voltage.

Description

Gate driver {Gate Driver}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate driver for a display device, and more particularly, to a gate driver capable of driving at a high speed by increasing the output arrival time of a scan pulse transmitted to pixels far from the gate driver.

BACKGROUND ART [0002] Recently, flat panel displays that are emerging include liquid crystal displays (LCDs), field emission displays, plasma display panels, and organic light emitting diodes Emitting Display). Among them, organic light emitting diode display devices are self-luminous devices that emit organic light emitting layers by recombination of electrons and holes, and are expected to be a next generation display device because they have high luminance, low driving voltage and ultra thin film.

Each of the plurality of unit pixels constituting the organic light emitting diode display device includes an organic light emitting diode composed of an organic light emitting layer between an anode and a cathode, and a pixel circuit for independently driving each organic light emitting diode.

The pixel circuit mainly includes a switching transistor, a capacitor, and a driving transistor. The switching transistor charges the data signal in response to a scan pulse from the gate driver. The driving transistor controls the magnitude of the current supplied to each organic light emitting diode according to the magnitude of the data voltage charged in the capacitor, Adjust the gradation.

The gate driver includes a shift register for sequentially outputting the scan pulse for each channel. The shift register consists of n stages which are connected to each other in dependence. One stage is assigned to each channel.

In each of the stages, an output unit composed of a PMOS transistor and an NMOS transistor having drain electrodes connected to each other is provided. A gate high voltage is connected to a source electrode of the PMOS provided in the output unit, and a gate low voltage is connected to a source electrode of the NMOS provided in the CMOS.

Each of the stages sequentially outputs the gate high voltage to the scan line of the display panel under the control of the shift register and outputs the gate low voltage during the remaining period when the gate high voltage is not output.

As the organic light emitting diode display device becomes larger, the length of a scan line for supplying scan pulses from the gate driver to each pixel becomes longer. Accordingly, the parasitic resistance occurring in the scan line itself is also so large that it can not be ignored. In addition, the influence of the parasitic capacitors formed between the gate electrode and the active layer of each thin film transistor (TFT) on one horizontal line connected to the scan line is also greatly increased. As a result, the rise / fall time of the scan pulse supplied to the pixel located away from the gate driver due to the parasitic resistance and the parasitic capacitor is determined by the rise / fall time of the scan pulse supplied to the pixel located close to the gate driver It increases greatly with time. The rise / fall time of the scan pulse decreases the driving speed of the entire gate driver.

According to an aspect of the present invention, there is provided a gate driver including a precharge output unit and a normal output unit, the gate driver including: And to provide a gate driver having a high driving speed by increasing the rising / falling speed.

In order to achieve the above object, a gate driver according to the present invention includes a normal output unit connected to a shift register, and a precharge output unit for outputting a gate high voltage and a gate low voltage higher than the normal output unit. The precharge output unit may be driven during a rising / falling period in which the scan pulse output voltage rises or falls, so that the output of the scan pulse may rise or fall at a high speed, The normal output unit is provided so that the output of the scan pulse can be maintained.

The gate driver according to the present invention drives the precharge output stage in the rising / falling interval in which the output of the scan pulse rises or falls, so that the rising / falling speed of the scan pulse supplied to the pixel remote from the gate driver is improved , Thereby improving the driving speed of the gate driver.

1 is an exemplary diagram illustrating an output portion of a gate driver according to the present invention.
2 is a waveform diagram showing a gate voltage applied to a pixel closer to the gate driver and a gate voltage applied to a pixel remote from the gate driver when a gate driver having only a conventional normal output portion is used.
FIG. 3 shows a scan pulse applied to a pixel from the gate driver and a scan pulse applied to a pixel distant from the gate driver when a second gate high voltage VGH_Pre and a second gate low voltage VGL_Pre are applied. It is a waveform diagram.
4 (a) is a waveform for driving the normal output unit and the precharge output unit of the gate driver according to the present invention, and FIG. 4 (b) And a scan pulse applied to a pixel far from the gate driver.
5 is an exemplary view for explaining a gate driver according to a second embodiment of the present invention.

Hereinafter, the gate driver according to the present invention will be described in more detail with reference to the drawings.

FIG. 1 is an exemplary view for explaining an output part of a gate driver according to the first embodiment of the present invention. FIG.

The gate driver according to the present invention includes a shift register 2 for sequentially outputting a scan pulse to a scan line connected to a display panel through a plurality of channels, a plurality of normal output sections 3 and a precharge output section 4. The normal output section 3 outputs a first gate high voltage VGH or a first gate low voltage VGL in the sustain period of the scan pulse Wherein the precharge output unit is configured to output a second gate high voltage (VGH_PRE) higher than the first gate high voltage (VGH) or lower than the first gate low voltage (VGL) during a rising or falling period of the scan pulse And outputs the second gate-low voltage VGL_PRE.

The normal output section 2 is connected to a first gate high voltage source VGH through a source electrode thereof and a drain electrode connected to an output terminal 5 of the normal output section 3 and a gate electrode connected to the shift register (PMOS1) and the first gate low voltage source (VGL) connected to the first output pin (P1) of the normal output section (3) and the drain electrode is connected to the output terminal (5 And a first NMOS (NMOS1) having a gate electrode connected to a second output pin P2 of the shift register 2. The first NMOS

 The precharge output section 4 has a source electrode connected to the second gate high voltage source VGL_Pre, a drain electrode connected to the output terminal 6 of the precharge output section 4, A source electrode is connected to the second PMOS (PMOS2) connected to the third output pin (P3) of the register (2) and the second gate low voltage source (VGL_Pre), and a drain electrode is connected to the precharge output And a second NMOS (NMOS2) connected to an output terminal (6) and having a gate electrode connected to a fourth output pin (P4) of the shift register (2).

Principle of Improvement of Driving Speed in the Case of Using Gate Driver Having Normal Output Unit 3 and Precharge Output Unit 4 According to the Present Invention The driving method of the gate driver according to the present invention will be described with reference to the drawings do.

2 is a waveform diagram showing a gate voltage applied to a pixel closer to the gate driver and a gate voltage applied to a pixel remote from the gate driver when a gate driver having only the conventional normal output unit 3 is used. In FIG. 2, it is assumed that the gate high voltage (VGH) output from the conventional gate driver is 10V and the gate low voltage (VGL) is -5V.

The conventional gate driver sequentially outputs scan pulses to the scan lines connected to the respective channels. The normal output section 3 outputs the first gate high voltage VGH in the rising period and the rising period of the scan pulse, and the normal output section 3 in the falling and falling sustain periods of the scan pulse And outputs the first gate low voltage VGL.

In the rising period of the scan pulse, in the pixel near the gate driver, the first gate high voltage (VGH) is outputted from the normal output section (3), and at the same time, Voltage (VGH) value.

Also, during a falling period of the scan pulse, the first gate low voltage (VGL) is outputted from the normal output unit (3) in a pixel near the gate driver, and at the same time, Falls to the low voltage (VGL) value.

On the other hand, the scan pulse applied to the Far pixel from the gate driver generates a delay due to the resistance of the scan line itself and the parasitic capacitor as described above.

That is, in the rising period of the scan pulse, in the Far pixel far from the gate driver, the first gate high voltage (VGH) is outputted from the normal output unit 3, To the first gate high voltage (VGH) value.

Similarly, during the falling period of the scan pulse, the first gate low voltage (VGL) is output from the normal output unit (3) at a Far pixel from the gate driver, Falls to the value of the first gate low voltage (VGL).

A second gate high voltage (VGH_Pre) higher than the first gate high voltage (VGH) to reduce the delay and a second gate low voltage (VGH_Pre) lower than the first gate low voltage VGL_Pre) must be applied.

FIG. 3 is a graph illustrating a relationship between a first gate high voltage VGH_Pre and a second gate low voltage VGL_Pre, which are higher than the first gate high voltage VGH and the first gate low voltage VGL, A gate voltage applied to a pixel nearest to the gate driver, and a gate voltage applied to a pixel far from the gate driver. At this time, it is assumed that the output second gate high voltage VGH_Pre is 20V and the gate low voltage VGL_Pre is -10V.

As shown in FIG. 3, the second gate high voltage (VGH_Pre) and the second gate high voltage (VGH_Pre), as compared with the case of applying the first gate high voltage (VGH) of 10V and the first gate low voltage It can be seen that the rising or falling speed of the scan pulse of the (FAR) pixel farther from the scan line is increased when the voltage VGL_Pre is applied.

That is, when a higher gate high voltage and a lower gate low voltage are applied to the scan line when the scan pulse is outputted, the rising or falling speed of the scan pulse of the pixel remote from the scan line is improved.

However, when a higher second gate high voltage VGH_Pre and a lower second gate low voltage VGL_Pre are applied to the scan lines as described above, an overcurrent flows to the scan transistors connected to the scan lines, There is a fear that the deterioration of the driving transistor or the organic light emitting diode element may be accelerated.

Therefore, the gate driver according to the present invention includes the normal output unit 3 and the precharge output unit 4, and during the rising / falling period of the scan pulse, the second gate high voltage VGH_Pre and the second gate And outputs the first gate high voltage VGH and the first gate low voltage VGL in the sustain period of the scan pulse.

4 (a) is a waveform for driving the normal output section 3 and the precharge output section 4 of the gate driver according to the present invention, and FIG. 4 (b) A scan pulse applied to a pixel nearest to the gate driver and a scan pulse applied to a pixel far from the gate driver. Here, the first gate high voltage is 10V, the first gate low voltage is -5V, the second gate high voltage is 20V, and the second gate low voltage is -10V.

The gate driver according to the present invention outputs a second gate high voltage VGH_Pre higher than the first gate high voltage VGH in the rising period t1 of the scan pulse, ) Outputs a second gate low voltage (VGL_Pre) lower than the first gate low voltage (VGL) to improve the rising and falling speed of the scan pulse of the pixel away from the scan line, and when the scan pulse is in the high state And outputs the first gate high voltage VGH during a period t2 during which the scan pulse is maintained at a low level and outputs the first gate low voltage VGL during a period t4 during which the scan pulse remains at a low level. .

4A, the shift register 2 is connected to the second PMOS of the precharge output unit 4 through the third output pin P3 in order to shift the scan pulse to a high state. A low signal is applied. Accordingly, the precharge output section 4 outputs a second gate high voltage VGH_Pre, which is higher than the first gate high voltage VGH, to the scan line. The second gate high voltage VGH_Pre enables the scan pulse to rise at a high speed.

When the magnitude of the scan pulse applied to the Far pixel from the gate driver is close to the first gate high voltage VGH (after a low signal is applied to the second PMOS and a predetermined time t1 has elapsed , The shift register 2 applies a high signal to the second PMOS and simultaneously applies a low signal to the first PMOS of the normal output unit 3 through the first output pin P1. Accordingly, the normal output unit 3 holds the scan pulse at 10V which is the first gate high voltage VGH.

At this time, the shift register 2 applies a low signal to the first NMOS and the second NMOS through the second and fourth output pins P2 and P4, and the first NMOS and the second NMOS are turned off State.

The shift register 2 then applies a high signal to the second NMOS of the precharge output section 4 through the fourth output pin P4 to transition the scan pulse to a low state. Accordingly, the precharge output section 4 outputs the second gate low voltage VGL_Pre to the scan line. The second gate low voltage (VGL_Pre) allows the scan pulse to fall at a high speed.

A time when a magnitude of a scan pulse applied to a Far pixel from the gate driver approaches the first gate low voltage VGL (after a high signal is applied to a second NMOS and a predetermined time t3 elapses) The shift register 2 applies a low signal to the second NMOS and a high signal to the first NMOS of the normal output unit 3. Accordingly, the normal output unit 3 outputs the first gate low voltage VGL to the scan line to maintain the scan pulse at -5V.

At this time, the shift register 2 applies a high signal to the first PMOS transistor and the second PMOS transistor through the first and third output pins P1 and P3, Off state.

At this time, as shown in FIG. 4A, when driving the gate driver, in order to prevent a collision of different voltages, a period t1 during which the second PMOS is turned on, A period t2 during which the first PMOS is turned on and a period during which the second NMOS is turned on during a period t2 during which the PMOS is turned on and a period during which the second NMOS is turned on during a period t3 during which the second NMOS is turned on, For a very short period of time between a period during which the first NMOS is turned on and a period during which the first NMOS is turned on and a period during which the first NMOS is turned on and a period during which the second PMOS is turned on, , 2 PMOS and NMOS are both turned off to set a short dead time t 'that does not drive both the normal output unit 3 and the precharge output unit 4. The dead time t 'shown in FIG. 4 (a) is shown slightly longer for convenience of explanation.

By driving the gate driver as described above, the rising / falling speed of the scan pulse supplied to the Far pixel from the gate driver is improved as shown in Fig. 4 (b). In addition, a scan pulse supplied to the near pixel from the gate driver is applied to the second gate high voltage VGH_Pre, the first gate high voltage VGH_Pre, the second gate low voltage VGL_Pre, VGL), and has a step-like waveform. However, since the time for outputting the second gate high voltage VGH_Pre and the second gate low voltage VGL_Pre is considerably shorter than the total driving time (1.1-1.5 s ) The effect on the near pixel from the gate driver is limited.

The precharge output unit 4 may have 2 to 4 precharge output units. If the number of the precharge output units is increased, the gate high voltage or the gate low voltage may be output at various levels. have.

5 is an exemplary view for explaining a gate driver according to a second embodiment of the present invention.

The gate driver according to the second embodiment of the present invention includes two or more shift registers 11 and 12 for controlling the plurality of output units 13 and 14. [ FIG. 5 shows a gate driver provided with two shift registers 11 and 12 for convenience of explanation.

The first output unit 13 is connected to each channel of the first shift register 11.

The first output section 13 is connected to a first gate high voltage source VGH through a source electrode thereof and a drain electrode connected to an output terminal 15 of the first output section 13, A source electrode is connected to the first PMOS transistor PMOS1 connected to the first output plate P1a of the first shift register 12 and the first gate low voltage source VGL and a drain electrode is connected to the first output unit 13 And a first NMOS transistor NMOS1 having a gate electrode connected to a second output pin P2a of the first shift register 11,

The second output unit 14 is connected to each channel of the second shift register 12.

 The second output section 14 is connected to the second gate high voltage source VGL_Pre with a source electrode connected to the second output section 14 and a drain electrode connected to the output terminal 16 of the second output section 14, A source electrode is connected to the second PMOS (PMOS2) connected to the first output pin (P1b) of the shift register 12 and the second gate low voltage source (VGL_Pre), and a drain electrode is connected to the second output unit And a second NMOS transistor NMOS2 having a gate electrode connected to a second output pin P2b of the second shift register 12. The second NMOS transistor NMOS2 has a gate electrode connected to the second output pin P2b of the second shift register 12,

The gate driver driving method according to the second embodiment of the present invention is almost the same as the gate driver driving method according to the first embodiment of the present invention.

That is, the gate driver according to the second embodiment of the present invention is driven in the same manner as described in FIG. 4, and the first shift register 11 is connected to the first PMOS The second shift register 12 outputs a high signal or a low signal to the second PMOS transistor PMOS1 and the second PMOS transistor PMOS2 while the second shift register 12 outputs the second PMOS transistor PMOS2 and the second NMOS transistor NMOS2, And outputs a high signal or a low signal. In this case, the first output unit 13 of the present invention can be driven in the same manner as the normal output unit 3 of the first embodiment, and the second output unit 14 can be driven in the same manner as the normal output unit 3 of the first embodiment, (4).

When the shift registers 11 and 12 are provided as described above, even if the number of the output units 13 and 14 increases, the shift registers 11 and 12 are connected to the output units 13 and 14, The malfunction of the shift registers 11 and 12 can be reduced and the collision of signals can be reduced. However, when the number of the shift registers 11 and 12 increases, malfunctions or signal collisions of the shift registers 11 and 12 themselves may be frequent, so that the number of shift registers 11 and 12 is not more than four desirable.

Table 1 below shows the rise / fall time of a scan pulse of a pixel distant from the gate driver when a conventional gate driver is driven and a rise / fall time of a scan pulse of pixels far from the gate driver when the gate driver according to the first embodiment of the present invention is driven. And the rise / fall time of the scan pulse of FIG.

Based on Far pixel VGH = 10V, VGL = -5V VGH = 20V, VGL = -10V Invention Rise time 4.05 s 0.98 s 1.11 μs Fall Time 4.08 s 1.58 s 1.59 s

According to Table 1, when the conventional gate driver is driven and a gate high voltage of 10V and a gate low voltage of -5V are outputted, the rising time of the scan pulse is 4.05 μs and the falling time is 4.08 μs.

Also, when a conventional gate driver is driven to output a gate high voltage of 20V and a gate low voltage of -10V, the rise time of the scan pulse is 0.98 mu s and the fall time is 1.58 mu s.

When the first and second gate high voltages VGH and VGH_Pre and the first and second gate low voltages VGL and VGL_Pre are outputted by driving the gate driver according to the present invention, the rise time of the scan pulse is 1.11 ㎲, The falling time is 1.59 ㎲.

That is, as shown in Table 1, the gate driver according to the present invention can shorten the rise / fall time of a scan pulse of a pixel distant from the gate driver to 1/3 to 1/4 have.

Although the rising / falling time of the scan pulse is slightly increased as compared with the case where the gate high voltage of 20V and the gate low voltage of -10V are outputted by driving the conventional gate driver, the conventional gate driver having the wide voltage swing range It is possible to prevent deterioration of the pixel and to shorten the rise / fall time of the scan pulse.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention.

2: shift register 3: normal output section
4: Pre-charge output section 5: Normal output section Output section
6: Pre-charge output section Output stage 11: First shift register
12: second shift register 13: first output terminal
14: 2nd output stage

Claims (5)

A shift register for sequentially outputting scan pulses to a plurality of scan lines connected to the display panel through a plurality of channels,
And a plurality of output sections connected to at least two or more respective channels of the shift register,
Wherein each of the output units comprises:
A normal output section for outputting a first gate high voltage or a first gate low voltage in the sustain period of the scan pulse,
At least one pre-charge output for outputting a second gate high voltage higher than the first gate high voltage or a second gate low voltage lower than the first gate low voltage in the rising / falling period before and after the sustain period of the scan pulse, Wherein the gate driver comprises: The method according to claim 1,
Wherein the normal output unit comprises:
A first PMOS having a source electrode connected to a first gate high voltage source, a drain electrode connected to an output terminal of the normal output unit, a first PMOS having a gate electrode connected to a first output pin of the shift register, And a first NMOS transistor having a drain electrode connected to an output terminal of the normal output section and a gate electrode connected to a second output pin of the shift register,
The pre-
A source electrode is connected to the second PMOS having the gate electrode connected to the shift register and the second gate low voltage source connected to the source electrode of the second gate high voltage source, the drain electrode is connected to the output terminal of the precharge output portion, And a second NMOS having a drain electrode connected to the output terminal of the precharge output portion and a gate electrode connected to the shift register. The method according to claim 1,
And a dead time in which neither the normal output section nor the precharge output section is driven between the rising period and the sustain period of the scan pulse or between the sustain period and the falling period of the scan pulse. At least a first shift register and a second shift register for sequentially outputting scan pulses to a plurality of scan lines connected to the display panel through a plurality of channels,
A plurality of first outputs connected to the respective first channels of the first shift register,
And a plurality of second outputs connected to the respective channels of the second shift register,
Wherein the plurality of first output units and the plurality of second output units output different gate high voltages and gate low voltages to the scan lines under the control of first and second shift registers, driver. The method of claim 4,
Wherein each of the first output units comprises:
A first PMOS having a source electrode connected to a first gate high voltage source, a drain electrode connected to an output terminal of the normal output unit, a first PMOS having a gate electrode connected to a first output pin of the shift register, And a first NMOS transistor having a drain electrode connected to an output terminal of the normal output section and a gate electrode connected to a second output pin of the shift register,
Wherein each of the second output units comprises:
A source electrode is connected to the second PMOS having the gate electrode connected to the shift register and the second gate low voltage source connected to the source electrode of the second gate high voltage source, the drain electrode is connected to the output terminal of the precharge output portion, And a second NMOS having a drain electrode connected to the output terminal of the precharge output portion and a gate electrode connected to the shift register.

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