KR20160092183A - Organic electro luminescent device - Google Patents

Abstract

The present invention relates to an organic electroluminescent device having a structure which is repairable when a short is generated in a pixel area, and minimizing an overlapping part between components to improve an aperture ratio. The organic electroluminescent device comprises a substrate, a first data wiring, a second data wiring, a third data wiring, a fourth data wiring, a power wiring, a first auxiliary wiring, a gate wiring, switching thin transistors, driving thin transistors, sense thin transistors and an organic electroluminescent diode. The substrate has one pixel area formed by four subpixel areas in such a manner that the four subpixel areas are arranged in two rows and two columns in the pixel area. The first data wiring, the second data wiring, the third data wiring, and the fourth data wiring are positioned on the left side and the right side of each of the subpixel areas of a first column and a second column on the substrate to be extended in a first direction. The power wiring is arranged adjacent to the first data wiring and the fourth data wiring in a line. The first auxiliary wiring is arranged between the second data wiring and the third data wiring. The gate wiring is arranged in a second direction intersecting with the first direction and has a first hole and a second hole allowing the gate wiring to be branched from a part intersecting with the first data wiring, the second data wiring, the third data wiring, the fourth data wiring, the power wiring and the first auxiliary wiring to make double overlapping. The switching thin transistors are included in each subpixel area and are connected to one of the gate wiring, the first data wiring, the second data wiring, the third data wiring and the fourth data wiring. The driving thin transistors are included in the each subpixel area and are connected to the switching thin transistor. The sense thin transistors are included in each subpixel area and are arranged adjacent to the first hole while having the gate wiring part capturing the first hole as a gate electrode. The organic electroluminescent diode is connected to the driving thin transistors.

Description

[0001] The present invention relates to an organic electroluminescent device,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an organic electro luminescent device, and more particularly, to an organic electro luminescent device capable of repairing a short circuit in a pixel region, minimizing the overlapping portion between components, And an organic electroluminescent device.

An organic electroluminescent device, which is one of flat panel displays (FPDs), has high luminance and low operating voltage characteristics.

In addition, since it is a self-luminous type that emits light by itself, it has a large contrast ratio, can realize an ultra-thin display, has a response time of several microseconds (μs), is easy to implement a moving image, Since it is stable and driven by a low voltage of 5V to 15V, it is easy to manufacture and design a driving circuit.

Therefore, the organic electroluminescent device having the advantages as described above has recently been used in various IT devices such as a TV, a monitor, and a mobile phone.

The basic structure and operational characteristics of such an organic electroluminescent device will be described in detail with reference to the drawings.

1 is a circuit diagram for one sub-pixel region of a basic organic electroluminescent device having one switching thin film transistor and one driving thin film transistor.

As shown in the figure, in the organic EL device ELD1 including one switching thin film transistor STr and one driving thin film transistor DTr, the switching thin film transistor STr and the driving thin film transistor STr are formed in one sub- A thin film transistor DTr, a storage capacitor StgC, and an organic light emitting diode E are formed.

That is, a gate line GL is formed in a first direction, and a data line DL is formed in a second direction intersecting the first direction. The data line DL is spaced apart from the data line DL, The power supply line PL for applying the power supply line PL is formed.

A switching thin film transistor STr is formed at the intersection of the data line DL and the gate line GL and a driving thin film transistor DTr electrically connected to the switching thin film transistor STr is formed have.

The first electrode, which is one terminal of the organic electroluminescent diode E, is connected to the drain electrode of the driving thin film transistor DTr, the second electrode of the other electrode is grounded, The electrode is connected to the power supply line PL so that the power supply line PL transfers the power supply voltage VDD to the organic light emitting diode E.

A storage capacitor StgC is formed between the gate electrode and the source electrode of the driving thin film transistor DTr.

Therefore, when a signal is applied through the gate line GL, the switching thin film transistor STr is turned on and the signal of the data line DL is transmitted to the gate electrode of the driving thin film transistor DTr, The transistor DTr is turned on so that light is output through the organic electroluminescent diode E.

At this time, when the driving thin film transistor DTr is turned on, a level of a current flowing from the power supply line PL to the organic light emitting diode E is determined. Accordingly, the organic light emitting diode E The storage capacitor StgC is capable of maintaining a constant gate voltage of the driving thin film transistor DTr when the switching thin film transistor STr is turned off The level of the current flowing through the organic light emitting diode E can be kept constant until the next frame even if the switching thin film transistor STr is turned off.

The organic electroluminescent device ELD1 having such a configuration is the most basic and shows that one switching thin film transistor STr and one driving thin film transistor DTr are provided in each sub pixel area SP.

However, in the organic electroluminescent device, in order to stably drive the driving thin film transistor DTr or reliably and reliably realize the luminance characteristic in consideration of the position of the sub pixel area SP in the display area, a plurality of auxiliary thin film transistors A plurality of auxiliary thin film transistors (not shown) and a plurality of auxiliary thin film transistors (not shown) and a plurality of switching thin film transistors STr or power supply lines PL ) Can be variously modified.

That is, in addition to the switching thin film transistor STr and the driving thin film transistor DTr, the array element may further include an auxiliary thin film transistor (not shown) for selectively improving image quality and driving stability.

On the other hand, the organic electroluminescent device has three sub pixel areas for emitting red, green, and blue colors that can be implemented in all colors by mixing colors in order to realize full color in one pixel area, Pixel regions form one pixel region.

FIG. 2 is a plan view of one pixel region of an organic electroluminescent device including four conventional sub-pixel regions as one pixel region. Here, for convenience, the switching, driving, and sense thin film transistors, which are components formed identically in each sub pixel region, are denoted by reference numerals only for one sub pixel region.

As shown in the figure, the conventional organic electroluminescent device 1 has four pixel regions SP1, SP2, SP3 and SP4 which are continuous in one direction (left and right direction) Within each pixel region P, the sub-pixel regions SP are arranged in a column spaced apart by a predetermined distance.

In the pixel region P, first and second data lines DL1, DL2 are formed in a pair and are spaced apart from each other at the boundaries of the first and second sub-pixel regions SP1, SP2. And third and fourth data lines DL3 and DL4 which are spaced apart from each other and arranged in a boundary between the third and fourth sub-pixel regions SP3 and SP4 are disposed. For convenience of description, the first, second, third, and fourth data lines DL1, DL2, DL3, and DL4 provided in the pixel region P are connected to the data lines DL (DL1, DL2, DL3, DL4) .

A power supply line PL for applying a power source voltage V _DD extends in the first direction on the left and right sides of each pixel region P and more precisely on the boundary between adjacent pixel regions P In each pixel region P, a Vref wiring Vref for applying a common voltage is arranged at the boundary between the second and third sub-pixel regions SP2 and SP4.

The data lines DL1, DL2, DL3, DL4) and the power supply line PL and the Vref line Vref intersect the upper and lower boundaries of each pixel region P, A long line is arranged in the second direction in each pixel region P in each pixel region P away from the gate line GL and the Vref line Vref and the And a second auxiliary pattern AP2 connected to the first auxiliary pattern AP1 and the power supply line PL connected thereto.

Although the second auxiliary pattern AP2 is shown as being formed in each pixel region P, the second auxiliary pattern AP2 may be formed through two neighboring pixel regions P, Half of the length is formed in the left pixel region P and the other half is formed in the right pixel region P so that one pixel region P is formed substantially corresponding to one pixel region P. [

Each of the sub-pixel regions SP includes a switching thin film transistor STr connected to the gate line GL and the data lines DL1, DL2, DL3 and DL4, a power line PL and an organic light emitting diode And a sense thin film transistor SeTr connected to the Vref wiring Vref, the gate wiring GL and the driving thin film transistor DTr.

At this time, the gate line GL intersects the intersecting lines PL, DL2, DL3, and DL4 and the Vref line Vref, The first auxiliary pattern AP1 connected to the Vref wiring Vref is also provided with a hole h1 corresponding to the gate line GL and the first auxiliary pattern AP1 connected to the Vref line Vref. Holes h1 are provided at portions overlapping the data lines DL1, DL2, DL3, and D14, overlapping the data lines DL1, DL2, DL3, and D14.

That is, the gate line GL and the first auxiliary pattern AP1 overlap the data lines DL1, DL2, DL3, and D4 extending in the first direction, the Vref line Vref, and the power line PL (PL, DL1, DL2, DL3, DL4) extending in the first direction and forming a double wiring structure by branching before overlapping with the wires (PL, DL1, DL2, DL3, DL4, Vref) DL3, DL4, and Vref), the double wiring is formed again to form a single wiring structure. At this time, the holes h1 provided in the gate line GL and the first auxiliary pattern AP1 are formed for the respective wirings PL, DL1, DL2, DL3, DL4, and Vref extending in the first direction (DL1, DL2, DL3, DL4) arranged in the first direction are arranged adjacent to each other when the wirings (PL, DL1, DL2, DL3, DL4, Vref) One hole hl is formed for each group.

The first auxiliary pattern AP1 and the second auxiliary pattern AP1 are formed so as to overlap and overlap each other in correspondence to the wirings PL, DL1, DL2, DL3, DL4, and Vref extending in the first direction overlapping the gate wiring GL and the first auxiliary pattern AP1 If the insulation is broken due to a process problem in the overlapped portion and a short failure occurs, even if the shorted portion is cut, the current flows through the other overlapping portion, thereby eliminating short defects So that the repair process can be carried out.

However, in the conventional organic electroluminescent device 1 having the above-described configuration, the four sub-pixel regions SP1, SP2, SP3, and SP4 are arranged in one row on the same line in each pixel region P, P, there are three boundary regions between the four sub-pixel regions SP1, SP2, SP3, and SP4 within the pixel region P in order to achieve a repair process for repairing the short- DL1, DL2, DL3, DL4, and Vref extending in the first direction in which the respective components overlap each other, the gate wiring GL extending in the second direction, and the first and second auxiliary patterns AP1, AP2), the aperture ratio is lowered.

SUMMARY OF THE INVENTION The present invention has been conceived to solve the problems described above, and it is an object of the present invention to provide an organic light emitting display device capable of minimizing a spacing region between pixel regions in a pixel region and minimizing overlapping portions, And an object of the present invention is to provide an electroluminescent element.

According to an aspect of the present invention, there is provided an organic electroluminescent device including four sub-pixel regions constituting one pixel region, wherein the four sub-pixel regions are arranged in two rows and two columns in the pixel region First, second, third and fourth data lines provided on left and right sides of first and second column pixel regions on the substrate, respectively, and extending in a first direction; A first auxiliary wiring arranged between the second and third data wirings; and a second auxiliary wiring arranged in a second direction intersecting the first direction, wherein the first, second, third, A gate wiring provided in the sub-pixel region and having a first and a second hole for branching and doubling in a portion intersecting the fourth data wiring, the power wiring, and the first auxiliary wiring; , 2, 3, or 4 data lines And a gate thin film transistor provided in each of the sub pixel regions and capturing the first hole as a gate electrode, the thin film transistor having a gate electrode, A sense thin film transistor disposed around the first hole, and an organic light emitting diode connected to the driving thin film transistor.

At this time, a first auxiliary pattern provided in the second hole and in contact with the first auxiliary wiring is provided. In the first auxiliary pattern, holes corresponding to the portions overlapping the second and third data lines And the second data line and the third data line are overlapped with each other.

The second hole is provided corresponding to the first and fourth data wirings arranged adjacent to the power supply wiring.

The two pixel regions adjacent to each other in the left and right directions are in contact with the power supply wiring, overlapping the first and fourth data wirings located on both sides thereof, and being in contact with the source electrode of the driving thin film transistor 2 auxiliary pattern may be provided. In this case, the gate wiring, the first auxiliary pattern and the second auxiliary pattern are formed in the same layer.

The first and second sub-pixel regions are located on the upper side in the pixel region, the third and fourth sub-pixel regions are located on the lower side in the pixel region, and the third and fourth sub- Each of the switching thin film transistors is characterized in that a portion of the gate wiring that branches off from the portion capturing the first hole is a gate electrode of the switching thin film transistor.

The organic electroluminescent device according to the embodiment of the present invention includes a structure in which four sub-pixel regions are arranged in two rows and two columns in each pixel region, a structure having a first hole and a second hole in a gate wiring, A structure in which a first auxiliary pattern connected to a Vref wiring is inserted in a hole and a structure in which a sense thin film transistor is concentrated around a central portion of each pixel region around the second hole, So that repairing can be performed when a short circuit occurs, thereby preventing the short-circuit failure.

Further, in the organic electroluminescent device according to the embodiment of the present invention, overlapping portions between the first and second auxiliary patterns and the data lines intersecting with each other in the pixel regions and overlapping portions between the second auxiliary patterns and the data lines are minimized This has the effect of further suppressing the occurrence of short defects in the portions overlapping each other and further improving the aperture ratio of the pixel region by reducing the overlap region.

1 is a circuit diagram of one basic pixel region of a basic organic light emitting device having one switching thin film transistor and one driving thin film transistor.
BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an organic electroluminescent device, and more particularly,
FIG. 3 is a plan view of one pixel region of an organic electroluminescent device according to an embodiment of the present invention, in which four sub-pixel regions emitting red, blue, white, and green are used as one pixel region, In which one switching thin film transistor, one driving thin film transistor, and one auxiliary thin film transistor are provided.
4 is a circuit diagram of one sub-pixel region of an organic electroluminescent device according to an embodiment of the present invention.
FIG. 5 is a view showing an overlapped region between wirings crossing each other within a pixel region in the organic electroluminescent device according to the embodiment of the present invention, and an overlapping region between the first auxiliary pattern and the data wirings; FIG.
Fig. 6 is a diagram showing an overlapped region between wirings crossing each other within a pixel region and an overlap region between the first auxiliary pattern and the data wirings in a conventional organic electroluminescent device as a comparative example; Fig.
7 is a cross-sectional view of a portion where a second auxiliary pattern and a driving TFT are formed in one sub-pixel region in the organic electroluminescent device according to an embodiment of the present invention, and FIG. 3 is a sectional view taken along a line VII- Sectional view of a portion.
FIG. 8 is a cross-sectional view of a portion where a switching thin film transistor is formed in one sub-pixel region in an organic electroluminescent device according to an embodiment of the present invention, and FIG.
FIG. 9 is a cross-sectional view of a portion where a first auxiliary pattern and a sense thin film transistor are formed in one sub-pixel region in the organic electroluminescent device according to an embodiment of the present invention, and FIG. 3 is a cross- Sectional view of a portion.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the drawings.

FIG. 3 is a plan view of one pixel region of an organic electroluminescent device according to an embodiment of the present invention, in which four sub-pixel regions emitting red, blue, white, and green are used as one pixel region, FIG. 4 is a diagram illustrating a single thin film transistor as one switching thin film transistor, one driving thin film transistor and an auxiliary thin film transistor, and FIG. 4 is a cross- Lt; / RTI >

Here, for convenience of description, the sub-pixel regions located on the upper side in each pixel region P are referred to as first and second sub-pixel regions SP1 and SP2, the sub-pixel regions located on the lower side are referred to as third and Pixel regions SP3 and SP4 and the first and third sub-pixel regions SP1 and SP3 are positioned on the left side in the pixel region P and the second and fourth sub-pixel regions SP2 and SP4 ) Were defined as located on the right side. The first, second, third, and fourth sub-pixel regions SP1, SP2, SP3, and SP4 emit red, blue, white, and green, respectively. The arrangement of light emission of red, blue, white, and green for the pixel regions SP1, SP2, SP3, and SP4 can be variously changed.

As shown in the drawing, the organic electroluminescent device 101 according to the embodiment of the present invention is one of the most distinctive features, and each pixel region P includes four sub-pixel regions (red, green, blue and white) SP1, SP2, SP3 and SP4 are arranged vertically and horizontally so that the sub-pixel areas SP1, SP2, SP3 and SP4 form a two-row, two-column arrangement structure in the pixel area P.

The spacing between the sub-pixel regions SP1, SP2, SP3, and SP4 in the pixel region is determined by the layout structure of the sub-pixel regions SP1, SP2, SP3, (SP1, SP2, SP3, SP4 in FIG. 2) of the pixel regions P are reduced compared to the arrangement in which one row is arranged, the aperture ratio of each pixel region P itself is improved.

That is, in the case of the conventional organic electroluminescent device (1 in FIG. 2) having a configuration in which four sub-pixel regions (SP1, SP2, SP3, SP4 in FIG. 2) are arranged in the pixel region P, And a spacing region (boundary region) between the pixel regions is required.

On the other hand, in the organic EL device 101 according to the embodiment of the present invention, one spacing region between the sub-pixel regions SP1 and SP2 located on the upper side and the sub-pixel regions Sp3 and SP4 located on the lower side, Only one of the two spacing regions is required between the sub-pixel regions SP1 and SP3 located on the left and the sub-pixel regions SP2 and SP4 located on the right.

Therefore, the spacing between one sub-pixel region is reduced compared to the conventional organic electroluminescent device (1 of FIG. 2), so that the aperture ratio of the pixel region P is primarily improved.

The organic light emitting device 101 according to the embodiment of the present invention is characterized in that the first auxiliary pattern AP1 connected to the Vref wiring Vref is extended by an arrangement characteristic of the elements in each pixel region P The distance is minimized compared to the conventional organic electroluminescent device (1 in FIG. 2), which further enhances the aperture ratio of the pixel region P. [

In the conventional organic electroluminescent device (1 in Fig. 2), the first auxiliary pattern (AP1 in Fig. 2) in each pixel region (P in Fig. 2) (SP2, SP2 in FIG. 2) on the left side and to the third and fourth sub-pixel regions (SP3, SP4 in FIG. 2) on the right side. Therefore, the first auxiliary pattern (AP1 in FIG. 2) is extended in the second direction so as to be arranged for the first, second, third, and fourth sub pixel regions (SP1, SP2, SP3, SP4 in FIG. 2) As shown in FIG.

However, in the organic electroluminescent device 101 according to the embodiment of the present invention, the first, second, third, and fourth portions are adjacent to each other in the upper left, upper right, lower left, The widths of one sub-pixel region SP1, SP2, SP3, and SP4 at the upper and lower boundaries of each of the sub-pixel regions SP1, SP2, SP3, Only the predetermined length shorter than the first auxiliary pattern AP1 is formed so as to extend to thereby enhance the aperture ratio of the pixel region P by minimizing the occupied area in the pixel region P of the first auxiliary pattern AP1.

In addition, the first auxiliary pattern AP1 may have the second and third data lines DL2 and DL3 among the wirings extending in the first direction, The overlapping portions are minimized, and the effect of suppressing the short defects and the aperture ratio of the pixel region is further improved.

The organic electroluminescent device 101 according to the embodiment of the present invention includes a structure in which sense thin film transistors SeTr1, SeTr2, SeTr3, and SeTr4, which are auxiliary thin film transistors, are concentratedly disposed at the center of each pixel region P (SeTr1, SeTr2, SeTr3, and SeTr4) in the pixel region is suppressed from being unnecessarily extended, thereby contributing to the improvement of the aperture ratio and minimizing the overlapping portion with other components Implementing the effect is another feature.

The arrangement and structural characteristics of each element in one pixel region P of the organic electroluminescent element 101 according to the embodiment of the present invention having such a structure will be described in more detail.

First, the organic electroluminescent device 101 according to the embodiment of the present invention is provided with a power supply line PL for applying a V _DD voltage in a first direction extending in a longitudinal direction at the boundary of each pixel region. The data lines DL1 and DL4 are further provided so as to be adjacent to the power source line PL and to the sub-pixel regions SP1 and SP2 and the power source line PL.

At this time, the data line DL provided adjacent to the power supply line PL becomes the first data line DL1 adjacent to the first and third sub-pixel regions SP1 and SP3, And the fourth data line DL4 is adjacent to the sub-pixel regions SP2 and SP4.

The center of the boundary between the first and third sub-pixel regions SP1 and SP3 located on the left side of the pixel region P and the second and fourth sub-pixel regions SP2 and SP4 located on the right side, A Vref line Vref for applying a reference voltage Vref voltage extends in the first direction and further includes first and third sub-pixel regions SP1 and SP3 located on the left side and a Vref line Vref for applying a voltage Adjacent to the first and third sub-pixel regions SP1 and SP3, respectively, on the left and right sides of the Vref line Vref at the boundary between the first sub-pixel region SP2 and the fourth sub-pixel region SP2, And a third data line DL3 is provided adjacent to the second and fourth sub-pixel regions SP2 and SP4.

For convenience, the first, second, third, and fourth data lines DL1, DL2, DL3, and DL4 are collectively referred to as a data line DL.

Next, between the first and second sub-pixel regions SP1 and SP2 located at the upper center of the pixel region P and the third and fourth sub-pixel regions SP3 and SP4 located at the lower side, The data lines DL1, DL2, DL3, and DL4 and the gate lines GL extending in the second direction intersect the Vref lines Vref.

At this time, each of the gate lines GL is connected to the power supply line PL disposed adjacent to the boundary of the pixel region P, the first data line DL1 and the fourth data line DL4 located on both sides thereof, A first hole hl1 is provided correspondingly and a central portion of each pixel region P has a larger area than the first hole hl1 to capture the first auxiliary pattern AP1 And the second hole hl2 is provided.

The reason why the first hole hl1 and the second hole hl2 are formed in the gate wiring GL in this way is that the gate wiring GL is divided into two wirings in one wiring, So that repair can be performed even if a short defect occurs.

At this time, in the gate line GL, the portion where the first and second holes hl1 and hl2 are provided has a greater width than the other regions, and the first and second holes hl1 and hl2 and hl2 are provided so that they are branched into two wirings at portions where the first and second holes hl1 and hl2 are provided.

For convenience of explanation, the gate wiring portions located on the upper and lower sides of the first hole hl1 in the gate wiring GL are divided with reference to the first hole hl1 as the first and second partial wiring (GLA1, GLA2). The gate wiring portions located on the upper and lower sides of the second hole (hl2) branch off with respect to the second hole (hl2) as the third and fourth partial wirings (GLA3, GLA4).

The third partial wiring line GLA3 of the gate line GL itself is connected to the sense thin film transistor SeTr1 of the first sub-pixel region SP1 adjacent to the first sub- And the portion adjacent to the second sub-pixel region SP2 serves as the gate electrode 115c of the sense thin film transistor SeTr2 of the second sub-pixel region SP2.

The fourth partial wiring GLA4 of the gate wiring GL itself has a portion adjacent to the third sub-pixel region SP3 as the sense thin film transistor SeTr3 of the third sub- And a portion adjacent to the fourth sub-pixel region SP4 serves as a gate electrode 115c of the sense thin film transistor SeTr4 of the fourth sub-pixel region SP4 .

On the other hand, in the portion of the gate wiring line GL which is adjacent to the first sub pixel region SP1, the first sub pixel region SP is divided into the first sub pixel region SP1, Pixel region SP2 by branching to the second sub-pixel region SP2 at a portion adjacent to the second sub-pixel region SP2. The second sub-pixel region SP2 is connected to the gate electrode 115a of the switching thin- The gate electrode 115a of the switching thin film transistor STr2.

In the fourth partial wiring GLA4, fifth and sixth partial wirings are provided in the third and fourth sub-pixel regions SP3 and SP4, respectively. The fifth and sixth partial wirings The partial wirings constitute the gate electrodes 115a of the switching thin film transistors STr3 and STr4 provided in the third and fourth sub-pixel regions SP3 and SP4, respectively.

In each of the sense thin film transistors SeTr1, SeTr2, SeTr3 and SeTr4 provided in the first, second, third and fourth sub-pixel regions SP1, SP2, SP3 and SP4, And each sense source electrode 133a which is in contact with the end of the first auxiliary pattern AP1 electrically connected to the Vref wiring Vref through a contact hole ch1, And a sense drain electrode 136c connected to each drain electrode 136b of each of the driving thin film transistors DTr1, DTr2, DTr3 and DTr4.

The first auxiliary pattern AP1 is electrically connected to the Vref wiring Vref through a contact hole chl and the second and first auxiliary patterns AP1 and Vref are electrically connected to each other on both sides of the Vref wiring Vref. The third hole hl3 and the fourth hole hl4 are provided corresponding to the three data lines DL2 and DL3 so as to overlap with the second and third data lines DL2 and DL3 at two places As a result, it is possible to repair a short defect.

As described above, both ends of the first auxiliary pattern AP1 are connected to the sub-pixel regions SP1, SP2, SP3, and SP4, respectively, And the sense-source electrode 133c of the sense thin film transistors SeTr1, SeTr2, SeTr3, and SeTr4 provided in the semiconductor substrate 100 through the contact hole chl.

The switching thin film transistors STr1, STr2, STr3 and STr4 provided in the respective sub-pixel regions SP1, SP2, SP3 and SP4 are branched at the single wiring portion of the above-mentioned gate wiring GL, The switching gate electrode 115a is formed by branching from the wiring GLA4 and is branched into the first, second, third and fourth data lines DL1, DL2, DL3 and DL4, And a plurality of switching drain electrodes 136a spaced apart from the respective switching source electrodes 133a.

In addition to the switching thin film transistors STr1, STr2, STr3 and STr4 and the sensing thin film transistors SeTr1, SeTr2, SeTr3 and SeTr4 described above, the driving thin film transistors DTr1, DTr2, DTr3, and DTr4).

Each of the driving thin film transistors DTr1, DTr2, DTr3 and DTr4 is electrically connected to the driving source electrode 133b electrically connected to the switching thin film transistor STr1, A drive gate electrode 115b connected to the switching drain electrode 136a of the organic light emitting diodes STr1, STr2, STr3 and STr4, a first electrode 160 of the organic light emitting diode, and sense thin film transistors SeTr1, SeTr2, SeTr3 and SeTr4 And a driving drain electrode 136b connected to the drain electrode 136c.

At this time, the switching drain electrode 136a of each of the switching thin film transistors STr1, STr2, STr3 and STr4 provided in each of the sub-pixel regions SP1, SP2, SP3 and SP4 and each of the driving thin film transistors DTr1, DTr2, And the driving drain electrode 136b of the driving transistor DTr4 are overlapped with each other with an insulating layer, that is, a gate insulating layer (not shown) and an interlayer insulating layer (not shown) interposed therebetween, to form a storage capacitor StgC.

The first electrode 160 connected to the driving drain electrodes 136b of the driving TFTs DTr1, DTr2, DTr3, and DTr4 is connected to each of the sub-pixel regions SP1, SP2, SP3, and SP4, And an organic light emitting diode (not shown) including an organic light emitting layer (not shown) and a second electrode (not shown) disposed on the entire surface of the display region.

In the organic electroluminescent device 101 according to the embodiment of the present invention including such a configuration, the first, second, third, and fourth sub-pixel regions SP1, SP2, SP3, And a structure in which a first hole hl1 and a second hole hl2 of the gate wiring GL are formed and a structure in which a second hole hl2 is formed in the second hole hl2, 1 auxiliary patterns AP1 are inserted and sense thin film transistors SeTr1, SeTr2, SeTr3 and SeTr4 are arranged in the central portion of each pixel region P around the second hole hl2, It is possible to improve the aperture ratio of the pads P and to repair the short circuit between the interconnections crossing each other and between the first and second auxiliary patterns and the interconnections intersecting with each other.

In the case of the conventional organic electroluminescent device (P in Fig. 2) provided with the pixel region (P in Fig. 2) in which four sub-pixel regions (SP1, SP2, SP3, SP4 in Fig. 2) The ratio of the spacing between the sub-pixel areas (SP1, SP2, SP3, and SP4 in FIG. 2) is relatively high, resulting in an aperture ratio of about 42.7%. However, in one pixel area P In the case of the organic electroluminescent device 101 according to the embodiment of the present invention having the arrangement structure of the sub-pixel areas (SP1, SP2, SP3, SP4) of 2 rows and 2 columns, the aperture ratio is 52.3% It can be seen that the aperture ratio is improved.

Further, the organic light emitting device 101 according to the embodiment of the present invention includes overlapping portions between the wirings PL, DL1, DL2, DL3, DL4, and Vref crossing the gate lines GL in each pixel region P The overlapped portion between the first auxiliary pattern AP1 and the data lines DL2 and DL3 intersecting with each other and the overlapping portion between the second auxiliary pattern AP2 and the data lines DL1 and DL4 intersecting with each other are minimized, It is possible to further suppress the occurrence of a short defect in the pixel region P and to further improve the aperture ratio of the pixel region P by reducing the overlap region.

FIG. 5 is a view showing an overlap region between wirings intersecting with each other within a pixel region, an overlap region between the first auxiliary pattern and the data wirings in the organic electroluminescent device according to the embodiment of the present invention, For example, in the conventional organic electroluminescent device, overlapping regions between wirings intersecting within one pixel region and overlapping regions between the first auxiliary patterns and data wirings are shown.

5, the organic light emitting device 101 according to the embodiment of the present invention includes two rows and two columns of four sub-pixel regions SP1, SP2, SP3, and SP4 in each pixel region P, (PL, DL1, DL2, DL3, DL4) crossing the gate line GL in one pixel region P due to the structural feature that the sense thin film transistors SeTr1, SeTr2, SeTr3, , Vref) and the overlapping area between the first auxiliary pattern AP1 and the data lines DL2 and DL3 and between the second auxiliary pattern AP2 and the data lines DL1 and DL4 are 18 .

That is, in one pixel region P of the organic EL device 101 according to the embodiment of the present invention, two overlapping portions between the gate line GL and the power line PL, Two overlapping portions between the data lines DL1, DL2, DL3 and DL4 and the overlapping portions between the gate lines GL and the Vref lines Vref and the overlapping two portions between the first auxiliary patterns AP1 and the data lines DL2 And DL3 and the second auxiliary pattern AP2 and the data lines DL1 and DL4 are overlapped with each other, a total of 18 overlapping portions are generated.

6, the conventional organic electroluminescent device 1 according to the comparative example has four sub-pixel regions SP1, SP2, SP3 and SP4 electrically connected to the Vref line Vref The first auxiliary pattern AP1 is extended to a relatively long length so that the first auxiliary pattern AP1 is overlapped with the four first, second, third and fourth data lines DL1, DL2, DL3 and DL4, Two overlapping portions are generated between the gate lines GL and the power lines PL and eight overlapping portions are generated between the gate lines GL and the data lines DL1, DL2, DL3 and DL4, Two overlapped portions are generated between the Vref wirings Vref and four overlapping portions are generated between the second auxiliary patterns AP2 and the data wirings DL1, DL2, DL3 and DL4. .

5, an organic light emitting device 101 according to an embodiment of the present invention includes a gate line GL and wiring lines PL, DL1, DL2, DL3, and DL4 Overlapping portions between the first and second auxiliary patterns AP1 and AP2 and the wirings DL2, DL3, DL1 and D14 intersecting the first and second auxiliary patterns AP1 and AP2 and Vref are compared with each other in comparison with the conventional organic electroluminescent device 1 6, which means that the overlap area is reduced by 25%. Further, it can be seen that the effect of reducing the occurrence of short defects and the effect of improving the aperture ratio are obtained by reducing the overlapped areas.

Hereinafter, a cross-sectional structure of an organic electroluminescent device according to an embodiment of the present invention having the above-described planar structure will be described.

7 is a cross-sectional view of a portion where a second auxiliary pattern and a driving thin film transistor are formed in one sub-pixel region SP in the organic electroluminescent device according to an embodiment of the present invention, and FIG. 3 is a sectional view taken along a line VII- 8 is a cross-sectional view of a portion where a switching thin film transistor is formed in one sub-pixel region in an organic electroluminescent device according to an embodiment of the present invention, and FIG. 3 is a sectional view taken along a line VIII- FIG. 9 is a cross-sectional view of a portion where a first auxiliary pattern and a sense thin film transistor are formed in one sub-pixel region in the organic electroluminescent device according to the embodiment of the present invention, and FIG. Sectional view taken along the cutting line IX-IX.

7, 8, and 9 show only the first sub-pixel region SP1 and the constituent elements disposed at the boundary and the periphery thereof, the first, second, third, and fourth sub- All of the components that have been given different names are collectively referred to as first, second, third, and fourth. For example, the data line associated with the first sub-pixel region SPa is the first data line, but this is called the first data line without the first data line.

Since the switching and driving thin film transistors STr1 and DTr1 and the sense thin film transistor SeTr1 for driving each sub pixel region all have the same sectional configuration, only the sectional configuration of the driving thin film transistor DTr1 is described For convenience of explanation, the constituent elements formed only in correspondence with the respective thin film transistors STr1, DTr1 and SeTr1 among the constituent elements constituting the switching and driving thin film transistors STr1 and DTr1 and the sense thin film transistor SeTr1, The source electrode 133 and the drain electrode 136 which are spaced apart from the gate electrode 115 and the semiconductor layer 120 are denoted by the same reference numerals and the switching and driving and sense thin film transistors STr1, A, b, and c are added together at the end of each numeral of each numeral in order of the gate insulating layer 118, the interlayer insulating layer 123, and the passivation layer 140, Since the component is formed of a sintered state was given only the reference numerals of the same number.

As shown in the figure, in the organic light emitting device 101 according to the embodiment of the present invention, a plurality of thin film transistors STr1, SeTr1 and DTr1 and an organic light emitting diode E are provided in each sub- And a second substrate 170 for encapsulation for protecting the organic electroluminescent diode E against moisture or oxygen from the outside and facing the first substrate 110 .

Although not shown, a printed circuit board (not shown) having a driving circuit (not shown) for driving is mounted on the non-display area of the first substrate 110 outside the display area.

Meanwhile, although the second substrate 170 is shown to be spaced apart from the first substrate 110 in the organic electroluminescent device 101 according to the embodiment of the present invention, The first electrode 170 may be configured to contact the second electrode 168 provided on the uppermost layer of the first substrate 110 in the form of a film including an adhesive layer, An insulating film (not shown) or an inorganic insulating film (not shown) may be further provided and used as an encapsulation film (not shown).

Since the organic electroluminescent device 101 according to the embodiment of the present invention has a characteristic feature on the first substrate 110, the following description will focus on the structure of the first substrate 110. FIG.

The first substrate 110 is provided with three thin film transistors STr1, DTr1, and SeTr1 for switching, driving, and sensing in each subpixel region SP in the pixel region P, And an organic light emitting diode E connected to the driving thin film transistor DTr1.

The gate line GL and the data line DL1 are connected to the switching thin film transistor (not shown) and intersect with each other. The gate line GL and the data line DL1 intersect with the gate line GL and are spaced apart from the data line DL1 A power supply line PL is provided and a central portion of each pixel region P is provided with a Vref line Vref extending in the first direction in the vertical direction and being in parallel with the data line DL1.

The first auxiliary pattern AP1 is provided in the second hole hl2 provided in the gate line GL and connected to the power line PL in the pixel region P and in the boundary thereof And a second auxiliary pattern AP2 is provided in parallel with the gate line GL.

The gate line GL is provided with a first hole hl1 corresponding to a portion intersecting the power supply line PL and the first and fourth data lines DL1 and DL4 arranged adjacent to each other, A second hole hl2 is provided corresponding to a portion intersecting the second data line DL2, the Vref line Vref, and the third data line DL3.

The first auxiliary pattern Ap1 is provided with third and fourth holes hl3 and hl4 corresponding to the second and third data lines DL2 and DL3 intersecting with each other. The planar shapes of the gate line GL and the first auxiliary pattern AP1 provided with the first through fourth holes hl1 and hl2m hl3m hl4 have been described in detail with reference to FIG. 3 and will not be described here.

The driving thin film transistor DTr1 is connected to the switching thin film transistor STr1 and the sensing thin film transistor SeTr1 and is connected to the power supply line PL and the organic light emitting diode E, The transistor SeTr1 is connected to the Vref line Vref via the first auxiliary pattern AP1 in addition to the driving thin film transistor DTr1.

The driving thin film transistor DTr1 includes a driving gate electrode 115b, a gate insulating layer 118, an oxide semiconductor layer 120b, and a semiconductor layer contact hole sch on the first substrate 110 A source electrode 133b and a drain electrode 136b which are separated from each other on the interlayer insulating film 123 and are in contact with the oxide semiconductor layer 120b through the semiconductor layer contact hole sch, Are sequentially stacked.

At this time, the switching thin film transistor STr1 and the sense thin film transistor SeTr1 also have the same lamination structure as the driving thin film transistor DTr1.

The source electrode 133b of the driving thin film transistor DTr1 is connected via the power supply line PL and the second auxiliary pattern AP2.

On the other hand, the same layer on which the driving gate electrode 115b of the driving thin film transistor DTr is formed, that is, the first substrate 1410, is made of the same metal material as the driving gate electrode 115b, A first auxiliary pattern AP1 having third and fourth holes hl3 and hl4 is formed in the second hole hl2 of the gate line GL while being spaced apart from the second auxiliary pattern AP2, And a driving gate electrode 115b of the driving thin film transistor DTr1 is formed in each sub pixel area SP1 to form the first electrode 116 of the storage capacitor StgC.

At this time, the first and second auxiliary patterns AP1 and AP2 functioning to simultaneously contact two different components at the same time to electrically connect the two components are formed in the layer on which the gate line GL is formed This is to suppress the progress of a separate additional mask process for these first and second auxiliary pattern formation (AP1, AP2).

The same layer as the driving source and drain electrodes 133b and 136b of the driving thin film transistor DTr1 is formed of the same metal material as the driving source and drain electrodes 133b and 136b on the interlayer insulating film 123 The data lines DL1 and DL2 extend in a first direction intersecting with the gate line GL and are spaced apart from and adjacent to the first and fourth data lines to form a power line PL A Vref wiring Vref is formed at the center of the pixel region P and a second storage electrode 137 is partially formed to overlap with the first storage electrode 116. [ At this time, the second storage electrode 137 is connected to the driving drain electrode 136b of the driving thin film transistor DTr1 and the sense drain electrode 136c of the sense thin film transistor SeTr.

The switching gate electrode 115a of the switching thin film transistor STr1 is branched from the gate wiring GL or the fourth wiring portion GLA4 of the gate wiring GL, STr1 are connected to the data line DL1.

The third wiring portion GLA3 and fourth wiring portion GLA4 branched from the gate wiring GL and more precisely on the gate wiring GL are connected to the sense gate electrode 115c of the sense thin film transistor SeTr1 And the first auxiliary pattern AP1 connected to the Vref wiring Vref is connected to the sense source electrode 133c of the sense thin film transistor SeTr1, 2 auxiliary pattern AP2 to the driving source electrode 133b of the driving thin film transistor DTr1.

On the other hand, between the first auxiliary pattern AP1 and the sense source electrode 133c of the sense thin film transistor SeTr1, a contact hole (chl (n)) is formed in the gate insulating film 118 and the interlayer insulating film 123, The second auxiliary patterns AP2 and the power supply lines PL are also in contact with each other through the contact holes CH1.

The oxide semiconductor layers 120a, 120c and 120c and the source electrodes 133a and 133b and 133c and the oxide semiconductor layers 120a and 120c and 120c and the drain electrodes 136a and 136b and 136c are formed on the interlayer insulating film The semiconductor layer contact holes sch expose the oxide semiconductor layers 120a, 120c and 120c in contact with the semiconductor layer contact holes sch.

That is, between the two constituent elements formed by different layers, a contact hole (chl) or a semiconductor layer contact hole (not shown) is formed in an insulating layer interposed between the two components, for example, the gate insulating film 118 or and two constituent elements provided on different layers are in contact with each other through the contact holes chl or the semiconductor layer contact holes sch.

Although the switching and driving thin film transistors STr1 and DTr1 and the sensing thin film transistor SeTr1 form the bottom gate structure in the drawing, the switching and driving thin film transistors STr1 and DTr1 and the sensing thin film transistor (SeTr1) may be variously modified.

For example, the switching and driving thin film transistors STr1 and DTr1 and the sense thin film transistor SeTr1 may have a polysilicon semiconductor layer and may be configured as a top gate type.

In this case, the switching and driving thin film transistors STr1 and DTr1 and the sense thin film transistor SeTr1 include a semiconductor layer composed of an active region of pure polysilicon and source and drain regions of polysilicon doped with impurities on both sides thereof, An interlayer insulating film having an insulating film, a gate electrode formed to overlap with the active region, and a semiconductor layer contact hole exposing the source and drain regions, respectively, and an interlayer insulating film which contacts the source and drain regions through the semiconductor layer contact holes, And source and drain electrodes formed spaced apart from each other.

On the other hand, the gate electrodes 115a, 115b and 115c and the gate line GL, the data lines DL1, DL2 and DL3, the power supply line PL, the source and drain electrodes 133a, 133b, 133c and 136a And the first and second auxiliary patterns AP1 and AP2 are formed of a metal material having low resistance characteristics such as copper (Cu), copper alloy (AlNd), aluminum (Al) Aluminum alloy (AlNd), molybdenum (Mo), and moly titanium (MoTi) to form a single layer or a multilayer structure of more than two layers.

Next, a protective film 140 made of an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is formed on the switching and driving thin film transistors STr 1 and DTr 1 and the sense thin film transistor SeTr ₁ , A planarization layer 150 having a flat surface on the protective film 140 is formed over the entire display region.

The planarization layer 150 and the passivation layer 140 are provided with a drain contact hole 153 exposing the driving drain electrode 136b corresponding to the driving TFT DTr1.

A first electrode 160 is formed on the planarization layer 150 to contact the driving drain electrode 136b through the drain contact hole 153 for each sub-pixel region SP1.

The first electrode 160 may have a two-layer structure, and the upper layer 160b of the first electrode 160 may function as an anode electrode. , And the lower layer 160a is formed to serve as a reflection layer.

The upper layer 160b of the first electrode 160 may be formed of a transparent conductive material having a relatively large work function value such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) And the lower layer 160a of the first electrode 160 may be formed of a metal material or an alloy having excellent reflection efficiency such as aluminum (Al), aluminum-neodymium (AlNd), silver (Ag), silver- APC), the light emitted from the organic light emitting layer 165 formed on the first electrode 160 is reflected upward and recycled to improve the light emitting efficiency.

However, the first electrode 160 does not need to have a bilayer structure. When the first electrode 160 is operated as a bottom emission type, a transparent conductive material having a relatively large work function value such as indium-tin oxide ) Or indium-zinc-oxide (IZO).

In the drawing, the first electrode 160 has a double layer structure. Work

On the other hand, a bank 163 is formed on the boundary of each sub-pixel region SP1 on the first electrode 160. [

At this time, the bank 163 is formed to surround the sub-pixel region SP1 and expose a central portion of the first electrode 160, overlapping a predetermined width of the edge of the first electrode 160.

The bank 163 having such a structure is made of a transparent organic insulating material, for example, polyimide, or made of a black material, for example, a black resin.

An organic emission layer 165 is formed on the first electrode 160 surrounded by the banks 163 of the respective sub-pixel regions SP1.

A metal material having a relatively low work function value such as aluminum (Al), an aluminum alloy (AlNd), or the like may be formed on the organic light emitting layer 165 and the bank 163, A second electrode 168 made of any one of or a mixture of two or more of silver (Ag), magnesium (Mg), gold (Au), and aluminum magnesium alloy (AlMg) is formed.

In the sub-pixel region SP1, the first and second electrodes 160 and 168 and the organic light emitting layer 165 formed therebetween form an organic light emitting diode E.

Although not shown, a multilayer structure (not shown) may be formed between the first electrode 160 and the organic emission layer 165 and between the organic emission layer 165 and the second electrode 168 to improve the emission efficiency of the organic emission layer 165, A first light emission compensation layer (not shown) and a second emission compensation layer (not shown) may be further formed.

The first emission compensation layer (not shown) may be sequentially stacked on the first electrode 160, and may include a hole injection layer and a hole transporting layer. 2 emission compensation layer (not shown) may be sequentially stacked from the organic emission layer 165 and may include an electron transporting layer and an electron injection layer.

Although the first luminescence compensation layer (not shown) and the second luminescence compensation layer (not shown) have a bilayer structure as an example, the bilayer structure is not necessarily required. That is, the first emission compensation layer (not shown) may be a hole injection layer or a hole transport layer to form a single layer structure, and the second emission compensation layer (not shown) may also be an electron injection layer or an electron transport layer, Structure.

In addition, the first emission compensation layer (not shown) may further include an electron blocking layer, and the second emission compensation layer (not shown) may further include a hole blocking layer.

The organic electroluminescent device 101 according to the embodiment of the present invention includes a second substrate 170 for encapsulation of the organic electroluminescent diode E corresponding to the first substrate 110 having the above- .

In this case, the first substrate 110 and the second substrate 170 are provided with an adhesive (not shown) made of a sealant or a frit along the edge thereof. The adhesive (not shown) 110 and the second substrate 170 are adhered to each other to maintain the panel state.

At this time, a vacuum state is formed between the first substrate 110 and the second substrate 170 which are spaced apart from each other, or an inert gas atmosphere may be obtained by being filled with an inert gas.

The second substrate 170 for the encapsulation may be made of plastic having a flexible property, or may be made of a glass substrate.

Meanwhile, the organic electroluminescent device 101 according to the embodiment of the present invention may have a configuration in which the second substrate 170 for encapsulation is omitted.

That is, the second substrate 170 may be configured to contact the second electrode 168 provided on the uppermost layer of the first substrate 110 in the form of a film including an adhesive layer, An organic insulating film (not shown) or an inorganic insulating film (not shown) may further be formed on the insulating layer 168 to form a capping film. The organic insulating film (not shown) or the inorganic insulating film (not shown) (Not shown). In this case, the second substrate 170 is omitted.

In the organic EL device 101 according to the embodiment of the present invention having such a configuration, four sub-pixel regions (SP1, SP2, SP3, and Sp4 in FIG. 3) are arranged in two rows and two columns And a structure having a first hole hl1 and a second hole hl2 of a gate wiring GL and a structure having a first auxiliary pattern AP1 connected to a Vref wiring Vref inside the second hole hl2, And the sense-film transistor SeTr1 are arranged concentrically in the central portion of each pixel region P around the second hole hl2, the aperture ratio of the pixel region P is improved, It is possible to repair the short-circuit between the wirings or between the auxiliary patterns and the wirings which intersect with each other.

Further, the organic light emitting diode 101 according to the embodiment of the present invention may be configured such that the gate wiring GL and the wirings PL, DL1, DL2, DL3, DL4, and Vref intersecting with each other in each pixel region P, The overlapped portion between the intersecting first auxiliary pattern AP1 and the data lines DL2 and D13 and the overlapped portion between the second auxiliary pattern AP2 and the data lines DL1 and DL4 are minimized, And the aperture ratio of the pixel region is further improved by reducing the overlap region.

The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit and scope of the present invention.

101: Organic electroluminescent device
115a, 115b, and 115c: switching, driving, and sense gate electrodes
116: first storage electrode
120a, 120b, and 12c: switching, driving, and sense oxide semiconductor layers
133a, 133b, 133c: switching, drive and sense source electrodes
136a, 136b, 136c: switching, driving and sense drain electrodes
137: second storage electrode
160: first electrode
153: drain contact hole
AP1, AP2: First and second auxiliary patterns
chl: contact hole
DL1, DL2, DL3, DL4: First, second, third, and fourth data lines
DTr1, DTr2, DTr3, DTr4: driving thin film transistor
GL: gate wiring
GLA1, GLA2, GLA3, GLA4: First, second, third, and fourth partial wiring
hl1, hl2, hl3, hl4: first, second, third, and fourth holes
P: pixel area
PL: Power supply wiring
sch: semiconductor layer contact hole
SeTr1, SeTr2, SeTr3, SeTr4: a sense thin film transistor
SP1, SP2, SP3, and SP4: first, second, third, and fourth sub-
STr1, STr2, STr3, STr4: switching thin film transistor
Vref: Vref wiring

Claims (7)

A substrate on which four sub-pixel regions form one pixel region and the four sub-pixel regions are arranged in two rows and two columns in the pixel region;
First, second, third, and fourth data lines disposed on left and right sides of the first and second column pixel regions on the substrate, respectively, and extending in a first direction;
A power supply line arranged in parallel adjacent to the first and fourth data lines;
A first auxiliary wiring disposed between the second and third data wirings;
The first and second holes are arranged in a second direction intersecting with the first direction and are branched at a portion intersecting the first, second, third, and fourth data lines, the power supply wiring, and the first auxiliary wiring. A gate wiring provided on the substrate;
A switching thin film transistor provided in each of the sub-pixel regions and connected to the gate wiring and any one of the first, second, third, and fourth data lines;
A driving thin film transistor provided in each sub-pixel region and connected to the switching thin film transistor;
A sense thin film transistor provided around each of the sub-pixel regions and having a gate wiring portion for capturing the first hole as a gate electrode;
An organic light emitting diode connected to the driving thin film transistor
And an organic electroluminescent device.
The method according to claim 1,
And a first auxiliary pattern provided in the second hole and in contact with the first auxiliary wiring.
3. The method of claim 2,
Wherein the first auxiliary pattern includes a hole corresponding to a portion overlapping the second and third data lines, and overlaps the second and third data lines with each other.
The method according to claim 1,
And the second hole is provided corresponding to the first and fourth data lines arranged adjacent to the power supply line.
The method according to claim 1,
And a second pixel region adjacent to the first pixel electrode and the second pixel electrode, the second pixel electrode being in contact with the power supply wiring and being in contact with the source electrode of the driving TFT included in each of the first and fourth data lines, An organic electroluminescent device having an auxiliary pattern.
6. The method of claim 5,
Wherein the gate wiring, the first auxiliary pattern and the second auxiliary pattern are formed in the same layer.
The method according to claim 1,
Wherein the first and second sub-pixel regions are located on the upper side in the pixel region, the third and fourth sub-pixel regions are located on the lower side in the pixel region, and the switching thin film Wherein each of the transistors comprises a gate electrode of the switching thin film transistor, the portion of the gate wiring branched at a portion capturing the first hole.

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