KR20160083593A - Array substrate and manufacturing method thereof - Google Patents

Abstract

An array substrate comprises: a pixel electrode and a common electrode line on an insulating layer; and a connection electrode connected to a common electrode through a contact hole on the common electrode line, thereby easily connecting the common electrode line to a common line through the connection electrode.

Description

[0001] The present invention relates to an array substrate and a manufacturing method thereof,

The present invention relates to an array substrate and a manufacturing method thereof.

The display device is a device for displaying images or information. A liquid crystal display device among display devices displays an image by adjusting the light transmittance of a liquid crystal using an electric field.

In the liquid crystal display device, a data voltage is supplied from the source drive to the liquid crystal display panel based on the timing control signal supplied from the timing control section, and an image is displayed.

The liquid crystal display panel includes an array substrate on which a plurality of thin film transistors are arrayed, a color filter substrate on which a plurality of color filters corresponding to each thin film transistor are arranged, and a liquid crystal layer disposed between the substrates.

In addition to the thin film transistors, many layers of the array substrate have to be patterned, thereby increasing the number of masks.

One mask process is required to be a pre-cleaning process, a photolithography process, an exposure process, a development process, and a post-process. In addition, an aline process is required between these processes.

Thus, as the number of masks increases, the sub-processes increase exponentially.

In recent years, various processing methods have been developed to reduce the number of masks, but it is difficult to reduce the number of masks to a satisfactory level.

In addition, there is a problem that misalignment occurs due to difficulty in alignment control due to process restrictions used in each mask process.

The present invention is directed to solving the above-mentioned problems and other problems.

Another object of the present invention is to provide an array substrate in which the number of masks is reduced and a manufacturing method thereof.

It is still another object of the present invention to provide an array substrate for preventing mis-alignment and a method of manufacturing the same.

According to an aspect of the present invention, an array substrate includes a pixel electrode and a common electrode line on an insulating layer, and a connection electrode connected to the common electrode through a contact hole on a common electrode line , The common electrode line can be easily connected to the common line through the connection electrode.

A method of manufacturing an array substrate includes forming an alignment key, forming a planarization layer on a data line, a source electrode, and a drain electrode, wherein a planarization layer is not formed on the alignment key, and an opaque conductive film Even if the alignment key is difficult to identify in the alignment process, it is possible to align the alignment mark by presence or absence of the flattening layer, thereby preventing misalignment.

The effect of the terminal according to the present invention is as follows.

According to at least one of the embodiments of the present invention, a flattening layer is formed in the display area, while a flattening layer is not formed in the non-display area, and even if the alignment key is difficult to identify by the opaque metal film in the subsequent step It is possible to prevent occurrence of misalignment in the pattern of the photosensitive film for forming the photosensitive pattern due to the step difference due to the presence or absence of the organic film in the area and the non-display area.

According to at least one embodiment of the present invention, a semiconductor layer, a data line and the like are simultaneously formed, a planarization layer and a common electrode are formed at the same time, and a connection electrode for connecting the common electrode line to a common line is formed Thereby reducing the number of mask processes and simplifying the process.

Further scope of applicability of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples, such as the preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art.

1 is a plan view showing an array substrate of a liquid crystal display panel according to the present invention.
2 is a cross-sectional view showing an array substrate of a liquid crystal display panel according to the present invention.
3 to 7 are views showing a method of manufacturing an array substrate of a liquid crystal display panel according to the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, wherein like reference numerals are used to designate identical or similar elements, and redundant description thereof will be omitted. The suffix "module" and " part "for the components used in the following description are given or mixed in consideration of ease of specification, and do not have their own meaning or role. In the following description of the embodiments of the present invention, a detailed description of related arts will be omitted when it is determined that the gist of the embodiments disclosed herein may be blurred. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. , ≪ / RTI > equivalents, and alternatives.

1 is a plan view showing an array substrate of a liquid crystal display panel according to the present invention.

The liquid crystal display panel according to the present invention may include an array substrate, a color filter substrate, and a liquid crystal layer formed between the substrates.

A plurality of pixels P can be defined by the intersection of the plurality of gate lines 11 and the plurality of data lines 23 on the array substrate. Each pixel P may include a thin film transistor connected to the gate line 11 and the data line 23 and a pixel electrode 45 connected to the thin film transistor. The pixel electrodes 45 formed on each pixel P may be spaced apart from each other.

A common electrode 37 for supplying a common voltage separately from the pixel electrode 45 may be provided.

The liquid crystal display panel according to the present invention may be driven by an in-plane switching (IPS) method.

To this end, a horizontal electric field is generated by the data voltage applied to the pixel electrode 45 and the common voltage applied to the common electrode 37, and the liquid crystal molecules of the liquid crystal layer are displaced by this horizontal electric field, The light transmittance can be adjusted and an image can be displayed.

Referring to FIG. 1, the gate lines 11 may be disposed along a first direction, for example, a lateral direction, and the data lines 23 may be disposed along a second direction, for example, a longitudinal direction. The gate line 11 and the data line 23 may be arranged to intersect with each other.

The gate electrode 13 may be disposed extending from the first side of the gate line 11. [ The source electrode 24 may extend from the first side of the data line 23 and the drain electrode 33 may be disposed apart from the source electrode 24. The source electrode 24 and the drain electrode 33 may be disposed on the gate electrode 13. [

Although not shown, a semiconductor layer may be disposed between the gate electrode 13 and the source electrode 24 / drain electrode 33. Therefore, a thin film transistor composed of the gate electrode 13, the semiconductor layer, and the source electrode 24 / the drain electrode 33 can be constituted. The thin film transistor is activated by the scan signal applied to the gate electrode 13 through the gate line 11 and the data voltage Vd applied to the source electrode 24 through the data line 23, May be supplied to the drain electrode 33 via the semiconductor layer 18. The data voltage supplied to the drain electrode 33 may be supplied to the pixel electrode 45 electrically connected to the drain electrode 33. [

The source electrode 24 and the drain electrode 33 are formed on the gate line 11 in such a case that the gate electrode 11 itself serves as the gate electrode 13. In this case, .

And the gate lower electrode 19 may be disposed extending from the second side of the gate line 11. [ And the data lower electrode 29 may be disposed extending from the second side of the data line 23.

The gate upper electrode 21 may be electrically connected to the gate lower electrode 19 through the gate contact hole 17. [ The gate contact hole 17 may be formed to connect the gate lower electrode 19 and the gate upper electrode 21 to each other and to connect them to each other. The gate pad portion 15 may be constituted by the gate lower electrode 19 and the gate upper electrode 21. The gate driving circuit can be electrically connected to the gate pad portion 15, specifically, the gate upper electrode 21. [ Accordingly, a scan signal supplied from the gate drive circuit can be supplied to the gate line 11 and the gate electrode 13 through the gate pad portion 15. [

The data upper electrode 31 may be electrically connected to the data lower electrode 29 through the data contact hole 27. [ The data contact hole 27 may be formed to connect and connect the data lower electrode 29 and the data upper electrode 31 to each other in a different layer. The data pad portion 25 may be formed by the data lower electrode 29 and the data upper electrode 31. [ The data driving circuit can be electrically connected to the data pad unit 25, specifically, the data upper electrode 31. [ Accordingly, a scan signal supplied from the data driving circuit can be supplied to the data line 23 and the source electrode 24 through the data pad unit 25. [

The alignment key 20 can be disposed adjacent to the gate pad portion 15. [ The alignment key 20 may be disposed on the same layer as the gate line 11, the gate electrode 13, and the gate lower electrode 19. The alignment key 20 may serve as a reference key for aligning the photosensitive film to a specific region of the photosensitive film as an exposure source of the exposure apparatus when the photosensitive film is patterned by the exposure process.

The liquid crystal display panel can be divided into a display area and a non-display area. The display area is an area for displaying an image, and the non-display area is an area for not displaying an image. A plurality of pixels each including a thin film transistor and a pixel electrode 45 may be included in the display area. The gate pad portion 15, the data pad portion 25, and the alignment key 20 may be disposed in the non-display region.

The pixel may include a thin film transistor and a pixel electrode 45. The pixel electrode 45 may be electrically connected to the drain electrode 33 of the thin film transistor through the pixel contact hole 35. The pixel contact hole 35 may be formed to connect the drain electrode 33 and the pixel electrode 45 to each other and to connect them.

The pixel electrode 45 may include a plurality of pixel electrode bars 41 to 44 along the second direction. And the pixel electrode bars 41 to 44 may be spaced apart from each other.

A part of each of the pixel electrode bars 41 to 44 may be bent. For example, each of the pixel electrode bars 41 to 44 may be bent so as to have an acute angle with respect to the reference line along the first direction, for example, the horizontal direction when viewed from right to left. The data lines 23 corresponding to the respective pixel electrode bars 41 to 44 may also be bent. As described above, by bending the pixel electrode bars 41 to 44, the displacement of the liquid crystal molecules due to the horizontal electric field is further increased, and particularly the liquid crystal molecules can be easily recovered and the image quality can be improved.

Although not shown, the common electrode 37 may be disposed below each of the pixel electrode bars 41 to 44. The common electrode 37 may be disposed integrally with all of the pixels P. In other words, the common electrode 37 may be disposed integrally with all the pixels without being separated by the pixel P like the pixel electrode 45. Accordingly, the common electrode 37 can be disposed not only on the pixel but also on the gate line 11, the data line 23, and the thin film transistor disposed adjacent to the boundary between the pixels. On the other hand, the pixel electrode 45 can be disposed on the pixel without being disposed on the gate line 11, the data line 23, and the thin film transistor.

The common electrode line 47 may be disposed on the gate line 11. [ Although not shown, a pad portion (not shown) of the common electrode 37 connected to the common electrode line 47 may be disposed separately from the gate pad. By arranging the common electrode line 47 on the gate line 11, the aperture ratio of the pixel can be improved.

The connection electrode 50 electrically connects the common electrode line 47 to the common electrode 37. The first side of the connecting electrode 50 may be electrically connected to the common electrode line 47 and the second side of the connecting electrode 50 may be electrically connected to the common electrode 37 through the jumping contact hole 49 have. The jumping contact hole 49 may be formed to connect the common electrode 37 and the common electrode line 47 to each other and to connect them to each other.

The jumping contact hole 49 may be positioned adjacent to the gate line 11 or on a part of the gate line 11. [ In addition, the jumping contact hole 49 may be disposed adjacent to the common electrode line 47. The jumping contact hole 49 is disposed adjacent to the common electrode line 47 so that the connection electrode 50 connected from the common electrode line 47 through the jumping contact hole 49 to the common electrode 37, Can be minimized.

Since the size of the connecting electrode 50 is at least larger than the width of the common electrode line 47, the connecting electrode 50 can cover the common electrode line 47 along the width direction of the common electrode line 47 . The connecting electrode 50 may be in direct contact with the upper surface and the side surface of the common electrode line 47. Therefore, a common voltage applied to the common electrode line 47 can be supplied to the common electrode 37 through the connection electrode 50. [

2 is a cross-sectional view showing an array substrate of a liquid crystal display panel according to the present invention.

FIG. 2 is a cross-sectional view of the array substrate of the liquid crystal display panel of FIG. 1 taken along lines I-I, II-II ', and III-III.

2, a gate line 11, a gate electrode 13, a gate lower electrode 19, and an alignment key 20 may be disposed on a substrate 10.

The gate electrode 13 may be a part of the thin film transistor and the gate lower electrode 19 may be a component of the gate pad portion 15. [

The gate electrode 13 may extend from the first side of the gate line 11 and the gate lower electrode 19 may extend from the second side of the gate line 11. [ The alignment key 20 may be spaced apart from the gate line 11, the gate electrode 13 and the gate lower electrode 19. [

Each of the gate line 11, the gate electrode 13, the gate lower electrode 19 and the alignment key 20 may include first through third conductive patterns 101, 103, and 105. The second conductive patterns 103a, 103b and 103c are arranged on the first conductive patterns 101a, 101b and 101c and the third conductive patterns 105a, 105b and 105c are arranged on the second conductive patterns 103a, 103b and 103c ). ≪ / RTI >

Each of the first through third conductive patterns 101, 103, and 105 may have the same size, but the present invention is not limited thereto. Since the first through third conductive patterns 101, 103, and 105 have the same size, the first through third conductive patterns 101, 103, and 105 are simultaneously formed by one etching process, .

The first conductive patterns 101a, 101b and 101c include MoTi, the second conductive patterns 103a, 103b and 103c include, for example, Cu, and the third conductive patterns 105a, 105b and 105c include ITO But is not limited thereto. The first conductive patterns 101a, 101b, and 101c can enhance the adhesion to the substrate 10. [ The second conductive patterns 103a, 103b, and 103c have excellent electrical characteristics and facilitate signal flow. The third conductive patterns 105a, 105b, and 105c may prevent the second conductive patterns 103a, 103b, and 103c from being corroded by the etching solution during the patterning process of the common electrode line 47, You can give.

The first insulating layer 12 may be disposed on the gate line 11, the gate electrode 13, the gate lower electrode 19 and the alignment key 20. [ The first insulating layer 12 may be formed of an inorganic material such as SiOx or SiNx, but the present invention is not limited thereto.

The semiconductor layer 18, the data line 23, the source electrode 24, the drain electrode 33, and the data lower electrode 29 may be disposed on the first insulating layer 12.

The semiconductor layer 18 is disposed on the gate electrode 13 and the source electrode 24, the drain electrode 33 and the data lower electrode 29 are disposed on the semiconductor layer 18 so as to be spaced apart from each other. The source electrode 24 may be disposed to extend from the first side of the data line 23 and the data lower electrode 29 may be disposed to extend from the second side of the data line 23. [

The semiconductor layer 18 may include any one of amorphous silicon (a-Si), polysilicon (p-Si), low temperature polysilicon (LTPS), and oxide.

Each of the data lower electrodes 29 may include a semiconductor pattern 113a and a conductive pattern 115a. The semiconductor pattern 113a may be formed of the same material as the semiconductor layer 18 and the conductive pattern 115a may be formed of the same material as the data line 23, the source electrode 24, and the drain electrode 33. [

Each of the conductive pattern 115a, the data line 23, the source electrode 24 and the drain electrode 33 is electrically connected to the gate line 11, the gate electrode 13, the gate lower electrode 19 and the alignment key 20, And may include the first to third conductive patterns 101, 103, and 105, respectively. The first conductive patterns 101a, 101b and 101c include MoTi, the second conductive patterns 103a, 103b and 103c include, for example, Cu, and the third conductive patterns 105a, 105b and 105c include ITO But is not limited thereto.

The first insulating layer 12 may electrically isolate the gate line 11 and the data line 23 from each other.

The second insulating layer 14 is disposed on the data line 23, the source electrode 24, the drain electrode 33, the data lower electrode 29, the gate lower electrode 19 and the alignment key 20 . Specifically, the second insulating layer 14 is disposed on the first insulating layer 12 corresponding to the gate lower electrode 19 and the alignment key 20, and the data line 23, the source electrode 24, The drain electrode 33, and the data lower electrode 29, respectively.

The second insulating layer 14 may be formed of an inorganic material such as SiOx or SiNx, but the present invention is not limited thereto.

The planarization layer 16 may be disposed on the second insulating layer 14 corresponding to the display region including the plurality of pixels P. [ The planarizing layer 16 is not disposed on the gate lower electrode 19, the data lower electrode 29, and the alignment key 20 disposed in the non-display region.

The planarization layer 16 may be formed of an organic material such as photo acryl, but is not limited thereto. The planarization layer 16 has a flat upper surface to prevent disconnection of a pattern or a layer on the planarization layer 16 and to prevent breakage of the layer or the like between the common electrode 37 and the pixel electrode 45, A uniform horizontal electric field can be generated to improve the image quality.

The planarization layer 16 may have a pixel contact hole 35. The pixel contact hole 35 may be formed so as to pass through the upper surface from the lower surface of the planarization layer 16. The pixel contact hole 35 may be disposed on a part of the drain electrode 33. [ The pixel contact hole 35 may be formed to electrically connect the pixel electrode 45 to be described later to the drain electrode 33 of the thin film transistor.

The second insulating layer 14 may compensate for the low adhesion between the planarization layer 16 and the data line 23, the source electrode 24, the drain electrode 33 and the data lower electrode 29. That is, since the second insulating layer 14 is excellent in adhesion to the data line 23, the source electrode 24, the drain electrode 33 and the data lower electrode 29, The planarization layer 16 is strongly adhered to the data line 23, the source electrode 24, the drain electrode 33 and the data lower electrode 29 to prevent peeling-off of the planarization layer 16 .

A common electrode 37 may be disposed on the planarization layer 16. The common electrode 37 may be disposed on the entire display region, that is, on the plurality of pixels P. [

The common electrode 37 may be formed of, for example, a transparent conductive material such as ITO, but is not limited thereto.

A third insulating layer 39 may be disposed on the common electrode 37. The third insulating layer 39 may be disposed on the second insulating layer 14 corresponding to the gate lower electrode 19, the alignment key 20 and the data lower electrode 29.

The third insulating layer 39 may be formed of an inorganic material such as SiOx or SiNx, but the present invention is not limited thereto.

The third insulating layer 39 may have a jumping contact hole 49. Although not shown, the jumping contact hole 49 is disposed adjacent to the gate line 11 or on a part of the gate line 11, so that the aperture ratio of the pixel can be secured.

The pixel electrode 45 and the common electrode line 47 may be disposed on the third insulating layer 39. [ That is, the pixel electrode 45 and the common electrode line 47 can be disposed on the same layer. Since the pixel electrode 45 and the common electrode line 47 are not disposed in different layers, the thickness of the array substrate can be reduced.

The pixel electrode 45 may include a plurality of pixel electrode bars 41 to 44 spaced from each other. A part of the pixel electrode 45 may be electrically connected to the drain electrode 33 of the thin film transistor through the pixel contact hole 35.

When the semiconductor layer 18 is activated by the scan signal supplied to the gate electrode 13 through the gate line 11, the data line 23, the source electrode 24, the semiconductor layer 18, and the drain electrode 33 may be applied to the pixel electrode bars 41 to 44 of the pixel electrode 45. [

A horizontal electric field can be generated by the data voltage applied to the pixel electrode bars 41 to 44 and the common voltage applied to the common electrode 37. [ In addition, since the common electrode 37 is disposed below the pixel electrode bars 41 to 44, a vertical electric field can also be generated. Since the horizontal electric field and the vertical electric field are generated between the pixel electrode bars 41 to 44 and the common electrode 37 as described above, the displacement of the liquid crystal molecules can be further increased while the displacement of the liquid crystal molecules can be controlled more precisely The image quality can be remarkably improved.

The pixel electrode 45 may be formed of a transparent conductive material such as ITO.

The common electrode line 47 may be disposed adjacent to the pixel electrode 45. [ In addition, the common electrode line 47 may be disposed adjacent to the jumping contact hole 49. The jumping contact hole 49 may be disposed between the pixel electrode 45 and the common electrode line 47.

The common electrode line 47 may be a single metal or an alloy thereof selected from the group consisting of Mo, Al, Cr, Au, Ti, Ni, and Cu, and may be formed as a single layer or multiple layers. The common electrode line 47 is opaque and can be disposed on the gate line 11 so as not to interfere with the aperture ratio of the pixel.

The common voltage supplied to the common electrode line 47 may be applied to the common electrode 37 through the connection electrode 50 and the jumping contact hole 49.

The connecting electrode 50 may be disposed on the third insulating layer 39 to connect the common electrode line 47 and the common electrode 37. [ The connecting electrode 50 may be in direct contact with the common electrode line 47 while contacting the common electrode 37 through the jumping contact hole 49. [

In this manner, the thickness of the array substrate can be reduced by connecting the connection electrode 50 directly to the common electrode line 47 without being connected to the common electrode 37 through the contact hole formed in the separate insulating layer.

The connection electrode 50 may be formed of a transparent conductive material such as ITO. The connecting electrode 50 may be formed of the same material as the pixel electrode 45, but is not limited thereto.

On the other hand, the gate upper electrode 21 and the data upper electrode 31 may be disposed on the third insulating layer 39.

The gate upper electrode 21 may be electrically connected to the gate lower electrode 19 through the gate contact hole 17. Accordingly, the gate pad portion 15 can be constituted by the gate lower electrode 19 and the gate upper electrode 21.

The data upper electrode 31 may be electrically connected to the data lower electrode 29 through the data contact hole 27. Accordingly, the data pad portion 25 can be formed by the data lower electrode 29 and the data upper electrode 31. [

3 to 7 are views showing a method of manufacturing an array substrate of a liquid crystal display panel according to the present invention.

The first mask process

3 shows a first mask process for forming gate lines, gate electrodes, gate bottom electrodes and alignment keys.

3A, the first conductive film 101, the second conductive film 103, and the third conductive film 105 are sequentially formed on the substrate 10, and the third conductive film 105, A photosensitive film may be formed on the photosensitive film. The photosensitive film may be exposed using an exposure process to form a photosensitive pattern 107 on the third conductive film 105.

The first conductive film 101 includes, for example, MoTi, the second conductive film includes, for example, Cu, and the third conductive film may include, but not limited to, ITO. The first conductive film 101 can enhance the adhesion to the substrate 10. The second conductive film 103 has excellent electrical characteristics and facilitates signal flow. The third conductive layer 103 can prevent the second conductive layer 103 from being corroded by the etching solution during the patterning process of the common electrode line 47, as will be described later in the process.

The third conductive film 105, the second conductive film 103 and the first conductive film 101 are patterned in this order using the photosensitive pattern 107 as a mask to form the gate line 11, The gate electrode 13, the gate lower electrode 19, and the alignment key 20 may be formed.

Each of the gate line 11, the gate electrode 13, the gate lower electrode 19 and the alignment key 20 includes a first conductive pattern 101a, 101b, 101c formed from the first conductive film 101, 105b and 105c formed from the second conductive patterns 103a, 103b and 103c formed from the conductive film 103 and the third conductive film 105. The third conductive patterns 105a,

Since the first to third conductive patterns 101, 103, and 105 are collectively formed by the same photosensitive pattern 107, the etching process can be simplified.

As the first to third conductive patterns 101, 103, and 105 are collectively formed, the sizes of the first to third conductive patterns 101, 103, and 105 are the same.

The second mask process

4 shows a second mask process for forming a semiconductor layer, a data line, a source electrode, a drain electrode and a data lower electrode.

The insulating film 111, the semiconductor film 113, and the conductive film (not shown) are formed on the gate line 11, the gate electrode 13, the gate lower electrode 19 and the alignment key 20, 115 are sequentially formed, and a photosensitive film may be formed on the conductive film 115. The photosensitive film may be exposed using the exposure process to form the photosensitive pattern 117 on the conductive film 115. [

The insulating film 111 may be formed of an inorganic material such as SiOx or SiNx, but the present invention is not limited thereto. The semiconductor film 112 may comprise any one of amorphous silicon (a-Si), polysilicon (p-Si), low temperature polysilicon (LTPS), and oxide. The conductive film 113 may include first to third conductive films 101, 103, and 105, as shown in FIG. 3A. For example, the first conductive film 101 may include MoTi, the second conductive film 103 may include, for example, Cu, and the third conductive film 105 may include, for example, ITO. Not limited.

The conductive film 115 and the semiconductor film 113 are patterned in this order using the photosensitive pattern 117 as a mask so that the data line 23, the source electrode 24, the drain electrode 33, And the data lower electrode 29 may be formed. The insulating film 111 may be the first insulating layer 12. [ Since the third conductive pattern 105 which is the uppermost layer of the drain electrode 33 is formed of ITO, when the conductive film (133 in FIG. 6B) is patterned in the subsequent process by the third layer 105, The second conductive pattern 103 disposed under the third conductive pattern 105 can be prevented from being corroded.

The semiconductor layer 18, the data line 23, the source electrode 24, the drain electrode 33 and the data lower electrode 29 are simultaneously formed by the same photosensitive pattern 117, so that the process can be simplified.

In the present invention, the semiconductor layer 18 and the source electrode 24 / the drain electrode 33 are simultaneously formed by the second mask process, so that the process can be simplified.

Third mask process

5 shows a third mask process for forming a common electrode.

5A, an insulating film 121, an organic film 123 (not shown) are formed on the semiconductor layer 18, the data line 23, the source electrode 24, the drain electrode 33 and the data lower electrode 29, And a conductive film 125 are sequentially formed, and a photosensitive film may be formed on the conductive film 125. The photosensitive film may be exposed using an exposure process to form a first photosensitive pattern 127 on the conductive film.

The insulating film 121 may be formed of an inorganic material such as SiOx or SiNx, but the present invention is not limited thereto. The organic film 123 may be formed of an organic material such as photo acryl, but is not limited thereto. The conductive film 125 may be formed of a transparent conductive material such as ITO, but the present invention is not limited thereto.

The conductive film 125 and the organic film 123 can be sequentially patterned using the first photosensitive pattern 127 as a mask, as shown in FIG. 5B. Since the organic film 123 has a higher etching rate than the conductive film 125, the organic film 123 underlying the conductive film 125 can be overetched. The pixel contact hole 35 can be formed by etching the organic film 123. [ At this time, the insulating layer 121 may be a second insulating layer 14.

The organic film 123 having the pixel contact hole 35 may be the planarization layer 16.

Both the conductive film 125 and the organic film 123 corresponding to the non-display region can be removed and the second insulating layer 14 can be exposed.

The conductive film 125 and the organic film 123 can all be removed on the alignment key 20 in particular. That is, the organic film 125 and the conductive film 123 are formed in the display region, while the organic film 125 and the conductive film 123 are removed in the non-display region, 6A) due to the presence of the organic film 125 in the display area and the non-display area even if the alignment key 20 is difficult to identify by the metal film 133 The occurrence of misalignment in the patterning of the photosensitive film can be prevented.

The upper surface and the side surface of the first photosensitive pattern 127 are etched to form the second photosensitive pattern 129 and a part of the upper surface of the conductive film 125 around the pixel contact hole 35 Can be exposed.

The exposed conductive layer 125 may be etched and removed using the second photosensitive pattern 129 as a mask. Thus, the common electrode 37 can be formed on the planarization layer 16. [

The common electrode 37 may be formed on the entire display region including the plurality of pixels P. [ Since the common electrode 37 is formed in a plate shape rather than a pattern, a separate etching process is not required and only a vapor deposition process is required, so that the process can be simplified.

Fourth mask process

6 shows a fourth mask process for forming a common electrode line.

An insulating film 131 and a metal film 133 may be formed on the common electrode 37 and a photoresist film may be formed on the metal film 133 as shown in Fig. The photosensitive film may be exposed using an exposure process to form the first photosensitive pattern 135 on the metal film.

The aligning process can be performed before the photosensitive film is exposed. The substrate 10 can be moved relative to the alignment key 20 for the alignment process. However, the opaque metal film 133 may be formed on the alignment key 20, so that the identification of the alignment key 20 may be difficult.

In the present invention, the planarization layer 16 is not formed in the non-display area including the alignment key 20, but the planarization layer 16 is formed in the display area, Misalignment due to difficulty in identification of the alignment key 20 can be prevented.

The insulating film 131 may be formed of an inorganic material such as SiOx or SiNx, but is not limited thereto. The metal film 133 may be one metal selected from the group consisting of Mo, Al, Cr, Au, Ti, Ni, and Cu, or an alloy thereof, and may be formed as a single layer or multiple layers.

The metal film 133 and the insulating film 131 may be sequentially patterned using the first photosensitive pattern 135 as a mask so that the drain electrode 33 of the thin film transistor may be exposed. And a pixel contact hole 35 may be formed in a region where the drain electrode 33 is exposed. At this time, the insulating layer 131 may be a third insulating layer 39.

The second and third insulating layers 14 and 39 corresponding to the gate lower electrode 19 and the data lower electrode 29 disposed in the non-display region can also be patterned. The gate contact hole 17 may be formed by patterning the second and third insulating layers 14 and 39 corresponding to the gate lower electrode 19. The data contact holes 27 may be formed by patterning the second and third insulating layers 14 and 39 corresponding to the data lower electrode 29. [

The metal film 133 and the insulating film 131 corresponding to a part of the common electrode 37 are patterned using the first photosensitive pattern 135 as a mask so that the jumping contact hole 49 can be formed. A part of the common electrode 37 can be exposed by the jumping contact hole 49. [

As shown in FIG. 6C, an ashing process may be performed so that the first photosensitive pattern 135 is patterned to form the second photosensitive pattern 137. FIG. The second photosensitive pattern 137 may be formed on the metal film 133 corresponding to the gate line 11. [

The metal film 133 is patterned using the second photosensitive pattern 137 as a mask so that the metal film 133 except the metal film 133 on the gate line 11 can be removed as shown in FIG. have. The metal film 133 left on the gate line 11 may be the common voltage line 47. [

All of the metal film 133 formed on the insulating film 131 corresponding to the non-display area can also be removed.

As described above, the drain electrode 33, the gate lower electrode 19, and the data lower electrode 29 may include the first to third conductive patterns 101, 103, and 105 shown in FIG. 3A . The third conductive pattern 105, which is the uppermost layer among the first through third conductive patterns 101, 103, and 105, may include ITO, but the present invention is not limited thereto.

 When the metal film 133 for forming the common electrode line 47 is patterned using the second photosensitive pattern 137 as a mask, the drain electrode 33, the gate lower electrode 19, Each of the second conductive patterns 103 may be corroded. The present invention can form a third conductive pattern 105 that prevents corrosion of a second conductive pattern 103 including, for example, ITO on a second conductive pattern 103 including Cu, The second conductive pattern 103 can be prevented from being corroded by the etching solution used when the metal film 133 is patterned by the pattern 105.

Further, in the present invention, the jumping contact hole 49 and the common electrode line 47 are simultaneously formed by the fourth mask process, so that the process can be simplified.

The fifth mask process

7 shows a fifth mask process for forming a pixel electrode and a connection electrode.

A conductive film 141 is formed on the third insulating layer 39 on the non-display region and the common voltage line 47 on the display region as shown in Fig. 7A, and a photosensitive film is formed on the conductive film 141 . The photosensitive film may be exposed using the exposure process to form the photosensitive pattern 143 on the metal film.

The conductive film 141 may be formed of a transparent conductive material such as ITO, but the present invention is not limited thereto.

The conductive film 141 may be patterned using the photosensitive pattern 143 as a mask so that the pixel electrode 45 and the connection electrode 50 may be formed.

A part of the pixel electrode 45 may contact the drain electrode 33 of the thin film transistor through the pixel contact hole 35. [

The pixel electrode 45 may include a plurality of pixel electrode bars 41 to 44. Each of the pixel electrode bars 41 to 44 may be spaced apart from each other.

A horizontal electric field and a vertical electric field can be generated between the plurality of pixel electrode bars 41 to 44 and the common electrode 37. The liquid crystal molecules are displaced more largely by the horizontal electric field and the vertical electric field, and can be more precisely controlled and the image quality can be improved.

The connection electrode 50 is in direct contact with the common electrode line 47 and can be in contact with the common electrode 37 through the jumping contact hole 49. [

The connection electrode 50 may be in contact with both the top surface and the side surface of the common electrode line 47.

The connection electrode 50 may be disposed adjacent to the pixel electrode 45.

In the present invention, since the pixel electrode 45 and the connection electrode 50 are formed simultaneously by the fifth mask process, the process can be simplified.

The foregoing detailed description should not be construed in all aspects as limiting and should be considered illustrative. The scope of the present invention should be determined by rational interpretation of the appended claims, and all changes within the scope of equivalents of the present invention are included in the scope of the present invention.

10: substrate 11: gate line
12: first insulating layer 13: gate electrode
14: second insulating layer 15: gate pad portion
16: planarization layer 17: gate contact hole
18: semiconductor layer 19: gate lower electrode
20: Align key 21: upper gate electrode
23: Data line 24: Source electrode
25: Data pad part 27: Data contact hole
29: data lower electrode 31: data upper electrode
33: drain electrode 35: pixel contact hole
37: common electrode 39: third insulating layer
41 to 44: pixel electrode bar 45: pixel electrode
47: common electrode line 49: jumping contact hole
50: connecting electrode

Claims (9)

Board;
A gate line on the substrate;
A data line crossing the gate line on the gate line;
A thin film transistor connected to the gate line and the data line;
A planarization layer disposed on the thin film transistor and including a first contact hole;
A common electrode on the planarization layer;
An insulating layer disposed on the common electrode and including a second contact hole;
A pixel electrode and a common electrode line on the insulating layer; And
And a connection electrode connected to the common electrode through the second contact hole on the common electrode line. The method according to claim 1,
Wherein the pixel electrode includes a plurality of pixel electrode bars and is connected to the thin film transistor through the first contact hole. The method according to claim 1,
Wherein the common electrode line is disposed on the gate line,
And the second contact hole is disposed adjacent to the common electrode line. The method according to claim 1,
A gate pad portion extending from the gate line; And
And a data pad portion extending from the data line. Forming a gate line, a gate electrode and an alignment key using a first mask process;
Forming a semiconductor layer, a data line, a source electrode, and a drain electrode on the gate line, the gate electrode, and the alignment key using a second mask process;
Forming a planarization layer having a first contact hole on the data line, a source electrode, and a drain electrode using a third mask process and a common electrode on the planarization layer;
Forming an insulating layer having a second contact hole on the common electrode and a common electrode line on the insulating layer using a fourth mask process; And
Forming a pixel electrode and a connection electrode using a fifth mask process,
The pixel electrode is connected to the drain electrode through the first contact hole,
Wherein the planarization layer is not formed on the alignment key. 6. The method of claim 5,
And the connection electrode is connected to the common electrode through the second contact hole on the common electrode line. 6. The method of claim 5,
Wherein the pixel electrode includes a plurality of pixel electrode bars. 6. The method of claim 5,
Forming a gate lower electrode together with the gate line;
Forming a data lower electrode together with the data line; And
Forming a gate upper electrode and a data upper electrode together with the pixel electrode,
The gate lower electrode and the gate upper electrode constitute a gate pad portion,
Wherein the data lower electrode and the data upper electrode constitute a data pad portion. 9. The method of claim 8,
Wherein the drain electrode, the gate lower electrode, and the data lower electrode each include a plurality of conductive patterns,
Wherein the first layer, which is the uppermost layer among the plurality of conductive patterns, comprises ITO, and the second layer disposed below the first layer comprises Cu.

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