KR20160078781A - Display device, gate signal sensing circuit and data driver - Google Patents

Abstract

The present invention provides a display device and a data driving part thereof. The display device includes a display panel which includes pixels arranged in the intersection point of date lines and gate lines, a data driving part which supplies data signals to the data lines, a gate driving part which supplies gate signals to the gate lines, a gate signal sensing circuit part which senses a gate signal, and a timing controller which matches the timing of a sensed gate signal and controls a data driving part to supply the data signals to the data lines. So, the driving timing of the data signal can be optimized.

Description

DISPLAY DEVICE AND GATE SIGNAL SENSING CIRCUIT AND DATA DRIVER [0002]

The present invention relates to a display device for displaying an image.

As the information technology is developed, the market of display devices, which is a connection medium between users and information, is getting larger. Accordingly, a liquid crystal display (LCD), an organic light emitting diode (OLED), an electrophoretic display (EPD), and a plasma display panel (PDP) ) Have been increasingly used.

Generally, a display device includes pixels arranged at a point where data lines and gate lines cross each other in a display panel, and supplies a data signal to data lines and a gate signal to gate lines.

However, the gate signal supplied to the gate lines has a time delay due to various reasons. The driving timing of the data signal supplied to the data lines is not matched with the time delay of the gate signal. Particularly, as the size of a display device becomes larger, a driving timing problem of a data signal due to a time delay of a gate signal lowers the luminance uniformity of the display panel, and the driving frequency is lowered in some cases.

According to an aspect of the present invention, there is provided a display device, a gate signal sensing circuit, and a data driver for optimizing a driving timing of a data signal by supplying a data signal in accordance with a gate signal.

In addition, the present invention provides a display device, a gate signal sensing circuit, and a data driver for improving luminance uniformity of a display panel and improving a driving frequency under various conditions such as a data driver including two or more data driver integrated circuits .

According to an aspect of the present invention, there is provided a display panel including pixels disposed at intersections of data lines and gate lines, a data driver for supplying data signals to data lines, A gate signal sensing circuit for sensing the gate signal, and a timing controller for controlling the data driver to supply a data signal to the data lines according to the timing of the sensed gate signal.

According to another aspect of the present invention, there is provided a liquid crystal display device including a sensing unit sensing a gate signal supplied to a gate line, a control unit positioned between the gate line and the sensing unit and controlling a sensing timing according to a control signal, And a pixel circuit section including the pixel circuit section.

According to still another aspect of the present invention, there is provided a liquid crystal display device including a digital-analog converter for converting a digital data signal for each pixel into an analog data signal, and an output circuit for supplying an analog data signal to the data lines in accordance with the timing of the sensed gate signal. Thereby providing a driving unit.

Since the present invention supplies the data signal in accordance with the gate signal, the driving timing of the data signal can be optimized.

In addition, the present invention has the effect of improving the luminance uniformity of the display panel and improving the driving frequency even under various conditions such that the data driver is composed of two or more data driving integrated circuits.

1 is a schematic system configuration diagram of a display apparatus according to an embodiment.
Figure 2a shows the time delay of the gate signal.
FIG. 2B shows a problem of inconsistency between the gate signal and the data signal in accordance with the time delay of the gate signal.
FIG. 3 shows waveforms of a gate signal and a data signal according to a gate driver including two or more gate drive integrated circuits located on both sides of the display panel of FIG.
4A and 4B show that the writing time of the data signal is short in both portions of the gate line compared to the writing time of the data signal in the central portion of the gate line in accordance with the mismatch between the gate signal and the data signal.
5 is a timing chart for numerically calculating a time delay of a gate signal when the data driver includes two or more data driver ICs (SDIC # 1 to SDIC # 12) and optimizing the data signal timing in units of the data driver IC .
FIG. 6 shows that a luminance level difference occurs between pixels between data driving integrated circuits.
7 is a schematic system configuration diagram of a display device according to another embodiment.
FIGS. 8A and 8B show gate signal sensing of the gate signal sensing circuit unit and driving timing of the data driver of FIG. 7, respectively.
9 is an exemplary view of a pixel structure of a display device according to the embodiments.
10 is a configuration diagram of a gate signal sensing circuit included in the gate signal sensing circuit unit in the display device according to the embodiments.
11 shows the components that influence the time delay of the gate signal of the gate line in the display panel.
12 is a schematic configuration diagram of the data driver of FIG.
13 is an example of the gate signal sensing circuit SC included in the gate signal sensing circuit portion of FIG.
Fig. 14A shows an example of the driving timing of the gate signal sensing circuit SC shown in Fig.
Fig. 14B shows another example of the drive timing of the gate signal sensing circuit SC shown in Fig.
FIG. 15 shows another example of the gate signal sensing circuit SC included in the gate signal sensing circuit portion of FIG.
16A shows an example of driving timing of the gate signal sensing circuit SC shown in Fig.
Fig. 16B shows another example of the driving timing of the gate signal sensing circuit SC of Fig.
FIGS. 17A and 17B show the luminance uniformity of the display panel and the driving frequency according to the position of the display panel in the display device according to the embodiment described with reference to FIGS. 1 to 6. FIG.
18A and 18B show the luminance uniformity of the display panel and the driving frequency according to the position of the display panel in the display device according to another embodiment described with reference to Figs. 7 to 16B.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In the drawings, like reference numerals are used to denote like elements throughout the drawings, even if they are shown on different drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

In describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are intended to distinguish the components from other components, and the terms do not limit the nature, order, order, or number of the components. When a component is described as being "connected", "coupled", or "connected" to another component, the component may be directly connected or connected to the other component, Quot; intervening "or that each component may be" connected, "" coupled, "or " connected" through other components.

1 is a schematic system configuration diagram of a display apparatus according to an embodiment. Figure 2a shows the time delay of the gate signal. FIG. 2B shows a problem of inconsistency between the gate signal and the data signal in accordance with the time delay of the gate signal. FIG. 3 shows waveforms of a gate signal and a data signal according to a gate driver including two or more gate drive integrated circuits located on both sides of the display panel of FIG.

1 and 3, a display device 100 according to an embodiment includes data lines DL1 to DLm and gate lines GL1 to GLn, data lines DL1 to DLm, And a display panel 140 in which pixels are arranged at each intersection of the gate lines GL1 to GLn. The display device 100 further includes a data driver 120 for supplying a data signal to the data lines DL1 to DLm, a gate driver 130 for supplying a gate signal to the gate lines GL1 to GLn, 120 and a timing controller 140 for supplying a control signal to the gate driver 130.

When the gate driver 130 sequentially supplies the gate signals to the gate lines in the display device 100, the data driver 120 supplies the data signals to the pixels connected to the gate lines, Pixels.

As shown in FIG. 2A, the gate signal sequentially supplied to the gate lines is divided into a resistance component of the gate line itself, a parasitic capacitor component in a region intersecting the data line, a gate electrode of the switching transistor, Due to the capacitor component, a time delay may occur while moving along the gate line.

3, the data driver 120 includes two or more data drive ICs (SDIC # 1 to SDIC # 12) and the gate driver 130 is disposed on both sides of the display panel 110 The display device 100 constituted by the gate drive integrated circuits GDIC * 1 to SDIC * 5 is driven from the gate drive integrated circuits GDIC * 1 to SDIC * 5 arranged on both sides for optimization of the drive timing of the data signal A data signal is supplied to the data line based on the gate signal of the central portion of each supplied gate line (for example, the pixels corresponding to the data line DLx in Fig. 3).

When the data signal DATA is supplied to the data line based on the gate signal SCAN at the center of the gate line as shown in FIG. 2B, the gate signal SCAN and the data A problem of inconsistency of the signal (DATA) may occur. Since the data signal DATA is supplied to the data line based on the gate signal SCAN at the center of the gate line, the gate signal SCAN and the data signal DATA are identical at the central portion of the gate line, The mismatch width between the gate signal and the data signal DATA may become larger as the gate driver 130 is closer to the gate driver 130.

As shown in FIG. 4A, as shown in FIG. 4B, the gate signal SCAN and the data signal DATA are applied to both sides of the gate line The writing time of the data signal DATA may be very short.

In order to solve the problem of inconsistency between the gate signal and the data signal due to the time delay of the gate signal, the time delay of the gate signal is numerically calculated to optimize the data signal timing so that the discrepancy between the gate signal and the data signal I try to solve the problem.

However, as shown in FIGS. 1 and 5, when the data driver 120 includes two or more data drive ICs (SDIC # 1 to SDIC # 12), the time delay of the gate signal is numerically calculated, Data signal timing optimization can be performed on an integrated circuit basis. The data signal timing optimization is performed on a data drive integrated circuit basis, so that the width of the data signals between the data driver ICs is smaller than the width of the data signals at other locations, A brightness step may occur.

Hereinafter, a display device according to another embodiment in which data signal timing is optimized without generating a luminance step between data driving integrated circuits will be described in detail with reference to the drawings.

7 is a schematic system configuration diagram of a display device according to another embodiment. FIGS. 8A and 8B show gate signal sensing of the gate signal sensing circuit unit and driving timing of the data driver of FIG. 7, respectively.

7, the display device 700 according to another embodiment includes a timing controller 740, a data driver 720, a gate driver 730 and a display panel 710, a gate signal sensing circuit 720, Sensing Circuit Unit, 750).

The timing controller 740 receives a digital data signal RGB from a system board in addition to a driving signal such as a data enable signal, a vertical synchronizing signal, a horizontal synchronizing signal, and a clock signal. The timing controller 740 outputs a gate timing control signal GDC for controlling the operation timing of the gate driver 730 and a data timing control signal DDC for controlling the operation timing of the data driver 720, . The timing controller 740 outputs the digital data signal DDATA in response to the gate timing control signal GDC and the data timing control signal DDC generated based on the driving signal.

The data driver 720 samples and latches the digital data signal DDATA in response to the data timing control signal DDC supplied from the timing controller 740 and converts the digital data signal DDATA into an analog data signal corresponding to the gamma reference voltage. The data driver 720 may include two or more data driver ICs (SDIC # 1 to SDIC # 12) as described with reference to FIG.

The gate driver 730 outputs a gate signal while shifting the level of the gate voltage in response to the gate timing control signal GDC supplied from the timing controller 740. The gate driver 730 outputs a gate signal through the gate lines GL1 to GLm. The gate driver 730 supplies gate signals to the gate lines GL1 to GLn extending to the display area AA and the gate lines GL0 arranged in the non-display area NAA.

The display panel 710 includes a display area (Active Area, AA) and a non-display area (NAA). The display panel 710 includes pixels arranged at the intersection of the data lines DL1 to GLn and the gate lines GL1 to GLm in the display area AA.

Each pixel P disposed in the display area AA has a red subpixel SPr, a green subpixel SPg, a blue subpixel SPb, and a red subpixel SPp in order to increase the light efficiency, And a white sub-pixel SPw (hereinafter abbreviated as RGBW sub-pixel). That is, one pixel P may include RGBW sub-pixels (SPr, SPg, SPb, SPw). The pixels P are formed in a number corresponding to the resolution of the display panel 710.

The gate signal sensing circuit portion 750 is disposed in the non-display area NAA of the display panel 710. Some of the components of the gate signal sensing circuit unit 750 may be disposed in the display panel 710, for example, the data driver 720 or the timing controller 740.

The gate signal sensing circuit unit 750 controls the number of pixels in the first column (e.g., the number of pixels in the first column) in the non-display area NAA between the data driver 720 and the pixels of the first column connected to the first gate line GL1 (M = 1 to m in FIG. 7) arranged in a row. The gate signal sensing circuits SCx (X = 1 to m) The m gate signal sensing circuits SCx (X = 1 to m) are arranged with the gate line GL0 separately from the gate lines GL1 to GLn extending to the display area AA, Signal. m gate signal sensing circuits SCx (X = 1 to m) are connected to m data lines, respectively. Each of the gate signal gate signal sensing circuits SCx (X = 1 to m) includes dummy pixels formed in the same process when the pixels included in the display panel 740 are formed in the non-display area NAA. Lt; / RTI >

The gate signal sensing circuit unit 750 senses the gate signal SCAN in the m gate signal sensing circuits SCx (X = 1 to m) as shown in FIG. 8A. The gate signal sensing circuit unit 750 supplies the gate signal SCAN sensed by the m gate signal sensing circuits SCx (X = 1 to m) to the timing controller 740.

The timing controller 740 controls the data driver 720 to supply the data signals DATA to the data lines in accordance with the gate signal SCAN sensed by the gate signal sensing circuit unit 750. The data driver 720 may supply the data signals DATA to the data lines in accordance with the timing of the gate signal SCAN sensed under the control of the timing controller 740.

For example, as shown in FIG. 8B, the timing controller 740 controls the gate signal SCAN supplied from the gate signal sensing circuit unit 750 so that a falling time of each gate signal SCAN causes a threshold value A timing control signal TCS is supplied to the data driver 720 so as to supply the data signal DATA at the timing of the gate signal SCAN so as to be the end point of the data signal at a time point corresponding to 0.5 V, for example.

The data driver 720 supplies the data signal DATA to the data lines in accordance with the timing of the gate signal SCAN sensed according to the timing control signal TCS of the timing controller 740. Therefore, as shown in FIGS. 8B and 8C, the data driver 720 applies the data signal DATA at a time point corresponding to the threshold of the gate signal SCAN sensed at the position corresponding to all the pixels of the gate line, So that the data signal DATA is supplied to the data lines.

In particular, as shown in FIGS. 8B and 8C, since the data signal DATA is applied in accordance with the sensed gate signal, the writing time of the data signal in all the pixels is substantially the same, thereby improving the luminance uniformity. 5 and 6, even if the data driver 720 includes two or more data driver ICs (SDIC # 1 to SDIC # 12), the time delay of the gate signal is calculated for each data driver IC The luminance uniformity of the entire display panel 710 is improved as compared with the case of applying the data signal in accordance with the gate signal. This will be described later with reference to Figs. 17A and 18A.

Fig. 9 is an exemplary view of the pixel structure of the display device 100 according to the embodiments.

9 shows an organic light emitting diode (OLED) and a 3T (Transistor) 1C (OLED) including one driving transistor DT, two switching transistors SW1 and SW2 and one storage capacitor Cst Capacitor) structure.

In each pixel, the driving transistor DT is connected to a driving voltage line DVL (Driving Voltage Line) for supplying a driving voltage EVDD to a first electrode (e.g., an anode electrode or a cathode electrode) of the organic light emitting diode OLED, And is connected between connection lines connected thereto.

The driving transistor DT is a driving transistor for driving the organic light emitting diode OLED and is controlled by the voltage of the first node N1 Thereby driving the organic light emitting diode OLED.

The first switching transistor SW1 is controlled by the gate signal SCAN supplied from the gate line GL and is connected between the first node N1 of the driving transistor DT and the data line DL.

The first switching transistor SW1 is also referred to as a switching transistor or a scan transistor and is controlled by a gate signal SCAN to drive a voltage (data voltage) supplied from the data line DL To the first node N1 of the transistor DT. Thus, the on-off of the driving transistor DT can be controlled.

A storage capacitor Cst connected between the first node N1 of the driving transistor DT and the second node N2 (for example, a source node or a drain node depending on the P / N type of the transistor) is disposed.

The storage capacitor Cst serves to maintain a constant voltage for one frame and is also referred to as a storage capacitor.

The second switching transistor SW2 is controlled by the gate signal SCAN and is connected to the second node N2 of the driving transistor DT and a reference voltage line RVL to which the reference voltage Vref is applied, Respectively.

With this second switching transistor SW2, the voltage of the second node N2 (e.g., a source node or a drain node) of the driving transistor DT can be adjusted.

Since the voltage of the second node N2 (e.g., a source node or a drain node) of the driving transistor DT can be sensed by the second switching transistor SW2, the second switching transistor SW2 ) Is also referred to as a sensing transistor.

One pixel is formed of a 3T (Capacitor) structure including two switching transistors SW1 and SW2, a driving transistor DR, a capacitor Cst and an organic light emitting diode (OLED). However, , 4T2C, 5T2C, and the like.

10 is a configuration diagram of a gate signal sensing circuit included in the gate signal sensing circuit unit 150 in the display device 100 according to the embodiments.

10, the gate signal sensing circuit SC includes a sensing portion 910 for sensing a gate signal supplied to the gate line GL, a control portion 910 located between the gate line GL and the sensing portion 910, A control unit 920 for controlling the sensing timing according to a control signal CS, and a pixel circuit unit 930 electrically connected to the gate line GL and including a pixel structure.

The control unit 920 and the pixel circuit unit 930 are disposed in the non-display area NAA of the display panel 710 and the sensing unit 910 is connected to the display panel 710, the data driver 720, the timing controller 740, And the like.

The pixel circuit portion 930 includes components that affect the time delay of the gate signal described with reference to FIGS. 2A to 5 in the pixel structure described with reference to FIG. The components affecting the time delay of the gate signal are the resistance component R of the gate line GL itself or the resistance component R of the data line DL and the gate line GL as shown in FIG. A parasitic capacitor component (parasitic Cap), and (3) a TFT capacitor component (TFT Cap) between the gate electrode of the switching transistor SW and the source / drain electrodes. Accordingly, the pixel circuit portion 930 may include a first switching transistor SW1, a second switching transistor SW2, and a storage capacitor Cst that affect the time delay of the gate signal in the pixel structure of FIG.

 The control signal applied to the controller 920 may be one of a sensing control signal or a data signal.

12 is a schematic configuration diagram of the data driver of FIG.

12, the data driver 720 includes a shift register unit 721, a latch unit 722, a gamma voltage generator 724, a digital-to-analog converter (hereinafter referred to as DA converter 723) And an output circuit portion 725 are included.

A source sampling clock (SSC), a source output enable signal (Source Output Enable, SOE), and the like are input to the data timing control signal DDC output from the timing controller 740. [ ) And the like. The source start pulse SSP controls the data sampling start timing of the data driver 720. The source sampling clock SSC is a clock signal for controlling the sampling operation of data in the data driver 720 based on the rising or falling edge. The source output enable signal SOE controls the output of the data driver 720.

The shift register unit 721 outputs a sampling signal SAM in response to the source start pulse SSP and the source sampling clock SSC output from the timing controller 740.

The latch unit 722 sequentially samples the digital data signal DDATA in response to the sampling signal SAM output from the shift register unit 721 and outputs the sampled data in response to the source output enable signal SOE And simultaneously outputs sampled color data signals DDATA for one line. The latch portion 722 may be composed of at least two latches, but only one of the latches 722 has been shown and described for convenience of explanation.

The gamma voltage generator 724 generates first to n-th gamma gradation voltages GMA1 to GMAn corresponding to voltages or signals supplied from the outside or the inside.

The DA converter 723 converts the color data signal DDATA for one line in accordance with the first to the n-th gamma gradation voltages GMA1 to GMAn output from the gamma voltage generator 724 into analog color data signals (ADATA).

The output circuit unit 725 amplifies (or amplifies and compensates) the analog color data signal ADATA output from the DA converter 723 and outputs the amplified and amplified color data signal ADATA to each data line. The output circuit 725 supplies the data signals to the data lines in accordance with the timing of the gate signal sensed according to the timing control signal (TCS) of the timing controller 740.

The output circuit portion 725 supplies the data signal to the data line so that the data signal becomes the end point of the data signal at a time point corresponding to the threshold value of the sensed gate signal, as shown in Figs. 8B and 8C.

FIG. 13 is an example of a gate signal sensing circuit SC included in the gate signal sensing circuit portion 750 of FIG. Fig. 14A shows an example of the driving timing of the gate signal sensing circuit SC shown in Fig. Fig. 14B shows another example of the drive timing of the gate signal sensing circuit SC shown in Fig.

9 and 13, the gate signal sensing circuit SC is disposed between the analog digital converter ADC, the gate line GL, and the ADC, which is the sensing unit 910, and outputs a control signal CS And a control transistor CT for controlling the sensing timing. The control transistor CT may be smaller in size than the driving transistor DT of the pixel included in the display panel 740. [ The control transistor CT is the same as the batch driving transistor DT. However, unlike the case where the driving transistor DT drives the organic light emitting diode OLED in the pixel, the control transistor CT does not need to be as large as the driving transistor DT of the pixel since it transmits only the gate signal of the gate line to the ADC . On the other hand, the control signal applied to the control transistor CT is a sensing control signal (Ctrl). Therefore, a control line CL for applying a sensing control signal Ctrl to the gate signal sensing circuit SC is separately required.

7, the gate signal sensing circuit SC is electrically connected to the gate line GL ₀ arranged in the non-display area NAA, and is connected to the pixel circuit part 930 including the pixel structure, A first switching transistor SW1 located between the data line DL and the capacitor C and a second switching transistor SW2 located between the reference voltage line RVR and the capacitor c do. The gates of the first switching transistor SW1 and the second switching transistor SW2 are connected to the gate line, respectively.

The first switching transistor SW1 located between the capacitor C and the data line DL and the capacitor C by the pixel circuit portion 930 and the second switching transistor SW2 located between the reference voltage line RVL and the capacitor C, The switching transistor SW2 has the same structure and the same manufacturing process as the first switching transistor SW1, the second switching transistor SW2, and the storage capacitor Cst that affect the time delay of the gate signal in the pixel structure of FIG. It is an implementation.

The operation of the gate signal sensing circuit SC will now be described with reference to Figs. 13 and 14A.

The data voltage applied through the data line DL and the reference voltage Vref applied through the reference voltage line RVL are maintained in a constant state and the voltage is applied through the control line CL connected to the gate of the control transistor CT The sensing control signal (Ctrl) is applied for a predetermined time. And applies the two gate signals through the gate line GL ₀ during the time that the sensing control signal Ctrl is applied. Therefore, the time during which the sensing control signal Ctrl is applied to the control transistor CT is greater than the time during which the two gate signals are applied. In addition, the ADC senses the two gate signals, respectively, and provides the sensed gate signal to the timing controller 740.

The timing controller 740 selects the second provided gate signal as a gate signal applied to the gate line GL ₀ and supplies a data signal to each data line in accordance with the gate signal as described with reference to FIGS. 8B and 8C . In order to apply the second gate signals and supply the data signals to the respective data lines in accordance with the second gate signals, the first gate signals are supplied to the capacitors C by turning on the first switching transistors SW1 and the second switching transistors SW2, (Voltage applied to Vg) and reference voltage (voltage applied to Vs). That is, to prevent unnecessary components from being stored in the capacitor C due to noise or other components other than the gate signal.

However, since noise or other components other than the gate signal are less effective, there is no problem in sensing the gate signal. Therefore, one gate signal is applied at the time when the control signal is applied to the control transistor CT as shown in FIG. 14B Time and the ADC may sense only one gate signal and provide it to the timing controller 740. [

FIG. 15 shows another example of the gate signal sensing circuit SC included in the gate signal sensing circuit portion 750 of FIG. 16A shows an example of driving timing of the gate signal sensing circuit SC shown in Fig. Fig. 16B shows another example of the driving timing of the gate signal sensing circuit SC of Fig.

9 and 15, the gate signal sensing circuit SC is disposed between the analog digital converter ADC, the gate line GL, and the ADC 910, which is a sensing unit 910, and includes a control signal, CS in that it includes a control transistor CT for controlling the sensing timing in accordance with the gate signal CS. The control signal applied to the control transistor CT is the data voltage DATA. Therefore, a control line for applying a control signal to the gate signal sensing circuit SC is not required separately.

 The operation of the gate signal sensing circuit SC will now be described with reference to Figs. 15 and 16A.

The reference voltage Vref applied through the reference voltage line RVL is kept constant and the data voltage DATA is applied for a predetermined time through the data line DL connected to the gate of the control transistor CT And applies the two gate signals through the gate line for a period of time during which the voltage (DATA) is applied. Therefore, the time during which the data voltage DATA is applied as the control signal to the control transistor CT is greater than the time during which the two gate signals are applied. In addition, the ADC senses the two gate signals, respectively, and provides the sensed gate signal to the timing controller 740.

The timing controller 740 selects the second supplied gate signal as the gate signal applied to the gate line as described above with reference to FIGS. 13 and 14A.

16B, the time during which the data voltage DATA is applied to the control transistor CT is set to be larger than the time during which one gate signal is applied, and the ADC senses only one gate signal and provides it to the timing controller 740 Is the same as that described with reference to Fig. 14 (b).

The display device 700 according to another embodiment described with reference to FIGS. 7 to 16B may sense the gate signals for each pixel and supply the data signals to the data lines in accordance with the sensed gate signals, so that the driving timing is optimized . In contrast to the display device 100 according to the embodiment described with reference to Figs. 1 to 6, the display device 700 according to another embodiment described with reference to Figs. 7 to 16B may improve the luminance uniformity and the driving frequency .

FIGS. 17A and 17B show the luminance uniformity of the display panel 110 and the driving frequencies of the display panel in the display device 100 according to the embodiment described with reference to FIGS. 1 to 6. FIG. 18A and 18B show the luminance uniformity of the display panel 110 and the driving frequency according to the position of the display panel in the display device 700 according to another embodiment described with reference to FIGS. 7 to 16B.

As shown in FIG. 17A, the luminance uniformity of the display panel 110 in the display device 100 according to one embodiment is 72.4% (minimum value / maximum value of luminance in the display panel) based on 255 gray On the other hand, as shown in FIG. 18A, the luminance uniformity of the display panel 110 in the display device 700 according to another embodiment is 83.6% based on 255 gray.

17B, in the display device 100 according to one embodiment and the display device 700 according to another embodiment as shown in FIG. 18B, a driving frequency is set at a central portion of each of the display panels 110 and 710 The driving frequency of the sixth pixel on the left in the horizontal direction is 140 Hz in the case of the display device 100 according to one embodiment, whereas the driving frequency is improved to 177 Hz in the case of the display device 700 according to another embodiment, . Similarly, the driving frequencies of the sixth and seventh columns of the display panel 110 and 710 are the same, while the driving frequency of the sixth pixel on the left in the horizontal direction is 134 Hz in the case of the display device 100 according to one embodiment, In the case of the display device 700 according to the embodiment, it can be confirmed that the driving frequency is improved at 170 Hz.

According to the embodiments described above, since the data signal is supplied in accordance with the gate signal, the driving timing of the data signal can be optimized.

Also, according to some of the above-described embodiments, the luminance uniformity of the display panel can be improved and the driving frequency can be improved even under various conditions such that the data driver is composed of two or more data driving integrated circuits.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the following claims rather than the detailed description. Also, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

110, 710: display panel
120, 720:
130, 730: Gate driver
140, 740: Timing controller
724: DA conversion section
725: Output circuit part
750: Gate signal sensing circuit part
SC: gate signal sensing circuit

Claims (17)

A display panel including pixels arranged at a point where data lines and gate lines intersect;
A data driver for supplying a data signal to the data lines;
A gate driver for supplying a gate signal to the gate lines;
A gate signal sensing circuit for sensing the gate signal; And
And a timing controller for controlling the data driver to supply the data signal to the data lines according to the timing of the sensed gate signal. The method according to claim 1,
Wherein the data driver supplies the data signal according to a timing of the gate signal so as to be an end point of the data signal at a time point corresponding to a threshold value in a falling time of the sensed gate signal. . The method according to claim 1,
And the gate signal sensing circuit part is located in a non-display area of the display panel. The method of claim 3,
Wherein the gate signal sensing circuitry comprises at least two gate signal sensing circuits,
Each gate signal sensing circuit comprises:
A sensing unit sensing a gate signal supplied to the gate line;
A control unit which is located between the gate line and the sensing unit and controls sensing timing according to a control signal; And
And a pixel circuit portion electrically connected to the gate line and including a pixel structure. 5. The method of claim 4,
Wherein the pixel structure is the same as a part of pixels included in the display panel. 5. The method of claim 4,
The pixel structure includes:
A capacitor;
A first switching transistor positioned between the data line and the capacitor;
And a second switching transistor positioned between the reference voltage line and the capacitor,
And the gates of the first switching transistor and the second switching transistor are connected to the gate line. The method according to claim 6,
The control unit is a control transistor,
Wherein the control transistor is smaller in size than the driving transistor of the pixel included in the display panel. The method of claim 3,
Wherein the control signal applied to the control unit is one of a sensing control signal and a data signal. 5. The method of claim 4,
The control signal applied to the control unit is greater than the time during which the two gate signals are applied,
And the sensing unit senses the two gate signals, respectively. A sensing unit sensing a gate signal supplied to the gate line;
A control unit which is located between the gate line and the sensing unit and controls sensing timing according to a control signal; And
And a pixel circuit portion that is electrically connected to the gate line and includes a pixel structure. 11. The method of claim 10,
Wherein the pixel structure is the same as a part of pixels included in the display panel. 11. The method of claim 10,
The pixel circuit section includes:
A capacitor;
A first switching transistor positioned between the data line and the capacitor;
And a second switching transistor positioned between the reference voltage line and the capacitor,
And the gates of the first switching transistor and the second switching transistor are connected to the gate line. 13. The method of claim 12,
The control unit is a control transistor,
Wherein the control transistor is smaller in size than a driving transistor of a pixel included in the display panel. 11. The method of claim 10,
Wherein the control signal applied to the control unit is one of a sensing control signal and a data signal. 12. The method of claim 11,
The control signal applied to the control unit is greater than the time during which the two gate signals are applied,
And the sensing unit senses the two gate signals, respectively. A digital-analog converter for converting the digital data signal for each pixel into an analog data signal; And
And an output circuit for supplying the analog data signal to the data lines according to the timing of the sensed gate signal. 17. The method of claim 16,
Wherein the output circuit part supplies the data signal according to a timing of the gate signal so as to be an end point of the data signal at a time point corresponding to a threshold value in a falling time of the sensed gate signal.

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