KR20160068257A - routable QFN semiconductor package and method thereof - Google Patents

routable QFN semiconductor package and method thereof Download PDF

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Publication number
KR20160068257A
KR20160068257A KR1020140173714A KR20140173714A KR20160068257A KR 20160068257 A KR20160068257 A KR 20160068257A KR 1020140173714 A KR1020140173714 A KR 1020140173714A KR 20140173714 A KR20140173714 A KR 20140173714A KR 20160068257 A KR20160068257 A KR 20160068257A
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KR
South Korea
Prior art keywords
insulating space
lead
die pad
upper insulating
semiconductor chip
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KR1020140173714A
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Korean (ko)
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KR101631558B1 (en
Inventor
천정환
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주식회사 에스에프에이반도체
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Priority to KR1020140173714A priority Critical patent/KR101631558B1/en
Publication of KR20160068257A publication Critical patent/KR20160068257A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/122—Polycrystalline

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

Disclosed is a routable quad flat no-leads (QFN) package, capable of minimizing strip warpage of the package. The routable QFN package includes a lead frame and a molding member. The lead frame includes: a die pad provided thereon with a semiconductor chip; an inner lead which is electrically connected with the semiconductor chip by a conductive wire and insulated from the die pad by a first insulation space; and an outer lead insulated from the inner lead by a second insulation space. The molding member seals off the semiconductor chip, and the first and second insulation spaces. Each of the first and second insulation spaces consists of a top insulation space and a bottom insulation space. The bottom insulation space, on the bottom surface of the lead frame, extends to a width greater than that of the top insulation space.

Description

A routable QFN package and method therefor,

The present invention relates to a QFN package and a manufacturing method thereof, and more particularly, to a QFN package capable of minimizing strip warpage and a manufacturing method thereof.

In recent years, electronic products such as personal computers, cellular phones, and camcorders have been pursuing downsizing of their products while seeking to increase the capacity of internal processing. As a result, even in the semiconductor package, a semiconductor package of a small size, large capacity, and high processing speed is desperately required.

Accordingly, the direction of development of the semiconductor package is a surface mount type quad flat non-lead (QFN), a thin small out-line package (TSOP), a TQFP Thin Quad Flat Package) and BGA (Ball Grid Array).

Among the surface mount type packages, the QFN package is a semiconductor package which is attracting attention because it can remarkably reduce the size and weight of the semiconductor package while achieving high quality and reliability while using a lead frame as a general semiconductor package.

Meanwhile, as shown in FIG. 1, the upper and lower surfaces of the lead frame 10 are half-etched according to a predetermined pattern.

Next, as shown in FIG. 2, a resin 12 such as PSR (Photo Sensitive Resist) is pre-molded on the half-etched portion of the lower surface of the lead frame 10 , Thereby forming the structure of the substrate.

When the structure of the lead frame is formed, as shown in FIG. 3, half-etching is performed on the half-etched portion of the upper surface to form an empty space 14 for insulation.

Next, the semiconductor chip 16 is attached to the upper surface of the lead frame 10, the semiconductor chip 16 and the land portion 18 are connected to each other by wire bonding with a bonding wire 153, Molding with a molding material such as an insulation material such as an epoxy (Epoxy Molding Compound), the manufacturing process of the conventional QFN package is completed.

However, in the conventional QFN package manufactured according to the above-described manufacturing process, when the pre-molding is performed with a resin such as PSR, the difference in the coefficient of thermal expansion (CTE) Warpage occurs in the package, which causes defects such as cracks in the package, thereby deteriorating the mass productivity.

In addition, since the conventional QFN package is molded only on the upper portion of the lead frame 10, there is a limit in performing the lead locking function.

In addition, since the conventional QFN package performs half-etching, the etching quality is degraded.

Accordingly, an object of the present invention is to provide a package structure capable of preventing warpage in a package due to a difference in thermal expansion coefficient between dissimilar materials (for example, PSR and EMC) during pre-molding, maximizing the role of EMC locking, The present invention provides a routerable QFN package and a method of manufacturing the same that can improve etching quality by performing full etching instead of half etching at the same time.

According to an aspect of the present invention, there is provided a router QFN semiconductor package including: a die pad to which a semiconductor chip is attached; a die pad electrically connected to the semiconductor chip by a conductive wire, A lead frame including an inner lead insulated from the pad and an outer lead insulated from the inner lead by a second insulation space, and a molding member sealing the semiconductor chip, the conductive wire, and the first and second insulation spaces do. Each of the first and second insulating spaces may include an upper insulating space and a lower insulating space extending on a lower surface of the lead frame to a width greater than the width of the upper insulating space.

According to another aspect of the present invention, there is provided a method of manufacturing a router QFN package, including the steps of forming a lead frame on a photosensitive film, forming a top insulating space through the lead frame, A step of patterning the inner lead and the outer lead on the photosensitive film, and exposing and developing the photosensitive film exposed by the upper insulating space to form a lower insulating space extending to a width larger than the width of the upper insulating space A step of attaching a semiconductor chip to the die pad and electrically connecting the semiconductor chip to the inner lead and the outer lead with a conductive wire; and a step of electrically connecting the semiconductor chip, the conductive wire, Sealing the lower insulating space with a molding resin, removing the photosensitive film W, and a step and forming a solder ball on the lower surface of the exposed inner lead and outer lead for exposing the lower surface of the inner lead and the outer lead the die pad.

According to the present invention, it is possible to prevent a package from being warped due to a difference in CTE between different materials during pre-molding, realize locking of a lead frame by EMC, Full etching can be performed to improve the etching quality.

Figs. 1 to 4 are process flow diagrams illustrating a method of manufacturing a conventional QPN package.
5 is a cross-sectional view of a routerable QFN package fabricated by a method according to an embodiment of the present invention.
6 to 14 are cross-sectional views illustrating a process sequence of a router QFN package according to an embodiment of the present invention.

The embodiments of the present invention are described in order to more fully explain the present invention to those skilled in the art, and the following embodiments may be modified into various other forms, It is not limited to the embodiment. Rather, these embodiments are provided so that this disclosure will be more thorough and complete, and will fully convey the concept of the invention to those skilled in the art. In the drawings, the thickness and size of each layer are exaggerated for convenience and clarity of explanation.

It is to be understood that throughout the specification, when an element such as a film, an area, or a substrate is referred to as being "on", "connected to", or "coupled to" another element, May be interpreted as being "on", "connected", or "coupled" to another element, or there may be other elements intervening therebetween.

On the other hand, when one element is referred to as being "directly on", "directly connected", or "directly coupled" to another element, it is interpreted that there are no other components intervening therebetween do.

Like numbers refer to like elements. As used herein, the term "and / or" includes any and all combinations of one or more of the listed items.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

As used herein, the singular forms "a," "an," and "the" include singular forms unless the context clearly dictates otherwise. Also, " comprise "and / or" comprising "when used herein should be interpreted as specifying the presence of stated shapes, numbers, steps, operations, elements, elements, and / And does not preclude the presence or addition of one or more other features, integers, operations, elements, elements, and / or groups.

Hereinafter, embodiments of the present invention will be described with reference to the drawings schematically showing ideal embodiments of the present invention.

5 is a cross-sectional view of a routable QFN package made in accordance with one embodiment of the present invention.

5, a router QFN package 100 according to an embodiment of the present invention includes a die pad 112, an inner lead 114, and an outer lead 114 to which a semiconductor chip 140 is attached according to a predetermined pattern. A lead frame 110 patterned with an outer lead 116 and a molding 110 for locking the lead frame 110 so as to seal the upper portion of the lead frame 110 as well as the lower portion of the lead frame 110 Resin (160, Epoxy Molding Compound)).

According to an embodiment of the present invention, the locking structure of the lead frame 110 by the molding resin 160 prevents warpage of the package, thereby improving the reliability and mass productivity of the package. .

Such a locking structure is made possible by filling the insulating space IS formed in the process of patterning the lead frame 110 with the molding resin 160. The insulating space IS includes a first insulating space IS1, 2 insulation space (IS2).

The die pad 112 and the inner lead 114 are insulated by the first insulation space IS1 and the inner lead 114 and the outer lead 116 are insulated from the second insulation space IS2.

Each of the first and second insulating spaces IS1 and IS2 includes an upper insulating space TS and a lower insulating layer TS extending from the lower portion of the lead frame 110 to a width greater than the width of the upper insulating space TS. And an insulating space (BS).

Since the conventional QPN package is filled only in the empty space 14 in which the molding resin 20 is partially formed in the lead frame 10 and the upper portion of the lead frame 10 as shown in Fig. There is a limit in locking.

However, in one embodiment of the present invention, the molding resin 160 is formed to have a larger width than the upper insulating space TS in the upper insulating space TS penetrating the lead frame 110 as well as the upper portion of the lead frame 110 The molding resin 160 locks the lead frame 110 to the lower insulating space BS.

The router QFN package 100 according to an exemplary embodiment of the present invention includes a heat spread 160 formed on the bottom surface of the die pad 112 to maximize heat dissipation, Heat Spread).

First of all, the heat spread 160 is formed on the bottom surface of the die pad 112 without increasing the overall height of the package. This will be described below. A space for forming the heat spread 160 on the bottom surface of the die pad 112 is secured.

6 to 14 are cross-sectional views illustrating a manufacturing process of a router QFN package according to an embodiment of the present invention.

6, the process of preparing the metal frame 110 and the photosensitive film 120 and forming the prepared metal frame 110 on the photosensitive film is performed. For example, the photosensitive film 120 is coated over the entire lower surface of the lead frame 110. In this case, a dry film resist (DFR) or a liquid resist may be used as the photosensitive film, There is no particular limitation on the material of the resist material used for assembling the semiconductor package.

Next, as shown in Fig. 7, a lead frame patterned with a die pad 112, an inner lead 114, and an outer lead 116 is formed on the photosensitive film 120. Then, as shown in Fig. A full etching process may be performed according to a predetermined pattern to form an upper insulating space TS penetrating the metal frame 110 by the full etching process, The inner leads 114 and the outer leads 116 are formed on the photosensitive film 120. The insulating film 114 is formed on the insulating film 120,

In the conventional manufacturing process of the routerable QFN package, as described above, the half etching process for the pre-molding is performed, so that the mass productivity is lowered due to the deterioration of the etching quality due to the half etching.

In contrast, in the manufacturing process of the QFN package according to the embodiment of the present invention, since the half etching process is performed through the metal frame 110 for molding, it is possible to prevent deterioration of the etching quality due to the half etching Thus, the mass productivity can be increased.

Next, as shown in Fig. 8, the process of attaching the tape 130 to the back surface of the photosensitive film proceeds.

9, the photosensitive film 120 exposed by the upper insulating space TS is exposed and developed to expose the upper insulating space TS, ). At this time, the process of exposing and developing the photosensitive film 120 of the exposed portion is performed so that the lower insulating space BS extends to a width larger than the width of the upper insulating space TS.

The lower insulation space BS formed by the exposure and development process exposes a lower surface of the lead frame, that is, a part of the lower surface of the die pad 112, the inner lead 114, and the outer lead 116 . This can be viewed as an undercut area.

As described above, the upper insulating space TS passing through the metal frame 110 and the lower insulating space BS extending more than the width of the upper insulating space TS are made of a molding resin capable of locking the lead frame And serves as a filling space.

10, a semiconductor chip 140 is attached on the die pad 112, and the semiconductor chip 140 is electrically connected to the inner leads and the outer leads by the conductive wires 144 A wire bonding process is performed.

11, the semiconductor chip 140, the conductive wire 144, the upper insulating space TS and the lower insulating space BS are covered with a molding resin 160 (EMC: Epoxy Molding compound is sealed.

According to this molding process, when the molding resin 160 is filled in the lower insulating space BS extending in a width larger than the width of the upper insulating space TS on the lower surface of the lead frame and hardened, By forming the structure in which the lead frame 160 locks the lead frame, warping of the package can be prevented.

Next, as shown in Fig. 12, the tape 130 is removed, and the partially remaining photosensitive film 120a is exposed. The exposed photosensitive film 120a is peeled off.

Next, as shown in FIG. 13, a process of forming solder balls 150 on the lower surfaces of the inner leads and the outer leads exposed by the peeled photosensitive film 120a is performed. At this time, the space 60 is secured also on the lower surface of the die pad 112 during the peeling of the photosensitive book sheet 120a. As shown in FIG. 14, The process of attaching the heat spread 170 for the heat spread 170 is performed.

As described above, in the manufacturing process according to the embodiment of the present invention, the space 60 on the lower side of the die pad 112 in the process of removing the photosensitive film and the tape used for forming the upper and lower insulation spaces .

The heat spread 170 can be formed on the bottom surface of the die pad 112 without increasing the overall height of the package by utilizing the reserved space 60 as a space for attaching the heat spread 160. [ .

14, when the process of forming the heat spread 160 on the bottom surface of the die pad 112 is completed, a singulation process for separating into the individual QFN packages is performed .

As described above, in one embodiment of the present invention, by molding the insulation space to be formed with a structure capable of locking the lead frame without using a pre-mold, using a molding resin such as EMC, The occurrence of warpage of the package can be minimized.

In addition, as in the conventional and manufacturing processes, full etching is performed without performing a half-etching process, so that etching quality and mass productivity can be ensured.

In addition, since the heat sprayer 170 for increasing the heat release effect is formed by utilizing the space secured in the process of removing the photosensitive film, the total height of the package must be considered in designing the heat sprayer There are no restrictions.

Claims (7)

An inner lead which is electrically connected to the semiconductor chip by a conductive wire and which is insulated from the die pad by a first insulating space and an outer lead which is insulated from the inner lead by a second insulating space, A lead frame including a lead; And
And a molding member sealing the semiconductor chip, the conductive wire, and the first and second insulation spaces,
Wherein each of the first and second insulating spaces is formed by:
An upper insulating space and a lower insulating space extending on the lower surface of the lead frame to a width greater than the width of the upper insulating space.
2. The router QFN package of claim 1, wherein the upper insulating space is formed by a full etching process.
2. The router QFN package according to claim 1, wherein the lower insulating space is formed by an exposure / development process using a dry film resist (DFR) film.
The heat spreader of claim 1, further comprising: a heat spread attached on a lower surface of the die pad; And
A solder ball formed on a lower surface of the inner lead and the outer lead,
Further comprising the step of:
Forming a lead frame on the photosensitive film;
Forming an upper insulating space penetrating the lead frame to pattern the die pad, the inner lead, and the outer lead insulated by the upper insulating space on the photosensitive film;
Exposing and developing the photosensitive film exposed by the upper insulating space to form a lower insulating space which expands to a width larger than the width of the upper insulating space;
Attaching a semiconductor chip to the die pad, and electrically connecting the semiconductor chip to the inner lead and the outer lead with a conductive wire;
Sealing the semiconductor chip, the conductive wire, and the upper insulating space and the lower insulating space with a molding resin;
Removing the photosensitive film to expose the lower surface of the die pad, the inner lead, and the outer lead; And
Forming a solder ball on the exposed lower surface of the inner lead and the outer lead;
Lt; RTI ID = 0.0 > QFN < / RTI > package.
6. The method of claim 5, further comprising forming a heat spread on a lower surface of the exposed die pad.
6. The method of claim 5, wherein patterning the die pad, the inner lead, and the outer lead on the photosensitive film comprises:
And performing a full etching process to form the upper insulating space. ≪ RTI ID = 0.0 > 11. < / RTI >
KR1020140173714A 2014-12-05 2014-12-05 routable QFN semiconductor package and method thereof KR101631558B1 (en)

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KR101631558B1 KR101631558B1 (en) 2016-06-24

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20080058491A (en) * 2005-11-16 2008-06-25 오키 엘렉트릭 인더스트리 캄파티,리미티드 Double-faced electrode package, and its manufacturing method
KR20100127925A (en) * 2009-05-27 2010-12-07 엘지이노텍 주식회사 Leadframe and method of manufacturig semiconductor chip package using the same
KR20120005171A (en) * 2010-07-08 2012-01-16 엘지이노텍 주식회사 Manufacturing method for chip package and chip package produced by the method
US20140353809A1 (en) * 2013-05-29 2014-12-04 Renesas Electronics Corporation Semiconductor device and manufacturing method of semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20080058491A (en) * 2005-11-16 2008-06-25 오키 엘렉트릭 인더스트리 캄파티,리미티드 Double-faced electrode package, and its manufacturing method
KR20100127925A (en) * 2009-05-27 2010-12-07 엘지이노텍 주식회사 Leadframe and method of manufacturig semiconductor chip package using the same
KR20120005171A (en) * 2010-07-08 2012-01-16 엘지이노텍 주식회사 Manufacturing method for chip package and chip package produced by the method
US20140353809A1 (en) * 2013-05-29 2014-12-04 Renesas Electronics Corporation Semiconductor device and manufacturing method of semiconductor device

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