CN102254880B - Chip packaging device and manufacturing method thereof - Google Patents
Chip packaging device and manufacturing method thereof Download PDFInfo
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- CN102254880B CN102254880B CN201010190234.9A CN201010190234A CN102254880B CN 102254880 B CN102254880 B CN 102254880B CN 201010190234 A CN201010190234 A CN 201010190234A CN 102254880 B CN102254880 B CN 102254880B
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- chip
- covering
- heat sink
- adhesion layer
- carrier
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 title claims description 20
- 238000000034 method Methods 0.000 claims description 28
- 239000000853 adhesive Substances 0.000 claims description 20
- 230000001070 adhesive effect Effects 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 239000003292 glue Substances 0.000 claims description 2
- 239000000084 colloidal system Substances 0.000 abstract description 4
- 238000007789 sealing Methods 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 description 15
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 7
- 238000005520 cutting process Methods 0.000 description 7
- 239000000758 substrate Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 229920000297 Rayon Polymers 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000000839 emulsion Substances 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012856 packing Methods 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008034 disappearance Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The invention discloses a chip packaging device which comprises a carrier provided with a chip junction zone and at least one electric contact, a chip with an active face and a passive face, at least one lead, a bonding layer, a heat-radiating member and a packaging colloid, wherein the chip is arranged on the chip junction region of the carrier in a manner that the passive face faces the carrier. The active face of the chip comprises at least one bonding pad, and the lead is connected with the at least one bonding pad and the at least one electric contact correspondingly. The bonding layer covers the active face of the chip and wraps a part extending on the bonding pad in the lead. The heat-radiating member is fixed on the bonding layer and covers the chip. The packaging colloid is used for sealing the chip, the bonding layer and the circumferential side of the heat-radiating member, and a concave opening is formed on the packaging colloid for exposing the surface of the heat-radiating member.
Description
Technical field
The present invention is about a kind of chip packaging device and manufacture method thereof.
Background technology
Generally speaking, semiconductor packages refers to semiconductor crystal grain with a packaging body coats, and provide electric contact outward at packaging body, to connect external device (ED) or circuit, and ball grid array structure packing technique (Ball gridarray (BGA) package technology) is wherein usually used in the semiconductor grain of structure dress high density and high pin number.In a traditional BGA encapsulates, semiconductor grain is positioned on circuit substrate, and semiconductor grain overlaps (wire bond) to circuit substrate with conductor leading, and packaging body is by semiconductor grain and conducting wire cladding.The spherical back side that is formed in circuit substrate of tin, to be electrically connected external device (ED) and semiconductor grain.
When the circuit on semiconductor grain operates, semiconductor grain can produce heat.And in traditional BGA encapsulation, semiconductor grain is coated for not transcalent packaging body, therefore the heat of semiconductor grain generation is difficult for dispersing.
Separately, some BGA is encapsulated in package interior fin is set, and the phase is to promote the heat radiation of semiconductor grain.Yet because the packaging body capacity of heat transmission is poor, and fin is coated by packaging body, thereby makes its integral heat sink effect improved limited.
In addition, United States Patent (USP) the 6th, discloses a kind of encapsulating structure 458, No. 626, and it is surface exposed by heat sink, uses raising radiating efficiency.This encapsulating structure is coated after interface layer/heat sink and semiconductor chip completely with packing colloid, cuts.After cutting, utilize interface layer that the potting compound of heat sink top is removed, can expose heat sink.Yet the method that this patent discloses is complicated, and when carrying out cutting step, because cutting tool needs the heat sink of cutting metal system, and easy loss cutting tool.Moreover it is smooth that metal heat sink is difficult for cutting, causes product quality not good.
Because aforementioned existing semiconductor package is loaded onto the disappearance of heat radiation, therefore need a kind of new semiconductor heat-dissipating design.
Summary of the invention
An object of the present invention provides a kind of chip packaging device and manufacture method thereof.Chip packaging device comprises a heat sink, and heat sink can fully be exposed to outside the encapsulation of chip packaging device, makes the radiating efficiency that chip packaging device tool is good.And the manufacture method of a kind of chip packaging device that the present invention discloses can easily produce the encapsulating structure that heat sink is exposed, heat sink need not be cut after encapsulation, therefore technique is simple, yield is high.
According to above-mentioned purpose, one embodiment of the invention discloses a kind of chip packaging device, and it comprises a carrier, a chip, at least one wire, an adhesion layer, a heat sink and an adhesive body.Carrier comprises at least one chip bonding area and at least one electric contact, and wherein this at least one electric contact arranges along this at least one chip bonding area periphery.Chip has an active surface and one passive.Chip comprises at least one weld pad, and it is arranged on active surface.Chip, is arranged on this at least one chip bonding area of this carrier towards carrier with passive.At least one wire connects this at least one weld pad and this at least one electric contact.Adhesion layer covers the active surface of chip and be coated the part of extending at least one wire on corresponding at least one weld pad.Heat sink is fixed on adhesion layer, and covers this chip.Adhesive body partly seals all sides of this chip, this adhesion layer and this heat sink, and on this adhesive body, forms the opening of a depression, to expose this heat sink surface.
One embodiment of the invention discloses a kind of manufacture method of chip packaging device, and it comprises the following step: a carrier is provided, and wherein this carrier comprises at least one chip bonding area and at least one electric contact; At least one chip is provided, and this chip comprises and on the active surface of this chip, is formed with an active surface and one passive at least one weld pad, and is fixed on this at least one chip bonding area of this carrier with the passive face of this chip; With a wire, connect this at least one weld pad and this at least one electric contact; With an adhesion layer, cover the active surface of this chip, the part of wherein extending in coated this at least one wire of this adhesion layer on this at least one weld pad; Fix a radiating subassembly on this adhesion layer, wherein this radiating subassembly comprises a heat sink and a covering, and this heat sink is between this chip and this covering; Form an adhesive body, it is along all side seal settings of this chip, this adhesion layer and this radiating subassembly, and exposes this covering in the end face of this adhesive body; And remove this covering.
The above technical characterictic of this exposure of sketch out and advantage, obtained better understanding in order to do this exposure is below described in detail.Other technical characterictic and the advantage that form the claim target of this exposure will be described in below.In technical field, have and conventionally know that the knowledgeable should understand under this exposure, the concept below disclosing can be used as basis with specific embodiment and is revised quite easily or design other structure or technique and realize with this and disclose identical object.In technical field, have and conventionally know that the knowledgeable also should understand under this exposure, the construction of this class equivalence also cannot depart from the spirit and scope of this exposure that claims propose.
Accompanying drawing explanation
Fig. 1 shows the schematic cross-section of a kind of chip packaging device of one embodiment of the invention;
Fig. 2 to Fig. 6 process flow diagram, the manufacture method of the chip packaging device of its illustration one embodiment of the invention;
Fig. 7 to Fig. 9 process flow diagram, the manufacture method of the radiating subassembly of its illustration one embodiment of the invention; And
Figure 10 shows the schematic cross-section of a kind of chip packaging device of another embodiment of the present invention.
Embodiment
Fig. 1 shows the schematic cross-section of a kind of chip packaging device 1 of one embodiment of the invention.Shown in Fig. 1, chip packaging device 1 can comprise a carrier 11, a chip 14, at least one wire 16, an adhesion layer 17, a heat sink 18 and an adhesive body 19, and its chips 14 is arranged on carrier 11; Adhesion layer 17 is arranged on chip 14; Heat sink 18 is arranged on adhesion layer 17; Wire 16 is electrically connected chip 14 and is coated by adhesion layer 17 with carrier 11 and part; And adhesive body 19 part seals the territory, all lateral areas of chip 14, adhesion layer 17 and heat sink 18 stack architectures, and expose the surface 24 of heat sink 18.
In detail, carrier 11 can comprise at least one chip bonding area 25 and at least one electric contact 12, and wherein this at least one electric contact 12 is arranged at all sides of at least one chip bonding area 25.In one embodiment, carrier 11 comprises several electric contacts 12, and wherein those electric contacts 12 are along the periphery setting of this at least one chip bonding area 25.Carrier 11 can be printed circuit board (PCB) or is FR-4 substrate, FR-5 substrate, BT substrate or other similar support plate person.
At least one weld pad 15 of chip 14 is connected with wire 16 with corresponding at least one electric contact 12 on carrier 11.
On carrier 11, can separately form several tin balls 21, wherein tin ball 21 is oppositely arranged with chip 14.See through tin ball 21, chip 14 must with chip packaging device 1 outside device or circuit be electrically connected.
Fig. 2 to Fig. 6 process flow diagram, the manufacture method of the chip packaging device 1 of its illustration one embodiment of the invention.Shown in Fig. 2, first the manufacture method of chip packaging device 1 provides a carrier 11.Carrier 11 comprises at least one chip bonding area 25 and at least one electric contact 12, and wherein this at least one electric contact 12 is arranged at the territory, all lateral areas of at least one chip bonding area 25.Then, provide at least one chip 14.Chip 14 comprises at least one weld pad 15, an active surface 26 and one passive 27, and wherein at least one weld pad 15 is arranged on active surface 26.Then, in passive 27 mode towards carrier 11 of chip 14, utilize viscose 13, chip 14 is fixed on to corresponding at least one chip bonding area 25 on carrier 11.Afterwards, utilize at least one wire 16, correspondingly connect the electric contact 12 on weld pad on chip 14 15 and carrier 11.
Shown in Fig. 3, an adhesion layer 17 is covered to the active surface 26 of chip 14, wherein adhesion layer 17 is at least coated on the part wire 16 extending on corresponding at least one weld pad 15.
Shown in Fig. 4, a radiating subassembly 28 is fixed on adhesion layer 17, wherein radiating subassembly 28 comprises a heat sink 18 and a covering 30.In one embodiment, the large I of heat sink 18, adhesion layer 17, covering 30 and chip 14 is suitable.
Shown in Fig. 5, in chip 14, adhesion layer 17, form an adhesive body 19 with all sides of radiating subassembly 28, to seal all sides of chip 14, adhesion layer 17 and radiating subassembly 28, and expose covering 30 in the end face of adhesive body 19.
Shown in Fig. 6, after cutting, obtaining most independences and top is the chip packaging device 1 that covering 30 covers, and finally removes covering 30 again.Covering 30 is the glued membrane of a high temperature can resistance to adhesive body 19 moulding time.Covering 30 can be a hot release film (thermal release film), and covering 30 can remove by mode of heating.In addition, covering 30 also can be to utilize and removes the glued membrane that mode removes.
Fig. 7 to Fig. 9 process flow diagram, the manufacture method of the radiating subassembly 28 of its illustration one embodiment of the invention.Shown in Fig. 7, first the manufacture method of radiating subassembly 28 provides a wafer 31.Then paste an emulsion sheet 32 on the surface 33 of wafer 31.
Shown in Fig. 8, by wafer 31 thinnings, with obtain a thinning wafer 31 '.Then, with chemical etching or ion etching, by wafer 31 ' surface 34 alligatoring or on surface, form some nests hole (dimple) on 34.
Shown in Fig. 9, finally cut thinning wafer 31 ' with the combination of emulsion sheet 32, to obtain several radiating subassemblies 28.
Figure 10 shows the schematic cross-section of a kind of chip packaging device 3 of another embodiment of the present invention.Shown in Figure 10, chip packaging device 3 can comprise a carrier 11, a chip 14, at least one wire 16, an adhesion layer 17, a heat sink 38 and an adhesive body 39.Chip 14 is fixed in its passive 27 mode that is attached to the chip bonding area 25 on carrier 11, and correspondingly connects weld pad 15 and the electric contact 12 that is positioned at the 25 weeks sides in chip bonding area with wire 16.Adhesion layer 17 covers the active surface 26 of chip 14 and is coated on the part wire 16 extending on corresponding weld pad 15.Heat sink 38 is fixed and is covered on adhesion layer 17.Adhesive body 39 parts seal the territory, all lateral areas of chip 14, adhesion layer 17 and heat sink 38 stack architectures, and expose the surface 40 of heat sink 18.In the present embodiment, the surface area of heat sink 38 is greater than the surface area of chip 14.The material of heat sink 38 can be metal (as copper) or silicon.Again, heat sink 38 has one and is fixed on the surface 41 of adhesion layer 17 and with respect to another surface 40 of 41, surface, wherein surface 41 can more surperficial 40 be coarse, to increase the Bonding strength of 17 of heat sink 38 and adhesion layers.
On carrier 11, can separately form several tin balls 21, wherein tin ball 21 is oppositely arranged with chip 14.See through tin ball 21, chip 14 must with chip packaging device 3 outside device or circuit be electrically connected.
To sum up, the present invention discloses a kind of chip packaging device, and it comprises a heat sink.Heat sink can fully be exposed to outside the encapsulation of chip packaging device, so the good radiating efficiency of chip packaging device tool.In addition, chip packaging device separately comprises an adhesion layer, and adhesion layer covered section connects the wire of chip and carrier.The another manufacture method that discloses a kind of chip packaging device of the present invention, the method utilizes covering to hide heat sink, all sides at chip, adhesion layer, heat sink and covering form an adhesive body afterwards, so can easily produce the encapsulating structure that heat sink is exposed, and need not cut heat sink.
Technology contents and the technical characterstic of this exposure disclose as above, however the teaching that the personage who is familiar with the technology still may be based on this exposure and announcement and do all replacement and modifications that does not deviate from this exposure spirit.Therefore, the protection range of this exposure should be not limited to those disclosed embodiments, and should comprise various replacement and the modifications that do not deviate from this exposure, and is contained by claims.
Claims (6)
1. a manufacture method for chip packaging device, comprises the following step:
One carrier is provided, and wherein this carrier comprises at least one chip bonding area and at least one electric contact;
At least one chip is provided, and wherein this chip comprises and an active surface and one passive is formed with at least one weld pad on this active surface of this chip, and this chip, is fixed on this at least one chip bonding area of this carrier towards this carrier with this passive;
With a wire, connect this at least one weld pad and this at least one electric contact;
With an adhesion layer, cover this active surface of this chip, the part of wherein extending in coated this wire of this adhesion layer on this at least one weld pad;
Fix a radiating subassembly on this adhesion layer, wherein this radiating subassembly comprises a heat sink and a covering, and this heat sink is between this adhesion layer and this covering;
Form an adhesive body, it is along all side seal settings of this chip, this adhesion layer and this radiating subassembly, and exposes this covering in the end face of this adhesive body; And
Remove this covering;
Wherein, the manufacture method of this radiating subassembly comprises the following step:
Paste a covering on a wafer, wherein this covering covers a surface of this wafer;
Another this wafer of surperficial thinning not covered by this covering from this wafer;
By this another surface coarsening of this wafer or form some nests hole on this another surface; And
Cut the combination of this covering and this wafer, to obtain several these radiating subassemblies.
2. manufacture method according to claim 1, is characterized in that, the material of this heat sink is silicon.
3. manufacture method according to claim 1, is characterized in that, the mode that the step that removes this covering comprises to heat or remove removes this covering.
4. manufacture method according to claim 1, is characterized in that, after removing this covering, in the end face of this adhesive body, forms an opening to expose this heat sink surface.
5. manufacture method according to claim 1, is characterized in that, this adhesion layer is the glue material that film covers bonding wire.
6. manufacture method according to claim 1, is characterized in that, the material of this heat sink is metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010190234.9A CN102254880B (en) | 2010-05-21 | 2010-05-21 | Chip packaging device and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201010190234.9A CN102254880B (en) | 2010-05-21 | 2010-05-21 | Chip packaging device and manufacturing method thereof |
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| CN102254880A CN102254880A (en) | 2011-11-23 |
| CN102254880B true CN102254880B (en) | 2014-04-30 |
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| WO2020103147A1 (en) * | 2018-11-23 | 2020-05-28 | 北京比特大陆科技有限公司 | Chip heat dissipation structure, chip structure, circuit board and supercomputing device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1835195A (en) * | 2005-03-14 | 2006-09-20 | 日月光半导体制造股份有限公司 | Method for manufacturing a semiconductor package with a laminated chip cavity |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6833287B1 (en) * | 2003-06-16 | 2004-12-21 | St Assembly Test Services Inc. | System for semiconductor package with stacked dies |
| TWI246757B (en) * | 2004-10-27 | 2006-01-01 | Siliconware Precision Industries Co Ltd | Semiconductor package with heat sink and fabrication method thereof |
| US20080308914A1 (en) * | 2006-03-17 | 2008-12-18 | Chipmos Technologies Inc. | Chip package |
| CN101207044A (en) * | 2006-12-18 | 2008-06-25 | 矽品精密工业股份有限公司 | Heat dissipation type semiconductor package part and method for making the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1835195A (en) * | 2005-03-14 | 2006-09-20 | 日月光半导体制造股份有限公司 | Method for manufacturing a semiconductor package with a laminated chip cavity |
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