KR20160056650A - Organic light emitting device - Google Patents

Abstract

The present invention relates to an organic light emitting display device which can maintain the capacitance of a capacitor even in a high-resolution organic light emitting display device. The organic light emitting display device according to the present invention comprises: a pixel region defined by a data line and a power line arranged parallel to each other while crossing a gate line; at least two thin film transistors; a first insulation layer; a first storage electrode; a second storage electrode; a first electrode; and a second electrode. The first insulation layer covers the at least two thin film transistors and has at least one hole. The first storage electrode is disposed on the first insulation layer to have a curved portion along the inner surface of the hole. The second storage electrode is disposed to be overlapped with the first storage electrode with a second insulation layer interposed therebetween, wherein the second insulation layer has a curved portion corresponding to the inner surface of the hole of the first insulation layer. The first electrode is disposed to be overlapped with the second storage electrode with a third insulation layer interposed therebetween. The second electrode is disposed to be overlapped with the first electrode with an organic light emitting layer interposed therebetween.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an organic light-

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an organic light emitting display, and more particularly, to an organic light emitting display capable of realizing a high resolution by securing a capacitance of a high capacity in a limited area.

2. Description of the Related Art In recent years, various flat panel display devices capable of reducing weight and volume, which are disadvantages of CRT (Cathode Ray Tube), have been developed. Examples of such flat panel display devices include a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), and an organic light emitting display (OLED) : Organic Light Emitting Display). Of these flat panel display devices, the organic light emitting display (OLED) is a self-emission type display device which excites an organic compound to emit light. It does not require a backlight used in an LCD, Can be simplified. Further, the organic light emitting display device is widely used because it can be manufactured at low temperature, has a response speed of 1 ms or less and has a high response speed as well as low power consumption, wide viewing angle, and high contrast have.

The organic light emitting display includes an organic light emitting diode (OLED) for converting electrical energy into light energy. The organic light emitting diode includes an anode electrode, a cathode electrode, and an organic light emitting layer disposed between the electrodes. Holes are injected from the anode electrode and electrons are injected from the cathode electrode. When an electron is injected into the hole injected through the anode and the cathode and injected into the emission layer (EML), an exciton is formed. The exciton emits light while emitting energy to light.

Such an organic light emitting display device includes a switching thin film transistor and a driving thin film transistor for each pixel in order to apply a driving signal to an anode of a display area. A switching thin film transistor receives a signal from a gate line and a data line to drive a pixel.

In recent years, with the increase in size of display devices and high resolution, a pixel size tends to become smaller. One pixel is divided by the intersection of a gate line, a data line, and a common power supply line, and a switching thin film transistor, a driving thin film transistor, a capacitor, and an organic light emitting diode are formed in this pixel. In this configuration, as the pixel size becomes smaller, the thin film transistors and the above-described lines are integrated and arranged very close to each other. Therefore, the conventional high-resolution organic light emitting display device has a problem that the area of the capacitor is reduced and the capacitance of the capacitor becomes insufficient.

SUMMARY OF THE INVENTION An object of the present invention is to provide an organic light emitting display capable of maintaining the capacitance of a capacitor even in a high resolution organic light emitting display.

According to an aspect of the present invention, there is provided an organic light emitting display including: a pixel region defined by a data line and a power supply line which are arranged in parallel with each other and which are arranged in parallel with each other; at least two thin film transistors; An electrode, a second storage electrode, a first electrode, and a second electrode. The first insulating film covers at least two thin film transistors, and has at least one hole. The first storage electrode is disposed on the first insulating film so as to have a bent portion along at least one hole inner surface. The second storage electrode is disposed so as to overlap the first storage electrode with a second insulating film having a bent portion corresponding to the inner surface of the hole of the first insulating film interposed therebetween. The first electrode is disposed so as to overlap with the second storage electrode and the third insulating film interposed therebetween. And the second electrode overlaps the first electrode with the organic light emitting layer therebetween.

The organic light emitting display device of the present invention further includes an interlayer insulating film for insulating the gate electrode and the source and drain electrodes of each thin film transistor. The first insulating film is made of a photosensitive organic material, the interlayer insulating film is made of an inorganic insulating material, the second insulating film is made of an inorganic insulating material, and the third insulating film is made of a photosensitive organic material or an inorganic insulating material.

The organic light emitting display device of the present invention further includes an interlayer insulating film for insulating the gate electrode and the source and drain electrodes of each thin film transistor. The first insulating film is made of an inorganic insulating material, and the interlayer insulating film is made of an inorganic insulating material having a high etch selectivity to the inorganic insulating material. The second insulating film may be made of the inorganic insulating material or the other inorganic insulating material, and the third insulating film may be made of any one of the photosensitive organic material, the inorganic insulating material, and the other inorganic material.

In the above configuration, at least two thin film transistors include a first active layer, a first gate electrode, a first source electrode, and a first drain electrode. The first active layer is disposed on the substrate. The first gate electrode is disposed on the gate insulating film covering the first active layer. The first source electrode is disposed on the interlayer insulating film covering the first gate electrode and is connected to the first source region of the first active layer exposed through the first contact hole passing through the interlayer insulating film and the gate insulating film . The first drain electrode is connected to the first drain region of the first active layer exposed through the second contact hole passing through the interlayer insulating film and the gate insulating film.

Alternatively, at least two thin film transistors include a second active layer, a second gate electrode, a second source electrode, and a second drain electrode. The second active layer is disposed on the substrate and spaced apart from the first active layer. The second gate electrode is disposed apart from the first gate electrode on the gate insulating film covering the second active layer. The second source electrode is disposed on the interlayer insulating film covering the second gate electrode and is connected to the second source region of the second active layer exposed through the fourth contact hole passing through the interlayer insulating film and the gate insulating film. do. The first drain electrode is connected to the second drain region of the second active layer exposed through the fifth contact hole passing through the interlayer insulating film and the gate insulating film.

The first storage electrode is connected to the first drain electrode exposed through the seventh contact hole passing through the second insulating film and the first insulating film.

And the second storage electrode is connected to the second drain electrode exposed through the eighth contact hole passing through the second insulating film and the first insulating film.

The first electrode is connected to the second storage electrode exposed through the ninth contact hole passing through the third insulating film.

The first drain electrode is connected to the second gate electrode exposed through the third contact hole passing through the interlayer insulating film and the gate insulating film.

The organic electroluminescent display device of the present invention further includes an auxiliary electrode disposed on the interlayer insulating film in parallel with the data line and the power source line, and a source electrode and a drain electrode of the data line, the power source line, And a fourth insulating film disposed under the first insulating film, wherein the fourth insulating film is made of an inorganic insulating material.

According to the organic electroluminescence display device of the present invention, the first storage electrode is located along the path of at least one contact hole formed in the insulating film below the first electrode, and the second storage electrode is located on the insulating film covering the first storage electrode. The first storage electrode and the second storage electrode opposed to each other are significantly opposed to each other. Therefore, the capacitance of the storage capacitor can be remarkably increased in the pixel region of the same size.

According to the organic electroluminescent display device of the present invention, since the etching process is unnecessary by using the photosensitive organic material as the insulating film covering the thin film transistor, it is not necessary to consider the etch selectivity of the lower insulating film, The effect of improving the degree of freedom can be obtained.

1 is an equivalent circuit diagram showing one pixel of an organic light emitting display according to an embodiment of the present invention,
2 is a plan view showing one pixel of an organic light emitting diode display according to an embodiment of the present invention,
3 is a cross-sectional view taken along line II and II-II 'of FIG. 2,
FIG. 4A is a plan view showing a first mask process of an organic light emitting display according to an embodiment of the present invention, FIG.
FIG. 4B is a cross-sectional view taken along line II and II-II 'of FIG. 4A,
5A is a plan view showing a second mask process of an organic light emitting display according to an embodiment of the present invention,
FIG. 5B is a cross-sectional view taken along line II and II-II 'of FIG. 5A,
6A is a plan view showing a third mask process of an organic light emitting display according to an embodiment of the present invention,
FIG. 6B is a cross-sectional view taken along line II and II-II 'of FIG. 6A,
7A is a plan view showing a fourth mask process of an organic light emitting display according to an embodiment of the present invention,
FIG. 7B is a cross-sectional view taken along line II and II-II 'of FIG. 7A,
8A is a plan view showing a fifth mask process of an organic light emitting display according to an embodiment of the present invention,
FIG. 8B is a cross-sectional view taken along line II and II-II 'of FIG. 8A,
FIG. 9A is a plan view showing a sixth mask process of an organic light emitting display according to an embodiment of the present invention, FIG.
FIG. 9B is a cross-sectional view taken along line II and II-II 'of FIG. 9A,
10A is a plan view showing a seventh mask process of an organic light emitting display according to an embodiment of the present invention,
FIG. 10B is a cross-sectional view taken along line II and II-II 'of FIG. 10A,
11A is a plan view showing an eighth mask process of an organic light emitting display according to an embodiment of the present invention,
11B is a cross-sectional view taken along line II and II-II 'of FIG. 11A,
12A is a plan view showing a ninth mask process of an organic light emitting display according to an embodiment of the present invention,
FIG. 12B is a sectional view taken along line II and II-II 'of FIG. 12A,
13A is a plan view showing a tenth mask process of an organic light emitting display according to an embodiment of the present invention,
FIG. 13B is a cross-sectional view taken along line II and II-II 'of FIG. 13A,
FIG. 14A is a plan view showing one pixel of an OLED display according to another embodiment of the present invention, FIG.
FIG. 14B is a cross-sectional view taken along line II and II-II 'of FIG. 14A,
FIG. 15A is a plan view showing one pixel of an OLED display according to another embodiment of the present invention, FIG.
FIG. 15B is a cross-sectional view taken along line II and II-II 'of FIG. 15A. FIG.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, well-known functions or constructions are not described in detail to avoid unnecessarily obscuring the subject matter of the present invention.

1 to 3, an organic light emitting display according to an embodiment of the present invention will be described. FIG. 1 is a circuit diagram showing one pixel of an organic light emitting display according to an embodiment of the present invention. FIG. 2 is a plan view showing one pixel of an organic light emitting display according to an embodiment of the present invention. 3 is a cross-sectional view taken along line II and II-II 'in Fig.

1, one pixel of an organic light emitting display according to an embodiment of the present invention includes a cell driver DU connected to a gate line GL, a data line DL, and a power supply line PL, And an organic light emitting diode (OLED) connected between the cell driver DU and the ground GND.

The cell driving unit DU includes a switching thin film transistor T1, a driving thin film transistor T2, and a storage capacitor Cst. The switching thin film transistor T1 includes a gate electrode connected to the gate line GL, a source electrode connected to the data line DL, and a drain electrode connected to the first node n1. The driving thin film transistor T2 includes a source electrode connected to the power supply line PL, a gate electrode connected to the first node n1, and a drain electrode connected to the second node n2. The storage capacitor Cst includes a first electrode connected to the first node n1 and a second electrode connected to the second node n2. The drain electrode of the switching thin film transistor T1, the gate electrode of the driving thin film transistor T2, and the first electrode of the storage capacitor Cst are connected to the first node n1. A drain electrode of the driving thin film transistor T2, a second electrode of the capacitor Cst, and an anode electrode of the organic light emitting diode OLED are connected to the second node n2.

The organic light emitting diode OLED is connected between the second node n2 of the cell driving unit DU and the ground GND.

The switching thin film transistor T1 is turned on when a scan pulse is supplied to the gate line GL to supply the data signal supplied to the data line DL to the storage capacitor C and the driving thin film transistor T2, As shown in FIG. The driving thin film transistor T2 controls the amount of light emitted from the organic light emitting diode OLED by controlling the current I supplied from the power supply line PL to the organic light emitting diode OLED in response to the data signal supplied to the gate electrode do. Even if the switching thin film transistor T1 is turned off, the driving thin film transistor T2 supplies a constant current I until the data signal of the next frame is supplied by the voltage charged in the storage capacitor Cst, Thereby maintaining the light emission of the light emitting diode OLED.

2 and 3, an inorganic insulating film such as silicon nitride (SiNx) or silicon oxide (SiOx) or a buffer insulating film BUF made of multiple layers thereof is applied over the substrate SUB and a buffer insulating film The first active layer A1 and the second active layer A2 spaced apart from each other are disposed on the second active layer BUF. The buffer insulating film BUF may be omitted. The first active layer A1 and the second active layer A2 are semiconductor active layers formed by implanting impurity ions into amorphous silicon (a-Si). The first active layer A1 is composed of a first source region SA1 and a first drain region DA1 arranged with the first active region AA1 therebetween. The second active layer A2 includes a second source region SA2 and a second drain region DA2 disposed with the second active region AA2 interposed therebetween.

A gate insulating film GI is disposed on the first active layer A1 and the second active layer A2 so as to cover and insulate them. The gate insulating film GI may be formed of an inorganic insulating film such as silicon nitride (SiNx), silicon oxide (SiOx), or a multilayer thereof, similar to the buffer layer BUF. On the gate insulating film GI, the gate line GL, the first gate electrode G1, and the second gate electrode G2 are located. The first gate electrode G1 extends from the gate line GL and overlaps at least a part with the first active area AA1 of the first active layer A1. The second gate electrode G2 is disposed apart from the gate line GL and the first gate electrode G1. The gate line GL, the first gate electrode G1 and the second gate electrode G2 may be formed of a metal such as aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti) ), Silver (Ag), tungsten (W), or an alloy thereof, or a multilayer thereof.

An interlayer insulating film ILD is disposed on the gate insulating film GI on which the gate line GL, the first gate electrode G1 and the second gate electrode G2 are disposed to insulate and cover them. The interlayer insulating film (ILD) may be an inorganic insulating film such as silicon nitride (SiNx), silicon oxide (SiOx), or a multilayer thereof.

On the interlayer insulating film ILD, a data line DL and a power source line PL which are in parallel with the data line DL are arranged to intersect the gate line GL. The first source electrode S1 and the first drain electrode D1 of the switching thin film transistor T1 and the second source electrode S2 and the second drain electrode D1 of the driving thin film transistor T2 are formed on the interlayer insulating film ILD, (D2). The data line DL, the power supply line PL, the first and second source electrodes S1 and S2 and the first and second drain electrodes D1 and D2 may be formed of aluminum (Al), copper (Cu) A single layer of any one selected from the group consisting of molybdenum (Mo), chrome (Cr), titanium (Ti), gold (Au), silver (Ag), tungsten (W) Lt; / RTI >

The first source electrode S1 of the switching thin film transistor T1 may extend from the data line DL or may be a part of the data line DL and may be connected to the first interlayer insulating film ILD through the gate insulating film GI, And is arranged to be in contact with the first source region SA1 of the first active layer A1 exposed through the contact hole CH1. The first drain electrode D1 of the switching thin film transistor T1 is formed so as to overlap the gate line GL, the first drain region DA1 of the first active layer A2, and the second gate electrode G2, ILD). The first drain electrode D1 of the switching thin film transistor T1 is connected to the first active layer A1 exposed through the second contact hole CH2 penetrating the interlayer insulating film ILD and the gate insulating film GI, Drain region DA1 and is connected to the second gate electrode G2 of the driving thin film transistor T2 exposed through the third contact hole CH3 penetrating the interlayer insulating film ILD.

 The second source electrode S2 of the driving thin film transistor T2 may extend from the power source line PL or may be a part of the power source line PL and may include a fourth And is in contact with the second source region SA2 of the second active layer A2 exposed through the contact hole CH4. The second drain electrode D2 of the driving thin film transistor T2 is disposed on the interlayer insulating film ILD so as to overlap with the second drain region DA2 of the second active layer A2. The second drain electrode D2 of the driving thin film transistor T2 is electrically connected to the second active layer A2 of the second active layer A2 exposed through the fifth contact hole CH5 passing through the interlayer insulating film ILD and the gate insulating film GI. Drain region DA2.

The first source electrode S1 and the first drain electrode D1 of the switching thin film transistor T1 and the second source electrode S2 of the driving thin film transistor T2 and the data line DL, On the interlayer insulating film ILD on which the second drain electrode D2 is disposed, the first planarizing film PLN1 is positioned to cover them. The first planarizing film PLN1 is formed of a photosensitive organic film such as photosensitive polyacryl and polyimide. The first planarizing film PLN1 is formed of at least one material that is formed to expose the interlayer insulating film ILD in the pixel region defined by the data line DL, the power source line PL and the adjacent gate lines GL. 6 contact holes CH6. A region R indicated by a dotted line in Fig. 2 represents an area where a plurality of sixth contact holes CH6 can be formed.

Since the etching process is unnecessary when the first planarizing film PLN1 is formed of a photosensitive organic material, it is not necessary to consider the etch selectivity, and the degree of freedom in material selection can be improved. For example, when the interlayer insulating film ILD and the first planarizing film PLN1 are formed of an inorganic material, the interlayer insulating film ILD is damaged when the first planarizing film PLN1 on the interlayer insulating film ILD is etched (ILD) and the first planarizing film (PLN1) must be formed by using silicon nitride and silicon oxide having large mutual etching ratios. However, if the first planarizing film PLN1 is formed using the photosensitive organic film, it is not necessary to etch the first planarizing film PLN1, so that the etching selectivity for protecting the interlayer insulating film ILD becomes unnecessary. Therefore, since both silicon nitride and silicon oxide can be used to form the interlayer insulating film (ILD), the effect of improving the degree of freedom in material selection can be obtained.

A first storage electrode ST1 of the storage capacitor is disposed in a pixel region on the first planarization film PLN1 on which a plurality of sixth contact holes CH6 are formed. Since the first storage electrode ST1 is formed along the inner wall path of the sixth contact holes CH6, the area of the first storage electrode ST1 increases as the number of the sixth contact holes CH6 increases.

A passivation film PAS is disposed on the first planarizing film PLN1 on which the first storage electrode ST1 is located to cover the first storage electrode ST1. The passivation film PAS may be formed of an inorganic insulating film such as silicon nitride (SiNx) or silicon oxide (SiOx). The passivation film PAS has a plurality of recesses along the shape of the sixth contact holes CH6 formed in the first planarizing film PLN1.

A portion of the first drain electrode D1 of the switching thin film transistor T1 is exposed through the seventh contact hole CH7 passing through the passivation film PAS and the first planarization film PLN1. The seventh contact hole CH7 also exposes a portion of the first storage electrode ST1 located on the first planarization layer PLN1. The second drain electrode D2 of the driving thin film transistor T2 is partially exposed through the passivation film PAS and the eighth contact hole CH8 passing through the first planarization film PLN1.

The second storage electrode ST2 is positioned on the passivation film PAS where the seventh and eighth contact holes CH7 and CH8 are formed so as to face the first storage electrode ST1 of the storage capacitor. A connection CP connecting the first drain electrode D1 of the switching TFT T1 exposed through the seventh contact hole C7 and the first storage electrode ST1 is located on the passivation film PAS . The first and second storage electrodes ST1 and ST2 and the connection pattern CP may be formed of a material selected from the group consisting of aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti) Silver (Ag), tungsten (W), or an alloy thereof.

The second storage electrode ST2 is located along the plurality of recesses formed in the passivation film PAS by the plurality of sixth contact holes CH6 and CH6 and the first storage electrode ST1 is located along the plurality of recesses formed in the passivation film PAS, (CH6, CH6) formed in the first storage electrode PLN1, the opposed areas of the first storage electrode ST1 and the second storage electrode ST2 opposed to each other are remarkably widened . Therefore, the capacitance of the storage capacitor can be remarkably increased in the pixel region of the same size.

The second planarization layer PLN2 is positioned on the passivation layer PAS where the second storage electrode ST2 and the connection portion CP are located to cover the second storage electrode ST2 and the connection portion CP. The second planarizing film PLN2 is formed of a photosensitive organic film such as photosensitive polyacryl or photosensitive polyimide. The second planarization layer PLN2 includes a ninth contact hole CH9 that exposes a portion of the second storage electrode ST2.

The anode electrode of the organic light emitting diode is positioned on the second planarizing film PLN2 having the ninth contact hole CH9 so as to be in contact with the second storage electrode ST2 exposed through the ninth contact hole CH9 . An organic light emitting layer (not shown) and a cathode electrode (not shown) are sequentially formed on the anode electrode (AND) to form an organic light emitting diode (OLED of FIG. 1). The anode electrode AND and the cathode electrode may be formed of a metal such as aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), gold (Au), silver (Ag), tungsten The alloy may be selected from the group consisting of alloys. The structure of the upper portion of the anode electrode (AND) can be applied to a well-known structure already known, so further explanation will be omitted in order to avoid complexity of the description.

Next, a method of manufacturing an organic light emitting display according to an embodiment of the present invention will be described with reference to FIGS. 4A to 13B. Hereinafter, for convenience of explanation, one pixel region of the organic light emitting display will be mainly described.

FIG. 4A is a plan view showing a first mask process of an organic light emitting display according to an embodiment of the present invention, and FIG. 4B is a cross-sectional view taken along lines I-I and II-II 'of FIG. 4A.

4A and 4B, a buffer insulating layer and a semiconductor material are deposited on an entire surface of a substrate SUB by, for example, a sputtering process, and then a first active layer and a second active layer, Layer.

More specifically, a buffer layer made of an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) is formed on the entire surface of the substrate SUB through a sputtering process and a buffer layer made of a semiconductor such as amorphous silicon A first photoresist pattern (not shown) for exposing the semiconductor layer is formed by sequentially depositing a first semiconductor layer, a first photoresist layer, and a photolithography process using a first mask. Then, after removing the semiconductor layer exposed by the first photoresist pattern, the first active layer A1 and the second active layer A2 spaced apart from each other on the buffer layer BUF are formed by ashing the remaining first photoresist pattern, . The buffer layer BUF may be omitted.

The first active layer A1 and the second active layer A2 are semiconductor active layers formed by implanting impurity ions into amorphous silicon (a-Si). The first active layer A1 is composed of a first source region SA1 and a first drain region DA1 arranged with the first active region AA1 therebetween. The second active layer A2 includes a second source region SA2 and a second drain region DA2 disposed with the second active region AA2 interposed therebetween.

FIG. 5A is a plan view showing a second mask process of an organic light emitting display according to an embodiment of the present invention, and FIG. 5B is a cross-sectional view taken along lines I-I and II-II 'of FIG. 5A.

5A and 5B, a gate insulating material and a first metal material are sequentially deposited on a buffer layer BUF on which a first active layer A1 and a second active layer A2 are formed through, for example, a sputtering process After the deposition, a first metal material is patterned using a second mask process to form a gate metal layer including the gate line GL and the first and second gate electrodes G1 and G2.

More specifically, the gate insulating material, the first metal material, and the second photoresist are entirely deposited through a sputtering process on the buffer layer BUF on which the first active layer A1 and the second active layer A2 are formed . Then, a photolithography process using a second mask is performed to form a second photoresist pattern (not shown) exposing a part of the first metal material. The first metal material exposed by the second photoresist pattern is removed through etching and the remaining second photoresist pattern is ashed so that the gate line GL and the first and second Thereby forming a gate metal layer including the gate electrodes G1 and G2. The first gate electrode G1 extends from the gate line GL and overlaps at least a part with the first active area AA1 of the first active layer A1. On the other hand, the second gate electrode G2 is disposed apart from the gate line GL and the first gate electrode G1.

The gate insulating film GI may be an inorganic insulating film such as silicon nitride (SiNx), silicon oxide (SiOx), or a multilayer thereof. The first metal material may be at least one selected from the group consisting of Al, Cu, Mo, Cr, Ti, Au, A single layer made of any one selected from the group consisting of the above, or a multilayer composed of these.

FIG. 6A is a plan view showing a third mask process of an organic light emitting display according to an embodiment of the present invention, and FIG. 6B is a cross-sectional view taken along lines I-I and II-II 'of FIG. 6A.

6A and 6B, on the gate insulating film GI on which the gate line GL and the first and second gate electrodes G1 and G2 are formed, an interlayer insulating film (not shown) is formed through, for example, a sputtering process ILD), and then the first to fifth contact holes CH1 to CH5 are formed using a third mask process.

Specifically, an interlayer insulating film (ILD) and a third photoresist are deposited on the gate insulating film GI on which the gate line GL and the first and second gate electrodes G1 and G2 are formed through, for example, a sputtering process Second, fourth, and fifth contact holes CH1, CH2, CH4, and CH5 that pass through the interlayer insulating film ILD and the gate insulating film GI by performing a photolithography process using a third mask, And a third contact hole CH3 penetrating the interlayer insulating film ILD are formed. Then, the remaining third photoresist pattern is ashed to form an interlayer insulating film (ILD) in which the first to fifth contact holes CH1 to CH5 are formed. The interlayer insulating film (ILD) may be an inorganic insulating film such as silicon nitride (SiNx), silicon oxide (SiOx), or a multilayer thereof.

The first contact hole CH1 exposes the first source region SA1 of the first active layer A1 and the second contact hole CH2 exposes the first drain region DA1 of the first active layer A1. Lt; / RTI > The third contact hole CH3 exposes the second gate electrode G2 of the second active layer A2 and the fourth contact hole CH4 exposes the second source region SA2 of the second active layer A2 ). The fifth contact hole CH5 exposes the second drain region DA2 of the second active layer A2.

FIG. 7A is a plan view showing a fourth mask process of an organic light emitting display according to an embodiment of the present invention, and FIG. 7B is a cross-sectional view taken along lines I-I and II-II 'of FIG. 7A.

Referring to FIGS. 7A and 7B, a source / drain metal material as a second metal material is deposited on the interlayer insulating film ILD on which the first through fifth contact holes CH1 through CH5 are formed through, for example, a sputtering process The first source electrode S1 and the first drain electrode D1 of the switching thin film transistor T1, the driving thin film transistor T2, the data line DL, the power source line PL, A second source electrode S2 and a second drain electrode D2 are formed.

More specifically, a source / drain metal material as a second metal material and a fourth photoresist are deposited on the interlayer insulating film (ILD) on which the first to fifth contact holes CH1 to CH5 are formed through, for example, a sputtering process A photolithography process using a fourth mask is performed to form a fourth photoresist pattern (not shown) exposing the source / drain metal material. The power line PL, and the switching thin film transistor Tl by ashing the remaining fourth photoresist pattern after removing the exposed source / drain metal material through the fourth photoresist pattern through etching, A source / drain electrode layer including a first source electrode S1 and a first drain electrode D1 of the driving TFT T2 and a second source electrode S2 and a second drain electrode D2 of the driving TFT T2 are formed

The second metal material may be at least one selected from the group consisting of Al, Cu, Mo, Cr, Ti, Au, A single layer made of any one selected from the group consisting of the above, or a multilayer composed of these.

The data line DL and the power source line PL are arranged side by side and in a direction crossing the gate line GL. The first source electrode S1 of the switching thin film transistor T1 may extend from the data line DL and is connected to the first source region SA1 exposed through the first contact hole CH1. The first drain electrode D1 of the switching thin film transistor T1 is connected to the first drain region DA1 exposed through the second contact hole CH2, And is connected to the second gate electrode G2 of the transistor T2. The second source electrode S2 of the driving thin film transistor T2 may extend from the power source line PL and is connected to the second source region SA2 exposed through the fourth contact hole CH4. And the second drain electrode D2 of the driving thin film transistor T2 is connected to the second drain region DA2 exposed through the fifth contact hole CH5.

FIG. 8A is a plan view showing a fifth mask process of an organic light emitting display according to an embodiment of the present invention, and FIG. 8B is a cross-sectional view taken along lines I-I and II-II 'of FIG. 8A.

8A and 8B, a first planarizing film PLN1 made of a photosensitive organic film is deposited on an interlayer insulating film ILD having a source / drain electrode layer formed thereon through, for example, a spin coating process, A plurality of sixth contact holes CH6 and CH6 are formed by using a mask process.

More specifically, the data line DL includes a power source line PL, a first source electrode S1, a first drain electrode D1, a second source electrode S2, and a second drain electrode D2. A first planarizing film (PLN1) and a fifth photoresist made of a photosensitive organic film are sequentially deposited on the interlayer insulating film (ILD) on which the source / drain electrodes are formed through, for example, a spin coating process. Then, a fifth mask process is performed to form a fifth photoresist pattern (not shown) exposing a part of the interlayer insulating film. The first planarizing film PLN1 exposed by the fifth photoresist pattern is removed by photolithography and then the fifth photoresist pattern is ashed to form a plurality of sixth contact holes CH6 and CH6 which expose portions of the interlayer insulating film ). When the first planarizing layer PLN1 is formed of a photosensitive organic material such as photosensitive polyacryl or photosensitive polyimide, the deposition of the fifth photoresist and the pattern formation process may be omitted and the photosensitive organic layer may be directly exposed to form a pattern, Can be simplified and costs can be reduced. In addition, since the etching process is unnecessary, it is not necessary to consider the etch selectivity, and the effect of selecting the material of the interlayer insulating film (ILD) can be improved.

FIG. 9A is a plan view showing a sixth mask process of an organic light emitting display according to an embodiment of the present invention, and FIG. 9B is a cross-sectional view taken along lines I-I and II-II 'of FIG. 9A.

9A and 9B, after a third metal material is deposited on the first planarizing film PLN1 having a plurality of sixth contact holes CH6 and CH6 through, for example, a sputtering process, 6 mask process is used to form the first storage electrode ST1 of the storage capacitor.

More specifically, the third metal material and the sixth photoresist are sequentially deposited on the first planarizing film PLN1 on which the sixth contact holes CH6 and CH6 are formed through, for example, a sputtering process. Then, a photolithography process using a sixth mask is performed to form a sixth photoresist pattern (not shown) exposing the third metal material. The third metal material exposed by the sixth photoresist pattern is removed through etching and the remaining sixth photoresist pattern is ashed to form the first storage electrode ST1 of the storage capacitor located in the pixel region. Since the first storage electrode ST1 is formed along the inner wall path of the sixth contact holes CH6, the area of the first storage electrode ST1 increases as the number of the sixth contact holes CH6 increases. Therefore, the effect of improving the capacitance of the storage capacitor can be obtained.

The third metal material may be at least one selected from the group consisting of Al, Cu, Mo, Cr, Ti, Au, A single layer made of any one selected from the group consisting of the above, or a multilayer composed of these.

FIG. 10A is a plan view showing a seventh mask process of an organic light emitting display according to an embodiment of the present invention, and FIG. 10B is a cross-sectional view taken along lines I-I and II-II 'of FIG. 10A.

10A and 10B, after the passivation film PAS1 is deposited on the first planarizing film PLN1 on which the first storage electrode ST1 is formed through, for example, a sputtering process, a seventh mask process is performed A seventh contact hole CH7 and an eighth contact hole CH8 are formed through the passivation film PAS and the first planarization film PLN1.

More specifically, a passivation film PAS and a seventh photoresist are sequentially deposited on the first planarizing film PLN1 on which the first storage electrode ST1 is formed, for example, through a sputtering process. Then, a photolithography process using the seventh mask is performed to expose the regions of the passivation film (PAS) corresponding to a partial region of the first drain (D1) and a partial region of the second drain (D2) Thereby forming a pattern (not shown). The seventh photoresist pattern is removed by ashing after the passivation film PAS and the first planarizing film PLN1 exposed by the seventh photoresist pattern are removed to expose a part of the first drain D1, And an eighth contact hole CH8 exposing a part of the hole CH7 and the second drain D2 are formed. The passivation film PAS may be formed of an inorganic insulating film such as silicon nitride (SiNx), silicon oxide (SiOx), or multilayers thereof.

11A is a plan view showing an eighth mask process of an organic light emitting display according to an embodiment of the present invention, and FIG. 11B is a sectional view taken along lines I-I and II-II 'of FIG. 11A.

11A and 11B, a fourth metal material is deposited on a passivation film PAS having a seventh contact hole CH7 and an eighth contact hole CH8 through, for example, a sputtering process, The second storage electrode ST2 of the storage capacitor and the connection portion CP are formed by using the eighth mask process.

More specifically, the fourth metal material and the eighth photoresist are sequentially deposited on the passivation film PAS formed with the seventh contact hole CH7 and the eighth contact hole CH8 through, for example, a sputtering process . Then, the photolithography process using the eighth mask is performed to expose regions of the fourth metal material corresponding to the first storage electrode ST1 of the storage capacitor and the first and second drain electrodes D1 and D2 An eighth photoresist pattern (not shown) is formed. After the fourth metal material exposed by the eighth photoresist pattern is removed, the eighth photoresist pattern is ashed to form the second storage electrode ST2 of the storage capacitor and the connection CP.

The fourth metal material may be at least one selected from the group consisting of Al, Cu, Mo, Cr, Ti, Au, A single layer made of any one selected from the group consisting of a single layer or a multilayer thereof.

And the second storage electrode ST2 is connected to the second drain electrode D2 of the driving thin film transistor T2 exposed through the eighth contact hole CH8. The second storage electrode ST2 is located along the plurality of recesses formed in the passivation film PAS by the plurality of sixth contact holes CH6 and CH6 and the first storage electrode ST1 is located along the plurality of recesses formed in the passivation film PAS, (CH6, CH6) formed in the first storage electrode PLN1, the opposed areas of the first storage electrode ST1 and the second storage electrode ST2 opposed to each other are remarkably widened . Therefore, the capacitance of the storage capacitor can be remarkably increased in the pixel region of the same size.

The connection CP connects the first drain electrode D1 and the first storage electrode ST1 of the switching TFT T1 exposed through the seventh contact hole C7.

12A is a plan view showing a ninth mask process of an organic light emitting display according to an embodiment of the present invention, and FIG. 12B is a cross-sectional view taken along lines I-I and II-II 'of FIG. 12A.

12A and 12B, a second planarization layer PLN2 is deposited on a passivation layer PAS having a second storage electrode ST2 and a connection portion CP, for example, through a sputtering process, A ninth contact hole CH9 is formed by using the ninth mask process.

More specifically, the second planarizing film PLN2 and the ninth photoresist are sequentially deposited on the passivation film PAS on which the second storage electrode ST2 and the connecting portion CP are formed through, for example, a sputtering process . Then, a photolithography process using the ninth mask is performed to form a ninth photoresist pattern (not shown) exposing a region of the second planarization film PLN2 corresponding to a partial region of the second storage electrode ST1 of the storage capacitor ). The ninth photoresist pattern is ashed after the second planarizing film PLN2 exposed by the ninth photoresist pattern is removed to form the ninth contact hole CH9 for exposing the drain electrode D2 of the driving thin film transistor T2. ). The second planarizing layer PLN2 may be formed of a photosensitive organic layer such as photosensitive polyacryl or photosensitive polyimide, or may be formed of an inorganic insulating layer.

FIG. 13A is a plan view showing a tenth mask process of an organic light emitting display according to an embodiment of the present invention, and FIG. 13B is a cross-sectional view taken along lines I-I and II-II 'of FIG. 13A.

13A and 13B, a fifth metal material is deposited on the second planarizing film PLN2 having the ninth contact hole CH9 formed thereon through, for example, a sputtering process, and then a tenth mask process is used Thereby forming an anode electrode (AND).

More specifically, a fifth metal material and a tenth photoresist are sequentially deposited on the second planarizing film PLN2 on which the ninth contact hole CH9 is formed through, for example, a sputtering process. Then, a photolithography process using a tenth mask is performed to form a tenth photoresist pattern (not shown) corresponding to the pixel region. After the second planarization film PLN2 exposed by the tenth photoresist pattern is removed, the tenth photoresist pattern is ashed to contact the second storage electrode ST2 exposed through the ninth contact hole CH9 Thereby forming the anode electrode (AND) of the organic light emitting diode.

The fifth metal material may be at least one selected from the group consisting of Al, Cu, Mo, Cr, Ti, Au, And < / RTI >

Next, an organic light emitting display according to a second embodiment of the present invention will be described with reference to FIGS. 14A and 14B. FIG. 14A is a plan view showing one pixel of an OLED display according to another embodiment of the present invention, and FIG. 14B is a cross-sectional view taken along lines I-I and II-II 'of FIG. 14A.

In the organic light emitting display according to the second embodiment of the present invention, as shown in FIGS. 14A and 14B, the auxiliary electrode CE is disposed on the interlayer insulating film ILD and covers the auxiliary electrode CE Is substantially the same as that of the organic light emitting display according to the first embodiment of the present invention except that the first passivation film PAS1 is disposed. The auxiliary electrode CE may be used when a switching thin film transistor or a driving thin film transistor for driving the organic light emitting diode is required in addition to the first passivation film PAS1, ST1), it is possible to obtain an effect of increasing the capacitance of the storage capacitor. Hereinafter, the organic light emitting display according to the second embodiment of the present invention will be described in more detail with reference to FIGS. 14A and 14B.

14A and 14B, an inorganic insulating film such as silicon nitride (SiNx) or silicon oxide (SiOx), or a buffer insulating film BUF made of multiple layers thereof is applied on the substrate SUB in its entirety, The first active layer A1 and the second active layer A2 spaced apart from each other are disposed on the second active layer BUF. The buffer insulating film BUF may be omitted. The first active layer A1 and the second active layer A2 are semiconductor active layers formed by implanting impurity ions into amorphous silicon (a-Si). The first active layer A1 is composed of a first source region SA1 and a first drain region DA1 arranged with the first active region AA1 therebetween. The second active layer A2 includes a second source region SA2 and a second drain region DA2 disposed with the second active region AA2 interposed therebetween.

A gate insulating film GI is disposed on the first active layer A1 and the second active layer A2 so as to cover and insulate them. The gate insulating film GI may be formed of an inorganic insulating film such as silicon nitride (SiNx), silicon oxide (SiOx), or a multilayer thereof, similar to the buffer layer BUF. On the gate insulating film GI, the gate line GL, the first gate electrode G1, and the second gate electrode G2 are located. The first gate electrode G1 extends from the gate line GL and overlaps at least a part with the first active area AA1 of the first active layer A1. The second gate electrode G2 is disposed apart from the gate line GL and the first gate electrode G1. The gate line GL, the first gate electrode G1 and the second gate electrode G2 may be formed of a metal such as aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti) ), Silver (Ag), tungsten (W), or an alloy thereof, or a multilayer thereof.

An interlayer insulating film ILD is disposed on the gate insulating film GI on which the gate line GL, the first gate electrode T1 and the second gate electrode 120c are disposed to insulate and cover them. The interlayer insulating film (ILD) may be an inorganic insulating film such as silicon nitride (SiNx), silicon oxide (SiOx), or a multilayer thereof.

A data line DL intersecting the gate line GL, a third storage electrode ST3 and a power line PL aligned with the data line DL are arranged on the interlayer insulating film ILD. The auxiliary electrode CE is disposed between the data line DL and the power supply line PL. The first source electrode S1 and the first drain electrode D1 of the switching thin film transistor T1 and the second source electrode S2 and the second drain electrode D1 of the driving thin film transistor T2 are formed on the interlayer insulating film ILD, (D2). The data line DL, the power supply line PL, the auxiliary electrode CE, the first and second source electrodes S1 and S2 and the first and second drain electrodes D1 and D2 are formed of aluminum (Al) A single layer made of any one selected from the group consisting of copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), gold (Au), silver (Ag), tungsten Or multiple layers thereof.

The first source electrode S1 of the switching thin film transistor T1 may extend from the data line DL or may be a part of the data line DL and may be connected to the first interlayer insulating film ILD through the gate insulating film GI, And is arranged to be in contact with the first source region SA1 of the first active layer A1 exposed through the contact hole CH1. The first drain electrode D1 of the switching thin film transistor T1 is formed so as to overlap the gate line GL, the first drain region DA1 of the first active layer A2, and the second gate electrode G2, ILD). The first drain electrode D1 of the switching thin film transistor T1 is connected to the first active layer A1 exposed through the second contact hole CH2 penetrating the interlayer insulating film ILD and the gate insulating film GI, Drain region DA1 and is connected to the second gate electrode G2 of the driving thin film transistor T2 exposed through the third contact hole CH2 penetrating the interlayer insulating film ILD.

The second source electrode S2 of the driving thin film transistor T2 may extend from the power source line PL or may be a part of the power source line PL and may include a fourth And is in contact with the second source region SA2 of the second active layer A2 exposed through the contact hole CH4. The second drain electrode D2 of the driving thin film transistor T2 is disposed on the interlayer insulating film ILD so as to overlap with the second drain region DA2 of the second active layer A2. The second drain electrode D2 of the driving thin film transistor T2 is electrically connected to the second active layer A2 of the second active layer A2 exposed through the fifth contact hole CH5 passing through the interlayer insulating film ILD and the gate insulating film GI. Drain region DA2.

The data line DL, the power supply line PL, the auxiliary electrode CE, the first source electrode S1 and the first drain electrode D1 of the switching thin film transistor T1, the second thin film transistor T2 of the driving thin film transistor T2, A first passivation film PAS1 and a first planarization film PLN1 made of a photosensitive organic film are sequentially stacked on the interlayer insulating film ILD on which the source electrode S2 and the second drain electrode D2 are disposed, do. The first passivation film PAS1 may be formed of an inorganic insulating film such as silicon nitride (SiNx) or silicon oxide (SiOx). The first planarizing film PLN1 is formed of a photosensitive organic film such as photosensitive polyacryl or photosensitive polyimide.

The first planarizing film PLN1 positioned on the first passivation film PAS1 is formed in the pixel region defined by the data line DL, the power supply line PL and the adjacent gate lines GL, And a plurality of sixth contact holes CH6 formed so as to expose the first to sixth contact holes CH6. A region R indicated by a dotted line in Fig. 14A represents an area where a plurality of sixth contact holes CH6 can be formed.

Since the etching process is unnecessary when the first planarizing film PLN1 is formed of a photosensitive organic material, it is not necessary to consider the etch selectivity, and the degree of freedom in material selection can be improved. For example, when the first passivation film PAS1 and the first planarization film PLN1 are formed of an inorganic material, when the first planarization film PLN1 on the first passivation film PAS1 is etched, The first passivation film PAS1 and the first planarization film PLN1 must be formed using silicon nitride and silicon oxide having mutually large etching ratios in order to prevent the first passivation film PAS1 from being damaged. However, if the first planarizing film PLN1 is formed using the photosensitive organic film, it is not necessary to etch the first planarizing film PLN1, so that the etching selectivity for protecting the first passivation film PAS1 becomes unnecessary. Therefore, since both silicon nitride and silicon oxide can be used to form the first passivation film PAS1, the effect of improving the degree of freedom in material selection can be obtained.

A first storage electrode ST1 of the storage capacitor is disposed in a pixel region on the first planarization film PLN1 on which a plurality of sixth contact holes CH6 are formed. Since the first storage electrode ST1 is formed along the inner wall path of the sixth contact holes CH6, the area of the first storage electrode ST1 increases as the number of the sixth contact holes CH6 increases.

A second passivation film PAS2 is disposed on the first planarizing film PLN1 on which the first storage electrode ST1 is located to cover the first storage electrode ST1. The second passivation film PAS2 may be formed of an inorganic insulating film such as silicon nitride (SiNx) or silicon oxide (SiOx) as the first passivation film PAS1. The second passivation film PAS2 has a plurality of recesses along the shape of the sixth contact holes CH6 formed in the first planarizing film PLN1.

The first drain electrode D1 of the switching thin film transistor T1 is electrically connected to the second passivation film PAS2 through the seventh contact hole CH7 passing through the first planarization film PLN1 and the first passivation film PAS1 A part thereof is exposed. The seventh contact hole CH7 also exposes a portion of the first storage electrode ST1 located on the first planarization layer PLN1. The second drain electrode D2 of the driving thin film transistor T2 is connected to the second passivation film PAS2 through the eighth contact hole CH8 passing through the first planarization film PLN1 and the first passivation film PAS1 A part thereof is exposed.

The second storage electrode ST2 is positioned on the second passivation film PAS2 on which the seventh and eighth contact holes CH7 and CH8 are formed so as to face the first storage electrode ST1 of the storage capacitor. A connecting portion CP for connecting the first drain electrode D1 of the switching thin film transistor T1 exposed through the seventh contact hole C7 and the first storage electrode ST1 is formed on the second passivation film PAS2 . The first and second storage electrodes ST1 and ST2 and the connection pattern CP may be formed of a material selected from the group consisting of aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti) A single layer of any one selected from the group consisting of silver (Ag), tungsten (W), and alloys thereof, or a multilayer thereof.

The second storage electrode ST2 is located along the plurality of recesses formed in the second passivation film PAS2 by the sixth contact holes CH6 and CH6 and the first storage electrode ST1 is located along the first passivation film PAS2, Since the first storage electrode ST1 and the second storage electrode ST2 oppose each other along the path of the sixth contact holes CH6 and CH6 formed in the planarization film PLN1, . Therefore, the capacitance of the storage capacitor can be remarkably increased in the pixel region of the same size.

The second planarization layer PLN2 is positioned on the second passivation layer PAS2 where the second storage electrode ST2 and the connection CP are located to cover the second storage electrode ST2 and the connection CP. The second planarizing layer PLN2 may be formed of a photosensitive organic layer such as photosensitive polyacryl or photosensitive polyimide, or may be formed of an inorganic insulating layer. The second planarization layer PLN2 includes a ninth contact hole CH9 that exposes a portion of the second storage electrode ST2.

The anode electrode of the organic light emitting diode is positioned on the second planarizing film PLN2 having the ninth contact hole CH9 so as to be in contact with the second storage electrode ST2 exposed through the ninth contact hole CH9 . An organic light emitting layer (not shown) and a cathode electrode (not shown) are sequentially formed on the anode electrode (AND) to form an organic light emitting diode (OLED of FIG. 1). The anode electrode AND and the cathode electrode may be formed of a metal such as aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), gold (Au), silver (Ag), tungsten The alloy may be selected from the group consisting of alloys. The structure of the upper portion of the anode electrode (AND) can be applied to a well-known structure already known, so further explanation will be omitted in order to avoid complexity of the description.

Next, an organic light emitting display according to a third embodiment of the present invention will be described with reference to FIGS. 15A and 15B. FIG. 15A is a plan view showing one pixel of an OLED display according to another embodiment of the present invention, and FIG. 15B is a cross-sectional view taken along lines I-I and II-II 'of FIG. 15A.

In the organic light emitting display according to the third embodiment of the present invention, as shown in FIGS. 15A and 15B, except for using the first passivation film instead of the planarization film, the organic light emitting display according to the first embodiment of the present invention Is the same as that of the organic electroluminescent display device. Hereinafter, the organic light emitting display according to the third embodiment of the present invention will be described in more detail with reference to FIGS. 15A and 15B.

15A and 15B, an inorganic insulating film such as silicon nitride (SiNx) or silicon oxide (SiOx), or a buffer insulating film BUF made of multiple layers thereof is applied over the substrate SUB, The first active layer A1 and the second active layer A2 spaced apart from each other are disposed on the second active layer BUF. The buffer insulating film BUF may be omitted. The first active layer A1 and the second active layer A2 are semiconductor active layers formed by implanting impurity ions into amorphous silicon (a-Si). The first active layer A1 is composed of a first source region SA1 and a first drain region DA1 arranged with the first active region AA1 therebetween. The second active layer A2 includes a second source region SA2 and a second drain region DA2 disposed with the second active region AA2 interposed therebetween.

A gate insulating film GI is disposed on the first active layer A1 and the second active layer A2 so as to cover and insulate them. The gate insulating film GI may be formed of an inorganic insulating film such as silicon nitride (SiNx), silicon oxide (SiOx), or a multilayer thereof, similar to the buffer layer BUF. On the gate insulating film GI, the gate line GL, the first gate electrode G1, and the second gate electrode G2 are located. The first gate electrode G1 extends from the gate line GL and overlaps at least a part with the first active area AA1 of the first active layer A1. The second gate electrode G2 is disposed apart from the gate line GL and the first gate electrode G1. The gate line GL, the first gate electrode G1 and the second gate electrode G2 may be formed of a metal such as aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti) ), Silver (Ag), tungsten (W), or an alloy thereof, or a multilayer thereof.

An interlayer insulating film ILD is disposed on the gate insulating film GI on which the gate line GL, the first gate electrode T1 and the second gate electrode 120c are disposed to insulate and cover them. The interlayer insulating film (ILD) may be an inorganic insulating film such as silicon nitride (SiNx), silicon oxide (SiOx), or a multilayer thereof.

On the interlayer insulating film ILD, a data line DL and a power source line PL which are in parallel with the data line DL are arranged to intersect the gate line GL. The first source electrode S1 and the first drain electrode D1 of the switching thin film transistor T1 and the second source electrode S2 and the second drain electrode D1 of the driving thin film transistor T2 are formed on the interlayer insulating film ILD, (D2). The data line DL, the power supply line PL, the first and second source electrodes S1 and S2 and the first and second drain electrodes D1 and D2 may be formed of aluminum (Al), copper (Cu) A single layer of any one selected from the group consisting of molybdenum (Mo), chrome (Cr), titanium (Ti), gold (Au), silver (Ag), tungsten (W) Lt; / RTI >

The first source electrode S1 of the switching thin film transistor T1 may extend from the data line DL or may be a part of the data line DL and may be connected to the first interlayer insulating film ILD through the gate insulating film GI, And is arranged to be in contact with the first source region SA1 of the first active layer A1 exposed through the contact hole CH1. The first drain electrode D1 of the switching thin film transistor T1 is formed so as to overlap the gate line GL, the first drain region DA1 of the first active layer A2, and the second gate electrode G2, ILD). The first drain electrode D1 of the switching thin film transistor T1 is connected to the first active layer A1 exposed through the second contact hole CH2 penetrating the interlayer insulating film ILD and the gate insulating film GI, Drain region DA1 and is connected to the second gate electrode G2 of the driving thin film transistor T2 exposed through the third contact hole CH2 penetrating the interlayer insulating film ILD.

 The second source electrode S2 of the driving thin film transistor T2 may extend from the power source line PL or may be a part of the power source line PL and may include a fourth And is in contact with the second source region SA2 of the second active layer A2 exposed through the contact hole CH4. The second drain electrode D2 of the driving thin film transistor T2 is disposed on the interlayer insulating film ILD so as to overlap with the second drain region DA2 of the second active layer A2. The second drain electrode D2 of the driving thin film transistor T2 is electrically connected to the second active layer A2 of the second active layer A2 exposed through the fifth contact hole CH5 passing through the interlayer insulating film ILD and the gate insulating film GI. Drain region DA2.

The first source electrode S1 and the first drain electrode D1 of the switching thin film transistor T1 and the second source electrode S2 of the driving thin film transistor T2 and the data line DL, On the interlayer insulating film ILD on which the second drain electrode D2 is disposed, the first passivation film PAS1 is positioned to cover them. The first passivation film PAS1 may be formed of an inorganic insulating film such as silicon nitride (SiNx) or silicon oxide (SiOx), and should have a high etching selection ratio with respect to the interlayer insulating film (ILD). The first passivation film PAS1 is formed to expose the interlayer insulating film ILD in the pixel region defined by the data line DL, the power source line PL and the adjacent gate lines GL. And contact holes (CH6). The region R indicated by the dotted line in Fig. 15A represents an area where a plurality of sixth contact holes CH6 can be formed.

A first storage electrode ST1 of the storage capacitor is disposed in a pixel region on the first passivation film PAS1 on which a plurality of sixth contact holes CH6 are formed. Since the first storage electrode ST1 is formed along the inner wall path of the sixth contact holes CH6, the area of the first storage electrode ST1 increases as the number of the sixth contact holes CH6 increases.

The second passivation film PAS2 is positioned on the first passivation film PAS1 where the first storage electrode ST1 is located to cover the first storage electrode ST1. The second passivation film PAS2 may be formed of an inorganic insulating film such as silicon nitride (SiNx) or silicon oxide (SiOx) as the first passivation film PAS1. The second passivation film PAS2 has a plurality of recesses along the shape of the sixth contact holes CH6 formed in the first passivation film PAS1.

A part of the first drain electrode D1 of the switching thin film transistor T1 is exposed through the seventh contact hole CH7 passing through the second passivation film PAS2 and the first passivation film PAS2. The seventh contact hole CH7 also exposes a portion of the first storage electrode ST1 located on the first passivation film PAS1. The second drain electrode D2 of the driving thin film transistor T2 is partially exposed through the second passivation film PAS2 and the eighth contact hole CH8 passing through the first passivation film PAS1.

The second storage electrode ST2 is positioned on the second passivation film PAS2 on which the seventh and eighth contact holes CH7 and CH8 are formed so as to face the first storage electrode ST1 of the storage capacitor. A connecting portion CP for connecting the first drain electrode D1 of the switching thin film transistor T1 exposed through the seventh contact hole C7 and the first storage electrode ST1 is formed on the second passivation film PAS2 . The first and second storage electrodes ST1 and ST2 and the connection pattern CP may be formed of a material selected from the group consisting of aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti) A single layer of any one selected from the group consisting of silver (Ag), tungsten (W), and alloys thereof, or a multilayer thereof.

The second storage electrode ST2 is located along the plurality of recesses formed in the second passivation film PAS2 by the sixth contact holes CH6 and CH6 and the first storage electrode ST1 is located along the first passivation film PAS2, Since the first storage electrode ST1 and the second storage electrode ST2 oppose each other along the path of the sixth contact holes CH6 and CH6 formed on the passivation film PAS1, . Therefore, the capacitance of the storage capacitor can be remarkably increased in the pixel region of the same size.

The planarization layer PLN is positioned on the second passivation layer PAS2 where the second storage electrode ST2 and the connection portion CP are located to cover the second storage electrode ST2 and the connection portion CP. The planarizing film PLN may be formed of a photosensitive organic film such as photosensitive polyacryl or photosensitive polyimide, or may be formed of an inorganic insulating film. The planarizing film PLN2 includes a ninth contact hole CH9 that exposes a portion of the second storage electrode ST2.

The anode electrode of the organic light emitting diode is positioned on the planarization layer PLN where the ninth contact hole CH9 is formed so as to be in contact with the second storage electrode ST2 exposed through the ninth contact hole CH9. An organic light emitting layer (not shown) and a cathode electrode (not shown) are sequentially formed on the anode electrode (AND) to form an organic light emitting diode (OLED of FIG. 1). The anode electrode AND and the cathode electrode may be formed of a metal such as aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), gold (Au), silver (Ag), tungsten The alloy may be selected from the group consisting of alloys. The structure of the upper portion of the anode electrode (AND) can be applied to a well-known structure already known, so further explanation will be omitted in order to avoid complexity of the description.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

SUB: Substrate BUF: Buffer insulation film
T1: switching thin film transistor T2: driving thin film transistor
A1, A2: active layer AA1, AA2: active region
DA1, DA2: drain region SA1, SA2: source region
GL: gate line G1, G2: gate electrode
GI: gate insulating film DL: data line
PL: power supply line D1, D2: drain electrode
S1, S2: Source electrode ILD: Interlayer insulating film
PLN, PLN1, PLN2: planarization film PAS: passivation film
ST1, ST2: storage electrode CP: connection portion
CE: auxiliary electrode

Claims (10)

A pixel region defined by a gate line on a substrate, a data line and a power source line intersecting with the gate line and arranged in parallel to each other;
At least two thin film transistors disposed on the substrate;
A first insulating layer covering the at least two thin film transistors and having at least one hole;
A first storage electrode disposed on the first insulating film so as to have a bent portion along the at least one hole inner surface;
A second storage electrode arranged to overlap the first storage electrode with a second insulating film having a bent portion corresponding to an inner surface of the hole of the first insulating film interposed therebetween;
A first electrode arranged to overlap the second storage electrode with a third insulating film interposed therebetween; And
And a second electrode arranged to overlap the first electrode with an organic light emitting layer interposed therebetween.
The method according to claim 1,
Further comprising an interlayer insulating film for insulating the gate electrode and the source and drain electrodes of each thin film transistor,
Wherein the first insulating film is made of a photosensitive organic material, the interlayer insulating film is made of an inorganic insulating material, the second insulating film is made of an inorganic insulating material, and the third insulating film is made of a photosensitive organic material or an inorganic insulating material Wherein the organic electroluminescent display device comprises:
The method according to claim 1,
Further comprising an interlayer insulating film for insulating the gate electrode and the source and drain electrodes of each thin film transistor,
Wherein the first insulating film is made of an inorganic insulating material, and the interlayer insulating film is made of another inorganic insulating material having a high etch selectivity with respect to the inorganic insulating material, and the second insulating film is made of the inorganic insulating material or the other inorganic insulating material And the third insulating film is made of any one of a photosensitive organic material, the inorganic insulating material, and the other inorganic insulating material.
The method according to claim 1,
Wherein the at least two thin film transistors comprise:
A first active layer disposed on the substrate;
A first gate electrode disposed on a gate insulating film covering the first active layer,
A gate insulating film formed on the gate insulating film, the gate insulating film being formed on the gate insulating film, the gate insulating film being formed on the gate insulating film, 1 source electrode,
And a first drain electrode connected to the first drain region of the first active layer exposed through the second contact hole passing through the interlayer insulating film and the gate insulating film. An electroluminescent display device.
5. The method of claim 4,
Wherein the at least two thin film transistors comprise:
A second active layer spaced apart from the first active layer and disposed on the substrate,
A second gate electrode disposed on the gate insulating film covering the second active layer and spaced apart from the first gate electrode;
And a gate insulating film formed on the gate insulating film and connected to a second source region of the second active layer exposed through a fourth contact hole passing through the interlayer insulating film and the gate insulating film, A second source electrode,
And a second drain electrode connected to the second drain region of the second active layer exposed through the fifth contact hole passing through the interlayer insulating film and the gate insulating film. An electroluminescent display device.
5. The method of claim 4,
Wherein the first storage electrode is connected to the first drain electrode exposed through the seventh contact hole passing through the second insulating film and the first insulating film.
6. The method of claim 5,
And the second storage electrode is connected to the second drain electrode exposed through the eighth contact hole passing through the second insulating film and the first insulating film.
8. The method of claim 7,
Wherein the first electrode is connected to the second storage electrode exposed through a ninth contact hole passing through the third insulating film.
9. The method of claim 8,
Wherein the first drain electrode is connected to the second gate electrode exposed through a third contact hole passing through the interlayer insulating film.
3. The method of claim 2,
An auxiliary electrode disposed on the interlayer insulating film in parallel with the data line and the power supply line; And
Further comprising a fourth insulating layer covering source and drain electrodes of the data line, the power supply line, the auxiliary electrode, and each thin film transistor and disposed under the first insulating layer,
Wherein the fourth insulating film is made of an inorganic insulating material.

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