KR102329158B1 - Organic light emitting device - Google Patents

Abstract

The present invention relates to an organic light emitting display device capable of maintaining the capacitance of a capacitor even in a high resolution organic light emitting display device, wherein a pixel area defined by a data line and a power line intersecting a gate line and arranged in parallel with each other, at least It includes two thin film transistors, a first insulating layer, a first storage electrode, a second storage electrode, a first electrode, and a second electrode. The first insulating layer covers at least two thin film transistors and has at least one hole. The first storage electrode is disposed on the first insulating layer to have a curved portion along the inner surface of the at least one hole. The second storage electrode is disposed to overlap the first storage electrode with a second insulating layer having a curved portion corresponding to an inner surface of the hole of the first insulating layer interposed therebetween. The first electrode is disposed to overlap with the second storage electrode and the third insulating layer therebetween. The second electrode is disposed to overlap the first electrode with the organic light emitting layer interposed therebetween.

Description

Organic electroluminescence display {ORGANIC LIGHT EMITTING DEVICE}

The present invention relates to an organic electroluminescent display, and more particularly, to an organic electroluminescent display capable of realizing a high resolution by securing a high capacitance in a limited area.

Recently, various flat panel display devices capable of reducing weight and volume, which are disadvantages of a cathode ray tube (CRT), have been developed. Examples of the flat panel display include a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), and an organic electroluminescence display (OLED). : Organic Light Emitting Display), etc. Among these flat panel displays, organic light emitting displays (OLEDs) are self-luminous display devices that emit light by excitation of organic compounds. This has the advantage of simplifying it. In addition, the organic light emitting display device is widely used in that it can be manufactured at a low temperature, has a high response speed with a response speed of 1 ms or less, and has characteristics such as low power consumption, wide viewing angle, and high contrast. have.

The organic electroluminescent display includes an organic light emitting diode (OLED) that converts electric energy into light energy. An organic light emitting diode includes an anode electrode, a cathode electrode, and an organic light emitting layer disposed between the electrodes. Holes are injected from the anode electrode and electrons are injected from the cathode electrode. Holes injected through the anode electrode and the cathode electrode, respectively, and when injected into an organic emission layer (EML) form excitons, which are excitons, and the excitons emit energy while emitting light.

Such an organic light emitting display device includes a switching thin film transistor and a driving thin film transistor for each pixel in order to apply a driving signal to the anode of the display area. The switching thin film transistor drives a pixel by receiving a signal from a gate line and a data line.

In recent years, as a high resolution is required along with an enlargement of a display device, a pixel size tends to become smaller. One pixel is partitioned by the intersection of a gate line, a data line, and a common power line, and a switching thin film transistor, a driving thin film transistor, a capacitor, and an organic light emitting diode are formed in this pixel. In this configuration, when the pixel size is reduced, the thin film transistors and the above-described lines are integrated and disposed very closely. Therefore, in the conventional high-resolution organic light emitting display device, there is a problem in that the capacitance of the capacitor is insufficient because the area of the capacitor is reduced.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an organic electroluminescent display capable of maintaining the capacitance of a capacitor even in a high-resolution organic electroluminescent display.

The organic light emitting display device of the present invention for achieving the above object is a pixel area defined by a data line and a power line intersecting a gate line and arranged in parallel with each other, at least two thin film transistors, a first insulating film, and a first storage an electrode, a second storage electrode, a first electrode, and a second electrode. The first insulating layer covers at least two thin film transistors and has at least one hole. The first storage electrode is disposed on the first insulating layer to have a curved portion along the inner surface of the at least one hole. The second storage electrode is disposed to overlap the first storage electrode with a second insulating layer having a curved portion corresponding to an inner surface of the hole of the first insulating layer interposed therebetween. The first electrode is disposed to overlap with the second storage electrode and the third insulating layer therebetween. The second electrode is disposed to overlap the first electrode with the organic light emitting layer interposed therebetween.

The organic electroluminescent display device of the present invention further includes an interlayer insulating film that insulates the gate electrode and the source and drain electrodes of each thin film transistor. The first insulating layer may be made of a photosensitive organic material, the interlayer insulating layer may be made of an inorganic insulating material, the second insulating layer may be made of an inorganic insulating material, and the third insulating layer may be made of a photosensitive organic material or an inorganic insulating material.

The organic electroluminescent display device of the present invention further includes an interlayer insulating film that insulates the gate electrode and the source and drain electrodes of each thin film transistor. The first insulating layer is made of an inorganic insulating material, and the interlayer insulating layer is made of another inorganic insulating material having a high etch selectivity with respect to the inorganic insulating material. The second insulating layer may be made of the inorganic insulating material or the other inorganic insulating material, and the third insulating layer may be made of any one of the photosensitive organic material, the inorganic insulating material, and the other inorganic material.

In the above configuration, the at least two thin film transistors include a first active layer, a first gate electrode, a first source electrode, and a first drain electrode. A first active layer is disposed on the substrate. The first gate electrode is disposed on the gate insulating layer covering the first active layer. The first source electrode is disposed to be spaced apart from each other on an interlayer insulating layer covering the first gate electrode, and is connected to a first source region of the first active layer exposed through a first contact hole penetrating the interlayer insulating layer and the gate insulating layer. . The first drain electrode is connected to a first drain region of the first active layer exposed through a second contact hole penetrating the interlayer insulating layer and the gate insulating layer.

Alternatively, the at least two thin film transistors include a second active layer, a second gate electrode, a second source electrode, and a second drain electrode. The second active layer is disposed on the substrate to be spaced apart from the first active layer. The second gate electrode is disposed on the gate insulating layer covering the second active layer to be spaced apart from the first gate electrode. The second source electrode is disposed to be spaced apart from each other on the interlayer insulating layer covering the second gate electrode, and is connected to the second source region of the second active layer exposed through the interlayer insulating layer and a fourth contact hole penetrating the gate insulating layer. do. The first drain electrode is connected to a second drain region of the second active layer exposed through a fifth contact hole penetrating the interlayer insulating layer and the gate insulating layer.

The first storage electrode is connected to the second insulating layer and the first drain electrode exposed through a seventh contact hole penetrating the first insulating layer.

The second storage electrode is connected to the second drain electrode exposed through an eighth contact hole penetrating the second insulating layer and the first insulating layer.

The first electrode is connected to the second storage electrode exposed through a ninth contact hole penetrating the third insulating layer.

The first drain electrode is connected to the second gate electrode exposed through a third contact hole penetrating the interlayer insulating layer and the gate insulating layer.

The organic light emitting display device of the present invention also covers the auxiliary electrode disposed on the interlayer insulating film in parallel with the data line and the power line, and the data line, the power line, the auxiliary electrode, and the source and drain electrodes of each thin film transistor. It further includes a fourth insulating layer disposed under the first insulating layer, the fourth insulating layer may be made of an inorganic insulating material.

According to the organic light emitting display device according to the present invention, the first storage electrode is positioned along the path of the at least one contact hole formed in the insulating layer thereunder, and the second storage electrode is the first storage electrode on the insulating layer covering the first storage electrode. Since the first storage electrode is disposed to face each other, the opposing area of the first storage electrode and the second storage electrode facing each other is significantly increased. Accordingly, the effect of remarkably increasing the capacitance of the storage capacitor in the pixel area of the same size can be obtained.

In addition, according to the organic light emitting display device according to the present invention, since the etching process is unnecessary by using the photosensitive organic material as the insulating film covering the thin film transistor, there is no need to consider the etching selectivity for the lower insulating film. The effect of improving the degree of freedom can be obtained.

1 is an equivalent circuit diagram showing one pixel of an organic electroluminescence display according to an embodiment of the present invention;
2 is a plan view illustrating one pixel of an organic light emitting display device according to an embodiment of the present invention;
Fig. 3 is a cross-sectional view taken along lines II and II-II' in Fig. 2;
4A is a plan view illustrating a first mask process of an organic light emitting display device according to an embodiment of the present invention;
Fig. 4b is a cross-sectional view taken along lines II and II-II' in Fig. 4a;
5A is a plan view illustrating a second mask process of an organic light emitting display device according to an embodiment of the present invention;
Fig. 5b is a cross-sectional view taken along lines II and II-II' in Fig. 5a;
6A is a plan view illustrating a third mask process of an organic light emitting display device according to an embodiment of the present invention;
Fig. 6b is a cross-sectional view taken along lines II and II-II' in Fig. 6a;
7A is a plan view illustrating a fourth mask process of an organic light emitting display device according to an embodiment of the present invention;
Fig. 7b is a cross-sectional view taken along lines II and II-II' in Fig. 7a;
8A is a plan view illustrating a fifth mask process of an organic light emitting display device according to an embodiment of the present invention;
Fig. 8b is a cross-sectional view taken along lines II and II-II' in Fig. 8a;
9A is a plan view illustrating a sixth mask process of an organic light emitting display device according to an embodiment of the present invention;
Fig. 9B is a cross-sectional view taken along lines II and II-II' in Fig. 9A;
10A is a plan view illustrating a seventh mask process of an organic light emitting display device according to an embodiment of the present invention;
Fig. 10B is a cross-sectional view taken along lines II and II-II' of Fig. 10A;
11A is a plan view illustrating an eighth mask process of an organic light emitting display device according to an embodiment of the present invention;
Fig. 11B is a cross-sectional view taken along lines II and II-II' in Fig. 11A;
12A is a plan view illustrating a ninth mask process of an organic electroluminescent display device according to an embodiment of the present invention;
Fig. 12b is a cross-sectional view taken along lines II and II-II' in Fig. 12a;
13A is a plan view illustrating a tenth mask process of an organic electroluminescent display device according to an embodiment of the present invention;
13B is a cross-sectional view taken along lines II and II-II' in FIG. 13A;
14A is a plan view illustrating one pixel of an organic light emitting diode display according to another embodiment of the present invention;
Fig. 14B is a cross-sectional view taken along lines II and II-II' of Fig. 14A;
15A is a plan view illustrating one pixel of an organic light emitting diode display according to another embodiment of the present invention;
Fig. 15B is a cross-sectional view taken along lines II and II-II' of Fig. 15A;

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals refer to substantially identical elements throughout. In the following description, if it is determined that a detailed description of known content or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

An organic electroluminescence display according to an embodiment of the present invention will be described with reference to FIGS. 1 to 3 . 1 is an example of a circuit diagram illustrating one pixel of an organic light emitting display device according to an embodiment of the present invention, and FIG. 2 is a plan view showing one pixel of an organic light emitting display device according to an embodiment of the present invention, FIG. 3 is a cross-sectional view taken along lines II and II-II' in FIG. 2 .

First, referring to FIG. 1 , one pixel of the organic light emitting display device according to an embodiment of the present invention includes a cell driver DU connected to a gate line GL, a data line DL, and a power line PL, and , an organic light emitting diode OLED connected between the cell driver DU and the ground GND.

The cell driver DU includes a switching thin film transistor T1 , a driving thin film transistor T2 , and a storage capacitor Cst. The switching thin film transistor T1 includes a gate electrode connected to the gate line GL, a source electrode connected to the data line DL, and a drain electrode connected to the first node n1 . The driving thin film transistor T2 includes a source electrode connected to the power line PL, a gate electrode connected to the first node n1 , and a drain electrode connected to the second node n2 . The storage capacitor Cst includes a first electrode connected to the first node n1 and a second electrode connected to the second node n2 . A drain electrode of the switching thin film transistor T1 , a gate electrode of the driving thin film transistor T2 , and a first electrode of the storage capacitor Cst are connected to the first node n1 . The drain electrode of the driving thin film transistor T2 , the second electrode of the capacitor Cst, and the anode electrode of the organic light emitting diode OLED are connected to the second node n2 .

The organic light emitting diode OLED is connected between the second node n2 of the cell driver DU and the ground GND.

In this configuration, the switching thin film transistor T1 is turned on when a scan pulse is supplied to the gate line GL, and transmits the data signal supplied to the data line DL to the storage capacitor C and the driving thin film transistor T2 . supplied to the gate electrode of The driving thin film transistor T2 controls the current I supplied from the power line PL to the organic light emitting diode OLED in response to a data signal supplied to the gate electrode, thereby controlling the amount of light emitted by the organic light emitting diode OLED. do. In addition, even when the switching thin film transistor T1 is turned off, the driving thin film transistor T2 by the voltage charged in the storage capacitor Cst supplies a constant current I until the data signal of the next frame is supplied to induce It keeps the light emitting diode (OLED) emitting light.

2 and 3, on the substrate SUB, an inorganic insulating film such as silicon nitride (SiNx) or silicon oxide (SiOx) or a buffer insulating film (BUF) made of multiple layers thereof is coated over the entire surface, and the buffer insulating film ( A first active layer A1 and a second active layer A2 spaced apart from each other are disposed on the BUF. The buffer insulating layer BUF may be omitted. The first active layer A1 and the second active layer A2 are semiconductor active layers formed by implanting impurity ions into amorphous silicon (a-Si). The first active layer A1 includes a first source area SA1 and a first drain area DA1 disposed with the first active area AA1 interposed therebetween. The second active layer A2 includes a second source area SA2 and a second drain area DA2 disposed with the second active area AA2 interposed therebetween.

A gate insulating layer GI is disposed on the first active layer A1 and the second active layer A2 to cover and insulate them. Similar to the buffer layer BUF, the gate insulating layer GI may be formed of an inorganic insulating layer such as silicon nitride (SiNx) or silicon oxide (SiOx), or a multilayer thereof. A gate line GL, a first gate electrode G1, and a second gate electrode G2 are positioned on the gate insulating layer GI. The first gate electrode G1 extends from the gate line GL and at least partially overlaps the first active area AA1 of the first active layer A1 . The second gate electrode G2 is spaced apart from the gate line GL and the first gate electrode G1 . The gate line GL, the first gate electrode G1 and the second gate electrode G2 are formed of aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), and gold (Au). ), silver (Ag), tungsten (W), or a single layer made of any one selected from the group consisting of alloys thereof or may be made of multiple layers thereof.

An interlayer insulating layer ILD is disposed on the gate insulating layer GI on which the gate line GL, the first gate electrode G1, and the second gate electrode G2 are disposed to insulate and cover them. The interlayer insulating layer ILD may be formed of an inorganic insulating layer such as silicon nitride (SiNx) or silicon oxide (SiOx), or a multilayer thereof.

A data line DL crossing the gate line GL and a power line PL parallel to the data line DL are disposed on the interlayer insulating layer ILD. The first source electrode S1 and the first drain electrode D1 of the switching thin film transistor T1 and the second source electrode S2 and the second drain electrode of the driving thin film transistor T2 are also formed on the interlayer insulating film ILD. (D2) is placed. The data line DL, the power line PL, the first and second source electrodes S1 and S2 and the first and second drain electrodes D1 and D2 are formed of aluminum (Al), copper (Cu), Molybdenum (Mo), chromium (Cr), titanium (Ti), gold (Au), silver (Ag), tungsten (W) or a single layer consisting of any one selected from the group consisting of alloys or multiple layers thereof can be done

The first source electrode S1 of the switching thin film transistor T1 may extend from the data line DL or may be a part of the data line DL, and the first source electrode S1 of the switching thin film transistor T1 may pass through the interlayer insulating layer ILD and the gate insulating layer GI. It is disposed to contact the first source area SA1 of the first active layer A1 exposed through the contact hole CH1. The first drain electrode D1 of the switching thin film transistor T1 has an interlayer insulating layer so as to overlap the gate line GL, the first drain region DA1 of the first active layer A2, and the second gate electrode G2. ILD). The first drain electrode D1 of the switching thin film transistor T1 is the first of the first active layer A1 exposed through the second contact hole CH2 penetrating the interlayer insulating layer ILD and the gate insulating layer GI. It is connected to the drain region DA1 and is connected to the second gate electrode G2 of the driving thin film transistor T2 exposed through the third contact hole CH3 penetrating the interlayer insulating layer ILD.

The second source electrode S2 of the driving thin film transistor T2 may extend from the power line PL or may be a part of the power line PL, and may be a fourth source electrode S2 passing through the interlayer insulating layer ILD and the gate insulating layer GI. It is disposed to contact the second source area SA2 of the second active layer A2 exposed through the contact hole CH4. The second drain electrode D2 of the driving thin film transistor T2 is disposed on the interlayer insulating layer ILD to overlap the second drain region DA2 of the second active layer A2 . The second drain electrode D2 of the driving thin film transistor T2 is the second active layer A2 exposed through the fifth contact hole CH5 penetrating the interlayer insulating layer ILD and the gate insulating layer GI. It is connected to the drain region DA2.

The data line DL, the power line PL, the first source electrode S1 and the first drain electrode D1 of the switching thin film transistor T1, the second source electrode S2 of the driving thin film transistor T2, and On the interlayer insulating film ILD on which the second drain electrode D2 is disposed, the first planarization film PLN1 is positioned to cover them. The first planarization layer PLN1 is made of a photosensitive organic layer such as photosensitive polyacryl or polyimide. The first planarization layer PLN1 is formed to expose the interlayer insulating layer ILD in the pixel area defined by the data line DL, the power line PL, and the adjacent gate lines GL. 6 contact holes CH6 are included. A region R indicated by a dotted line in FIG. 2 represents a region in which a plurality of sixth contact holes CH6 may be formed.

When the first planarization layer PLN1 is formed of the photosensitive organic material, an etching process is not required, and thus, it is not necessary to consider an etching selectivity, thereby improving the degree of freedom in material selection. For example, when the interlayer insulating layer ILD and the first planarization layer PLN1 are formed of an inorganic material, the interlayer insulating layer ILD is damaged when the first planarization layer PLN1 on the interlayer insulating layer ILD is etched. In order to prevent this, the interlayer insulating layer ILD and the first planarization layer PLN1 should be respectively formed using silicon nitride and silicon oxide having a high mutual etch ratio. However, when the first planarization layer PLN1 is formed using the photosensitive organic layer, it is not necessary to etch the first planarization layer PLN1 , and thus it becomes unnecessary to select an etch rate for protecting the interlayer insulating layer ILD. Therefore, since both silicon nitride and silicon oxide can be used to form the interlayer insulating layer ILD, the degree of freedom in material selection can be improved.

A first storage electrode ST1 of a storage capacitor is disposed in the pixel region on the first planarization layer PLN1 in which the plurality of sixth contact holes CH6 are formed. Since the first storage electrode ST1 is formed along the inner wall path of the plurality of sixth contact holes CH6, an area thereof increases as the number of the sixth contact holes CH6 increases.

A passivation layer PAS is disposed on the first planarization layer PLN1 on which the first storage electrode ST1 is positioned to cover the first storage electrode ST1 . The passivation layer PAS may be formed of an inorganic insulating layer such as silicon nitride (SiNx) or silicon oxide (SiOx). The passivation layer PAS has a plurality of concave portions along the shape of the sixth contact holes CH6 formed in the first planarization layer PLN1 .

A portion of the first drain electrode D1 of the switching thin film transistor T1 is exposed through the seventh contact hole CH7 penetrating the passivation layer PAS and the first planarization layer PLN1 . The seventh contact hole CH7 also exposes a portion of the first storage electrode ST1 positioned on the first planarization layer PLN1 . A portion of the second drain electrode D2 of the driving thin film transistor T2 is exposed through the eighth contact hole CH8 penetrating the passivation layer PAS and the first planarization layer PLN1 .

The second storage electrode ST2 is positioned to face the first storage electrode ST1 of the storage capacitor on the passivation layer PAS in which the seventh and eighth contact holes CH7 and CH8 are formed. A connection part CP connecting the first drain electrode D1 of the switching thin film transistor T1 exposed through the seventh contact hole C7 and the first storage electrode ST1 is also disposed on the passivation layer PAS. . The first and second storage electrodes ST1 and ST2 and the connection pattern CP may include aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), gold (Au), It may be selected from the group consisting of silver (Ag), tungsten (W), or an alloy thereof.

The second storage electrode ST2 is positioned along the plurality of concave portions formed in the passivation layer PAS by the plurality of sixth contact holes CH6 and CH6, and the first storage electrode ST1 is disposed along the first planarization layer. Since they are positioned along paths of the plurality of sixth contact holes CH6 and CH6 formed in PLN1 , the facing areas of the first storage electrode ST1 and the second storage electrode ST2 facing each other are significantly increased. . Accordingly, the effect of remarkably increasing the capacitance of the storage capacitor in the pixel area of the same size can be obtained.

A second planarization layer PLN2 is disposed on the passivation layer PAS in which the second storage electrode ST2 and the connection part CP are positioned to cover the second storage electrode ST2 and the connection part CP. The second planarization layer PLN2 is made of a photosensitive organic layer such as photosensitive polyacrylic or photosensitive polyimide. The second planarization layer PLN2 includes a ninth contact hole CH9 exposing a portion of the second storage electrode ST2 .

The anode electrode AND of the organic light emitting diode is positioned on the second planarization layer PLN2 in which the ninth contact hole CH9 is formed to contact the second storage electrode ST2 exposed through the ninth contact hole CH9. . An organic light emitting layer (not shown) and a cathode (not shown) are sequentially formed on the anode electrode AND to form an organic light emitting diode (OLED of FIG. 1 ). The anode electrode (AND) and the cathode electrode are aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), gold (Au), silver (Ag), tungsten (W) or these It may be selected from the group consisting of alloys of A known configuration that is already known may be applied to the configuration of the upper portion of the anode electrode AND, and thus, further description will be omitted to avoid complication of the description.

Next, a method of manufacturing an organic light emitting display device according to an exemplary embodiment of the present invention will be described with reference to FIGS. 4A to 13B . Hereinafter, for convenience of description, one pixel region of the organic light emitting display device will be mainly described.

4A is a plan view illustrating a first mask process of an organic light emitting display device according to an embodiment of the present invention, and FIG. 4B is a cross-sectional view taken along lines I-I and II-II' of FIG. 4A.

4A and 4B, after depositing a buffer insulating layer and a semiconductor material on the entire surface of the substrate SUB through, for example, a sputtering process, the first active layer and the second active layer are disposed to be spaced apart from each other. form a layer

More specifically, a buffer layer made of an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) on the entire surface of the substrate SUB through a sputtering process, and a semiconductor such as amorphous silicon (a-Si) A semiconductor layer made of a material and a first photoresist are sequentially deposited, and then a photolithography process using a first mask is performed to form a first photoresist pattern (not shown) exposing the semiconductor layer. And after removing the semiconductor layer exposed by the first photoresist pattern, the first active layer A1 and the second active layer A2 spaced apart from each other on the buffer layer BUF by ashing the remaining first photoresist pattern to form The buffer layer BUF may be omitted.

The first active layer A1 and the second active layer A2 are semiconductor active layers formed by implanting impurity ions into amorphous silicon (a-Si). The first active layer A1 includes a first source area SA1 and a first drain area DA1 disposed with the first active area AA1 interposed therebetween. The second active layer A2 includes a second source area SA2 and a second drain area DA2 disposed with the second active area AA2 interposed therebetween.

5A is a plan view illustrating a second mask process of an organic electroluminescent display device according to an embodiment of the present invention, and FIG. 5B is a cross-sectional view taken along lines I-I and II-II' of FIG. 5A.

5A and 5B , a gate insulating material and a first metal material are sequentially deposited on the buffer layer BUF on which the first active layer A1 and the second active layer A2 are formed, for example, through a sputtering process. After deposition, the gate metal layer including the gate line GL and the first and second gate electrodes G1 and G2 is formed by patterning the first metal material using a second mask process.

More specifically, a gate insulating material, a first metal material, and a second photoresist are entirely deposited on the buffer layer BUF on which the first active layer A1 and the second active layer A2 are formed through a sputtering process. . Then, by performing a photolithography process using the second mask, a second photoresist pattern (not shown) exposing portions of the first metal material is formed. After the first metal material exposed by the second photoresist pattern is removed through etching, the remaining second photoresist pattern is ashed on the gate line GL and the first and second materials on the gate insulating material GI. A gate metal layer including the gate electrodes G1 and G2 is formed. The first gate electrode G1 extends from the gate line GL and at least partially overlaps the first active area AA1 of the first active layer A1 . On the other hand, the second gate electrode G2 is spaced apart from the gate line GL and the first gate electrode G1 .

The gate insulating layer GI may be formed of an inorganic insulating layer such as silicon nitride (SiNx) or silicon oxide (SiOx), or a multilayer thereof. The first metal material is made of aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), gold (Au), silver (Ag), tungsten (W), or an alloy thereof. It may be made of a single layer made of any one selected from the group or a multilayer made of these.

6A is a plan view illustrating a third mask process of an organic electroluminescent display device according to an embodiment of the present invention, and FIG. 6B is a cross-sectional view taken along lines I-I and II-II' of FIG. 6A.

6A and 6B, the gate line GL and the first and second gate electrodes G1 and G2 are formed on the gate insulating film GI to insulate and cover them, for example, through a sputtering process. After the ILD is formed, first to fifth contact holes CH1 to CH5 are formed using a third mask process.

Specifically, an interlayer insulating layer (ILD) and a third photoresist are deposited through, for example, a sputtering process on the gate insulating layer GI on which the gate line GL and the first and second gate electrodes G1 and G2 are formed. Thereafter, by performing a photolithography process using a third mask, the first, second, fourth and fifth contact holes CH1, CH2, CH4, and CH5 passing through the interlayer insulating layer ILD and the gate insulating layer GI are performed. and a third contact hole CH3 penetrating the interlayer insulating layer ILD. Thereafter, by ashing the remaining third photoresist pattern, the interlayer insulating layer ILD in which the first to fifth contact holes CH1 to CH5 are formed is formed. The interlayer insulating layer ILD may include an inorganic insulating layer such as silicon nitride (SiNx) or silicon oxide (SiOx), or a multilayer thereof.

The first contact hole CH1 exposes the first source area SA1 of the first active layer A1, and the second contact hole CH2 exposes the first drain area DA1 of the first active layer A1. to expose In addition, the third contact hole CH3 exposes the second gate electrode G2 of the second active layer A2 , and the fourth contact hole CH4 exposes the second source region SA2 of the second active layer A2 . ) is exposed. The fifth contact hole CH5 exposes the second drain region DA2 of the second active layer A2 .

7A is a plan view illustrating a fourth mask process of an organic electroluminescent display device according to an embodiment of the present invention, and FIG. 7B is a cross-sectional view taken along lines I-I and II-II' of FIG. 7A.

7A and 7B, a source/drain metal material as a second metal material is deposited on the interlayer insulating layer ILD in which the first to fifth contact holes CH1 to CH5 are formed through, for example, a sputtering process. Then, the data line DL, the power line PL, the first source electrode S1 and the first drain electrode D1 of the switching thin film transistor T1, and the driving thin film transistor T2 using a fourth mask process A second source electrode S2 and a second drain electrode D2 of

More specifically, a source/drain metal material as a second metal material and a fourth photoresist are deposited on the interlayer insulating layer ILD in which the first to fifth contact holes CH1 to CH5 are formed, for example, through a sputtering process. Then, a fourth photoresist pattern (not shown) exposing the source/drain metal material is formed by performing a photolithography process using the fourth mask. The data line DL, the power line PL, and the switching thin film transistor T1 are formed by ashing the fourth photoresist pattern remaining after the source/drain metal material exposed through the fourth photoresist pattern is removed through etching. A source/drain electrode layer including a first source electrode S1 and a first drain electrode D1 of the driving thin film transistor T2 and a second source electrode S2 and a second drain electrode D2 of

The second metal material is made of aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), gold (Au), silver (Ag), tungsten (W), or an alloy thereof. It may consist of a single layer made of any one selected from the group or a multilayer made of these.

The data line DL and the power line PL are parallel to each other and are arranged in a direction crossing the gate line GL. The first source electrode S1 of the switching thin film transistor T1 may extend from the data line DL and is connected to the first source region SA1 exposed through the first contact hole CH1 . The first drain electrode D1 of the switching thin film transistor T1 is connected to the first drain region DA1 exposed through the second contact hole CH2 and the driving thin film exposed through the third contact hole CH3 It is connected to the second gate electrode G2 of the transistor T2. The second source electrode S2 of the driving thin film transistor T2 may extend from the power line PL and is connected to the exposed second source region SA2 through the fourth contact hole CH4 . The second drain electrode D2 of the driving thin film transistor T2 is connected to the second drain region DA2 exposed through the fifth contact hole CH5.

8A is a plan view illustrating a fifth mask process of an organic electroluminescent display device according to an embodiment of the present invention, and FIG. 8B is a cross-sectional view taken along lines I-I and II-II' of FIG. 8A.

Referring to FIGS. 8A and 8B , after depositing a first planarization layer PLN1 made of a photosensitive organic layer through, for example, a spin coating process on the interlayer insulating layer ILD on which the source/drain electrode layers are formed, a fifth A plurality of sixth contact holes CH6 and CH6 are formed using a mask process.

More specifically, it includes a data line DL, a power line PL, a first source electrode S1, a first drain electrode D1, a second source electrode S2, and a second drain electrode D2. A first planarization layer PLN1 made of a photosensitive organic layer and a fifth photoresist are sequentially deposited on the interlayer insulating layer ILD on which the source/drain electrodes are formed through, for example, a spin coating process. Then, a fifth mask process is performed to form a fifth photoresist pattern (not shown) exposing portions of the interlayer insulating layer. After the first planarization layer PLN1 exposed by the fifth photoresist pattern is removed by photosensitizing, the fifth photoresist pattern is ashed, thereby exposing portions of the interlayer insulating layer to the plurality of sixth contact holes CH6 and CH6 ) to form When the first planarization layer PLN1 is formed of a photosensitive organic material such as photosensitive polyacrylic or photosensitive polyimide, the deposition and pattern formation process of the fifth photoresist can be omitted and the photosensitive organic layer can be directly photosensitized to form a pattern. simplifies and reduces costs. In addition, since the etching process is unnecessary, there is no need to consider the etching selectivity, so that the degree of freedom in material selection of the interlayer insulating layer (ILD) can be improved.

9A is a plan view illustrating a sixth mask process of an organic electroluminescent display device according to an embodiment of the present invention, and FIG. 9B is a cross-sectional view taken along lines I-I and II-II' of FIG. 9A.

9A and 9B , after depositing a third metal material through a sputtering process, for example, on the first planarization layer PLN1 in which the plurality of sixth contact holes CH6 and CH6 are formed, the third metal material is deposited. 6 The first storage electrode ST1 of the storage capacitor is formed using a mask process.

More specifically, a third metal material and a sixth photoresist are sequentially deposited on the first planarization layer PLN1 in which the plurality of sixth contact holes CH6 and CH6 are formed, for example, through a sputtering process. Then, a photolithography process using the sixth mask is performed to form a sixth photoresist pattern (not shown) exposing the third metal material. After the third metal material exposed by the sixth photoresist pattern is removed through etching, the remaining sixth photoresist pattern is ashed to form the first storage electrode ST1 of the storage capacitor located in the pixel region. Since the first storage electrode ST1 is formed along the inner wall path of the plurality of sixth contact holes CH6, an area thereof increases as the number of the sixth contact holes CH6 increases. Accordingly, an effect of improving the capacitance of the storage capacitor may be obtained.

The third metal material is made of aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), gold (Au), silver (Ag), tungsten (W), or an alloy thereof. It may be made of a single layer made of any one selected from the group or a multilayer made of these.

10A is a plan view illustrating a seventh mask process of an organic electroluminescent display device according to an embodiment of the present invention, and FIG. 10B is a cross-sectional view taken along lines I-I and II-II' of FIG. 10A.

10A and 10B , after depositing a passivation layer PAS1 through a sputtering process, for example, on the first planarization layer PLN1 on which the first storage electrode ST1 is formed, a seventh mask process is performed. A seventh contact hole CH7 and an eighth contact hole CH8 that pass through the passivation film PAS and the first planarization film PLN1 are formed using the same.

More specifically, a passivation layer PAS and a seventh photoresist are sequentially deposited on the first planarization layer PLN1 on which the first storage electrode ST1 is formed, for example, through a sputtering process. Then, a seventh photoresist is performed to expose regions of the passivation layer PAS corresponding to a partial region of the first drain D1 and a partial region of the second drain D2 by performing a photolithography process using the seventh mask. A pattern (not shown) is formed. After removing the passivation film PAS and the first planarization film PLN1 exposed by the seventh photoresist pattern, the seventh photoresist pattern is ashed by the seventh contact exposing a partial region of the first drain D1. An eighth contact hole CH8 exposing a portion of the hole CH7 and the second drain D2 is formed. The passivation layer PAS may be formed of an inorganic insulating layer such as silicon nitride (SiNx) or silicon oxide (SiOx), or a multilayer thereof.

11A is a plan view illustrating an eighth mask process of an organic light emitting display device according to an embodiment of the present invention, and FIG. 11B is a cross-sectional view taken along lines I-I and II-II' of FIG. 11A.

11A and 11B, after depositing a fourth metal material through, for example, a sputtering process on the passivation layer PAS in which the seventh contact hole CH7 and the eighth contact hole CH8 are formed, The second storage electrode ST2 of the storage capacitor and the connection part CP are formed using the eighth mask process.

More specifically, a fourth metal material and an eighth photoresist are sequentially deposited on the passivation layer PAS in which the seventh contact hole CH7 and the eighth contact hole CH8 are formed, for example, through a sputtering process. . Then, by performing a photolithography process using the eighth mask, regions of the fourth metal material corresponding to the first storage electrode ST1 of the storage capacitor and the first and second drain electrodes D1 and D2 are exposed. An eighth photoresist pattern (not shown) is formed. After the fourth metal material exposed by the eighth photoresist pattern is removed, the eighth photoresist pattern is ashed to form the second storage electrode ST2 of the storage capacitor and the connection part CP.

The fourth metal material is made of aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), gold (Au), silver (Ag), tungsten (W), or an alloy thereof. It may be made of a single layer made of any one selected from the group or multiple layers thereof.

The second storage electrode ST2 is connected to the second drain electrode D2 of the driving thin film transistor T2 exposed through the eighth contact hole CH8. The second storage electrode ST2 is positioned along the plurality of concave portions formed in the passivation layer PAS by the plurality of sixth contact holes CH6 and CH6, and the first storage electrode ST1 is disposed along the first planarization layer. Since they are positioned along paths of the plurality of sixth contact holes CH6 and CH6 formed in PLN1 , the facing areas of the first storage electrode ST1 and the second storage electrode ST2 facing each other are significantly increased. . Accordingly, the effect of remarkably increasing the capacitance of the storage capacitor in the pixel area of the same size can be obtained.

The connection part CP connects the first drain electrode D1 of the switching thin film transistor T1 exposed through the seventh contact hole C7 and the first storage electrode ST1.

12A is a plan view illustrating a ninth mask process of an organic electroluminescent display device according to an embodiment of the present invention, and FIG. 12B is a cross-sectional view taken along lines I-I and II-II' of FIG. 12A.

12A and 12B , after depositing a second planarization layer PLN2 through a sputtering process, for example, on the passivation layer PAS on which the second storage electrode ST2 and the connection part CP are formed, A ninth contact hole CH9 is formed using a ninth mask process.

More specifically, a second planarization layer PLN2 and a ninth photoresist are sequentially deposited on the passivation layer PAS in which the second storage electrode ST2 and the connection part CP are formed, for example, through a sputtering process. . Then, a ninth photoresist pattern (not shown) exposing a region of the second planarization layer PLN2 corresponding to a partial region of the second storage electrode ST1 of the storage capacitor by performing a photolithography process using the ninth mask. ) to form The ninth contact hole CH9 exposing the drain electrode D2 of the driving thin film transistor T2 by removing the second planarization layer PLN2 exposed by the ninth photoresist pattern and then ashing the ninth photoresist pattern. ) to form The second planarization layer PLN2 may be formed of a photosensitive organic layer such as photosensitive polyacrylic or photosensitive polyimide, or may be formed of an inorganic insulating layer.

13A is a plan view illustrating a tenth mask process of an organic electroluminescent display device according to an embodiment of the present invention, and FIG. 13B is a cross-sectional view taken along lines I-I and II-II' of FIG. 13A.

13A and 13B , a fifth metal material is deposited on the second planarization layer PLN2 in which the ninth contact hole CH9 is formed, for example, by a sputtering process, and then a tenth mask process is used. to form the anode electrode AND.

More specifically, a fifth metal material and a tenth photoresist are sequentially deposited on the second planarization layer PLN2 in which the ninth contact hole CH9 is formed, for example, through a sputtering process. Then, a photolithography process using the tenth mask is performed to form a tenth photoresist pattern (not shown) corresponding to the pixel region. After the second planarization layer PLN2 exposed by the tenth photoresist pattern is removed, the tenth photoresist pattern is ashed to make contact with the second storage electrode ST2 exposed through the ninth contact hole CH9. The anode electrode AND of the organic light emitting diode is formed.

The fifth metal material is made of aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), gold (Au), silver (Ag), tungsten (W), or an alloy thereof. It includes any one selected from the group.

Next, with reference to FIGS. 14A and 14B , an organic light emitting display device according to a second embodiment, which is another embodiment of the present invention, will be described. 14A is a plan view illustrating one pixel of an organic light emitting diode display according to another exemplary embodiment, and FIG. 14B is a cross-sectional view taken along lines I-I and II-II' of FIG. 14A.

In the organic light emitting display device according to the second embodiment of the present invention, as shown in FIGS. 14A and 14B , the auxiliary electrode CE is disposed on the interlayer insulating layer ILD and covers the auxiliary electrode CE. It is substantially the same as the organic electroluminescent display device according to the first embodiment of the present invention, except that the first passivation layer PAS1 is disposed. The auxiliary electrode CE may be used when addition of a switching thin film transistor or a driving thin film transistor for driving the organic light emitting diode is required, and if necessary, a first storage electrode ( ST1), it is possible to obtain the effect of increasing the capacitance of the storage capacitor. Hereinafter, an organic light emitting display device according to a second embodiment of the present invention will be described in more detail with reference to FIGS. 14A and 14B .

14A and 14B, an inorganic insulating film such as silicon nitride (SiNx) or silicon oxide (SiOx) or a buffer insulating film (BUF) made of multiple layers thereof is coated on the substrate SUB, and the buffer insulating film ( A first active layer A1 and a second active layer A2 spaced apart from each other are disposed on the BUF. The buffer insulating layer BUF may be omitted. The first active layer A1 and the second active layer A2 are semiconductor active layers formed by implanting impurity ions into amorphous silicon (a-Si). The first active layer A1 includes a first source area SA1 and a first drain area DA1 disposed with the first active area AA1 interposed therebetween. The second active layer A2 includes a second source area SA2 and a second drain area DA2 disposed with the second active area AA2 interposed therebetween.

A gate insulating layer GI is disposed on the first active layer A1 and the second active layer A2 to cover and insulate them. Similar to the buffer layer BUF, the gate insulating layer GI may be formed of an inorganic insulating layer such as silicon nitride (SiNx) or silicon oxide (SiOx), or a multilayer thereof. A gate line GL, a first gate electrode G1, and a second gate electrode G2 are positioned on the gate insulating layer GI. The first gate electrode G1 extends from the gate line GL and at least partially overlaps the first active area AA1 of the first active layer A1 . The second gate electrode G2 is spaced apart from the gate line GL and the first gate electrode G1 . The gate line GL, the first gate electrode G1 and the second gate electrode G2 are formed of aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), and gold (Au). ), silver (Ag), tungsten (W), or a single layer made of any one selected from the group consisting of alloys thereof or may be made of multiple layers thereof.

An interlayer insulating layer ILD is positioned on the gate insulating layer GI on which the gate line GL, the first gate electrode T1, and the second gate electrode 120c are disposed to insulate and cover them. The interlayer insulating layer ILD may be formed of an inorganic insulating layer such as silicon nitride (SiNx) or silicon oxide (SiOx), or a multilayer thereof.

A data line DL crossing the gate line GL, a third storage electrode ST3 parallel to the data line DL, and a power line PL are disposed on the interlayer insulating layer ILD. The auxiliary electrode CE is disposed between the data line DL and the power line PL. The first source electrode S1 and the first drain electrode D1 of the switching thin film transistor T1 and the second source electrode S2 and the second drain electrode of the driving thin film transistor T2 are also formed on the interlayer insulating film ILD. (D2) is placed. The data line DL, the power line PL, the auxiliary electrode CE, the first and second source electrodes S1 and S2 and the first and second drain electrodes D1 and D2 are formed of aluminum (Al). , copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), gold (Au), silver (Ag), a single layer consisting of any one selected from the group consisting of tungsten (W) or alloys thereof Or it may be made of multiple layers thereof.

The first source electrode S1 of the switching thin film transistor T1 may extend from the data line DL or may be a part of the data line DL, and the first source electrode S1 of the switching thin film transistor T1 may pass through the interlayer insulating layer ILD and the gate insulating layer GI. It is disposed to contact the first source area SA1 of the first active layer A1 exposed through the contact hole CH1. The first drain electrode D1 of the switching thin film transistor T1 has an interlayer insulating layer so as to overlap the gate line GL, the first drain region DA1 of the first active layer A2, and the second gate electrode G2. ILD). The first drain electrode D1 of the switching thin film transistor T1 is the first of the first active layer A1 exposed through the second contact hole CH2 penetrating the interlayer insulating layer ILD and the gate insulating layer GI. It is connected to the drain region DA1 and is connected to the second gate electrode G2 of the driving thin film transistor T2 exposed through the third contact hole CH2 penetrating the interlayer insulating layer ILD.

The second source electrode S2 of the driving thin film transistor T2 may extend from the power line PL or may be a part of the power line PL, and may be a fourth source electrode S2 passing through the interlayer insulating layer ILD and the gate insulating layer GI. It is disposed to contact the second source area SA2 of the second active layer A2 exposed through the contact hole CH4. The second drain electrode D2 of the driving thin film transistor T2 is disposed on the interlayer insulating layer ILD to overlap the second drain region DA2 of the second active layer A2 . The second drain electrode D2 of the driving thin film transistor T2 is the second active layer A2 exposed through the fifth contact hole CH5 penetrating the interlayer insulating layer ILD and the gate insulating layer GI. It is connected to the drain region DA2.

The data line DL, the power line PL, the auxiliary electrode CE, the first source electrode S1 and the first drain electrode D1 of the switching thin film transistor T1, and the second of the driving thin film transistor T2 On the interlayer insulating film ILD in which the source electrode S2 and the second drain electrode D2 are disposed, a first passivation film PAS1 and a first planarization film PLN1 made of a photosensitive organic film are sequentially stacked to cover them. do. The first passivation layer PAS1 may be formed of an inorganic insulating layer such as silicon nitride (SiNx) or silicon oxide (SiOx). The first planarization layer PLN1 is made of a photosensitive organic layer such as photosensitive polyacrylic or photosensitive polyimide.

The first planarization layer PLN1 disposed on the first passivation layer PAS1 is an interlayer insulating layer ILD in a pixel area defined by the data line DL, the power line PL, and the adjacent gate lines GL. ) and a plurality of sixth contact holes CH6 formed to expose the . A region R indicated by a dotted line in FIG. 14A indicates a region in which a plurality of sixth contact holes CH6 may be formed.

When the first planarization layer PLN1 is formed of the photosensitive organic material, an etching process is not required, and thus, it is not necessary to consider an etching selectivity, thereby improving the degree of freedom in material selection. For example, when the first passivation layer PAS1 and the first planarization layer PLN1 are formed of an inorganic material, when the first planarization layer PLN1 on the first passivation layer PAS1 is etched, the first passivation layer In order to prevent the PAS1 from being damaged, the first passivation layer PAS1 and the first planarization layer PLN1 must be respectively formed using silicon nitride and silicon oxide having a high mutual etch ratio. However, when the first planarization layer PLN1 is formed using the photosensitive organic layer, it is not necessary to etch the first planarization layer PLN1 . Therefore, it is unnecessary to select an etch rate for protecting the first passivation layer PAS1 . Therefore, since both silicon nitride and silicon oxide can be used to form the first passivation layer PAS1, the degree of freedom in material selection can be improved.

A first storage electrode ST1 of a storage capacitor is disposed in the pixel region on the first planarization layer PLN1 in which the plurality of sixth contact holes CH6 are formed. Since the first storage electrode ST1 is formed along the inner wall path of the plurality of sixth contact holes CH6, an area thereof increases as the number of the sixth contact holes CH6 increases.

A second passivation layer PAS2 is disposed on the first planarization layer PLN1 on which the first storage electrode ST1 is positioned to cover the first storage electrode ST1 . Like the first passivation layer PAS1 , the second passivation layer PAS2 may be formed of an inorganic insulating layer such as silicon nitride (SiNx) or silicon oxide (SiOx). The second passivation layer PAS2 has a plurality of concave portions along the shape of the sixth contact holes CH6 formed in the first planarization layer PLN1 .

The first drain electrode D1 of the switching thin film transistor T1 is connected to the second passivation layer PAS2 , the first planarization layer PLN1 , and the first passivation layer PAS1 through a seventh contact hole CH7 passing through. part of it is exposed. The seventh contact hole CH7 also exposes a portion of the first storage electrode ST1 positioned on the first planarization layer PLN1 . The second drain electrode D2 of the driving thin film transistor T2 is connected to the second passivation layer PAS2 , the first planarization layer PLN1 , and the first passivation layer PAS1 through an eighth contact hole CH8 passing through. part of it is exposed.

The second storage electrode ST2 is positioned to face the first storage electrode ST1 of the storage capacitor on the second passivation layer PAS2 in which the seventh and eighth contact holes CH7 and CH8 are formed. A connection part CP connecting the first drain electrode D1 of the switching thin film transistor T1 exposed through the seventh contact hole C7 and the first storage electrode ST1 is also formed on the second passivation layer PAS2. is located The first and second storage electrodes ST1 and ST2 and the connection pattern CP may include aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), gold (Au), It may be made of a single layer made of any one selected from the group consisting of silver (Ag), tungsten (W), or alloys thereof or multiple layers thereof.

The second storage electrode ST2 is positioned along the plurality of concave portions formed in the second passivation layer PAS2 by the plurality of sixth contact holes CH6 and CH6, and the first storage electrode ST1 is disposed on the first Since they are positioned along the paths of the plurality of sixth contact holes CH6 and CH6 formed in the planarization layer PLN1 , the opposing areas of the first storage electrode ST1 and the second storage electrode ST2 facing each other are significantly wide. will lose Accordingly, the effect of remarkably increasing the capacitance of the storage capacitor in the pixel area of the same size can be obtained.

A second planarization layer PLN2 is disposed on the second passivation layer PAS2 where the second storage electrode ST2 and the connection part CP are positioned to cover the second storage electrode ST2 and the connection part CP. The second planarization layer PLN2 may be formed of a photosensitive organic layer such as photosensitive polyacrylic or photosensitive polyimide, or may be formed of an inorganic insulating layer. The second planarization layer PLN2 includes a ninth contact hole CH9 exposing a portion of the second storage electrode ST2 .

The anode electrode AND of the organic light emitting diode is positioned on the second planarization layer PLN2 in which the ninth contact hole CH9 is formed to contact the second storage electrode ST2 exposed through the ninth contact hole CH9. . An organic light emitting layer (not shown) and a cathode (not shown) are sequentially formed on the anode electrode AND to form an organic light emitting diode (OLED of FIG. 1 ). The anode electrode (AND) and the cathode electrode are aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), gold (Au), silver (Ag), tungsten (W) or these It may be selected from the group consisting of alloys of A known configuration that is already known may be applied to the configuration of the upper portion of the anode electrode AND, and thus, further description will be omitted to avoid complication of the description.

Next, with reference to FIGS. 15A and 15B , an organic electroluminescence display according to a third embodiment, which is another embodiment of the present invention, will be described. 15A is a plan view illustrating one pixel of an organic light emitting diode display according to another exemplary embodiment, and FIG. 15B is a cross-sectional view taken along lines I-I and II-II' of FIG. 15A.

As shown in FIGS. 15A and 15B, the organic electroluminescence display according to the third embodiment of the present invention is substantially according to the first embodiment of the present invention, except that the first passivation film is used instead of the planarization film. It is the same as the organic electroluminescent display device. Hereinafter, an organic electroluminescence display according to a third embodiment of the present invention will be described in more detail with reference to FIGS. 15A and 15B .

15A and 15B, an inorganic insulating film such as silicon nitride (SiNx) or silicon oxide (SiOx) or a buffer insulating film (BUF) made of multiple layers thereof is coated on the substrate SUB, and the buffer insulating film ( A first active layer A1 and a second active layer A2 spaced apart from each other are disposed on the BUF. The buffer insulating layer BUF may be omitted. The first active layer A1 and the second active layer A2 are semiconductor active layers formed by implanting impurity ions into amorphous silicon (a-Si). The first active layer A1 includes a first source area SA1 and a first drain area DA1 disposed with the first active area AA1 interposed therebetween. The second active layer A2 includes a second source area SA2 and a second drain area DA2 disposed with the second active area AA2 interposed therebetween.

A gate insulating layer GI is disposed on the first active layer A1 and the second active layer A2 to cover and insulate them. Similar to the buffer layer BUF, the gate insulating layer GI may be formed of an inorganic insulating layer such as silicon nitride (SiNx) or silicon oxide (SiOx), or a multilayer thereof. A gate line GL, a first gate electrode G1, and a second gate electrode G2 are positioned on the gate insulating layer GI. The first gate electrode G1 extends from the gate line GL and at least partially overlaps the first active area AA1 of the first active layer A1 . The second gate electrode G2 is spaced apart from the gate line GL and the first gate electrode G1 . The gate line GL, the first gate electrode G1 and the second gate electrode G2 are formed of aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), and gold (Au). ), silver (Ag), tungsten (W), or a single layer made of any one selected from the group consisting of alloys thereof or may be made of multiple layers thereof.

An interlayer insulating layer ILD is positioned on the gate insulating layer GI on which the gate line GL, the first gate electrode T1, and the second gate electrode 120c are disposed to insulate and cover them. The interlayer insulating layer ILD may be formed of an inorganic insulating layer such as silicon nitride (SiNx) or silicon oxide (SiOx), or a multilayer thereof.

A data line DL crossing the gate line GL and a power line PL parallel to the data line DL are disposed on the interlayer insulating layer ILD. The first source electrode S1 and the first drain electrode D1 of the switching thin film transistor T1 and the second source electrode S2 and the second drain electrode of the driving thin film transistor T2 are also formed on the interlayer insulating film ILD. (D2) is placed. The data line DL, the power line PL, the first and second source electrodes S1 and S2 and the first and second drain electrodes D1 and D2 are formed of aluminum (Al), copper (Cu), Molybdenum (Mo), chromium (Cr), titanium (Ti), gold (Au), silver (Ag), tungsten (W) or a single layer consisting of any one selected from the group consisting of alloys or multiple layers thereof can be done

The first source electrode S1 of the switching thin film transistor T1 may extend from the data line DL or may be a part of the data line DL, and the first source electrode S1 of the switching thin film transistor T1 may pass through the interlayer insulating layer ILD and the gate insulating layer GI. It is disposed to contact the first source area SA1 of the first active layer A1 exposed through the contact hole CH1. The first drain electrode D1 of the switching thin film transistor T1 has an interlayer insulating layer so as to overlap the gate line GL, the first drain region DA1 of the first active layer A2, and the second gate electrode G2. ILD). The first drain electrode D1 of the switching thin film transistor T1 is the first of the first active layer A1 exposed through the second contact hole CH2 penetrating the interlayer insulating layer ILD and the gate insulating layer GI. It is connected to the drain region DA1 and is connected to the second gate electrode G2 of the driving thin film transistor T2 exposed through the third contact hole CH2 penetrating the interlayer insulating layer ILD.

The second source electrode S2 of the driving thin film transistor T2 may extend from the power line PL or may be a part of the power line PL, and may be a fourth source electrode S2 passing through the interlayer insulating layer ILD and the gate insulating layer GI. It is disposed to contact the second source area SA2 of the second active layer A2 exposed through the contact hole CH4. The second drain electrode D2 of the driving thin film transistor T2 is disposed on the interlayer insulating layer ILD to overlap the second drain region DA2 of the second active layer A2 . The second drain electrode D2 of the driving thin film transistor T2 is the second active layer A2 exposed through the fifth contact hole CH5 penetrating the interlayer insulating layer ILD and the gate insulating layer GI. It is connected to the drain region DA2.

The data line DL, the power line PL, the first source electrode S1 and the first drain electrode D1 of the switching thin film transistor T1, the second source electrode S2 of the driving thin film transistor T2, and On the interlayer insulating film ILD on which the second drain electrode D2 is disposed, the first passivation film PAS1 is positioned to cover them. The first passivation layer PAS1 may be made of an inorganic insulating layer such as silicon nitride (SiNx) or silicon oxide (SiOx), and should be made of a material having a high etch selectivity with respect to the interlayer insulating layer ILD. The first passivation layer PAS1 is formed to expose the interlayer insulating layer ILD in the pixel area defined by the data line DL, the power line PL, and the adjacent gate lines GL. It includes contact holes CH6. A region R indicated by a dotted line in FIG. 15A indicates a region in which a plurality of sixth contact holes CH6 may be formed.

The first storage electrode ST1 of the storage capacitor is disposed in the pixel region on the first passivation layer PAS1 in which the plurality of sixth contact holes CH6 are formed. Since the first storage electrode ST1 is formed along the inner wall path of the plurality of sixth contact holes CH6, an area thereof increases as the number of the sixth contact holes CH6 increases.

A second passivation layer PAS2 is disposed on the first passivation layer PAS1 on which the first storage electrode ST1 is positioned to cover the first storage electrode ST1 . Like the first passivation layer PAS1 , the second passivation layer PAS2 may be formed of an inorganic insulating layer such as silicon nitride (SiNx) or silicon oxide (SiOx). The second passivation layer PAS2 has a plurality of concave portions along the shape of the sixth contact holes CH6 formed in the first passivation layer PAS1 .

A portion of the first drain electrode D1 of the switching thin film transistor T1 is exposed through the second passivation layer PAS2 and the seventh contact hole CH7 penetrating the first passivation layer PAS2. The seventh contact hole CH7 also exposes a portion of the first storage electrode ST1 positioned on the first passivation layer PAS1 . A portion of the second drain electrode D2 of the driving thin film transistor T2 is exposed through the eighth contact hole CH8 penetrating the second passivation layer PAS2 and the first passivation layer PAS1 .

The second storage electrode ST2 is positioned to face the first storage electrode ST1 of the storage capacitor on the second passivation layer PAS2 in which the seventh and eighth contact holes CH7 and CH8 are formed. A connection part CP connecting the first drain electrode D1 of the switching thin film transistor T1 exposed through the seventh contact hole C7 and the first storage electrode ST1 is also formed on the second passivation layer PAS2. is located The first and second storage electrodes ST1 and ST2 and the connection pattern CP may include aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), gold (Au), It may be made of a single layer made of any one selected from the group consisting of silver (Ag), tungsten (W), or alloys thereof or multiple layers thereof.

The second storage electrode ST2 is positioned along the plurality of concave portions formed in the second passivation layer PAS2 by the plurality of sixth contact holes CH6 and CH6, and the first storage electrode ST1 is disposed on the first Since they are positioned along the paths of the plurality of sixth contact holes CH6 and CH6 formed in the passivation layer PAS1 , the opposing areas of the first storage electrode ST1 and the second storage electrode ST2 facing each other are significantly wide. will lose Accordingly, the effect of remarkably increasing the capacitance of the storage capacitor in the pixel area of the same size can be obtained.

A planarization layer PLN is disposed on the second passivation layer PAS2 in which the second storage electrode ST2 and the connection part CP are positioned to cover the second storage electrode ST2 and the connection part CP. The planarization layer PLN may be made of a photosensitive organic layer such as photosensitive polyacrylic or photosensitive polyimide, or may be formed of an inorganic insulating layer. The planarization layer PLN2 includes a ninth contact hole CH9 exposing a portion of the second storage electrode ST2 .

The anode electrode AND of the organic light emitting diode is positioned on the planarization layer PLN in which the ninth contact hole CH9 is formed to contact the second storage electrode ST2 exposed through the ninth contact hole CH9. An organic light emitting layer (not shown) and a cathode (not shown) are sequentially formed on the anode electrode AND to form an organic light emitting diode (OLED of FIG. 1 ). The anode electrode (AND) and the cathode electrode are aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), gold (Au), silver (Ag), tungsten (W) or these It may be selected from the group consisting of alloys of A known configuration that is already known may be applied to the configuration of the upper portion of the anode electrode AND, and thus, further description will be omitted to avoid complication of the description.

Those skilled in the art from the above description will be able to see that various changes and modifications can be made without departing from the technical spirit of the present invention. Accordingly, the present invention should not be limited to the contents described in the detailed description, but should be defined by the claims.

SUB: Substrate BUF: Buffer Insulation Film
T1: switching thin film transistor T2: driving thin film transistor
A1, A2: active layer AA1, AA2: active area
DA1, DA2: drain region SA1, SA2: source region
GL: gate line G1, G2: gate electrode
GI: gate insulating film DL: data line
PL: power line D1, D2: drain electrode
S1, S2: source electrode ILD: interlayer insulating film
PLN, PLN1, PLN2: planarization film PAS: passivation film
ST1, ST2: storage electrode CP: connection
CE: auxiliary electrode

Claims (10)

a pixel region defined by a gate line and a data line and a power line intersecting the gate line and being parallel to each other on a substrate;
a switching thin film transistor and a driving thin film transistor disposed on the substrate;
an interlayer insulating film covering the gate electrode of each of the switching thin film transistor and the driving thin film transistor;
an auxiliary electrode positioned between the data line and the power line on the interlayer insulating layer on which the data line and the power line are disposed;
a protective film covering the auxiliary electrode, the data line, and the power line;
a first insulating layer disposed on the passivation layer and having at least one hole;
a first storage electrode disposed on the first insulating layer to have a curved portion along the inner surface of the at least one hole, overlapping the auxiliary electrode with the passivation layer interposed therebetween, and connected to a first drain electrode of the switching thin film transistor;
a second storage electrode disposed to overlap the first storage electrode with a second insulating layer having a curved portion corresponding to an inner surface of the hole of the first insulating layer and connected to a second drain electrode of the driving thin film transistor;
a first electrode disposed to overlap with the second storage electrode and a third insulating layer therebetween; and
a second electrode disposed to overlap the first electrode with an organic light emitting layer interposed therebetween;
The data line, the power line, and the auxiliary electrode are located on the same layer,
a first capacitance is formed by the auxiliary electrode and the first storage electrode, and a second capacitance is formed by the first storage electrode and the second storage electrode;
and the auxiliary electrode, the first storage electrode, and the second storage electrode are formed of a metal material.
The method of claim 1,
The first insulating film is made of a photosensitive organic material, the interlayer insulating film is made of an inorganic insulating material, the second insulating film is made of an inorganic insulating material, and the third insulating film is made of a photosensitive organic material or an inorganic insulating material. An organic electroluminescent display device characterized in that.
The method of claim 1,
Source and drain electrodes of each of the switching thin film transistor and the driving thin film transistor are disposed between the interlayer insulating layer and the protective layer to be spaced apart from the auxiliary electrode,
The first insulating layer is made of an inorganic insulating material, the interlayer insulating layer is made of another inorganic insulating material having a high etch selectivity with respect to the inorganic insulating material, and the second insulating layer is made of the inorganic insulating material or the other inorganic insulating material. and the third insulating layer is made of any one of a photosensitive organic material, the inorganic insulating material, and the other inorganic insulating material.
The method of claim 1,
The switching thin film transistor,
a first active layer disposed on the substrate;
a first gate electrode disposed on a gate insulating film covering the first active layer;
a first source region of the first active layer exposed through a first contact hole penetrating the interlayer insulating layer and the gate insulating layer, the first source region being spaced apart from each other on the interlayer insulating layer covering the first gate electrode 1 a source electrode;
and the first drain electrode connected to a first drain region of the first active layer exposed through a second contact hole penetrating the interlayer insulating layer and the gate insulating layer.
5. The method of claim 4,
The driving thin film transistor,
a second active layer spaced apart from the first active layer and disposed on the substrate;
a second gate electrode disposed to be spaced apart from the first gate electrode on the gate insulating layer covering the second active layer;
It is disposed on the interlayer insulating layer that covers the second gate electrode and is spaced apart from each other, and is connected to a second source region of the second active layer exposed through a fourth contact hole penetrating the interlayer insulating layer and the gate insulating layer. a second source electrode;
and the second drain electrode connected to a second drain region of the second active layer exposed through a fifth contact hole penetrating the interlayer insulating layer and the gate insulating layer.
5. The method of claim 4,
and the first storage electrode is connected to the second insulating layer and the first drain electrode exposed through a seventh contact hole penetrating the first insulating layer.
6. The method of claim 5,
and the second storage electrode is connected to the second drain electrode exposed through an eighth contact hole penetrating the second insulating layer and the first insulating layer.
8. The method of claim 7,
and the first electrode is connected to the second storage electrode exposed through a ninth contact hole penetrating the third insulating layer.
9. The method of claim 8,
and the first drain electrode is connected to the second gate electrode exposed through a third contact hole penetrating the interlayer insulating layer.
3. The method of claim 2,
and a fourth insulating layer covering the data line, the power line, the auxiliary electrode, the first drain electrode of the switching thin film transistor, and the second drain electrode of the driving thin film transistor, and disposed under the first insulating layer;
The fourth insulating film is made of an inorganic insulating material,
and the auxiliary electrode is spaced apart from and parallel to the data line and the power line.

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