KR20160044676A - Manufacturing mehod of silicon carbide substrate - Google Patents

Manufacturing mehod of silicon carbide substrate Download PDF

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Publication number
KR20160044676A
KR20160044676A KR1020140139131A KR20140139131A KR20160044676A KR 20160044676 A KR20160044676 A KR 20160044676A KR 1020140139131 A KR1020140139131 A KR 1020140139131A KR 20140139131 A KR20140139131 A KR 20140139131A KR 20160044676 A KR20160044676 A KR 20160044676A
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South Korea
Prior art keywords
silicon carbide
carbide layer
layer
forming
present
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KR1020140139131A
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Korean (ko)
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김진혁
고병선
이근
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에스케이이노베이션 주식회사
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Priority to KR1020140139131A priority Critical patent/KR20160044676A/en
Publication of KR20160044676A publication Critical patent/KR20160044676A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02378—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/02447—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02529—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

According to an embodiment of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a buffer layer on a base substrate; forming a first silicon carbide layer having a cubic system structure on the buffer layer; 2 silicon carbide layer on the surface of the silicon carbide substrate.

Description

TECHNICAL FIELD [0001] The present invention relates to a method for manufacturing a silicon carbide substrate,

The present invention relates to a method of manufacturing a silicon carbide substrate.

Silicon (hereinafter referred to as a mixture of Si and silicon) is the basis of modern technology-intensive industries as a major axis material of the semiconductor industry. Recently, the need for efficient energy utilization has become more important, and SiC , And compound semiconductor materials such as GaN, ZnO and AlN are under development.

Of these materials, silicon carbide (SiC, hereinafter, SiC and silicon carbide are used in combination) has a band gap of 2 to 3 times higher than silicon and has a high thermal conductivity and a high limit temperature. In addition, silicon carbide is excellent in heat resistance and mechanical strength, and is physically and chemically stable. Therefore, silicon carbide has been attracting attention as an environmentally resistant semiconductor material. As a result, demand for silicon carbide substrates as substrates for high- have.

However, when a large-diameter silicon carbide substrate is manufactured, defects such as micropipes can be generated in many cases, and the reliability of the manufactured device is lowered.

Accordingly, there is a need in the art for a method capable of efficiently manufacturing a silicon carbide substrate on which crystal defects are reduced and electric characteristics can be improved.

According to an embodiment of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a buffer layer on a base substrate; forming a first silicon carbide layer having a cubic system structure on the buffer layer; 2 silicon carbide layer on the surface of the silicon carbide substrate.

In one embodiment of the present invention, the first silicon carbide layer may comprise 3C-SiC.

In one embodiment of the present invention, the second silicon carbide layer may include at least one of 4H-SiC and 6H-SiC.

In one embodiment of the present invention, the base substrate may be a silicon substrate.

In one embodiment of the present invention, the method may further include separating the base substrate from the buffer layer and the first silicon carbide layer before forming the second silicon carbide layer.

In an embodiment of the present invention, the buffer layer may be made of a nitride semiconductor.

In one embodiment of the present invention, the step of forming the second silicon carbide layer may be performed at a higher temperature than the step of forming the first silicon carbide layer.

In one embodiment of the present invention, the method further includes a temperature raising step for forming the second silicon carbide layer after the first silicon carbide layer is formed, and the raising temperature step may be performed linearly or stepwise.

In one embodiment of the present invention, the step of forming the first silicon carbide layer may be performed at a temperature of 900 to 1300 캜.

In one embodiment of the present invention, the step of forming the second silicon carbide layer may be performed at a temperature condition of 1300 to 1800 ° C.

In one embodiment of the present invention, the method may further include converting at least a portion of the first silicon carbide layer to a seed layer of a hexagonal system structure before forming the second silicon carbide layer.

In an embodiment of the present invention, the seed layer may be formed by heat-treating at least a part of the first silicon carbide layer at a temperature of 1300 to 1800 캜.

In one embodiment of the present invention, the method may further include forming a seed layer having a hexagonal system structure on the first silicon carbide layer before forming the second silicon carbide layer.

In an embodiment of the present invention, the second silicon carbide layer may be formed at a higher temperature than the step of forming the first silicon carbide layer using the seed layer as a seed.

In an embodiment of the present invention, the method may further include separating the buffer layer and the first silicon carbide layer from the second silicon carbide layer after the forming the second silicon carbide layer.

In one embodiment of the present invention, the thickness of the second silicon carbide layer may be 100 to 500 탆.

In an embodiment of the present invention, at least one of the first and second silicon carbide layers may be formed by an image vapor deposition.

In an embodiment of the present invention, at least one of the first and second silicon carbide layers may be in-situ doped.

As one example of the various effects of the present invention, manufacturing efficiency of a silicon carbide single crystal substrate having a hexagonal system structure is improved, and further, electrical characteristics can be improved by reducing crystal defects of the silicon carbide substrate.

The various and advantageous advantages and effects of the present invention are not limited to the above description, and can be more easily understood in the course of describing a specific embodiment of the present invention.

1 to 4 are flowcharts of main steps for explaining a method of manufacturing a silicon carbide substrate according to an embodiment of the present invention.
5 is a graph schematically showing a temperature increasing process for forming a silicon carbide layer having a hexagonal system structure in an embodiment of the present invention.
6 to 8 are flowcharts of main steps for explaining a method of manufacturing a silicon carbide substrate according to another embodiment of the present invention.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings. The embodiments may be modified in other forms or various embodiments may be combined with each other, and the scope of the present invention is not limited to the embodiments described below. Further, the embodiments are provided so that those skilled in the art can more fully understand the present invention. For example, the shapes and sizes of the elements in the drawings may be exaggerated for clarity of description, and the elements denoted by the same reference numerals in the drawings are the same elements. Also, in this specification, terms such as "upper", "upper surface", "lower", "lower surface", "side surface" and the like are based on the drawings and may actually vary depending on the direction in which the devices are arranged.

The term " one example " used in this specification does not mean the same embodiment, but is provided to emphasize and describe different unique features. However, the embodiments presented in the following description do not exclude that they are implemented in combination with the features of other embodiments. For example, although the matters described in the specific embodiments are not described in the other embodiments, they may be understood as descriptions related to other embodiments unless otherwise described or contradicted by those in other embodiments.

1 to 4 are flowcharts of main steps for explaining a method of manufacturing a silicon carbide substrate according to an embodiment of the present invention. 5 is a graph schematically showing a temperature increasing process for forming a silicon carbide layer having a hexagonal system structure in an embodiment of the present invention.

In the case of the present embodiment, in order to obtain a silicon carbide substrate, a buffer layer 102 is first formed on a base substrate 101, as shown in Fig. An example that can be used as the base substrate 101 is a silicon substrate, but silicon has a large difference in lattice constant and thermal expansion coefficient compared to silicon carbide to be grown thereon, especially silicon carbide having a cubic system structure such as 3C-SiC The buffer layer 102 is employed on the base substrate 101 in order to minimize such a problem. The buffer layer 102 may adopt a single layer or two or more multi-layer structures, and a nitride semiconductor such as AlN, GaN, InN, InGaN, AlGaN, or the like may be used. When a nitride semiconductor is used as the buffer layer 102, the difference in lattice constant and thermal expansion coefficient between silicon and silicon carbide can be greatly reduced. Accordingly, by employing the buffer layer 102 as in the present embodiment, crystal defects of the silicon carbide layer grown thereon can be reduced, and the electrical characteristics of the device can be improved.

Next, the first silicon carbide layer 103 is formed on the buffer layer 102, as shown in Fig. In the present embodiment, the first silicon carbide layer 103 may have a cubic structure, and specifically, it may be formed to include 3C-SiC. The first silicon carbide layer 103 may be formed in a single crystal form by epitaxial growth on the buffer layer 102. 3C-SiC can be hetero-crystal grown on a silicon substrate or an insulating film, unlike a hexagonal structure grown in a bulk form, for example, 4H-SiC or 6H-SiC. There is an advantage of easy control. As described above, 3C-SiC has a large difference in lattice constant and the like from the silicon substrate, and crystal defects are likely to occur during crystal growth. However, since the buffer layer 102 made of a nitride semiconductor or the like By employing this, crystal defects can be reduced.

Such 3C-SiC can be formed at a temperature of about 900 to 1300 DEG C, and at a higher temperature, another crystal structure such as silicon carbide having a hexagonal system structure can be formed. In addition, in the present embodiment, the first silicon carbide layer 103 may be doped with an n-type or p-type impurity to be used for a device such as a MOSFET (Metal Oxide Silicon Field Effect Transistor) or SBD (Schottky Barrier Diode) As an example of the process, it can be formed by situ doping during chemical vapor deposition (hereinafter, used in combination with CVD and image vapor deposition). In this case, the pressure of the CVD process can be adjusted in the range of atmospheric pressure to 100 torr. Further, the atmosphere in which the CVD process proceeds may be a hydrogen (H 2 ) atmosphere.

According to studies by the present inventors, when a doping method using an ion implantation and activation process is used for silicon carbide, heat treatment at a high temperature is required for the ion implanted silicon carbide, which may result in difficulty in mass production. Alternatively, when the chemical vapor deposition method is used as in the present embodiment, silicon carbide can be effectively inductively implanted at a relatively low temperature. For example, desired doping can be realized by injecting a gas for the doping source into the deposition chamber . In this case, N, P, As, Sb and Bi can be used as n-type impurities which can be doped to SiC, and B, Al, Ga, In and Ti can be used as p-type impurities. When the above-described process is used, in-situ doping of the silicon carbide layer at a relatively low temperature can ensure process efficiency compared with the ion implantation and activation process.

Next, the base substrate 101 is separated from the buffer layer 102 and the first silicon carbide layer 103, as shown in Fig. In this process, either chemical lift or physical lift can be used. Specifically, the base substrate 101 made of silicon or the like may be dissolved by an etching solution such as nitric acid or the base substrate 101 may be flattened and removed. The separation of the base substrate 101 is to prevent the base substrate 101 made of silicon or the like from deteriorating or melting at such a high temperature condition in a subsequent step of forming SiC having a hexagonal system structure at a high temperature . However, the step of removing the base substrate 101 is not necessarily performed in the present invention, and the base substrate 101 may not be removed as required or according to the conditions of the base substrate 101.

Next, as shown in FIG. 4, a second silicon carbide layer 104 is formed on the first silicon carbide layer 103, and a single crystal silicon layer 103 is formed by epitaxial growth like the first silicon carbide layer 103 . The second silicon carbide layer 104 may have a crystal structure different from that of the first silicon carbide layer 103, and may specifically include at least one of 4H-SiC and 6H-SiC. Unlike 3C-SiC, silicon carbide with such a hexagonal structure has an advantage that it can be used as a high-quality single crystal substrate of a large diameter. Particularly, 4H-SiC has high electron mobility and is less suitable as a material for power devices because it has less asymmetry with respect to crystal direction than 6H-SiC. However, not only 4H-SiC may be used as the second silicon carbide layer 104 in the present invention, but the second silicon carbide layer 104 may include 6H-SiC, as described above, You can do it.

In the present embodiment, silicon carbide having a hexagonal system structure included in the second silicon carbide layer 104 can be formed at a higher temperature than 3C-SiC. Specifically, according to research conducted by the present inventors, at a temperature of about 1300 to 1800 ° C It was confirmed that silicon carbide having a cubic system structure was formed. The second silicon carbide layer 104 may be formed by a CVD process in the same manner as the first silicon carbide layer 103. The silicon carbide layer 103 may be formed by a CVD process, Doping is possible. In this case, the second silicon carbide layer 104 may be doped with an n-type or a p-type impurity to be used for an element such as a MOSFET or an SBD and may be doped with the same or different impurity as the first silicon carbide layer 103 There will be.

As described above, the second silicon carbide layer 104 can be performed at a higher temperature than the step of forming the first silicon carbide layer 103 in order to form SiC having a hexagonal system. For this purpose, in this embodiment, As shown in FIG. 5, it may further include a temperature raising step for forming the second silicon carbide layer 104. In this case, the temperature rising step may be performed linearly or stepwise (stepwise). When the growth temperature is increased linearly or stepwise, it is possible to reduce the defects that may occur at the beginning of the chemical vapor deposition process by controlling the growth rate of SiC.

Meanwhile, in another embodiment of the present invention, the second silicon carbide layer 104 may be obtained by changing the crystal structure of the surface of the first silicon carbide layer 103 and then growing the seed layer. 6, at least a part of the first silicon carbide layer 103 can be converted into a seed layer H having a hexagonal system structure. As one example of the process, a first silicon carbide layer 103 may be heat-treated at a temperature of about 1300 to 1800 DEG C to obtain a seed layer (H). Referring to FIG. 7, the second silicon carbide layer 104 may be formed on the seed layer H formed as described above. As in the previous embodiment, the second silicon carbide layer 104 may have a thickness of about 1300 Lt; RTI ID = 0.0 > 1800 C. < / RTI > Alternatively, the seed layer (H) may be formed on the first silicon carbide layer (103) instead of the crystal structure of the first silicon carbide layer (103). In this case, the first silicon carbide layer 103 is heat-treated at a temperature of about 1300 to 1800 ° C to form a seed layer H, and a suitable source gas for growth of silicon carbide, such as (Hexamethyldisilane), MMS (Monomethylsilane ), TMS (Tetramethylsilane), MTCS (Methyltrichlorosilane), DES (Diethylsilane), TPS (Tripropylsilane) and DMDS (Dimethyldichlorosilane). When the seed layer H is used as in the present embodiment, the second silicon carbide layer 104 having a hexagonal crystal structure can be formed directly at a high temperature without going through the temperature raising process described with reference to FIG. 5, .

On the other hand, the second silicon carbide layer 104 obtained by the above-described manufacturing methods can be used as a substrate for semiconductor device fabrication, and can also be used as a free standing substrate through an appropriate subsequent process. 8, the buffer layer 102 and the first silicon carbide layer 103 can be separated from the second silicon carbide layer 104 in the stacked structure obtained by the foregoing embodiments, The thickness h of the second silicon carbide layer 104 may be in the range of about 100 to 500 mu m so as to be usable as a freestanding substrate. The freestanding silicon carbide substrate manufactured in this manner can be manufactured at a relatively lower cost than the silicon carbide substrate manufactured by the conventional ingot process, and further, loss due to ingot wafering can be reduced .

The present invention is not limited by the above-described embodiments and the accompanying drawings, but is intended to be limited only by the appended claims. It will be apparent to those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. something to do.

101: Base substrate
102: buffer layer
103: a first silicon carbide layer
104: second silicon carbide layer
H: Seed layer

Claims (18)

Forming a buffer layer on the base substrate;
Forming a first silicon carbide layer having a cubic system structure on the buffer layer; And
Forming a second silicon carbide layer having a hexagonal crystal structure on the first silicon carbide layer;
Wherein the silicon carbide substrate is a silicon carbide substrate.
The method according to claim 1,
Wherein the first silicon carbide layer comprises 3C-SiC.
The method according to claim 1,
Wherein the second silicon carbide layer comprises at least one of 4H-SiC and 6H-SiC.
The method according to claim 1,
Wherein the base substrate is a silicon substrate.
The method according to claim 1,
Further comprising separating the base substrate from the buffer layer and the first silicon carbide layer before forming the second silicon carbide layer.
The method according to claim 1,
Wherein the buffer layer is made of a nitride semiconductor.
The method according to claim 1,
Wherein the step of forming the second silicon carbide layer is performed at a higher temperature than the step of forming the first silicon carbide layer.
8. The method of claim 7,
Further comprising a temperature increasing step of forming the second silicon carbide layer after forming the first silicon carbide layer, wherein the temperature increasing step is performed linearly or stepwise.
The method according to claim 1,
Wherein the forming of the first silicon carbide layer is performed at a temperature of 900 to 1300 ° C.
The method according to claim 1,
Wherein the forming of the second silicon carbide layer is performed at a temperature of 1300 to 1800 ° C.
The method according to claim 1,
Further comprising the step of converting at least a part of the first silicon carbide layer into a seed layer having a hexagonal system structure before forming the second silicon carbide layer.
12. The method of claim 11,
Wherein the seed layer is formed by heat-treating at least a part of the first silicon carbide layer at a temperature of 1300 to 1800 ° C.
The method according to claim 1,
And forming a seed layer having a hexagonal system structure on the first silicon carbide layer before forming the second silicon carbide layer.
14. The method according to claim 11 or 13,
Wherein the second silicon carbide layer is formed at a higher temperature than the step of forming the first silicon carbide layer using the seed layer as a seed.
The method according to claim 1,
Further comprising the step of separating the buffer layer and the first silicon carbide layer from the second silicon carbide layer after the step of forming the second silicon carbide layer.
16. The method of claim 15,
Wherein the thickness of the second silicon carbide layer is 100 to 500 占 퐉.
The method according to claim 1,
Wherein at least one of the first and second silicon carbide layers is formed by an image vapor deposition.
18. The method of claim 17,
Wherein at least one of the first and second silicon carbide layers is in situ doped.
KR1020140139131A 2014-10-15 2014-10-15 Manufacturing mehod of silicon carbide substrate KR20160044676A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102236398B1 (en) * 2020-09-22 2021-04-02 에스케이씨 주식회사 Cleaning method for wafer and wafer with reduced impurities
KR20220039641A (en) * 2021-02-25 2022-03-29 주식회사 쎄닉 Cleaning method for wafer and wafer with reduced impurities

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102236398B1 (en) * 2020-09-22 2021-04-02 에스케이씨 주식회사 Cleaning method for wafer and wafer with reduced impurities
US11646209B2 (en) 2020-09-22 2023-05-09 Senic Inc. Method of cleaning wafer and wafer with reduced impurities
KR20220039641A (en) * 2021-02-25 2022-03-29 주식회사 쎄닉 Cleaning method for wafer and wafer with reduced impurities

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