KR20160042605A - Method for manufacturing stacked semiconductor package - Google Patents

Method for manufacturing stacked semiconductor package Download PDF

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Publication number
KR20160042605A
KR20160042605A KR1020140136740A KR20140136740A KR20160042605A KR 20160042605 A KR20160042605 A KR 20160042605A KR 1020140136740 A KR1020140136740 A KR 1020140136740A KR 20140136740 A KR20140136740 A KR 20140136740A KR 20160042605 A KR20160042605 A KR 20160042605A
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South Korea
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via hole
circuit board
printed circuit
forming
semiconductor chip
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KR1020140136740A
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Korean (ko)
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KR101648199B1 (en
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정현학
김영권
오지훈
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주식회사 에스에프에이반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/073—Apertured devices mounted on one or more rods passed through the apertures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

Disclosed is a method for manufacturing a stacked semiconductor package. According to an embodiment of the present invention, the method for manufacturing a stacked semiconductor package comprises: a step (a) of forming via hole structures (130a) on a peripheral area of a via hole pad (104), on a printed circuit board (100) including wiring patterns (101, 102) and the via hole pad (104); a step (b) of mounting a semiconductor chip (110) on the upper surface of the printed circuit board (100); a step (c) of forming a molding layer (140) on the printed circuit board (100) by molding only the upper surface of an area where the semiconductor chip (110) is embedded; and a step (d) of preparing a lower package by charging a metal filling (150) in a via hole (160) formed between the via hole structures (130a). According to the present invention, a fine pitch can be designed.

Description

[0001] METHOD FOR MANUFACTURING STACKED SEMICONDUCTOR PACKAGE [0002]

The present invention relates to a method of manufacturing a stacked semiconductor package, and more particularly, to a method of manufacturing a stacked semiconductor package capable of designing a fine pitch by forming a depressed via hole structure using a lithography patterning technique using a photoresist .

In general, the semiconductor industry is becoming more lightweight, compact, versatile, and high performance at a low price. One of the important technologies required to meet this trend is integrated circuit packaging technology.

Integrated circuit packaging protects semiconductor chips such as single elements and integrated circuits formed by stacking various electronic circuits and wiring lines from various external environments such as dust, moisture, electrical and mechanical loads and optimizes and maximizes the electrical performance of semiconductor chips Output terminal to the main board by using a lead frame, a printed circuit board (Printed Circuit Board), or the like, and molded by using an encapsulating material.

In recent years, as the products on which the integrated circuit packages are mounted are thin and short, and many functions are required, the integrated circuit package technology has been widely used in various fields such as SIP (System in Package), PoP ) And the like.

In addition, a printed circuit board on which high-integration and poly-film components are mounted must also be thinned. In order to satisfy this, the degree of freedom of circuit design of the substrate should increase, but various new technologies such as micro-vias and build-ups are adopted to solve these problems.

On the other hand, a blind via hole forming method of a printed circuit board is known as a mechanical drilling method, a plasma etching method, a laser drilling method, or the like.

The laser method is currently the most widely used method for forming a blind via hole of a printed circuit board, and includes a method using a laser drill of excimer, Nd: YAG, and CO2 type.

1A to 1C are diagrams illustrating a process of forming a via hole by a conventional laser drilling method. First, as shown in FIG. 1A, a semiconductor chip 20 is mounted on a printed circuit board 10, 1B, the laser drilling position coordinate 40 is determined on the molding portion 30 of the portion where the via hole is to be formed, and the laser drilling is performed on the portion of the laser drilling position 40. As a result, ) 50 are formed.

The laser drilling process according to the related art has a limitation on the support of a fine pitch of 0.3 mm or less and the position of the via hole is determined by determining the laser drilling position on the upper surface of the mold without the mark after the EMC molding process, It is not accurate and there is a great possibility that an error occurs.

In addition, plasma cleaning, reflow M / C, flux cleaner, off-loader, and the like are used to remove residues generated in the laser drilling process. Process technology is additionally required, and laser equipment is expensive, so that high-cost facility investment is required.

Korean Registered Patent Publication No. 10-0674316 (January 18, 2007)

SUMMARY OF THE INVENTION The present invention provides a method of manufacturing a stacked semiconductor package capable of designing a fine pitch by forming a depressed via hole structure by using a lithography patterning technique using photoresist .

The objects of the present invention are not limited to the above-mentioned objects, and other objects not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor package including: (a) forming a via hole on a printed circuit board including wiring patterns and a via hole pad; Forming a via hole structure (130a) in a region around the pad (104); (b) mounting the semiconductor chip 110 on the upper surface of the printed circuit board 100; (c) forming a molding layer (140) on the printed circuit board (100) by molding only the upper surface of the region where the semiconductor chip (110) is mounted; And (d) filling the via hole 160 formed between the via hole structures 130a with a metal filler 150 to prepare a lower package.

In the method of manufacturing a stacked semiconductor package according to an embodiment of the present invention, the step (a) may include forming the via hole structure 130a having a negative shape using a photolithography process using a photomask 170 .

(A) is a step of forming a photoresist layer 130 (130) on the upper surface of the printed circuit board 100 including the wiring pattern 101 and the via hole pad 104, Forming a photomask 170 having a pattern in a via hole region on the top surface of the photoresist layer 130 and irradiating light to remove the photoresist layer corresponding to the via hole region; .

According to another aspect of the present invention, there is provided a method of manufacturing a stacked semiconductor package, the method comprising: (e) stacking an upper package on which the semiconductor chip 110 'is mounted on the prepared lower package.

In a preferred embodiment, the step (e) may include soldering the metal filler 150 of the lower package and the wiring pattern 102 'provided in the upper package.

The method of manufacturing a stacked semiconductor package according to another aspect of the present invention includes the steps of: (a) forming a via hole in a peripheral region of the via hole pad 204 on a printed circuit board 200 having wiring patterns 201 and 202 and a via hole pad 204; Forming a structure 230a; (b) mounting the semiconductor chip 210 on the upper surface of the printed circuit board 200; (c) filling the via hole (260) formed between the via hole structures (230a) with a metal filler (250); (d) molding the upper surface of the printed circuit board 200 including the semiconductor chip 210, the via hole structure 230a and the metal filler 250 to form a molding layer 240; And (e) grinding the molding layer 240 such that an upper surface of the via hole structure 230a and the metal filler 250 is exposed.

In the method of manufacturing a stacked semiconductor package according to another aspect of the present invention, the step (a) may include forming the via hole structure of a negative shape using a photolithography process using a photomask.

According to another aspect of the present invention, in the step (a), a step of forming a photoresist layer on the upper surface of the printed circuit board including the wiring pattern and the via hole pads, And aligning a photomask having a pattern formed in the via hole region on the upper surface of the layer and irradiating light to remove the photoresist layer corresponding to the via hole region.

As described above, according to the present invention, since the lithography patterning technique using the photoresist is used, the economic burden on the investment of the high-cost laser equipment can be alleviated.

In addition, the position accuracy can be improved by forming the via hole structure directly around the via hole pads of the printed circuit board.

In addition, it is possible to prevent problems such as misalignment, ball bridges, and sewing balls caused by a laser drilling process.

Further, it is possible to eliminate the inconvenience of the generation of EMC residues by the laser drilling process and the progress of the additional process for removing the EMC residues.

In addition, the height of the via hole structure can be varied to minimize the distance between the lower package and the upper package.

1A to 1C are process cross-sectional views illustrating a process of forming a via hole by a conventional laser drilling method.
FIGS. 2A to 2E are cross-sectional views illustrating a process of manufacturing a stacked semiconductor package according to an embodiment of the present invention.
3A to 3E are process cross-sectional views illustrating a via hole structure forming process shown in FIG. 2A.
4 is a process sectional view showing the semiconductor package stacking process shown in FIG. 2E.
5A to 5F are cross-sectional views illustrating a process for fabricating a stacked semiconductor package according to another embodiment of the present invention.
6A to 6F are cross-sectional views illustrating a process for fabricating a stacked semiconductor package according to another embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. And is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined by the claims. It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. It is noted that " comprises, " or "comprising," as used herein, means the presence or absence of one or more other components, steps, operations, and / Do not exclude the addition.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawings, like reference numerals refer to like elements throughout. In the drawings, like reference numerals are used to denote like elements, and in the description of the present invention, In the following description, a detailed description of the present invention will be omitted.

2A to 2E are cross-sectional views illustrating a process of fabricating a stacked semiconductor package according to an embodiment of the present invention.

First, as shown in FIG. 2A, a via hole structure 130a is formed on the upper surface of the printed circuit board 100 to form a via hole 160 in a negative shape.

The via hole structure 130a is formed in a region around the via hole pad 104 of the printed circuit board 100, and a photolithography process using a photomask may be used. A detailed description thereof will be given later with reference to Figs. 3A to 3E.

Wiring patterns 101 and 102 and a via hole pad 104 are formed on the printed circuit board 100 and a via contact for electrically connecting the upper and lower wiring patterns 101 and 102 is provided.

Next, as shown in FIG. 2B, the semiconductor chip 110 is mounted on the upper surface of the printed circuit board 100. 2B, the semiconductor chip 110 is electrically connected to the printed circuit board 100 by a flip chip structure 112, but it is also possible to connect the semiconductor chip 110 by wire bonding.

Next, as shown in FIG. 2C, the molding layer 140 is formed on the printed circuit board 100 by using an epoxy molding compound (EMC) only on the upper surface of the area where the semiconductor chip 110 is mounted.

Next, as shown in FIG. 2D, the via hole 160 is filled with the metal filler 150. Next, as shown in FIG. The metal filler 150 may be charged at different heights. Particularly, when the upper package is laminated on the lower package, the filling height of the metal filler 150 can be set so that the interval between the upper and lower packages is minimized according to the diameter of the solder ball of the upper package.

Next, as shown in FIG. 2E, the upper package, on which the semiconductor chip 110 'is mounted, is stacked on the lower package on which the semiconductor chip 110 is mounted, the molding layer 140 is formed, do.

 At this time, the metal filler 150 filled in the via hole 160 of the lower package and the solder ball 120 provided on the wiring pattern 102 'of the upper package are soldered together.

3A to 3E are cross-sectional views illustrating a process of forming the via hole structure shown in FIG. 2A.

First, a printed circuit board 100 having the wiring patterns 101 and 102 and the via hole pads 104 as shown in FIG. 3A is prepared.

Next, as shown in FIG. 3B, a photoresist PR is coated on the entire surface of the printed circuit board 100. A photoresist refers to a material that receives light of a specific wavelength and uses solubility in a developer to selectively remove the light-receiving portion and the non-light-receiving portion during the subsequent development process.

After coating, a soft bake is performed at a low temperature to remove the organic solvent remaining in the photoresist. In order to prevent the exposure equipment and mask contamination due to the residual solvent and to keep the photoresist reaction characteristic constant, it is generally heated at about 90 to 110 ° C to remove the solvent and increase the density of the photoresist, thereby reducing the sensitivity to environmental change .

Next, as shown in FIG. 3C, the photomask 140 is aligned on the photoresist layer 130, and exposure is performed by irradiating light. At this time, the photomask 140 forms a pattern in the area around the via hole so that the photoresist layer under the photoresist layer can not be irradiated with light.

On the other hand, it is preferable that the photoresist is a photosensitive resin in which the polymer solubilizes only the portion irradiated with light and the resist disappears, that is, a positive type photoresist. For example, polymethyl methacrylate, naphthoquinone diazide, polybutene-1-one, and the like can be used as the positive type photoresist.

Next, as shown in FIG. 3D, the photoresist layer 130 formed on the remaining portion of the photomask 140 except for the region where the light is not irradiated is removed through a developing process.

As the developing solution of the photoresist, a water-soluble alkali solution can be used, and an aqueous solution of KOH and TMAH (TetraMethyl-Ammonium-Hydroxide) is used as the main raw material. When the development is finished, the developer can be removed and a hard bake can be performed as needed.

Through the above-described process, the photoresist layer 130 remaining in the region around the via hole 160 as shown in FIG. 3E forms the via hole structure 130a.

According to the present embodiment, since a via hole is formed in a printed circuit board by a photolithography process, a minute pitch of 0.3 mm or less can be realized and the positional accuracy of the via hole can be improved.

Further, EMC residues, which had been a problem in forming a via hole by the conventional laser drilling process, do not occur.

Further, when the upper package is laminated on the lower package, the filling height of the metal filler can be set according to the diameter of the solder ball of the upper package, so that the interval between the upper and lower packages can be minimized.

FIG. 4 is a process sectional view showing the semiconductor package stacking process shown in FIG. 2E.

4, the solder ball 120 provided in the wiring pattern 102 'of the upper package is inserted into the via hole 160 formed in the lower package and bonded to the metal filler 150. According to the present embodiment, by adjusting the filling height of the metal filler 150 in the via hole 160, it is possible to finely adjust the stacking interval have. 4B shows an example in which the solder ball 120 and the metal filler 150 are bonded to each other to minimize the stacking interval of the lower package and the upper package.

5A to 5F are cross-sectional views illustrating a process of fabricating a stacked semiconductor package according to another embodiment of the present invention. 5A to FIG. 5F, unlike the manufacturing method described above with reference to FIGS. 2A to 2E, the method for manufacturing a stacked semiconductor package according to another embodiment of the present invention differs from the manufacturing method described with reference to FIGS. 2A to 2E in that an epoxy molding compound Is applied to the entire area to form a molding layer, and then some molding layer is removed through a grinding process. Hereinafter, the process will be described in detail.

First, as shown in FIG. 5A, a via hole structure 230a is formed on the upper surface of the printed circuit board 200 to form a via hole 260 in a negative shape.

The via hole structure 230a is formed in a region around the via hole pads 204 of the printed circuit board 200, and a photolithography process using a photomask may be used. This process is the same as that described above with reference to Figs. 3A to 3E, and therefore, a detailed description thereof will be omitted.

Wiring patterns 201 and 202 and a via hole pad 204 are formed on the printed circuit board 100 and a via contact for electrically connecting the upper and lower wiring patterns 201 and 202 is provided.

Next, as shown in FIG. 5B, the semiconductor chip 210 is mounted on the upper surface of the printed circuit board 200. In FIG. 5B, the semiconductor chip 210 is electrically connected to the printed circuit board 200 by a flip chip structure 212, but may be connected by wire bonding.

Next, as shown in FIG. 5C, the via hole 260 is filled with the metal filler 250. Next, as shown in FIG. The metal filler 250 may be charged at different heights, as the case may be. Particularly, when the upper package is laminated on the lower package, the filling height of the metal filler 250 can be set so that the interval between the upper and lower packages is minimized according to the diameter of the solder ball of the upper package.

5D, an epoxy molding compound (EMC) is applied to the entire area including the semiconductor chip 210, the via hole structure 230a, and the metal filler 250 on the printed circuit board 200, The molding layer 240 is formed.

Next, as shown in FIG. 5E, the molding layer 240 is ground so that the upper surface of the via hole structure 230a and the metal filler 250 are exposed.

Next, as shown in FIG. 5F, on the lower package on which the semiconductor chip 210 is mounted, the metal filler 250 is filled, the molding layer 240 is formed and the grinding is completed, .

 At this time, the metal filler 250 filled in the via hole 260 of the lower package and the solder ball 220 provided on the wiring pattern 202 'of the upper package are bonded through soldering.

6A to 6F are cross-sectional views illustrating a process of fabricating a stacked semiconductor package according to another embodiment of the present invention. 6A to 6F, unlike the manufacturing method described above with reference to FIGS. 5A to 5F, the method of fabricating a stacked semiconductor package according to still another embodiment of the present invention may include filling a via hole structure The EMC is prevented from entering the via hole when the molding layer is formed on the entire upper surface of the printed circuit board by using an epoxy molding compound (EMC). As a result, the via hole can maintain the void state, and the height of the via metal can be controlled through the solder ball attachment in the via hole, which is advantageous in controlling the gap between the lower package and the upper package. Hereinafter, the process will be described in detail.

First, as shown in FIG. 6A, a via hole structure 330a is formed on the upper surface of the printed circuit board 300 to form a via hole 360 in a negative shape.

The via hole structure 330a is formed in a region around the via hole pad 304 of the printed circuit board 300, and a photolithography process using a photomask may be used. This process is the same as that described above with reference to Figs. 3A to 3E, and therefore, a detailed description thereof will be omitted.

Wiring patterns 301 and 302 and a via hole pad 304 are formed on the printed circuit board 300 and a via contact for electrically connecting wiring patterns 301 and 302 on upper and lower surfaces is provided.

Next, as shown in FIG. 6B, the semiconductor chip 310 is mounted on the upper surface of the printed circuit board 300. 6B, the semiconductor chip 310 is electrically connected to the printed circuit board 300 by a flip chip attachment structure 312, but it is also possible to have a structure in which the semiconductor chip 310 is connected by wire bonding.

Next, as shown in FIG. 6C, a photoresist film 350 is coated on the upper surface of the via hole structure 330a. In the embodiment of the present invention, the photoresist film 350 is coated from the via hole structure 330a formed in the left region of the printed circuit board 300 to the via hole structure 330a formed in the right region, The resist film 350 may be coated only on the upper surface of the via hole structure 330a.

Next, a photomask is aligned on the photoresist film 350, and light is irradiated to perform an exposure process. At this time, the photomask has a pattern formed in the area around the via hole, so that the photoresist layer under the photomask can not be irradiated with light.

On the other hand, it is preferable that the photoresist is a photosensitive resin in which the polymer solubilizes only the portion irradiated with light and the resist disappears, that is, a positive type photoresist.

Thereafter, the photoresist film formed on the remaining portion (that is, the region where the semiconductor chip is mounted) except for the region where the light is not irradiated is removed by the pattern of the photomask through the developing process.

6D, an epoxy molding compound (EMC) is molded on the entire area including the semiconductor chip 310 and the via hole structure 330a on the printed circuit board 300 to form a molding layer 340 ).

Next, as shown in FIG. 6E, the molding layer 340 is ground so that the upper surface of the via hole structure 330a is exposed.

Next, as shown in FIG. 6F, a solder ball 370 is attached to the via hole pad 304 located between the via hole structures 330a.

 It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description, and all changes or modifications derived from the scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

100, 100 ', 200, 200', 300: printed circuit board
101, 102, 201, 202, 301, 302: wiring patterns
104, 204, 304: via hole pads
110, 110 ', 210 and 310: semiconductor chips
120, 220: solder ball 130: photoresist layer
130a, 230a, 330a: a via hole structure
140, 140 ', 240, 340: molding layer 150, 250: metal filler
160, 260, 360: via hole 170: photomask
350: photoresist film 370: solder ball

Claims (10)

(a) forming a via hole structure (130a) in a region around the via hole pad (104) on a printed circuit board (100) having wiring patterns (101,102) and a via hole pad (104);
(b) mounting the semiconductor chip 110 on the upper surface of the printed circuit board 100;
(c) forming a molding layer (140) on the printed circuit board (100) by molding only the upper surface of the region where the semiconductor chip (110) is mounted; And
(d) filling a via hole (160) formed between the via hole structures (130a) with a metal filler (150) to prepare a lower package.
The method of claim 1, wherein the step (a)
And forming the via hole structure (130a) in a negative shape using a photolithography process using a photomask (170).
The method of claim 1, wherein the step (a)
Forming a photoresist layer (130) on the upper surface of the printed circuit board (100) including the wiring pattern (101) and the via hole pad (104)
And a step of aligning a photomask (170) having a pattern formed in a peripheral region of the via hole on the upper surface of the photoresist layer (130) and irradiating light to remove the photoresist layer corresponding to the via hole region Method of manufacturing a package.
The method according to claim 1,
(e) stacking the upper package on which the semiconductor chip 110 'is mounted on the prepared lower package.
5. The method of claim 4, wherein step (e)
And soldering the metal filler (150) of the lower package and the wiring pattern (102 ') provided in the upper package.
(a) forming a via hole structure 230a in a region around the via hole pad 204 on a printed circuit board 200 having wiring patterns 201 and 202 and a via hole pad 204;
(b) mounting the semiconductor chip 210 on the upper surface of the printed circuit board 200;
(c) filling the via hole (260) formed between the via hole structures (230a) with a metal filler (250);
(d) molding the upper surface of the printed circuit board 200 including the semiconductor chip 210, the via hole structure 230a and the metal filler 250 to form a molding layer 240; And
(e) grinding the molding layer (240) to expose the upper surfaces of the via hole structure (230a) and the metal filler (250).
The method of claim 1, wherein the step (a)
And forming the via hole structure in a negative shape using a photolithography process using a photomask.
8. The method of claim 7, wherein step (a)
Forming a photoresist layer on the upper surface of the printed circuit board including the wiring pattern and the via hole pads;
And aligning a photomask having a pattern formed in a via hole region on the upper surface of the photoresist layer and irradiating light to remove the photoresist layer corresponding to the via hole region.
(a) forming a via hole structure 330a in a region around the via hole pad 304 on a printed circuit board 300 having wiring patterns 301 and 202 and a via hole pad 304;
(b) mounting the semiconductor chip 310 on the upper surface of the printed circuit board 300;
(c) coating a photoresist film 350 on the upper surface of the via hole structure 330a;
(d) molding the upper surface of the printed circuit board 300 including the semiconductor chip 310 and the via hole structure 330a to form a molding layer 340; And
(e) grinding the molding layer (340) to expose the upper surface of the via hole structure (330a).
10. The method of claim 9,
(f) attaching a solder ball (370) on the via hole pad (304) located between the via hole structures (330a).
KR1020140136740A 2014-10-10 2014-10-10 Method for manufacturing stacked semiconductor package KR101648199B1 (en)

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Publication number Priority date Publication date Assignee Title
KR20050069938A (en) * 2004-05-31 2005-07-05 강준모 Method of aligning semiconductor device and semiconductor structure thereof
KR100674316B1 (en) 2005-11-25 2007-01-24 삼성전기주식회사 Method forming via hole that utilizes lazer drill
KR20070045929A (en) * 2005-10-27 2007-05-02 신꼬오덴기 고교 가부시키가이샤 Electronic-part built-in substrate and manufacturing method therefor
US20100144101A1 (en) * 2008-12-05 2010-06-10 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Conductive Posts Embedded in Photosensitive Encapsulant
US20130249101A1 (en) * 2012-03-23 2013-09-26 Stats Chippac, Ltd. Semiconductor Method of Device of Forming a Fan-Out PoP Device with PWB Vertical Interconnect Units

Patent Citations (5)

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Publication number Priority date Publication date Assignee Title
KR20050069938A (en) * 2004-05-31 2005-07-05 강준모 Method of aligning semiconductor device and semiconductor structure thereof
KR20070045929A (en) * 2005-10-27 2007-05-02 신꼬오덴기 고교 가부시키가이샤 Electronic-part built-in substrate and manufacturing method therefor
KR100674316B1 (en) 2005-11-25 2007-01-24 삼성전기주식회사 Method forming via hole that utilizes lazer drill
US20100144101A1 (en) * 2008-12-05 2010-06-10 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Conductive Posts Embedded in Photosensitive Encapsulant
US20130249101A1 (en) * 2012-03-23 2013-09-26 Stats Chippac, Ltd. Semiconductor Method of Device of Forming a Fan-Out PoP Device with PWB Vertical Interconnect Units

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