KR20160034055A - Semiconductor package an And Method Of Fabricating The Same - Google Patents

Semiconductor package an And Method Of Fabricating The Same Download PDF

Info

Publication number
KR20160034055A
KR20160034055A KR1020140125095A KR20140125095A KR20160034055A KR 20160034055 A KR20160034055 A KR 20160034055A KR 1020140125095 A KR1020140125095 A KR 1020140125095A KR 20140125095 A KR20140125095 A KR 20140125095A KR 20160034055 A KR20160034055 A KR 20160034055A
Authority
KR
South Korea
Prior art keywords
bump
film
forming
weight percent
semiconductor
Prior art date
Application number
KR1020140125095A
Other languages
Korean (ko)
Inventor
노보인
Original Assignee
삼성전자주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Priority to KR1020140125095A priority Critical patent/KR20160034055A/en
Publication of KR20160034055A publication Critical patent/KR20160034055A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

The present invention provides a semiconductor package and a method for manufacturing the same. The method for manufacturing the semiconductor package according to the embodiment includes the steps of: forming a first bump film including tin and bismuth on a semiconductor device; forming a bump part by reflowing the bump film; and providing a semiconductor chip on the bump part, wherein the semiconductor device is electrically connected to the substrate through the bump part. Reflow of the bump film is proceeded at the temperature between 138°C and 180°C, and the bismuth of 30 wt% ~ 60 wt% as to the bump part may be included.

Description

Technical Field [0001] The present invention relates to a semiconductor package and a fabrication method thereof.

The present invention relates to semiconductors, and more particularly to semiconductor packages.

[0002] As semiconductor integrated circuits used in electronic devices have become more dense and highly integrated, pin terminals and narrow pitches of electrode terminals of semiconductor devices are rapidly progressing. Semiconductor devices generally have an electrical connection structure such as solder balls or bumps in order to be electrically connected to other semiconductor devices or printed circuit boards. Accordingly, there is a need for an electrical connection structure of a semiconductor device that can realize electrical connection more reliably and stably.

An object of the present invention is to provide a reliable semiconductor package and a manufacturing method thereof by implementing electrical connection at a low temperature.

The present invention relates to a semiconductor package and a manufacturing method thereof. A method of manufacturing a semiconductor package according to the present invention includes: providing a semiconductor substrate having chip pads; Forming an under bump metal film on the semiconductor substrate in contact with the chip pad; Forming a mask pattern having openings vertically aligned with the chip pads on the semiconductor substrate; Forming a first bump film in the opening, the first bump film including tin and bismuth; Reflowing said first bump film to form a bump portion; Providing a package substrate having connection pads on the bump portion; And connecting the bump portion to the connection pad by soldering the bump portion at 138 占 폚 to 180 占 폚, wherein the first bump film is reflowed at 138 占 폚 to 180 占 폚, and the bismuth is 30 weight% Percent to 60 percent by weight.

According to an embodiment, the method further comprises forming a second bump film disposed on the first bump film and including silver, wherein forming the bump further comprises reflowing the second bump film, Silver (Ag) may be included in an amount of 0.1 weight percent and 0.25 weight percent relative to the bump portion.

According to an embodiment, forming the second bump film may comprise electrolytically plating the silver (Ag) onto the first bump film in the opening.

According to an embodiment, forming the second bump film comprises electrolytically plating the silver (Ag) and bismuth (Bi) on the first bump film in the opening, wherein the silver (Ag) From 0.1 weight percent to 3.5 weight percent of the bump film.

According to an embodiment, the method further comprises forming a pillar pattern on the under bump metal film, wherein forming the pillar pattern may be performed prior to forming the first bump film.

According to an embodiment, the package substrate may include a semiconductor chip.

According to an embodiment, the method may further include forming a molding film covering the semiconductor element on the package substrate.

A semiconductor package of the present invention includes: a package substrate; A semiconductor substrate provided on the package substrate and having a chip pad, the chip pad being disposed on a first side facing the package substrate; An under bump metal film provided on the chip pad of the semiconductor substrate; And a bump portion interposed between the package substrate and the under bump metal film, the bump portion electrically connecting the semiconductor substrate to the package substrate, the bump portion comprising: 30 to 60 weight percent of tin (Sn); 0.1 weight percent to 0.25 weight percent silver (Ag); And bismuth (Bi).

According to an embodiment, the under bump metal film and the pillar pattern interposed between the bumps may be further included.

According to an embodiment, the bump portion may have a melting temperature of 138 ° C to 180 ° C.

According to the present invention, reflow of the bump film and soldering of the bump portion can proceed at a low temperature. For example, the material and the composition ratio of the bump film can be adjusted so that the reflow of the bump film and the soldering temperature of the bump portion can be controlled. Thus, in the soldering process of the bump portion, damage of the package substrate such as warpage can be prevented. In addition, in the reflow and soldering process, the semiconductor chip and the package substrate may not be damaged by heat. As the reflow of the bump film and the soldering of the bump portion are performed at a low temperature, the semiconductor package can be easily manufactured.

According to the present invention, the material and the composition ratio of the bump film are adjusted, and the characteristics (for example, strength, etc.) of the bump film to be formed can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS For a more complete understanding and assistance of the invention, reference is made to the following description, taken together with the accompanying drawings,
1A to 1E are cross-sectional views illustrating a manufacturing process of a semiconductor device according to an embodiment.
FIGS. 2A to 2D are cross-sectional views illustrating a manufacturing process of a semiconductor device according to another embodiment of the present invention.
3A to 3D are cross-sectional views illustrating a manufacturing process of a semiconductor device according to still another embodiment.
4A and 4B are cross-sectional views illustrating a method of manufacturing a semiconductor package according to an embodiment of the present invention.
5A is a block diagram illustrating a memory card having a semiconductor package according to an embodiment of the present invention.
5B is a block diagram illustrating an information processing system using a semiconductor package according to an embodiment of the present invention.

In order to fully understand the structure and effects of the present invention, preferred embodiments of the present invention will be described with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. It will be apparent to those skilled in the art that the present invention may be embodied in many other specific forms without departing from the spirit or essential characteristics thereof. Those of ordinary skill in the art will understand that the concepts of the present invention may be practiced in any suitable environment.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. As used herein, the terms 'comprises' and / or 'comprising' mean that the stated element, step, operation and / or element does not imply the presence of one or more other elements, steps, operations and / Or additions.

When a film (or layer) is referred to herein as being on another film (or layer) or substrate it may be formed directly on another film (or layer) or substrate, or a third film Or layer) may be interposed.

 Although the terms first, second, third, etc. have been used in various embodiments herein to describe various regions, films (or layers), etc., it is to be understood that these regions, Can not be done. These terms are merely used to distinguish any given region or film (or layer) from another region or film (or layer). Thus, the membrane referred to as the first membrane in one embodiment may be referred to as the second membrane in another embodiment. Each embodiment described and exemplified herein also includes its complementary embodiment. Like numbers refer to like elements throughout the specification.

The terms used in the embodiments of the present invention may be construed as commonly known to those skilled in the art unless otherwise defined.

Hereinafter, a method of manufacturing a semiconductor package according to the concept of the present invention will be described.

1A to 1E are cross-sectional views illustrating a manufacturing process of a semiconductor device according to an embodiment.

Referring to FIG. 1A, a passivation film 120, a first metal film 210, and a second metal film 220 may be sequentially formed on a semiconductor substrate 100. The semiconductor substrate 100 may be, for example, a silicon substrate. The semiconductor substrate 100 may be a wafer level substrate including a semiconductor chip. Chip pads 110 may be provided on the semiconductor substrate 100. [ The chip pad 110 may comprise a metallic material (e.g., copper or aluminum).

A passivation film 120 may be formed on the semiconductor substrate 100. [ The passivation film 120 may open the chip pad 110. The passivation film 120 may include a silicon oxide film, a silicon nitride film, or a photosensitive polyimide. The first metal film 210 may be formed by depositing (e.g., sputtering) Ti, Ti-W, Cr, Al, or a combination thereof on the semiconductor substrate 100 and the pad. The first metal film 210 may function as an adhesive film, including a metal having good adhesion to the chip pad 110 or the passivation film 120.

The second metal film 220 may be formed by depositing (e.g., sputtering) Ni, NiV, Cu, Cr-Cu, or a combination thereof on the first metal film 210. The second metal film 220 may function as a barrier film, including a bump film (e.g., Sn-Bi and / or Sn-Ag or the like) described later in FIG. 1C or a metal capable of preventing diffusion of other metals have.

Referring to FIG. 1B, a mask pattern 250 having an opening 251 may be formed on the semiconductor substrate 100. For example, a photoresist layer may be applied on the semiconductor substrate 100, and the photoresist layer may be patterned to form a mask pattern 250. The opening 251 may expose the second metal film 220 on the chip pad 110. The opening 251 may overlap with the chip pad 110. The height of the mask pattern 250 can be adjusted. A third metal film 230 may be formed on the second metal film 220 in the opening 251 by an electrolytic plating method. For example, the third metal film 230 may be selectively formed in the opening portion 251 by electrolytic plating. The third metal film 230 may function as a wetting film, including the first bump film 310 described later in FIG. 1A and Ni, Cu, Au, or a combination thereof having good wetting.

Referring to FIG. 1C, a first bump film 310 may be formed on the third metal film 230 in the opening 251. The first bump film 310 may be formed by plating (for example, electrolytic plating) tin-bismuth (Sn-Bi). At this time, bismuth may be included in an amount of 30 to 60 percent by weight relative to the first bump film 310. The shape of the first bump film 310 may vary depending on the height of the mask pattern 250 or the volume of the first bump film 310. For example, when the first bump film 310 is formed higher than the upper surface of the mask pattern 250, the first bump film 310 may have a mushroom-shaped cross-section. Alternatively, the first bump film 310 may be formed to have a height substantially equal to or lower than the upper surface of the mask pattern 250, and may have a rectangular cross-section.

Referring to FIG. 1D, the mask pattern 250 may be removed. The mask pattern 250 may be removed by an ashing process. Accordingly, the second metal film 220 not covered by the first bump film 310 can be exposed. The second metal film 220 and the first metal film 210 not covered by the first bump film 310 can be removed by an etching process. Thus, the under bump metal film 200 can be formed. The under bump metal film 200 may include a first metal film 210, a second metal film 220, and a third metal film 230 stacked.

Referring to FIG. 1E and FIG. 1D, the first bump film 310 is reflowed to form the bump portion 300. The reflow of the first bump film 310 may proceed to a low temperature process. For example, the first bump film 310 may be reflowed at a temperature of 138 ° C to 180 ° C. Here, the reflow temperature may mean the temperature of the first bump film 310. When the first bump film 310 is reflowed, the first bump film 310 can be changed to a liquid phase. Due to the surface tension of the liquid solder, the first bump film 310 can form a bead-shaped bump portion 300. When the temperature of the first bump film 310 is lower than 138 占 폚 at the time of reflow, a part of the first bump film 310 may be changed into a liquid phase, but the other part may not change into a liquid phase. Accordingly, the characteristics of the formed bump portion 300 may be deteriorated. If the temperature applied to the first bump film 310 is higher than 180 占 폚, the semiconductor substrate 100 may be damaged by heat. For example, a circuit pattern (not shown) included in the semiconductor substrate 100 may be damaged.

The reflux temperature of the first bump film 310 can be controlled by adjusting the metal material and the composition of the first bump film 310. For example, bismuth may be included in the first bump film 310 in an amount of 30 to 60 percent by weight. If the content of bismuth is lower than 30 weight percent, the first bump film 310 may reflow at high temperature conditions (e.g., greater than 180 degrees Celsius). If the content of tin is higher than 60 weight percent, the formed bump part 300 may be easily damaged by an external impact in the manufacturing process. For example, the bump portion 300 may be brittle in the manufacturing process of the semiconductor element 11 or the manufacturing process of the semiconductor package 1 described later in FIGS. 4A and 4B. The bump portion 300 may have the same material and the same composition ratio as the first bump film 310. For example, the bump portion 300 may include tin-bismuth (Sn-Bi), and the bismuth may include 30 to 60 percent by weight of the bump portion 300. The bump portion 300 may have a melting temperature of 138 캜 to 180 캜.

The height of the mask pattern 250 formed in FIG. 1B may be adjusted, or the height of the first bump film 310 formed in FIG. 1C may be adjusted so that the height of the bump portion 300 may be adjusted. According to the production example described so far, the production of the semiconductor element 11 can be completed.

FIGS. 2A to 2D are cross-sectional views illustrating a manufacturing process of a semiconductor device according to another embodiment of the present invention. Hereinafter, duplicated description will be omitted.

2A, the semiconductor device includes a chip pad 110, a passivation film 120, a first metal film 210, a second metal film 220, a third metal film 230, and a mask pattern 250 A semiconductor substrate 100 may be provided. The passivation film 120, the first metal film 210, and the second metal film 220 may be formed as described above with reference to FIG. 1A, and the mask pattern 250 and the third metal film 230 may be formed as shown in FIG. 1b. ≪ / RTI > The first bump film 310 may be formed on the semiconductor substrate 100 in the opening portion 251. [ The first bump film 310 may be formed by plating (for example, electrolytic plating) tin-bismuth (Sn-Bi). Bismuth may be included in an amount of 30 to 60 percent by weight relative to the first bump film 310. At this time, the first bump film 310 may have a lower height than the metal film formed previously in FIG. 1C.

Referring to FIG. 2B, a second bump film 320 may be formed on the first bump film 310 in the opening 251. The second bump film 320 may include a metal other than the metal included in the first bump film 310, for example, silver (Ag). For example, the second bump film 320 may be formed by electrolytically plating silver (Ag) on the first bump film 310. As another example, the second bump film 320 may be formed by electrolytically plating tin-silver (Sn-Ag) on the first bump film 310. In this case, silver (Ag) may be included in an amount of 0.1 to 3.5 percent by weight relative to the second bump film 320. The thickness of the second bump film 320 and the ratio of the silver (Ag) content in the second bump film 320 can be adjusted.

Referring to FIG. 2C, the mask pattern 250 may be removed, and a portion of the second metal film 220 may be exposed. A part of the second metal film 220 and a part of the first metal film 210 may be removed so that the under bump metal film 200 can be formed. A portion of the second metal film 220 to be removed and a portion of the first metal film 210 may be portions not covered by the first and second bump films 310 and 320. The removal of the mask pattern 250, the first metal film 210, and the second metal film 220 may be performed in the same manner as described above with reference to FIG. 1D.

Referring to FIG. 2D and FIG. 2C, the first bump film 310 and the second bump film 320 are reflowed to form the bump portion 300. The first bump film 310 and the second bump film 320 can be reflowed by the same process.

The reflow of the first and second bump films 310 and 320 may proceed to a low temperature process. For example, the first and second bump films 310 and 320 may be reflowed at a temperature of 138 ° C to 180 ° C. Here, the reflow temperature may mean the temperature of the first and second bump films 310 and 320. If the temperature of the first and second bump films 310 and 320 is lower than 138 占 폚, a part of the first and second bump films 310 and 320 may not change into a liquid phase. If the temperature of the first and second bump films 310 and 320 is higher than 180 ° C, the semiconductor substrate 100 may be damaged by heat.

The material contained in the first bump film 310 (e.g., tin-bismuth Sn-Bi) and the material contained in the second bump film 320 (e.g., silver (Ag) (Sn-Ag)) can be mixed with each other by a reflow process. Accordingly, the bump portion 300 may include tin-bismuth-silver (Sn-Bi-Ag). Bismuth may be included in the bump portion 300 in an amount of 30 to 60 percent by weight. If the content of bismuth is lower than 30 weight percent, the first and second bump films 310 and 320 may reflow at high temperature conditions (e.g., greater than 180 degrees Celsius). When the content of bismuth is higher than 60 weight percent, the hardness of the bump portion may be low. The formed bump portion 300 may be easily damaged by external impacts. Silver (Ag) may be included in the range of 0.1 weight percent to 0.25 weight percent relative to the bump portion 300. At this time, the content of tin-bismuth-silver (Sn-Bi-Ag) contained in the bump portion 300 can be adjusted by adjusting the thicknesses of the first bump film 310 and the second bump film 320 have. Thus, the reflow temperature can be adjusted as described above. If the silver (Ag) is included less than 0.1 weight percent of the bump portion 300, the formed bump portion 300 may have low strength. The bump portion 300 may not be formed at the temperature of 138 캜 to 180 캜 described above when the silver (Ag) is contained in an amount exceeding 0.25% by weight with respect to the bump portion 300. For example, the bump portion 300 may be formed at a temperature condition higher than 180 ° C. According to the production example described so far, the production of the semiconductor element 12 can be completed.

3A to 3D are cross-sectional views illustrating a manufacturing process of a semiconductor device according to still another embodiment. Hereinafter, the same elements as those described above will be omitted.

The first metal film 210, the second metal film 220, the third metal film 230, and the mask pattern 250, as shown in FIG. 3A, a chip pad 9110), a passivation film 120, A semiconductor substrate 100 may be provided. The passivation film 120, the first metal film 210, and the second metal film 220 may be formed as described above with reference to FIG. 1A, and the mask pattern 250 and the third metal film 230 may be formed as shown in FIG. 1b. ≪ / RTI > A pillar pattern 400 may be formed on the semiconductor substrate 100 in the opening 251. [ The pillar pattern 400 may be formed by electrolytically plating a metal material (e.g., copper). In this case, the third metal film 230 may be omitted.

The first bump film 310 may be formed on the pillar pattern 400 in the opening 251. [ The first bump film 310 may be formed by plating (for example, electrolytic plating) tin-bismuth (Sn-Bi). Bismuth may be included in an amount of 30 to 60 percent by weight relative to the first bump film 310.

The second bump film 320 may be formed on the first bump film 310 in the opening portion 251. [ The second bump film 320 may be formed by the same method as described above with reference to FIG. 2B. For example, the second bump film 320 may be formed by electrolytically plating silver (Ag) on the first bump film 310. As another example, the second bump film 320 may be formed by electrolytically plating tin-silver (Sn-Ag) on the first bump film 310. In this case, silver (Ag) may be included in an amount of 0.1 to 3.5 percent by weight relative to the second bump film 320. The thickness of the second bump film 320 and the content ratio of silver can be adjusted. As another example, the formation of the second bump film 320 may be omitted.

Thereafter, the mask pattern 250 is removed, the mask pattern 250 is removed, and a part of the second metal film 220 can be exposed. The exposed second metal film 220 and the first metal film 210 may be selectively removed so that the under bump metal film 200 may be formed. Removal of the mask pattern 250 and removal of the first and second metal films 220 may be performed in the same manner as described above with reference to FIG.

Referring to FIG. 3B together with FIG. 3A, the first bump film 310 and the second bump film 320 are reflowed to form the bump portion 300. The first bump film 310 and the second bump film 320 may be reflowed by the same method as described above with reference to FIG. 2D. For example, the reflow of the first and second bump films 310 and 320 may be performed at a low-temperature process, for example, a temperature condition of 138 占 폚 to 180 占 폚. The material contained in the first bump film 310 (e.g., tin-bismuth Sn-Bi) and the material contained in the second bump film 320 (e.g., silver (Ag) (Sn-Ag)) can be mixed with each other by a reflow process. Accordingly, the bump portion 300 may include tin-bismuth-silver (Sn-Bi-Ag). Bismuth may be included in the bump portion 300 in an amount of 30 to 60 percent by weight. Silver (Ag) may be included in the range of 0.1 weight percent to 0.25 weight percent relative to the bump portion 300. The content of tin-bismuth-silver (Sn-Bi-Ag) contained in the bump portion 300 is controlled, and the reflow process temperature can be controlled. Thus, the manufacture of the semiconductor element 13 can be completed.

4A and 4B are cross-sectional views illustrating a method of manufacturing a semiconductor package according to an embodiment of the present invention. Hereinafter, duplicated description will be omitted.

Referring to FIG. 4A, a semiconductor substrate 100 on which a bump portion 300 is formed may be provided. The bump portion 300 can be manufactured by any one of the manufacturing methods of FIGS. 1A to 1E, the manufacturing examples of FIGS. 2A to 2D, and the manufacturing examples of FIGS. 3A and 3B. The semiconductor substrate 100 is a wafer level substrate, and may be the same as that described above with reference to FIG. 1A. The semiconductor substrate 100 may include a chip pad 110, an under bump metal film 200, and a bump portion 300. The bump portion 300 may have a melting temperature of 138 캜 to 180 캜. The semiconductor substrate 100 is sown, so that the semiconductor elements 10 can be separated from each other. For example, the semiconductor elements 10 may each comprise a semiconductor chip. Hereinafter, mounting of a plurality of semiconductor elements 10 will be described.

Referring to FIG. 4B, a semiconductor device 10 may be mounted on the package substrate 20. The package substrate 20 may be a printed circuit board (PCB) having a circuit pattern. As another example, the package substrate 20 may comprise a semiconductor chip. An external terminal 22 is provided on the lower surface of the package substrate 20 so that the package substrate 20 can be electrically connected to an external device (not shown). A connection pad 21 may be provided on the upper surface of the package substrate 20. [ The semiconductor element 10 can be mounted on the package substrate 20 by a flip chip method. The semiconductor element 10 may be disposed on the package substrate 20 such that the bump portion 300 of the semiconductor element 10 faces the connection pad 21 of the package substrate 20. [

The bump portion 300 is soldered so that the bump portion 300 can be connected to the connection pad. The bump portion 300 may be soldered at a low temperature. For example, the bump portion 300 may be soldered at a temperature that is the same as or similar to the reflow temperature described above in FIGS. 1E, 2D, and 3B. At this time, the soldering temperature of the bump unit 300 may mean the temperature applied to the bump unit 300.

The package substrate 20, the connection pad 21, and the bump portion 300 may have different coefficients of thermal expansion (CTE). If the temperature of the bump portion 300 is higher than 180 占 폚, the difference in temperature between the package substrate 20, the connection pad 21, and the bump portions 300 in the soldering process can be increased. As a result, a warpage phenomenon may occur in the package substrate 20. In addition, the circuit patterns (not shown) of the semiconductor element 10 can be damaged by the heat applied in the soldering process. If the temperature of the bump portion 300 is lower than 138 占 폚, the bump portion 300 may not be sufficiently liquefied. According to the present invention, the content ratio of tin-bismuth-silver (Sn-Bi-Ag) contained in the bump portion 300 is adjusted so that the bump portion 300 can be soldered at approximately 138 캜 to 180 캜. The semiconductor element 10 can be electrically connected to the package substrate 20 by soldering of the bump portion 300.

The underfill film 31 can be formed between the package substrate 20 and the semiconductor element 10 to cover the side surface of the bump portion 300. [ The molding film 30 can cover the semiconductor element 10 on the package substrate 20. The molding film 30 may comprise an epoxy based molding compound (EMC). As another example, the underfill film 31 may be omitted, and the molding film 30 may extend between the package substrate 20 and the semiconductor element 10.

<Application example>

5A is a block diagram illustrating a memory card having a semiconductor package according to an embodiment of the present invention. 5B is a block diagram illustrating an information processing system using a semiconductor package according to an embodiment of the present invention.

5A, a memory card 1200 may include a memory controller 1220 that controls the overall exchange of data between a host and a memory 1210. The SRAM 1221 may be used as an operating memory of the central processing unit 1222. [ The host interface 1223 may have a data exchange protocol of the host connected to the memory card 1200. [ The error correction code 1224 can detect and correct an error included in the data read from the memory 1210. The memory interface 1225 interfaces with the memory 1210. The central processing unit 1222 can perform all control operations for data exchange of the memory controller 1220. [ The memory 1210 may include a semiconductor package according to an embodiment of the present invention.

Referring to FIG. 5B, the information processing system 1300 may include a memory system 1310 having a semiconductor package in accordance with an embodiment of the present invention. The information processing system 1300 may include a mobile device, a computer, or the like. In one example, the information processing system 1300 includes a memory system 1310, a modem 1320, a central processing unit 1330, a RAM 1340, and a user interface 1350 that are electrically coupled to the system bus 1360 . The memory system 1310 may include a memory 1311 and a memory controller 1312 and may be configured substantially the same as the memory card 1200 of FIG. 5A. The memory system 1310 may store data processed by the central processing unit 1330 or externally input data. The information processing system 1300 may be provided as a memory card, a solid state disk, a camera image sensor, and other application chipsets.

It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and it will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit of the invention. The appended claims should be construed to include other embodiments.

Claims (10)

Providing a semiconductor substrate having a chip pad;
Forming an under bump metal film on the semiconductor substrate in contact with the chip pad;
Forming a mask pattern having openings vertically aligned with the chip pads on the semiconductor substrate;
Forming a first bump film in the opening, the first bump film including tin and bismuth;
Reflowing said first bump film to form a bump portion;
Providing a package substrate having connection pads on the bump portion; And
And soldering the bump portion at 138 占 폚 to 180 占 폚 to connect the bump portion to the connection pad,
The first bump film is reflowed at 138 캜 to 180 캜,
Wherein said bismuth is comprised between 30 weight percent and 60 weight percent relative to said bump portion.
The method according to claim 1,
Further comprising forming a second bump film disposed on the first bump film and comprising silver,
Forming the bump portion further includes reflowing the second bump film,
Wherein the silver (Ag) comprises 0.1 weight percent and 0.25 weight percent relative to the bump portion.
3. The method of claim 2,
Wherein forming the second bump film comprises electroplating the silver (Ag) on the first bump film in the opening.
3. The method of claim 2,
Forming the second bump film comprises electrolytically plating the silver (Ag) and bismuth (Bi) on the first bump film in the opening,
Wherein the silver (Ag) comprises from 0.1 weight percent to 3.5 weight percent of the second bump film.
The method according to claim 1,
Further comprising forming a pillar pattern on the under bump metal film in the opening, wherein forming the pillar pattern is performed prior to forming the first bump film.
The method according to claim 1,
Wherein the package substrate comprises a semiconductor chip.
The method according to claim 1,
And forming a molding film covering the semiconductor element on the package substrate.
A package substrate;
A semiconductor substrate provided on the package substrate and having a chip pad, the chip pad being disposed on a first side facing the package substrate;
An under bump metal film provided on the chip pad of the semiconductor substrate; And
And a bump portion interposed between the package substrate and the under bump metal film to electrically connect the semiconductor substrate to the package substrate,
The bump portion includes:
Tin (Sn) 30 weight percent to 60 weight percent;
0.1 weight percent to 0.25 weight percent silver (Ag); And
A semiconductor package comprising a bismuth (Bi).
9. The method of claim 8,
And a pillar pattern interposed between the under bump metal film and the bump.
9. The method of claim 8,
Wherein the bump portion has a melting temperature of 138 占 폚 to 180 占 폚.
KR1020140125095A 2014-09-19 2014-09-19 Semiconductor package an And Method Of Fabricating The Same KR20160034055A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020140125095A KR20160034055A (en) 2014-09-19 2014-09-19 Semiconductor package an And Method Of Fabricating The Same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020140125095A KR20160034055A (en) 2014-09-19 2014-09-19 Semiconductor package an And Method Of Fabricating The Same

Publications (1)

Publication Number Publication Date
KR20160034055A true KR20160034055A (en) 2016-03-29

Family

ID=55661905

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020140125095A KR20160034055A (en) 2014-09-19 2014-09-19 Semiconductor package an And Method Of Fabricating The Same

Country Status (1)

Country Link
KR (1) KR20160034055A (en)

Similar Documents

Publication Publication Date Title
KR102007780B1 (en) Methods for fabricating semiconductor devices having multi-bump structural electrical interconnections
TWI587462B (en) Method for forming semiconductor device
US9070671B2 (en) Microelectronic flip chip packages with solder wetting pads and associated methods of manufacturing
US8076232B2 (en) Semiconductor device and method of forming composite bump-on-lead interconnection
US7851345B2 (en) Semiconductor device and method of forming oxide layer on signal traces for electrical isolation in fine pitch bonding
US10593640B2 (en) Flip chip integrated circuit packages with spacers
US11894330B2 (en) Methods of manufacturing a semiconductor device including a joint adjacent to a post
US20080230925A1 (en) Solder-bumping structures produced by a solder bumping method
KR20060130688A (en) Under bump metallization layer to enable use of high tin content solder bumps
US20090302468A1 (en) Printed circuit board comprising semiconductor chip and method of manufacturing the same
TW201232681A (en) Semiconductor device and method of forming bump-on-lead interconnection
US9960143B2 (en) Method for manufacturing electronic component and manufacturing apparatus of electronic component
CN109390306A (en) Electronic package
US7759137B2 (en) Flip chip interconnection structure with bump on partial pad and method thereof
US11121101B2 (en) Flip chip packaging rework
TWI242866B (en) Process of forming lead-free bumps on electronic component
CN111199946A (en) Copper pillar bump structure and manufacturing method thereof
KR101926713B1 (en) Semiconductor package and method of fabricating the same
WO2022236640A1 (en) Integrated circuit stacking structure and manufacturing method therefor, and electronic apparatus
TW201225209A (en) Semiconductor device and method of confining conductive bump material with solder mask patch
KR100927773B1 (en) Semiconductor package and manufacturing method thereof
EP3704733B1 (en) Chip package assembly with enhanced interconnects and method for fabricating the same
KR20160034055A (en) Semiconductor package an And Method Of Fabricating The Same
US8759210B2 (en) Control of silver in C4 metallurgy with plating process
US8969192B1 (en) Low stress substrate and formation method

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination