WO2022236640A1

WO2022236640A1 - Integrated circuit stacking structure and manufacturing method therefor, and electronic apparatus

Info

Publication number: WO2022236640A1
Application number: PCT/CN2021/092904
Authority: WO
Inventors: 李珩; 张晓东; 孙梦龙; 王思敏; 刘阳; 洪正辉
Original assignee: 华为技术有限公司
Priority date: 2021-05-10
Filing date: 2021-05-10
Publication date: 2022-11-17
Also published as: CN116762167A

Abstract

Embodiments of the present application relate to the technical field of semiconductors, and provide an integrated circuit stacking structure and a manufacturing method therefor, and an electronic device, capable of solving the problem that a first conductive layer and a second conductive layer are not electrically connected due to large warpage of a first integrated circuit device and/or a second integrated circuit device or poor coplanarity of multiple solders. The manufacturing method for the integrated circuit stacking structure comprises: forming a solder on a first conductive layer exposed to a surface of a first integrated circuit device; forming a protrusion on a second conductive layer exposed to a surface of a second integrated circuit device; and heating the solder and the protrusion, and coupling the first integrated circuit device with the second integrated circuit device together, wherein the protrusion is inserted inside the solder.

Description

Integrated circuit stack structure and manufacturing method thereof, electronic device

technical field

The present application relates to the field of semiconductor technology, and in particular to an integrated circuit stack structure, a manufacturing method thereof, and electronic equipment.

Background technique

At present, the stacking structure is widely used in various fields. Taking the stacking structure applied in the field of semiconductor technology as an example to realize the stacking of multiple chips in the thickness direction, in the prior art, two of the integrated circuit stacking structures When the chips are interconnected, as shown in FIG. 1 , the first chip 10 includes a first substrate 10a, a first conductive layer 11 disposed on the first substrate 10a, and a first passivation layer disposed on the first conductive layer 11 12. The first passivation layer 12 includes a first opening, at least part of the first conductive layer 11 is exposed in the first opening. The second chip 20 includes a second substrate 20a, a second conductive layer 21 disposed on the second substrate 20a, and a second passivation layer 22 disposed on the second conductive layer 21, the second passivation layer 22 comprising a second opening At least part of the second conductive layer 21 is exposed in the second opening. When the first chip 10 and the second chip 20 are interconnected, solder 13 is formed on the first conductive layer 11 exposed on the surface of the first chip 10 , and the solder 13 is electrically connected to the first conductive layer 11 . An under bump metallurgy (UBM) 23 is formed on the second conductive layer 21 exposed on the surface of the second chip 20 , and the under bump metallurgy 23 is electrically connected to the second conductive layer 21 . The interconnection between the first chip 10 and the second chip 20 can be realized by soldering a plurality of solder 13 and a plurality of UBM layers 23 together one by one, and the solder 13 and the UBM layers 23 During soldering, the lower surface of the solder 13 is in contact with the upper surface of the UBM layer 23 . In addition, a buffer material 30 may be filled between the first chip 10 and the second chip 20 .

However, when the method provided by the prior art is used to realize the interconnection of the first chip 10 and the second chip 20, if the warpage of the first chip 10 and/or the second chip 20 is relatively large, or if multiple The coplanarity (coplanarity, COP) of solder 13 is poor, namely the difference of the distance between the surface of multiple solder 13 near the second chip 20 and the first substrate 10a is relatively large (only one solder ball is schematically shown in FIG. 1 ), then When a plurality of solders 13 and a plurality of UBM layers 23 are soldered in one-to-one correspondence, it may occur that part of the solder 13 and the UBM layers 23 are not in contact (non-touch), thereby causing the first conductive layer 11 and the second conductive layer 12 are not electrically connected, thereby causing the interconnection between the first chip 10 and the second chip 20 to fail.

Contents of the invention

Embodiments of the present application provide an integrated circuit stack structure and its manufacturing method, and electronic equipment, which can solve problems caused by the large warpage of the first integrated circuit device and/or the second integrated circuit device, or the coplanarity of multiple solders. Poor performance, resulting in the problem that the first conductive layer and the second conductive layer are not electrically connected.

In order to achieve the above object, the application adopts the following technical solutions:

In a first aspect, a method for manufacturing an integrated circuit stack structure is provided. The method for manufacturing the integrated circuit stack structure includes: first, forming solder on the first conductive layer exposed on the surface of the first integrated circuit device; forming bumps on the second conductive layer on the surface of the second integrated circuit device; next, heating the solder and the bumps to couple the first integrated circuit device and the second integrated circuit device; wherein the bumps are inserted into the solder . When the first integrated circuit device and the second integrated circuit device are coupled together, since the bumps are inserted into the solder, this insertion structure can tolerate greater warpage and coplanarity, so even the first Large warpage of the integrated circuit device and/or the second integrated circuit device, or poor coplanarity of multiple solders, can also ensure that the solder and bumps are soldered together, thereby ensuring that the first conductive layer and the second conductive layer The electrical connection of the two conductive layers ensures that the first integrated circuit device and the second integrated circuit device are coupled together. Based on this, in the embodiment of the present application, the protrusion is inserted into the solder, which can greatly reduce the risk of the first conductive layer and the second conductive layer not being electrically connected due to warpage and coplanarity. In this way, the manufacturing method of the integrated circuit stack structure provided by the embodiment of the present application can be applied to a large-sized component (such as a chip), or between two components (such as a chip) with a small distance between the centers of two adjacent solders. interconnection between.

On this basis, since the bumps are inserted into the solder, the bumps will pierce the surface of the solder when inserted, increasing the contact area between the solder and the bumps, thus reducing the risk of solder contact with the solder caused by insufficient flux or surface oxidation of the solder. The risk of bumps not being fully wetted can also be reduced for pillow-shaped solder joints.

In addition, during the soldering process, the protrusion is inserted into the solder, and after the solder and the protrusion are wetted, since the solder wraps the protrusion, the protrusion can block the flow of the solder, thereby avoiding the connection of two adjacent solders after flowing, resulting in risk of short circuit. In addition, when the first integrated circuit device and the second integrated circuit device are coupled, because the bumps are inserted into the solder, if the bumps and the solder are not aligned and there is a certain offset, the bumps and the solder will be wetted. Under the action of force, the solder will drive the first integrated circuit device (such as the first chip) to move, and/or the bump will drive the second integrated circuit device (such as the second chip) to move, so that the bump and the solder are aligned, Therefore the bumps and the solder have a self-aligning effect during soldering.

In a possible implementation manner, heating the solder and the bump includes: firstly bringing the solder into contact with the bump; next, heating the solder and the bump, and wrapping at least part of the bump after melting the solder. Considering that in the case of a small bump size, it may be difficult to insert the bump directly into the solder before heating, so the solder and the bump can be contacted first, and then the solder and the bump are heated, so that after the solder melts , due to surface tension, the solder wraps around the bump, allowing the bump to insert into the solder.

In a possible implementation manner, after forming the bump on the second conductive layer exposed on the surface of the second integrated circuit device, and before heating the solder and the bump, the above manufacturing method further includes: forming the first integrated circuit on which the solder is formed The circuit device is moved over the second integrated circuit device on which the bump is formed, so that the solder is located above the bump. Since the solder is on top of the bumps, the molten solder flows down to wrap around the bumps.

In a possible implementation manner, the shape of the protrusion is cone, column or platform. Exemplarily, the shape of the protrusion is conical, cylindrical or frustoconical. In the case where the shape of the protrusion is a cone, a column or a table, it is convenient for the protrusion to be inserted into the solder when soldering the protrusion and the solder.

In a possible implementation manner, the first integrated circuit device includes a first passivation layer disposed on the first conductive layer; the first passivation layer includes a first opening, at least part of the first conductive layer is located on the first An opening; and/or, the second integrated circuit device includes a second passivation layer disposed on the second conductive layer; the second passivation layer includes a second opening, at least part of the second conductive layer is located in the second opening . Here, the first passivation layer may function to electrically isolate adjacent first conductive layers, and the second passivation layer may function to electrically isolate adjacent second conductive layers.

In a possible implementation manner, the distance from the upper surface of the second passivation layer to the upper surface of the second conductive layer is greater than or equal to the height of the protrusion and the distance from the lower surface of the protrusion to the upper surface of the second conductive layer Sum. In this way, the second opening of the second passivation layer forms a cavity structure, and since the protrusion is located in the cavity structure, when the solder and the protrusion are soldered, solder spatter or overflow can be avoided, causing adjacent The two solders are electrically connected, thereby improving solder and bump soldering yield.

In a possible implementation manner, before forming protrusions on the second conductive layer exposed on the surface of the second integrated circuit device, the above manufacturing method further includes: A conductive base is formed; wherein the wettability of the conductive base is lower than that of the protrusion, and the projection of the protrusion on the conductive base is located within the boundary of the conductive base. Since the wettability of the conductive base is worse than that of the bump, the conductive base can inhibit the flow of the solder when the solder is soldered to the bump, so that the phenomenon of tin climbing can be avoided. In this way, the contact between two adjacent solders is avoided. resulting in a short circuit.

In a possible implementation manner, the material of the conductive base includes an inert metal. In the case where the material of the conductive base includes an inert metal, during the etching process, the inert metal is not affected by the etching or is less affected by the etching, so that the size of the conductive base remains unchanged after the etching process, or , is smaller than the shrinkage of the protrusion, and the size of the protrusion will be reduced during etching, so that the projection of the protrusion on the conductive base is located within the boundary of the conductive base.

In a possible implementation manner, after the bumps are formed on the second conductive layer exposed on the surface of the second integrated circuit device, the solder and the bumps are heated to couple the first integrated circuit device and the second integrated circuit device on the Before that, the above manufacturing method further includes: forming a protective layer on the protrusion; the protective layer covers at least part of the surface of the protrusion. Since a protective layer is formed on the bump, the protective layer can prevent the surface of the bump from being oxidized, so when the bump and solder are soldered, the process of deoxidizing the bump surface can be omitted, thereby simplifying the stacking of integrated circuits The manufacturing method of the structure reduces the production cost.

In a possible implementation manner, the material of the protective layer includes an inert metal. In the case where the material of the protective layer includes an inert metal, during the etching process, the inert metal is not affected by the etching or is less affected by the etching, so that the size of the protective layer remains unchanged after the etching process, or , the shrinkage of the protective layer relative to the protrusion is small.

In a possible implementation manner, before forming solder on the first conductive layer exposed on the surface of the first integrated circuit device, the above manufacturing method further includes: forming solder on the first conductive layer exposed on the surface of the first integrated circuit device Metal posts; the metal posts are electrically connected to the solder. Here, disposing the metal post can increase the size of the part electrically connected with the bump, which is convenient for solder and bump welding.

In a possible implementation manner, after heating the solder and the bumps to couple the first integrated circuit device and the second integrated circuit device, the above manufacturing method further includes: Buffer material is filled between devices. Here, filling the buffer material can enhance the strength and reliability of the integrated circuit stack structure.

In a possible implementation manner, the first integrated circuit device may be a first chip, and the second integrated circuit device may be a second chip; or, one of the first integrated circuit device and the second integrated circuit device is the first chip , and the other is a packaging substrate; or, one of the first integrated circuit device and the second integrated circuit device is a packaging substrate, and the other is a PCB.

In a second aspect, an integrated circuit stack structure is provided, and the integrated circuit stack structure includes: a first integrated circuit device, a second integrated circuit device and solder balls; the first integrated circuit device includes a first integrated circuit device exposed on the surface of the first integrated circuit device A conductive portion; the second integrated circuit device includes a second conductive portion exposed on the surface of the second integrated circuit device; solder balls are arranged between the first integrated circuit device and the second integrated circuit device, and the solder balls are respectively connected to the first conductive portion In contact with the second conductive portion, conductive intermetallic compounds are distributed inside the solder ball. Since conductive intermetallic compounds are distributed inside the solder balls, that is to say, the material of the solder balls as a whole includes intermetallic compounds, so the performance of the integrated circuit stack structure is more stable.

In a possible implementation manner, the first integrated circuit device is a first chip, and the second integrated circuit device is a second chip; or, one of the first integrated circuit device and the second integrated circuit device is the first chip, and the other One is a packaging substrate; or, one of the first integrated circuit device and the second integrated circuit device is a packaging substrate, and the other is a printed circuit board.

In a possible implementation manner, the first conductive portion includes a first conductive layer and a metal column disposed on a side of the first conductive layer close to the second integrated circuit device. Reference may be made to the description about the technical effect of the metal pillar in the first aspect above, and details are not repeated here.

In a possible implementation manner, the second conductive portion includes a second conductive layer and a conductive base disposed on a side of the second conductive layer close to the first integrated circuit device. Reference may be made to the description about the technical effects of the conductive base in the first aspect above, and details are not repeated here.

In a possible implementation manner, the material of the conductive base includes an inert metal. Reference may be made to the description of the technical effect that the material of the conductive base includes an inert metal in the first aspect above, and details are not repeated here.

In a possible implementation manner, the integrated circuit stack structure further includes a protective layer disposed inside the solder balls. Reference may be made to the description about the technical effect of the protective layer in the first aspect above, and details are not repeated here.

In a possible implementation manner, the material of the protective layer includes an inert metal. Reference can be made to the description about the technical effect of the material of the protective layer including an inert metal in the first aspect above, and details are not repeated here.

In a possible implementation manner, the stacked integrated circuit structure further includes: a buffer material filled between the first integrated circuit device and the second integrated circuit device. Reference may be made to the description about the technical effect of the cushioning material in the first aspect above, and details are not repeated here.

In a possible implementation manner, the first integrated circuit device further includes: a first passivation layer disposed on a side of the first conductive part close to the second integrated circuit device; the first passivation layer includes a first opening, and the first passivation layer At least part of a conductive portion is located in the first opening; and/or, the second integrated circuit device further includes: a second passivation layer disposed on a side of the second conductive portion close to the first integrated circuit device; the second passivation layer A second opening is included, at least part of the second conductive layer is located in the second opening. Reference may be made to the description about the technical effects of the first passivation layer and the second passivation layer in the first aspect above, and details are not repeated here.

In a third aspect, an electronic device is provided, including a case and the stacked integrated circuit structure provided in the second aspect. Since the electronic device has the same technical effect as that of the integrated circuit stacking structure provided by the second aspect, it will not be repeated here.

Description of drawings

FIG. 1 is a structural schematic diagram during the manufacturing process of a chip stack structure provided by the prior art;

FIG. 2 is a schematic structural diagram of an electronic device provided by an embodiment of the present application;

FIG. 3 is a schematic structural diagram of an integrated circuit stack structure provided by an embodiment of the present application;

FIG. 4 is a schematic flowchart of a method for manufacturing an integrated circuit stack structure provided by an embodiment of the present application;

Fig. 5a is a structural schematic diagram during the fabrication process of an integrated circuit stack structure provided by an embodiment of the present application;

Fig. 5b is a structural schematic diagram during the fabrication process of an integrated circuit stack structure provided by another embodiment of the present application;

Fig. 5c is a structural schematic diagram during the fabrication process of an integrated circuit stack structure provided by another embodiment of the present application;

Fig. 5d is a structural schematic diagram during the fabrication process of an integrated circuit stack structure provided by another embodiment of the present application;

Fig. 5e is a structural schematic diagram during the fabrication process of an integrated circuit stack structure provided by another embodiment of the present application;

FIG. 6 is a schematic structural diagram of a chip stacking structure provided by the prior art;

FIG. 7 is a schematic flowchart of a method for manufacturing a chip stack structure provided by an embodiment of the present application;

FIG. 8a is a schematic structural diagram during the fabrication process of a chip stack structure provided by an embodiment of the present application;

Fig. 8b is a structural schematic diagram during the fabrication process of a chip stack structure provided by another embodiment of the present application;

Fig. 8c is a structural schematic diagram during the fabrication process of a chip stack structure provided by another embodiment of the present application;

FIG. 9a is a schematic structural diagram of a chip stacking structure provided by an embodiment of the present application;

FIG. 9b is a schematic structural diagram of a chip stacking structure provided by another embodiment of the present application;

Fig. 10a is a schematic structural diagram during the fabrication process of a chip stack structure provided by another embodiment of the present application;

Fig. 10b is a schematic structural diagram of a chip stacking structure provided by another embodiment of the present application;

Fig. 11a is a structural schematic diagram during the fabrication process of a chip stack structure provided by another embodiment of the present application;

Fig. 11b is a schematic structural diagram during the manufacturing process of a chip stack structure provided by another embodiment of the present application;

FIG. 12 is a schematic structural diagram of a chip stacking structure provided by another embodiment of the present application;

FIG. 13 is a schematic structural diagram during the fabrication process of a chip stack structure provided by another embodiment of the present application;

FIG. 14 is a schematic structural diagram during the fabrication process of a chip stack structure provided by another embodiment of the present application;

FIG. 15 is a schematic structural diagram of a chip stacking structure provided by another embodiment of the present application.

Reference signs:

01-electronic equipment; 02-integrated circuit stacking structure; 1-chip packaging structure; 2-first connector; 3-chip stacking structure; 4-package substrate; 5-second connector; 6-third connector; 10-first chip; 10a-first substrate; 11-first conductive layer; 12-first passivation layer; 13-solder; 14-first seed layer; 15-first photoresist layer; 16-metal 20-second chip; 20a-second substrate; 20b-through-silicon via; 21-second conductive layer; 22-second passivation layer; 23-under-bump metal layer; 24-bump; 25- 26-second photoresist layer; 27-conductive base; 28-protective layer; 30-buffer material; 40-solder ball; 41-connection layer; 100-first conductive part; 200-second Conductive portion; 300—first integrated circuit device; 400—second integrated circuit device.

Detailed ways

The following will describe the technical solutions in the embodiments of the application with reference to the drawings in the embodiments of the application. Apparently, the described embodiments are only some of the embodiments of the application, not all of them.

Hereinafter, the terms "first", "second", etc. are used for convenience of description only, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Thus, a feature defined as "first", "second", etc. may expressly or implicitly include one or more of that feature. In the description of the present application, unless otherwise specified, "plurality" means two or more.

In the embodiments of the present application, unless otherwise specified and limited, the term "electrical connection" may be a direct electrical connection or an indirect electrical connection through an intermediary.

In the embodiments of the present application, words such as "exemplary" or "for example" are used as examples, illustrations or illustrations. Any embodiment or design scheme described as "exemplary" or "for example" in the embodiments of the present application shall not be interpreted as being more preferred or more advantageous than other embodiments or design schemes. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete manner.

In this embodiment of the application, "and/or" describes the association relationship of associated objects, indicating that there may be three relationships, for example, A and/or B, which may mean: A exists alone, A and B exist simultaneously, and there exists alone In the case of B, where A and B can be singular or plural. The character "/" generally indicates that the contextual objects are an "or" relationship.

In the embodiment of the present application, the direction indications such as up, down, left, right, front and back, etc. used to explain the structure and movement of different components in the present application are relative. These indications are pertinent when the parts are in the positions shown in the figures. However, should the description of component locations change, these directional indications will change accordingly.

An embodiment of the present application provides an electronic device, which may include a CMOS (complementary metal oxide semiconductor, complementary metal oxide semiconductor) image sensor, a NAND flash memory, a high bandwidth memory (high bandwidth memory, HBM), a mobile phone (mobile phone) , tablet computer (pad), TV, smart wearable products (for example, smart watch, smart bracelet), virtual reality (virtual reality, VR) terminal equipment, augmented reality (augmented reality, AR) terminal equipment and other electronic products. The embodiment of the present application does not specifically limit the specific form of the foregoing electronic device.

In some examples, as shown in FIG. 2 , the above-mentioned electronic device 01 may include a chip package structure 1 and a printed circuit board (printed circuit board, PCB), and the chip package structure 1 and the PCB are electrically connected. The electronic device 01 may also include a plurality of connectors, which are referred to as first connectors 2 herein for the convenience of distinguishing them from other connectors, and the chip package structure 1 may be electrically connected to the PCB through the plurality of first connectors 2 .

Here, the chip packaging structure 1 may adopt, for example, an integrated fan out (InFO) packaging method, or a packaging method in which bare chips and wafers are packaged on a substrate (chip on wafer on substrate, CoWoS). An embedded multi-die interconnect bridge (embedded multi-die interconnect bridge, EMIB) packaging method may also be used.

As shown in FIG. 2 , the chip packaging structure 1 may include a first chip 10 and a packaging substrate 4 , and the first chip 10 is electrically connected to the packaging substrate 4 . The chip packaging structure 1 may also include a plurality of connectors, which are referred to as second connectors 5 herein for the convenience of distinguishing them from other connectors, and the first chip 10 may be electrically connected to the packaging substrate 4 through a plurality of second connectors 5 .

It should be understood that the chip package structure 1 is electrically connected to the PCB through a plurality of first connectors 2 , that is, the package substrate 4 in the chip package structure 1 is electrically connected to the PCB through a plurality of first connectors 2 .

The above-mentioned chip packaging structure 1 may include one chip, such as the first chip 10 , or may include multiple chips. In the case that the chip package structure 1 includes a plurality of chips, in some examples, the plurality of chips do not adopt a stacked structure, that is, each chip is electrically connected to the packaging substrate 4 through the second connector 5; in other examples, A plurality of chips are stacked together sequentially, that is, the above-mentioned chip packaging structure 1 includes a chip stacking structure 3, and the chip stacking structure 3 includes a plurality of chips stacked in sequence. In FIG. 2, the chip stacking structure 3 includes two chips, the first chip 10 and the second chip. The two chips 20 are illustrated as an example. It should be understood that the chip stack structure 3 includes but is not limited to the first chip 10 and the second chip 20 , and may also include a third chip, a fourth chip, and the like. In the case that the chip package structure 1 includes multiple chips, the chip stacking structure 3 can be used to stack multiple chips in the thickness direction, which greatly improves the integration of the package and has significant benefits.

In the case that the chip package structure 1 includes a chip stack structure 3, the chip package structure 1 may also include a connector, which is referred to as a third connector 6 herein for the convenience of distinguishing it from other connectors. The first chip 10 and the second chip 20 can be electrically connected together through the third connecting member 6 .

It should be noted that the chip in the embodiment of the present application may be a wafer (wafer) formed with a functional layer, such as a metal layer, a dielectric layer or a circuit structure, or a bare chip (also called a grain or particle) (die). It can be understood that what is obtained by dicing the wafer is a bare chip. Based on this, in some embodiments, the plurality of chips in the above-mentioned chip stack structure 3 may all be bare chips. In some other embodiments, the plurality of chips in the above-mentioned chip stack structure 3 may all be wafers. In some other embodiments, among the plurality of chips in the above-mentioned chip stack structure 3 , some of the chips may be wafers, and some of the chips may be bare chips. In some cases, the chip may also be a packaged chip obtained by packaging a bare chip.

Here, any chip in the embodiment of the present application includes a substrate and a functional layer disposed on the substrate, such as a circuit structure, and the circuit structure can enable the chip to realize its own functions during operation, such as logic calculation functions Or storage function etc. In the chip, the surface of the above-mentioned circuit structure away from the substrate is called the active surface of the chip, and the surface of the substrate away from the circuit structure is called the passive surface or back surface of the chip.

Wherein, the material of the substrate may include, for example, one or more of silicon (Si), germanium (Ge), gallium nitride (GaN), gallium arsenide (GaAs) or other semiconductor materials. In addition, the material of the substrate may be, for example, glass, an organic material, or the like.

In addition, the above chips may be memory chips, logic chips or chips with any other functions. In addition, when the chip package structure 1 includes a chip stack structure 3, the multiple chips in the above chip stack structure 3 can be the same type of chips, for example, all are memory chips; they can also be different types of chips, such as the chip stack structure 3 Including memory chips and logic chips. Based on this, the chip stack structure 3 provided in the embodiment of the present application can realize the integration between chips of the same type or different types.

It should be noted that, in the case that the chip package structure 1 includes a chip stack structure 3, the chip stack structure 3 includes the first chip 10 and the second chip 20 as an example in the following, and the chip stack structure 3 and the chip stack structure 3 The production method is exemplified. When the chip stack structure 3 includes three or more chips, the structure and manufacturing method between any two chips can refer to the first chip 10 and the second chip 20 .

Based on the above, the electronic device 01 may further include a housing, and other structures in the electronic device 01 other than the housing may be disposed in the housing.

An embodiment of the present application provides an integrated circuit stack structure, which can be applied to the above-mentioned electronic equipment. As shown in FIG. 3 , the integrated circuit stack structure 02 includes a first integrated circuit device 300; the first integrated circuit device 300 includes a first substrate 10 a and a first conductive portion 100 disposed on the first substrate 10 a, and the first conductive portion 100 is exposed on the surface of the first integrated circuit device 300 .

Here, the first conductive part 100 may be partially exposed on the surface of the first integrated circuit device 300, or may be completely exposed on the surface of the first integrated circuit device 300.

In addition, the first integrated circuit device 300 may include other structures besides the first substrate 10 a and the first conductive portion 100 .

Please continue to refer to FIG. 3, the above integrated circuit stack structure 02 also includes a second integrated circuit device 400; the second integrated circuit device 400 includes a second substrate 20a and a second conductive part 200 disposed on the second substrate 20a, the second conductive The portion 200 is exposed on the surface of the second integrated circuit device 400 .

Here, the second conductive portion 200 may be partially exposed on the surface of the second integrated circuit device 400 , or may be completely exposed on the surface of the second integrated circuit device 400 .

In addition, the second integrated circuit device 400 may include other structures in addition to the second substrate 20 a and the second conductive portion 200 .

Please continue to refer to FIG. 3 , the above-mentioned integrated circuit stack structure 02 also includes solder balls 40 disposed between the first integrated circuit device 300 and the second integrated circuit device 400 , and the solder balls 40 are connected to the first conductive part 100 and the second conductive part 100 respectively. The solder ball 40 is in contact with the portion 200 , and a conductive intermetallic compound is spread inside the solder ball 40 .

It should be noted that, in this application, "the solder ball 40 is filled with conductive intermetallic compounds" includes two situations: first, the material of the solder ball 40 only includes intermetallic compounds; The overall material of 40 includes an intermetallic compound, that is, on the basis that the material at each position of the solder ball 40 includes an intermetallic compound, the material of the solder ball 40 also includes other materials except the intermetallic compound.

In FIG. 3 , the first conductive portion 100 is the first conductive layer 11 and the second conductive portion 200 is the second conductive layer 21 as an example.

It should be noted that the material of the "solder ball" mentioned in the prior art is generally some alloys containing tin, such as tin-silver alloy, tin-silver-copper alloy, etc., and the solder ball 40 in the embodiment of the present application is the same as the existing Unlike solder balls in the art, the material of the solder ball 40 in the embodiment of the present application includes intermetallic compounds.

In addition, in this application, "solder ball" is just a conventional term, and in actual products, the solder ball 40 is not necessarily spherical.

In some examples, the above-mentioned first integrated circuit device 300 is the first chip 10 , the above-mentioned second integrated circuit device 400 is the second chip 20 , and the solder ball 40 is the above-mentioned third connecting member 6 . In the case where the first integrated circuit device 300 is the first chip 10 and the second integrated circuit device 400 is the second chip 20 , the above integrated circuit stack structure 02 may also be referred to as the chip stack structure 3 .

In other examples, one of the above-mentioned first integrated circuit device 300 and the above-mentioned second integrated circuit device 400 is the first chip 10 , the other is the package substrate 4 , and the solder ball 40 is the above-mentioned second connector 5 . Here, the first integrated circuit device 300 may be the first chip 10, and the second integrated circuit device 400 may be the packaging substrate 4; or the first integrated circuit device 300 may be the packaging substrate 4, and the second integrated circuit device 400 may be the second integrated circuit device 400. A chip 10.

In some other examples, one of the above-mentioned first integrated circuit device 300 and the above-mentioned second integrated circuit device 400 is the package substrate 4 , the other is a PCB, and the solder ball 40 is the above-mentioned first connector 2 . Here, the first integrated circuit device 300 may be the packaging substrate 4 and the second integrated circuit device 400 may be the PCB; or the first integrated circuit device 300 may be the PCB and the second integrated circuit device 400 may be the packaging substrate 4 .

It should be noted that the above integrated circuit stack structure 02 includes but is not limited to the application in the field of chips, and can also be applied in other fields for realizing the interconnection of the first integrated circuit device 300 and the second integrated circuit device 400, that is to say , the first integrated circuit device 300 and the second integrated circuit device 400 include but are not limited to chips, packaging substrates or PCBs, and can also be other structures, for example, the first integrated circuit device 300 is a first circuit board, and the second integrated circuit device Device 300 is a second circuit board.

The embodiment of the present application also provides a method for fabricating an integrated circuit stack structure, which can be used to fabricate the above-mentioned integrated circuit stack structure 02, for example, for fabricating the integrated circuit stack structure 02 as shown in FIG. 3, as shown in FIG. 4, The manufacturing method of the integrated circuit stack structure includes:

S10. As shown in FIG. 5a, a first integrated circuit device 300 is provided, and the first integrated circuit device 300 includes a first substrate 10a and a first conductive layer 11 formed on the first substrate 10a; wherein, the first conductive layer 11 is exposed on the surface of the first integrated circuit device 300 .

It can be understood that, in addition to the first substrate 10 a and the first conductive layer 11 , the first integrated circuit device 300 may also include other structures such as circuit structures, which will not be repeated here.

It should be noted that, the first integrated circuit device 300 may be, for example, the first chip 10 , the packaging substrate 4 or a circuit board such as a printed circuit board.

Here, when the first integrated circuit device 300 is the first chip 10, the first conductive layer 11 can be formed on the active surface of the first chip 10, or can be formed on the passive surface of the first chip 10, that is, the back surface The first conductive layer 11 is formed.

In the case where the first conductive layer 11 is formed on the passive surface of the first chip 10, a through silicon via (through silicon via, TSV) may be formed on the first substrate 10a of the first chip 10, and the first conductive layer 11 passes through the TSV. It is electrically connected with the circuit structure of the first chip 10 .

In some examples, the TSVs may consist of an insulating layer, a barrier layer, a seed layer, and a conductive filler. Here, the insulating layer may be an inorganic insulating layer or an organic insulating layer. The material of the insulating layer includes but not limited to silicon dioxide (SiO ₂ ), benzocyclobutene (benzocyclobutene, BCB), polyimide (polyimide, PI), polyparaphenylene benzobisoxazole (poly -p-phenylene benzobisoxazole, PBO) etc. The material of the barrier layer includes one or more of titanium (Ti), tantalum (Ta), titanium nitride (TiN), nickel (Ni), cobalt (Co), tungsten (W) or related alloys. The material of the seed layer includes one or more of copper (Cu), Ti, Ta, Ni, Co, W, aluminum (Al) or related alloys. The material of the conductive filler includes one or more of Cu, Co, Ni, W, graphene or other conductive materials.

In addition, the first conductive layer 11 can be a metal pad; it can also be a layer of metal layer exposed on the surface of the first integrated circuit device 300 . For example, in a redistribution layer (redistribution layer, RDL) with a multilayer metal wiring structure (also called a redistribution layer or redistribution layer), the first conductive layer 11 may be a redistribution layer exposed to the first integrated circuit. One or more metal layers on the surface of device 300 .

The above-mentioned rewiring layer includes a metal layer and an insulating layer. The material of the metal layer may include, for example, one or more conductive materials selected from copper, aluminum, nickel, gold, silver, and titanium. The material of the insulating layer may include, for example, one or more of silicon oxide, silicon nitride, silicon oxynitride, silica gel, and polyimide.

In addition, the number of first conductive layers 11 can be set as required, and one or multiple first conductive layers 11 can be formed on the first substrate 10 a at the same time.

In some examples, the thickness a of the first conductive layer 11 ranges from 5 μm˜7 μm. For example, the thickness a of the first conductive layer 11 may be 5 μm, 6 μm or 7 μm.

In some examples, in the case that the first integrated circuit device 300 is the first chip 10 , before step S10 , the manufacturing method of the integrated circuit stack structure further includes: grinding and thinning the first chip 10 . The thickness of the first chip 10 after thinning can be determined according to product requirements and process requirements.

It should be noted that, in the embodiment of the present application, when the first integrated circuit device 300 is the first chip 10 , the first chip 10 may be a wafer or a bare chip.

S11 , as shown in FIG. 5 b , forming solder 13 on the first conductive layer 11 exposed on the surface of the first integrated circuit device 300 ; the solder 13 is electrically connected to the first conductive layer 11 .

Here, the solder 13 may have a single-layer structure or a multi-layer structure. On this basis, the material of the solder 13 may include, for example, tin (Sn) and/or indium (In), and may also include one of Ag (silver), gold (Au), copper, Bi (bismuth), nickel, or Various. For example, the material of the solder 13 includes tin-silver (SnAg) alloy. For another example, the solder 13 includes a copper layer and a tin-silver alloy layer, that is, Cu/SnAg, which are stacked. For another example, the solder 13 includes a copper layer, a nickel layer, and a tin-silver alloy layer that are stacked in sequence, that is, Cu/Ni/SnAg. For another example, the solder 13 includes a copper layer, a nickel layer, a copper layer, and a tin-silver alloy layer that are sequentially stacked, that is, Cu/Ni/Cu/SnAg.

On this basis, the solder 13 can be a solder ball; it can also be a solder paste, such as nano-solder paste.

In addition, when the solder 13 is a solder ball, the solder 13 can be formed by, for example, electroplating, electroless plating, printing, ball planting, or thin film deposition and etching. When the solder 13 is a solder paste, the solder 13 can be formed by, for example, smearing or spraying.

In addition, since the solder 13 is electrically connected to the first conductive layer 11 in one-to-one correspondence, the quantity of the solder 13 is the same as the quantity of the first conductive layer 11 , and the quantity of the solder 13 can be determined according to the quantity of the first conductive layer 11 .

It should be understood that when forming the solder 13, due to process differences, the heights of the multiple solders 13 may be different, the smaller the height difference of the multiple solders 13, the better the coplanarity of the multiple solders 13, and the multiple solders 13 The greater the difference in height, the poorer the coplanarity of the plurality of solders 13.

S12. As shown in FIG. 5c, a second integrated circuit device 400 is provided, and the second integrated circuit device 400 includes a second substrate 20a and a second conductive layer 21 formed on the second substrate 20a; wherein, the second conductive layer 21 is exposed on the surface of the second integrated circuit device 400 .

It can be understood that, in addition to the second substrate 20 a and the second conductive layer 21 , the second integrated circuit device 400 may also include other structures such as circuit structures, which will not be repeated here.

It should be noted that, when the first integrated circuit device 300 is the first chip 10 , the second integrated circuit device 400 may be, for example, the second chip 20 or the packaging substrate 4 . In the case that the first integrated circuit device 300 is the packaging substrate 4 , the second integrated circuit device 400 may be, for example, the first chip 10 or a PCB. In the case that the first integrated circuit device 300 is a PCB, the second integrated circuit device 400 may be, for example, the packaging substrate 4 .

Here, when the second integrated circuit device 400 is the second chip 20, the second conductive layer 21 may be formed on the active surface of the second chip 20, or the second conductive layer 21 may be formed on the passive surface of the second chip 20. Conductive layer 21.

In the case where the second conductive layer 21 is formed on the passive surface of the second chip 20, as shown in FIG. The through hole 20 b is electrically connected to the circuit structure of the second chip 20 . For the material of the TSV 20b, reference may be made to the description of the TSV material in the above step S10, which will not be repeated here.

It should be noted that, when the second integrated circuit device 400 is the second chip 20, the second chip 20 in FIG. 5c only shows the second substrate 20a and the second conductive layer 21 of the second chip 20, not The circuit structure of the second chip 20 is shown.

In addition, the second conductive layer 21 can be a metal pad, or a metal layer exposed on the surface of the second integrated circuit device 400 . For example, in a rewiring layer with a multilayer metal wiring structure, the second conductive layer 21 may be one or more metal layers of the rewiring layer exposed on the surface of the second integrated circuit device 400 .

In addition, the number of second conductive layers 21 can be set as required, and one or multiple second conductive layers 21 can be formed on the second substrate 20a of the second chip 21 at the same time.

In some examples, the thickness b of the second conductive layer 21 ranges from 5 μm to 7 μm. For example, the thickness b of the second conductive layer 21 may be 5 μm, 6 μm or 7 μm.

In some examples, in the case that the second integrated circuit device 400 is the second chip 20 , before step S12 , the manufacturing method of the integrated circuit stack structure further includes: grinding and thinning the second chip 20 . The thickness of the second chip 20 after thinning can be determined according to product requirements and process requirements.

It should be noted that, in the embodiment of the present application, when the second integrated circuit device 400 is the second chip 20 , the second chip 20 may be a wafer or a bare chip.

S13 , as shown in FIG. 5 d , forming a bump 24 on the second conductive layer 21 exposed on the surface of the second integrated circuit device 400 , and the bump 24 is electrically connected to the second conductive layer 21 .

Here, the shape of the protrusion 24 can be, for example, a cone shape (also called a needle cone shape), a columnar shape, a trapezoidal shape, other regular or other irregular shapes. The cross-sectional shape of the protrusion 24 can be triangular, trapezoidal, rectangular, hexagonal, etc.

Exemplarily, the shape of the protrusion 24 may be conical, cylindrical or frustoconical.

In addition, for example, the protrusions 24 may be formed by electroplating, electroless plating, or thin film deposition and etching.

In addition, the protrusion 24 may be a single-layer structure. In this case, the material of the protrusion 24 may include one or more of Cu, Au (gold), Ni, and Al (aluminum), for example. The protrusion 24 can also be a multi-layer laminated structure. In this case, for example, the protrusion 24 can include a stacked copper layer, a nickel layer and a gold layer (ie Cu/Ni/Au), and a stacked copper layer, a nickel layer , copper layer and gold layer (ie Cu/Ni/Cu/Au), laminated copper layer and nickel layer (ie Cu/Ni) or, laminated copper layer and gold layer (ie Cu/Au).

On this basis, since the bumps 24 are electrically connected to the second conductive layer 21 in one-to-one correspondence, the number of the bumps 24 is the same as the number of the second conductive layer 21, and the bumps 24 can be determined according to the number of the second conductive layer 21. quantity.

In some examples, the dimension c of the protrusion 24 close to the second conductive layer 21 ranges from 4 μm to 10 μm. For example, the dimension c of the protrusion 24 close to the second conductive layer 21 may be 4 μm, 8 μm or 10 μm.

In some examples, the height H of the protrusion 24 ranges from 4 μm to 10 μm, for example, the height H of the protrusion 24 may be 4 μm, 5 μm, or 10 μm.

It should be noted that the above step S10 and step S11 can be executed first, and then step S12 and step S13 can be executed; or step S12 and step S13 can be executed first, and then step S10 and step S11 can be executed; of course, it is also possible to execute step S10 Simultaneously with step S11, step S12 and step S13 are executed.

S14 , as shown in FIG. 5 e , heat the solder 13 and the bump 24 to couple the first integrated circuit device 300 and the second integrated circuit device 400 together; wherein, the bump 24 is inserted into the solder 13 .

It should be noted that the heating may include reflow soldering, and in some examples, the heating may also include thermocompression bonding.

In some examples, heating the solder 13 and the protrusion 24 in step S14 includes: inserting the protrusion 24 into the solder 13 first; and then heating the solder 13 and the protrusion 24 . In this way, the first integrated circuit device 300 and the second integrated circuit device 400 can be coupled together.

In some other examples, heating the solder 13 and the bump 24 in step S14 includes: first contacting the solder 13 and the bump 24, and the bump 24 is not inserted into the solder 13; next, heating the solder 13 and the bump 24 , the solder 13 wraps at least part of the protrusion 24 after melting. In this way, the protrusion 24 will be inserted into the solder 13 , so that the first integrated circuit device 300 and the second integrated circuit device 400 can be coupled together. Considering that when the size of the bump 24 is small, it may be difficult to insert the bump 24 directly into the solder 13 before heating. Therefore, the solder 13 and the bump 24 can be contacted first, and then the solder 13 and the bump can be heated. 24, so that after the solder 13 melts, due to the surface tension, the solder 13 will wrap the protrusion 24, so that the protrusion 24 is inserted into the solder 13.

On this basis, in order to couple the first integrated circuit device 300 and the second integrated circuit device 400 together, before step S14, in some examples, the manufacturing method of the above-mentioned integrated circuit stack structure further includes: forming solder The first integrated circuit device 300 of 13 moves over the second integrated circuit device 400 formed with the bump 24 , so that the solder 13 is located above the bump 24 . Since the solder 13 is located above the protrusion 24 , the solder 13 will flow down after melting, so as to wrap the protrusion 24 . In the case where the solder 13 is located above the protrusion 24, when the solder 13 and the protrusion 24 are heated, the first integrated circuit device 300 may be moved downward and/or the second integrated circuit device 400 may be moved upward, or the first integrated circuit device 400 may not be moved. The integrated circuit device 300 and the second integrated circuit device 400 .

In some other examples, the manufacturing method of the above-mentioned integrated circuit stack structure further includes: moving the second integrated circuit device 400 formed with the bump 24 above the first integrated circuit device 300 formed with the solder 13 , so that the bump 24 above the solder 13. Under the situation that bump 24 is positioned at the top of solder 13, when solder 13 melts, should move down to form second integrated circuit device 400 and/or move up first integrated circuit device 300, just can ensure that bump 24 inserts solder like this 13 inside.

Here, the protrusion 24 is inserted into the solder 13, and the welding of the solder 13 and the protrusion 24 can be realized in the following two ways. The first method: the solder 13 and the bump 24 are welded together by means of flip chip welding. The second method: the solder 13 and the bump 24 are welded together by means of thermal compression bonding (TCB).

It can be understood that the size of the portion of the protrusion 24 inserted into the solder 13 is smaller than that of the solder 13 .

It should be understood that, in the case of including multiple solders 13 and multiple bumps 24 , the multiple solders 13 and the multiple bumps 24 are welded together in one-to-one correspondence.

In addition, when the first integrated circuit device 300 is the first chip 10 and the second integrated circuit device 400 is the second chip 20, when the active surface of the first chip 10 is opposite to the active surface of the second chip 20 , it can be considered that the first chip 10 and the second chip 20 are interconnected face to face. When the active surface of the first chip 10 is opposite to the passive surface of the second chip 20, or when the passive surface of the first chip 10 is opposite to the active surface of the second chip 20, it can be considered that the first chip 10 and the The second chip 20 is interconnected face to back. When the passive surface of the first chip 10 and the passive surface of the second chip 20 are opposite, it can be considered that the first chip 10 and the second chip 20 are interconnected back to back.

It should be noted that, when the first integrated circuit device 300 and the second integrated circuit device 400 are coupled together, since the bump 24 is inserted into the solder 13, when the first integrated circuit device 300 or the second integrated circuit device 400 is warped , or when the heights of the plurality of solders 13 are different, the heights of the protrusions 24 inserted into the solders 13 may be different. For a position with a large degree of warpage, or a position with a relatively small height of the solder 13, the height of the protrusion 24 inserted into the interior of the solder 13 is relatively small; for a position with a small degree of warpage, or a position with a relatively high height of the solder 13, The height at which the protrusion 24 is inserted into the solder 13 is relatively large. It can be understood that although the height of the protrusion 24 inserted into the solder 13 is small, the electrical connection between the protrusion 24 and the solder 13 can still be ensured, that is, the electrical connection between the first conductive layer 11 and the second conductive layer 21 can be guaranteed, and then It can be ensured that the first integrated circuit device 300 and the second integrated circuit device 400 are coupled together.

Referring to Fig. 1, in the prior art, when the solder 13 and the UBM layer 23 are soldered, since the lower surface of the solder 13 contacts the upper surface of the UBM layer 23, when the first chip 10 and/or the second When the warpage of the chip 20 is large, or when the coplanarity of multiple solders 13 is poor, some solders 13 may not be in contact with the UBM layer 23, resulting in the first conductive layer 11 and the second conductive layer 11 being in contact with each other. The two conductive layers 12 are not electrically connected, thereby causing the interconnection between the first chip 10 and the second chip 20 to fail.

In addition, when the pitch between the centers of two adjacent solders 13 is small, if the height of the solders 13 is increased, that is, the amount of solder in the solders 13 is increased, tin creeping will easily occur. In this way, Two adjacent solders 13a may have the risk of being connected (bridge) together, causing a short circuit; The chip 10 and the second chip 20 have higher requirements on warpage, foreign matter in the solder 13 , flux (flux), etc., and the risk of non-contact between the solder 13 and the UBM layer 23 is likely to occur. Therefore, in the prior art, when the first chip 10 and the second chip 20 are interconnected, the distance between the centers of two adjacent solders 13 is generally relatively large, about 40 μm. In addition, the warpage of large-sized chips is generally greater than that of small-sized chips. Based on this, in the prior art, the interconnection between the first chip 10 and the second chip 20 is developed in the two directions of large-scale chips and the spacing between the centers of two adjacent solders 13 being a small pitch (fine pitch). and applications are limited.

The embodiment of the present application provides a method for fabricating an integrated circuit stack structure 02. Solder 13 is formed on the first conductive layer 11 exposed on the surface of the first integrated circuit device 300, and the solder 13 is electrically connected to the first conductive layer 11; On the second conductive layer 21 on the surface of the second integrated circuit device 400, a bump 24 is formed, and the bump 24 is electrically connected to the second conductive layer 21; next, the solder 13 and the bump 24 are heated, and the first integrated circuit device 300 Coupled with the second integrated circuit device 400 , the bump 24 is inserted into the solder 13 . When the first integrated circuit device 300 and the second integrated circuit device 400 are coupled together, since the bump 24 is inserted into the solder 13, this plug-in structure can be compatible with greater warpage and coplanarity, Therefore, even if the warpage of the first integrated circuit device 300 and/or the second integrated circuit device 400 is relatively large, or the coplanarity of the plurality of solders 13 is poor, it is possible to ensure that the solder 13 and the bump 24 are welded together, Therefore, the electrical connection between the first conductive layer 11 and the second conductive layer 21 can be ensured, thereby ensuring that the first integrated circuit device 300 and the second integrated circuit device 400 are coupled together. In the case where the first integrated circuit device 300 is the first chip 10 and the second integrated circuit device 400 is the second chip 20, the interconnection between the first chip 10 and the second chip 20 can be ensured; In the case that one of the second integrated circuit devices 400 is the first chip 10 and the other is the packaging substrate 4, the interconnection between the first chip 10 and the packaging substrate 4 can be ensured; In the case where one of the two integrated circuit devices 400 is the packaging substrate 4 and the other is a PCB, the interconnection between the packaging substrate 4 and the PCB can be ensured.

Based on this, in the embodiment of the present application, the protrusion 24 is inserted into the solder 13 , which can greatly reduce the risk of the first conductive layer 11 and the second conductive layer 21 not being electrically connected due to warpage and coplanarity. In this way, the manufacturing method of the integrated circuit stack structure 02 provided by the embodiment of the present application can be applied to large-sized components (such as chips), and the distance between the centers of two adjacent solders 13 is small (for example, two adjacent solders 13 The spacing between centers of 13 may be 20 μm) for interconnection between two components (eg chips).

On this basis, in the prior art, when the solder 13 and the UBM layer 23 are soldered, some flux needs to be adsorbed on the surface of the solder 13. If the amount of flux is insufficient or the surface of the solder 13 is oxidized, the solder 13 There may be a risk of non-wetting with the UBM layer 23, which will lead to poor soldering effect. However, in the embodiment of the present application, since the protrusion 24 is inserted into the inside of the solder 13, the protrusion 24 will pierce the surface of the solder 13 during insertion, increasing the contact area between the solder 13 and the protrusion 24, thus reducing the amount of solder flux deficiency or The risk of incomplete wetting of the solder 13 to the bumps 24 due to surface oxidation of the solder 13 also reduces the pillow-shaped solder joints.

In addition, during the soldering process, the bumps 24 are inserted into the solder 13. After the solder 13 and the bumps 24 are wetted, since the solder 13 wraps the bumps 24, the bumps 24 can block the flow of the solder 13, thereby avoiding two adjacent bumps. A solder 13 flows after the connection, resulting in the risk of a short circuit.

In addition, when the first integrated circuit device 300 and the second integrated circuit device 400 are coupled, because the bump 24 is inserted into the solder 13, if the bump 24 and the solder 13 are not aligned and there is a certain offset, the bump 24 Solder 13 will drive the first integrated circuit device 300 (such as the first chip 10) to move under the action of the force generated by wetting of the solder 13, and/or the protrusion 24 will drive the second integrated circuit device 400 (such as the second chip 10). The chip 20) moves so that the bumps 24 and the solder 13 are aligned, so the bumps 24 and the solder 13 have a self-alignment effect during soldering.

Based on the above, after step S14, the method for fabricating the integrated circuit stack structure further includes performing multiple reflows on the structure obtained in step S14. After multiple times of reflow soldering, the bumps 24 will gradually melt, and the material of the bumps 24 and the material of the solder 13 will react to form an intermetallic compound (IMC). The middle of the solder 13 first forms an intermetallic compound, and then , the intermetallic compound grows to both sides, and finally, under the condition that the protrusion 24 and the solder 13 fully react, a structure covered with the intermetallic compound is formed, that is, the above-mentioned solder ball 40 .

It should be understood that since the material of the protrusion 24 includes metal, the material of the solder 13 also includes metal, and the intermetallic compound formed between metal and metal is conductive, so the intermetallic compound in the embodiment of the present application is conductive.

It should be noted that, in the process of manufacturing the integrated circuit stack structure 02, if the bumps 24 and the solder 13 fully react, referring to FIG. compound. Here, the interior of the solder ball 40 is filled with intermetallic compounds, which may be that the material of the solder ball 40 only includes the intermetallic compound; In addition to the material including the intermetallic compound, the material of the solder ball 40 also includes other materials except the intermetallic compound. Wherein, “other materials” include one or more of unreacted solder 13 , unreacted bump 24 material or impurities. In the case where the material of the solder ball 40 includes unreacted material of the bump 24 , in some examples, a portion of the bump 24 may remain inside the solder ball 40 . In the case where the material of the solder ball 40 includes unreacted solder 13 , in some examples, a portion of the solder 13 may remain on the outer side of the solder ball 40 .

In addition, it can be understood that at different positions of the solder ball 40, the proportions of different metals in the intermetallic compound may be different. , the molar ratio of the material of the protrusion 24 in the intermetallic compound is relatively large, and at the position where the solder 13 is located, the molar ratio of the material of the solder 13 in the intermetallic compound is relatively large. For example, the material of the solder 13 is Sn, the material of the bump 24 is Cu, and the intermetallic compound formed after the reaction between the solder ball 13 and the bump 24 is Sn _x Cu _y , which is formed at the interface between the solder ball 13 and the bump 24 The intermetallic compound is SnCu, before the bump 24 reacts with the solder 13, the intermetallic compound formed at the position of the bump 24 is SnCu ₂ , SnCu ₃ or Sn ₂ Cu ₃ etc.; when the bump 24 reacts with the solder 13 Before, at the position where the solder 13 is, the intermetallic compound formed is Sn ₂ Cu, Sn ₃ Cu or Sn ₃ Cu ₂ and the like.

Based on the manufacturing method of the integrated circuit stack structure provided in the above steps S10-S14, it can be known that since the solder balls 40 in the above integrated circuit stack structure 02 are inserted into the solder 13 through the bumps 24, and the bumps 24 react with the solder 13, therefore When the bumps 24 and the solder 13 fully react, the solder ball 40 is filled with intermetallic compounds, so that the performance of the integrated circuit stack structure 02 is more stable.

The embodiment of the present application also provides a chip stack structure, which can be manufactured by using the method for manufacturing the integrated circuit stack structure provided in the above steps S10-S14. As shown in FIG. 3 , the chip stack structure 3 includes: a first chip 10; the first chip 10 includes a first substrate 10a and a first conductive portion 100 disposed on the first substrate 10a, the first conductive portion 100 is exposed to the first The surface of the chip 10; the chip stack structure 3 also includes a second chip 20; the second chip 20 includes a second base 20a and a second conductive portion 200 disposed on the second base 20a, and the second conductive portion 200 is exposed to the second chip 20; the chip stack structure 3 also includes a solder ball 40, which is arranged between the first conductive part 100 and the second conductive part 200, and the solder ball 40 is in contact with the first conductive part 100 and the second conductive part 200 respectively, and the solder ball 40 is filled with conductive intermetallic compounds.

In FIG. 3 , the first conductive portion 100 is the first conductive layer 11 and the second conductive portion 200 is the second conductive layer 21 as an example. Wherein, the materials and structures of the first conductive layer 11 and the second conductive layer 21 can be referred to above, and will not be repeated here.

Since the solder ball 40 is filled with conductive intermetallic compounds, the material at each position of the solder ball 40 includes the intermetallic compound, that is, the material of the solder ball 40 as a whole includes the intermetallic compound. In this way, in the first When the integrated circuit device 300 is the first chip 10 and the second integrated circuit device 400 is the second chip 20 , the performance of the chip stack structure 3 is more stable.

When the chip stack structure is produced by the chip stack structure manufacturing method provided by the prior art, since the solder 13 and the UBM layer 23 are soldered, the lower surface of the solder 13 is in contact with the upper surface of the UBM layer 23. After repeated reflow soldering, the lower surface of the solder 13 and the upper surface of the UBM layer 23 will react to form a metal compound at the interface between the solder 13 and the UBM layer 23 . In this way, the finally manufactured chip stack structure includes not only the intermetallic compound layer, but also the unreacted solder 13 and the UBM layer 23 .

Based on this, the chip stack structure 3 manufactured by the chip stack structure manufacturing method provided by the prior art, as shown in FIG. 6 , includes a first chip 10; The first conductive layer 11 on 10a and the first passivation layer 12 disposed on the first conductive layer 11; the first passivation layer 12 includes a first opening; at least part of the first conductive layer 11 is exposed in the first opening department. The chip stack structure 3 also includes a second chip 20; the second chip 20 includes a second substrate 20a, a second conductive layer 21 disposed on the second substrate 20a, and a second passivation layer 22 disposed on the second conductive layer 21 The second passivation layer 22 includes a second opening, at least part of the second conductive layer 21 is exposed in the second opening; the solder 13 disposed on the first conductive layer 11 exposed on the surface of the first chip 10 and disposed on the The UBM layer 23 exposed on the second conductive layer 21 on the surface of the second chip 20, the solder 13 is electrically connected to the first conductive layer 11, and the UBM layer 23 is electrically connected to the second conductive layer 21; The connecting layer 41 between the solder 13 and the UBM layer 23 , the conductive intermetallic compound is distributed inside the connecting member 41 ; the filling material 30 is filled between the first passivation layer 12 and the second passivation layer 22 . Wherein, the first conductive layer 11 and the second conductive layer 21 are electrically connected through the solder 13 , the connecting layer 41 and the UBM layer 23 .

Based on the manufacturing method of the chip stack structure provided by the above prior art, it can be known that the connection layer 41 is obtained by reacting part of the solder 13 and part of the UBM layer 23 during the reflow process. Since in the prior art, the solder 13 and the UBM layer 23 do not fully react, and an intermetallic compound is only formed at the interface between the solder 13 and the UBM layer 23, the chip stack structure 3 includes the connection layer 41 (connection Layer 41 is covered with conductive intermetallic compounds), and also includes unreacted solder 13 and UBM layer 23 respectively located on both sides of connection layer 41 , so the performance of chip stack structure 3 is unstable. Compared with the prior art, since the protrusion 24 is inserted into the solder 13 in the embodiment of the present application, the protrusion 24 and the solder 13 fully react, and the inside of the formed solder ball 40 is filled with conductive intermetallic compounds. Therefore, the embodiment of the present application produces The performance of chip stack structure 3 is more stable.

Taking the first integrated circuit device 300 as the first chip 10 and the second integrated circuit device 400 as the second chip 20 as examples below, several specific embodiments are provided for the fabrication of the integrated circuit stack structure 02 and the integrated circuit stack structure 02 The method is described in detail. In the case that the first integrated circuit device 300 is the first chip 10 and the second integrated circuit device 400 is the second chip 20 , the integrated circuit stack structure 02 may be called a chip stack structure 3 .

Embodiment one

Embodiment 1 provides a method for manufacturing a chip stack structure 3, as shown in FIG. 7 , specifically including the following steps:

S100, as shown in FIG. 8a, provide a first chip 10, the first chip 10 includes a first substrate 10a, a first conductive layer 11 disposed on the first substrate 10a, and a first passivation layer disposed on the first conductive layer 11 The passivation layer 12; wherein, the first passivation layer 12 includes a first opening, at least part of the first conductive layer 11 is located in the first opening, that is, the first conductive layer 11 is exposed on the surface of the first chip 10 .

It can be understood that the first conductive layer 11 may be partially exposed on the surface of the first chip 10 ; the first conductive layer 11 may also be completely exposed on the surface of the first chip 10 .

For the structure and material of the first conductive layer 11 , reference may be made to the above, and details will not be repeated here.

Here, the first passivation layer 12 may be a single-layer structure or a multi-layer structure.

In addition, the material of the first passivation layer 12 may include organic materials or inorganic materials. Exemplarily, the material of the first passivation layer 12 may include one or more of PI, PBO, nitride or oxide.

In the case where a through-silicon via is formed on the first substrate 10a of the first chip 10, the projection of the first opening of the first passivation layer 12 on the first substrate 10a may overlap with the through-silicon via, or No overlapping areas.

In some examples, the thickness d of the first passivation layer 12 ranges from 5 μm˜7 μm. For example, the thickness d of the first passivation layer 12 may be 5 μm, 6 μm or 7 μm, etc. FIG.

In some examples, the opening size e of the first opening of the first passivation layer 12 ranges from 10 μm to 14 μm. For example, the opening size e of the first opening of the first passivation layer 12 may be 10 μm, 11 μm, 12 μm or 14 μm.

S101 , as shown in FIG. 8 a , form a first seed layer 14 on the first passivation layer 12 ; the first seed layer 14 covers the first passivation layer 12 and the first conductive layer 11 .

Here, the first seed layer 14 may be a single-layer structure or a multi-layer structure.

In addition, the material of the first seed layer 14 includes one or more of Ti, Cu, Ni, Co, W or related alloys. Exemplarily, the first seed layer 14 includes a laminated Ti layer and a Cu layer. When forming the first seed layer 14 , the Ti layer may be deposited first, and then the Cu layer may be deposited.

S102 , as shown in FIG. 8 a , form a first photoresist layer 15 on the first seed layer 14 ; the first photoresist layer 15 includes a first hollow area. Wherein, the projection of the first hollow area on the first substrate 10 a and the projection of the first opening on the first substrate 10 a have overlapping areas.

In some examples, the projection of the first hollow area on the first chip 10 is located in the first opening.

Illustratively, forming the first photoresist layer 15 on the first seed layer 14 specifically includes: first, spin-coating a photoresist film on the first seed layer 14; the photoresist film can be a positive photoresist, or It may be a negative photoresist; next, mask exposure and development are performed on the photoresist film to form a first hollow area.

Here, the required first hollow area can be obtained by adjusting photolithography parameters. The cross-sectional shape of the first hollow area may be, for example, a rectangle, a trapezoid or an inverted trapezoid.

In addition, the sidewall of the first hollow area and the first substrate 10a of the first chip 10 may be vertical or inclined. Of course, the sidewall of the first hollow area may also be an arc with a certain curvature.

S103, as shown in FIG. 8a, forming a metal pillar (pillar) 16 in the first hollow area.

It should be noted that step S103 is an optional step, and in some examples, step S103 may also be omitted.

Here, the metal pillar 16 may be a single-layer structure or a multi-layer structure.

In addition, the material of the metal pillar 16 includes one or more of Cu, Ti, Ni, Co.

For example, the metal pillar 16 is a single-layer structure, and the material of the metal pillar 16 is Cu. For another example, the metal pillar 16 has a multi-layer structure, and the metal pillar 16 includes a Cu layer and a Ni layer stacked in sequence, or the metal pillar 16 includes a Cu layer, a Ni layer and a Cu layer stacked in sequence.

In addition, for example, the metal pillars 16 may be formed by electroplating or electroless plating.

On this basis, since the metal pillars 16 and the first conductive layer 11 are electrically connected in one-to-one correspondence, the number of the metal pillars 16 is the same as the number of the first conductive layers 11, and the metal pillars 16 can be determined according to the number of the first conductive layers 11. quantity.

It should be understood that when the metal pillars 16 are formed, the heights of the multiple metal pillars 16 may be different due to process differences, the smaller the height difference of the multiple metal pillars 16, the better the coplanarity of the multiple metal pillars 16, The greater the height difference of the plurality of metal pillars 16 is, the worse the coplanarity of the plurality of metal pillars 16 is.

In some examples, the range of the width m of the metal post 16 parallel to the first surface 10a of the first chip 10 is 5um-30um, for example, the width m of the metal post 16 parallel to the first surface 10a of the first chip 10 It can be 5um, 10um, 14um, 20um or 30um, etc.

In some examples, the distance between the centers of two adjacent metal pillars 16 ranges from 10um to 40um, for example, the distance between the centers of two adjacent metal pillars 16 can be 10μm, 20μm, 30μm or 40μm, etc. .

S104 , as shown in FIG. 8 a , forming solder 13 in the first hollow area; the metal pillar 16 is electrically connected to the solder 13 .

It should be noted that for step S104, reference may be made to the above step S11, which will not be repeated here.

In some examples, the surface of the solder 13 away from the first chip 10 is lower than the surface of the first photoresist layer 15 away from the first chip 10 .

S105 , as shown in FIG. 8 a , remove the first photoresist layer 15 , and remove the part of the first seed layer 14 except under the metal pillar 16 .

Here, the first photoresist layer 15 may be removed by a stripping solution. Parts of the first seed layer 14 except under the metal pillars 16 may be removed by an etching process. It can be understood that the etching process may be a dry etching process or a wet etching process.

After step S105, the surface of the first passivation layer 12 away from the first substrate 10a is exposed, and at least part of the surface of the first conductive layer 11 away from the first substrate 10a is exposed.

In some examples, when the solder 13 is a solder ball, after step S105, the manufacturing method of the chip stack structure further includes: performing reflow soldering on the structure obtained in step S105, after reflow soldering, as shown in FIG. In some examples, the solder 13 will form a hemispherical structure under the action of surface tension.

It should be noted that the structure obtained in step S105 can be reflowed in a formic acid atmosphere, or the structure obtained in step S105 can be reflowed in air or an inert atmosphere.

In order to increase the amount of solder 13 , in some examples, after reflowing the structure obtained in step S105 , the obtained solder 13 is hemispherical or larger than hemispherical. On this basis, in step S104 , when forming the solder 13 , the height of the solder 13 can be increased so that after reflow soldering, the obtained solder 13 is hemispherical or larger than hemispherical.

S106, as shown in FIG. 8b, provide a second chip 20, the second chip 20 includes a second substrate 20a, a second conductive layer 21 disposed on the second substrate 20a, and a second conductive layer formed on the second conductive layer 21. Passivation layer 22 ; wherein, the second passivation layer 22 includes a second opening, at least part of the second conductive layer 21 is located in the second opening, that is, the second conductive layer 11 is exposed on the surface of the second chip 20 .

It can be understood that, the second conductive layer 11 may be partially exposed on the surface of the second chip 20 ; the second conductive layer 11 may also be completely exposed on the surface of the second chip 20 .

The structure and material of the second conductive layer 11 can be referred to above, and will not be repeated here.

Here, the second passivation layer 22 may be a single-layer structure or a multi-layer structure.

In addition, the material of the second passivation layer 22 can refer to the material of the above-mentioned first passivation layer 12 , which will not be repeated here. The material of the first passivation layer 12 and the material of the second passivation layer 22 may be the same or different.

In the case where the TSV 20b is formed on the second substrate 20a of the second chip 20, the projection of the second opening of the second passivation layer 22 on the second substrate 20a may overlap with the TSV 20b, No overlapping regions are also possible.

In some examples, the thickness f of the second passivation layer 22 ranges from 5 μm˜7 μm. For example, the thickness f of the second passivation layer 22 may be 5 μm, 6 μm or 7 μm, etc. FIG.

In some examples, the opening size g of the second opening of the second passivation layer 22 ranges from 10 μm to 14 μm. For example, the opening size g of the second opening of the second passivation layer 22 may be 10 μm, 11 μm, 12 μm or 14 μm.

S107 , as shown in FIG. 8 b , forming a second seed layer 25 on the second passivation layer 22 ; the second seed layer 25 covers the second passivation layer 22 and the second conductive layer 21 .

Here, the second seed layer 25 may be a single-layer structure or a multi-layer structure.

In addition, the material of the second seed layer 25 can refer to the material of the first seed layer 14 , which will not be repeated here. The material of the second seed layer 25 and the material of the first seed layer 14 may be the same or different.

S108 , as shown in FIG. 8 b , forming a second photoresist layer 26 on the second seed layer 25 ; the second photoresist layer 26 includes a second hollow area. Wherein, the projection of the second hollow area on the second base 20 a and the projection of the second opening on the second base 20 a have overlapping areas.

It should be noted that, the method of forming the second photoresist layer 26 on the second seed layer 25 can refer to the method of forming the first photoresist layer 15 on the first seed layer 14 in step S102, which will not be repeated here. .

Here, the required second hollowed-out area can be obtained by adjusting photolithography parameters. The cross-sectional shape of the second hollow area may be, for example, a rectangle, a trapezoid or an inverted trapezoid. Fig. 8b is an illustration by taking the cross-sectional shape of the second hollow area as an inverted trapezoid as an example.

In addition, the sidewall of the second hollowed out area and the second substrate 20a of the second chip 20 may be vertical or inclined. Of course, the sidewall of the second hollowed out area may also be an arc surface with a certain curvature.

S109 , as shown in FIG. 8 b , forming a protrusion 24 in the second hollow area.

It should be noted that for step S109, reference may be made to the above step S13, which will not be repeated here.

In some examples, the surface of the protrusion 24 away from the second chip 20 is lower than the surface of the second photoresist layer 26 away from the second chip 20 .

S110 , as shown in FIG. 8 b , removing the second photoresist layer 26 , and removing the part of the second seed layer 25 except under the protrusion 24 .

Here, the second photoresist layer 26 may be removed by a stripping solution. The structure obtained after step S110 may be rinsed with a scrubber, and then the second seed layer 25 is removed by etching except for the part below the protrusion 24, so that the second passivation layer 22 is far away from the second substrate 20a surface exposed.

It should be understood that when the etching process is used to remove the part of the second seed layer 25 except the part below the protrusion 24, the etching process will also corrode the protrusion 24 at the same time, and the protrusion 24 will be affected by the corrosion and shrink. A needle-cone structure or a mesa-like structure will be formed, and of course a columnar or other shaped structure can also be formed. The shape of the protrusion 24 can refer to the above, and will not be repeated here.

It can be understood that the above etching process may be a dry etching process or a wet etching process.

It should be noted that steps S100 to S105 can be executed first, and then steps S106 to S110 can be executed; or steps S106 to S110 can be executed first, and then steps S100 to S105 can be executed; Simultaneously with step S105, step S106 to step S110 are executed.

S111 , as shown in FIG. 8 c , heat the solder 13 and the bump 24 to couple the first chip 10 and the second chip 20 together; wherein, the bump 24 is inserted into the solder 13 .

It should be noted that for step S111, reference may be made to the above step S14, which will not be repeated here.

Here, after step S110 and before step S111, the manufacturing method of the chip stack structure further includes: as shown in FIG. 8c, placing the first chip 10 and the second chip 20 relative to each other.

It should be understood that the provision of the metal post 16 can increase the size of the portion electrically connected to the protrusion 24 , which facilitates soldering of the solder 13 and the protrusion 24 .

S112 , as shown in FIG. 8 c , filling the buffer material 30 between the first chip 10 and the second chip 20 .

It should be noted that step S112 is an optional step, for example, in some examples, step S112 may also be omitted.

Exemplarily, a capillary underfill (CUF) process, a mold underfill (MUF) process, a non-conductive film (non-conductive film, NCF) process or a non-conductive paste (non-conductive paste) process may be used. , NCP) processes to fill the buffer material 30 between the first chip 10 and the second chip 20 .

Filling the buffer material 30 between the first chip 10 and the second chip 20 can enhance the strength and reliability of the chip stack structure.

It should be noted that after step S112, the manufactured chip stack structure can be used as a separate package interconnected with the package substrate 4 through the second connector 5, or can be bonded to other packages as a unit.

In the first embodiment, when the first chip 10 and the second chip 20 are interconnected, since the bump 24 is inserted into the solder 13, warpage of the first chip 10 and/or the second chip 20 can be better avoided, or , the impact of the flatness (also called coplanarity) of the metal post 16 and the solder 13 ensures the electrical connection between the first conductive layer 11 and the second conductive layer 21, thus ensuring the connection between the first chip 10 and the second chip 20 interconnection. The manufacturing method of the chip stack structure provided in the first embodiment can be compatible with a larger chip size and a smaller distance between the centers of two adjacent solders 13 .

In addition, since the protrusion 24 is inserted into the solder 13, the protrusion 24 will pierce the surface of the solder 13 when inserted, increasing the contact area between the solder 13 and the protrusion 24, thereby reducing the amount of solder flux shortage or surface oxidation of the solder 13. The resulting risk of incomplete wetting of the solder 13 to the bumps 24 also reduces pillow-shaped solder joints.

On this basis, during the soldering process, the protrusion 24 is inserted into the solder 13, and after the solder 13 and the protrusion 24 are wetted, since the solder 13 wraps the protrusion 24, the protrusion 24 can block the flow of the solder 13, thereby avoiding Two adjacent solders 13 are connected after flowing, which leads to the risk of short circuit.

In addition, when the first chip 10 and the second chip 20 are coupled, since the bump 24 is inserted into the solder 13, if the bump 24 and the solder 13 are not aligned and there is a certain offset, the bump 24 and the solder 13 will Under the action of the force generated by wetting, the solder 13 will drive the first chip 10 to move, and/or the protrusion 24 will drive the second chip 20 to move, so that the protrusion 24 and the solder 13 are aligned, so that the protrusion 24 and the solder 13 has a self-aligning effect when soldering.

Based on the above, after the step S112, the method for manufacturing the stacked chip structure further includes performing multiple reflow soldering on the structure obtained in the step S112. After multiple times of reflow soldering, the protrusions 24 will gradually melt, and the material of the protrusions 24 and the material of the solder 13 will react to form an intermetallic compound. Lateral growth, and finally, in the case of sufficient reaction of the bumps 24 and the solder 13, forms an intermetallic structure throughout.

The first embodiment also provides a chip stack structure 3, which can be manufactured by using the method for manufacturing the chip stack structure provided in the above steps S100-S112. As shown in FIG. 9a and FIG. 9b, the chip stack structure 3 includes a first chip 10, the first chip 10 includes a first substrate 10a and a first conductive portion 100 disposed on the first substrate 10a, the first conductive portion 100 is exposed to The surface of the first chip 10; the chip stack structure 3 also includes a second chip 20; the second chip 20 includes a second base 20a and a second conductive portion 200 disposed on the second base 20a, and the second conductive portion 200 is exposed to the second base 20a. The surface of the second chip 20; the chip stack structure 3 also includes a solder ball 40, the solder ball 40 is arranged between the first conductive part 100 and the second conductive part 200, and the solder ball 40 is connected to the first conductive part 100 and the second conductive part respectively 200 contacts, the solder ball 40 is covered with conductive intermetallic compounds. The first chip 10 also includes a first passivation layer 12 disposed on the side of the first conductive portion 100 close to the second chip 20; the first passivation layer 12 includes a first opening, and at least part of the first conductive portion 100 is located on the second chip 20. An opening; the second chip 20 also includes a second passivation layer 22 arranged on the side of the second conductive portion 200 close to the first chip 10; the second passivation layer 22 includes a second opening, the second conductive layer 200 at least partially located in the second opening.

Since the conductive intermetallic compound is distributed inside the solder ball 40, that is to say, the material at each position of the solder ball 40 includes an intermetallic compound, that is, the entire material of the solder ball 40 includes an intermetallic compound, so the chip stack structure 3 The performance is more stable.

In some examples, as shown in FIG. 9a, the first conductive part 100 includes a first conductive layer 11 and a first seed layer 14 disposed on the side of the first conductive layer 11 away from the first substrate 10a; the second conductive part 200 includes The second conductive layer 21 and the second seed layer 25 disposed on the side of the second conductive layer 21 away from the second substrate 20a.

In some other examples, as shown in FIG. 9b, the first conductive portion 100 includes a first conductive layer 11, a first seed layer 14 disposed on the side of the first conductive layer 11 away from the first substrate 10a, and a first seed layer 14 disposed on the first seed layer 11 The metal pillar 16 on the side of the layer 14 away from the first substrate 10a; the second conductive portion 200 includes the second conductive layer 21 and the second seed layer 25 disposed on the side of the second conductive layer 21 away from the second substrate 20a.

In the case that the first conductive part 100 includes the metal post 16 , the size of the first conductive part 100 can be increased, which is beneficial for the solder ball 40 to contact the first conductive part 100 .

In some examples, as shown in FIG. 9a and FIG. 9b , the chip stack structure 3 further includes: a buffer material 30 filled between the first chip 10 and the second chip 20 .

Based on the above, in the first embodiment, in step S106 , the thickness of the second passivation layer 22 in the provided second chip 20 is not limited. The thickness of the second passivation layer 22 can be smaller than the height of the protrusion 24 ; it can also be greater than the height of the protrusion 24 ; of course, it can also be equal to the height of the protrusion 24 . The thickness of the second passivation layer 22 can be set according to the height of the protrusion 24 .

In some examples, as shown in FIG. 10a, the distance L from the upper surface of the second passivation layer 22, that is, the surface away from the second substrate 20a, to the upper surface of the second conductive layer 21, that is, the surface away from the second substrate 20a, is greater than or It is equal to the sum M of the height H of the protrusion 24 and the distance from the lower surface of the protrusion 24 ie the surface close to the second base 20a to the upper surface of the second conductive layer 21 ie the surface away from the second base 20a.

The distance L between the surface of the second passivation layer 22 away from the second base 20a and the surface of the second conductive layer 21 away from the second base 20a is greater than or equal to the height H of the protrusion 24 and the surface of the protrusion 24 close to the second base 20a In the case of the sum M of distances from the surface of the second conductive layer 21 away from the second substrate 20a, the second opening of the second passivation layer 22 forms a cavity structure, and since the protrusion 24 is located in the cavity structure, Therefore, when the solder 13 and the protrusion 24 are welded, the solder 13 can be prevented from sputtering or overflowing, resulting in electrical connection between two adjacent solders 13 , thereby improving the soldering yield of the solder 13 and the protrusion 24 .

The distance L between the surface of the second passivation layer 22 away from the second base 20a and the surface of the second conductive layer 21 away from the second base 20a is greater than or equal to the height H of the protrusion 24 and the surface of the protrusion 24 close to the second base 20a In the case of the sum M of the distances from the surface of the second conductive layer 21 away from the second substrate 20a, the fabricated chip stack structure 3, as shown in FIG. 10b, the upper surface of the second passivation layer 22 is away from the second substrate The distance L from the surface of the second conductive layer 21 to the upper surface of the second conductive layer 21, that is, the surface away from the second substrate 20a, is greater than or equal to the height of the solder ball 40 and the lower surface of the solder ball 40, that is, the surface near the second substrate 20a to the second conductive layer 20a. The upper surface of the layer 21 is the sum T of the distances away from the surface of the second substrate 20a.

Embodiment two

The difference between the second embodiment and the first embodiment in the manufacturing method of the chip stack structure 3 is that in the second embodiment, after the step S108 of the first embodiment and before the step S109, a step is added, in the second hollow area A conductive base is formed, and the conductive base is electrically connected to the second conductive layer 21; wherein, the wettability of the conductive base is worse than that of the protrusion 24, and the projection of the protrusion 24 on the conductive base is located within the boundary of the conductive base.

The second embodiment provides a method for manufacturing a chip stack structure 3, which specifically includes the following steps:

S200, as shown in FIG. 8a, provide a first chip 10, the first chip 10 includes a first substrate 10a, a first conductive layer 11 disposed on the first substrate 10a, and a first passivation layer disposed on the first conductive layer 11 The passivation layer 12; wherein, the first passivation layer 12 includes a first opening, at least part of the first conductive layer 11 is located in the first opening, that is, the first conductive layer 11 is exposed on the surface of the first chip 10 .

It should be noted that for step S200, reference may be made to the above step S100, which will not be repeated here.

S201 , as shown in FIG. 8 a , form a first seed layer 14 on the first passivation layer 12 ; the first seed layer 14 covers the first passivation layer 12 and the first conductive layer 11 .

It should be noted that for step S201, reference may be made to the above step S101, which will not be repeated here.

S202 , as shown in FIG. 8 a , form a first photoresist layer 15 on the first seed layer 14 ; the first photoresist layer 15 includes a first hollow area. Wherein, the projection of the first hollow area on the first substrate 10a and the projection of the first opening on the first substrate 10a have overlapping areas.

It should be noted that for step S202, reference may be made to the above step S102, which will not be repeated here.

S203 , as shown in FIG. 8 a , forming metal pillars 16 in the first hollow area.

It should be noted that step S203 is an optional step, for example, in some examples, step S203 may also be omitted.

Here, for step S203, reference may be made to the above step S103, which will not be repeated here.

S204 , as shown in FIG. 8 a , forming solder 13 in the first hollow area; the metal pillar 16 is electrically connected to the solder 13 .

It should be noted that for step S204, reference may be made to the above step S104, which will not be repeated here.

S205 , as shown in FIG. 8 a , remove the first photoresist layer 15 , and remove the part of the first seed layer 14 except under the metal pillar 16 .

It should be noted that for step S205, reference may be made to the above step S105, which will not be repeated here.

S206, as shown in FIG. 11a, provide a second chip 20, the second chip 20 includes a second substrate 20a, a second conductive layer 21 disposed on the second substrate 20a, and a second conductive layer formed on the second conductive layer 21. Passivation layer 22 ; wherein, the second passivation layer 22 includes a second opening, at least part of the second conductive layer 21 is located in the second opening, that is, the second conductive layer 11 is exposed on the surface of the second chip 20 .

It should be noted that for step S206, reference may be made to the above step S106, which will not be repeated here.

S207 , as shown in FIG. 11 a , forming a second seed layer 25 on the second passivation layer 22 ; the second seed layer 25 covers the second passivation layer 22 and the second conductive layer 21 .

It should be noted that for step S207, reference may be made to the above step S107, which will not be repeated here.

S208 , as shown in FIG. 11 a , forming a second photoresist layer 26 on the second seed layer 25 ; the second photoresist layer 26 includes a second hollow area. Wherein, the projection of the second hollow area on the second base 20 a and the projection of the second opening on the second base 20 a have overlapping areas.

It should be noted that for step S208, reference may be made to the above step S108, which will not be repeated here.

S209 , as shown in FIG. 11 a , form a conductive base 27 in the second hollow area, and the conductive base 27 is located on the second conductive layer 21 and is electrically connected to the second conductive layer 21 .

Here, for example, the conductive base 27 can be formed by electroplating or electroless plating.

In addition, the conductive base 27 can be a single-layer structure or a multi-layer structure.

In some examples, the material of the conductive base 27 includes an inert metal. The inert metal may be, for example, one or more of Ni, Au, Co or other inert metals.

S210 , as shown in FIG. 11 a , forming a protrusion 24 in the second hollow area; wherein, the wettability of the conductive base 27 is worse than that of the protrusion 24 .

It should be noted that for step S210, reference may be made to the above step S109, which will not be repeated here.

In some examples, the material of the protrusion 24 includes a metal that is easy to be corroded, such as Cu, Al, and the like.

Here, the wettability of the conductive base 27 is worse than that of the protrusion 24 by selecting a suitable material for the conductive base 27 and the material for the protrusion 24, and the wettability of most inert metals is lower than that of the active metal. Poor humidity.

S211 , as shown in FIG. 11 a , remove the second photoresist layer 26 , and remove the part of the second seed layer 25 except under the conductive base 27 .

Here, the second photoresist layer 26 may be removed by a stripping solution. The structure obtained after step S211 may be rinsed with a scrubber, and then, an etching process is used to remove the part of the second seed layer 25 except under the conductive base 27 . The etching process may be a dry etching process or a wet etching process.

It should be understood that when the etching process is used to remove the part of the second seed layer 25 except the part below the conductive base 27, the etching process will also corrode the protrusion 24 at the same time, and the protrusion 24 will be affected by the corrosion and shrink. By controlling the shape or etching process of the second hollow area of the second photoresist layer 26, the shape of the formed protrusion 24 can be a needle-cone structure or a mesa structure, and of course a columnar or other shape structure can also be formed. . The shape of the protrusion 24 can be referred to above, and will not be repeated here.

It should be noted that, in the case where the material of the conductive base 27 includes an inert metal, the inert metal is not affected by the etching or is less affected by the etching, so after the etching process, the conductive base The size of the protrusion 27 is constant, or shrinks smaller relative to the protrusion 24 , so that the projection of the protrusion 24 on the conductive base 27 is located within the boundary of the conductive base 27 .

S212 , as shown in FIG. 11 b , heating the solder 13 and the bump 24 to couple the first chip 10 and the second chip 20 together; wherein, the bump 24 is inserted into the solder 13 .

It should be noted that for step S212, reference may be made to the above step S111, which will not be repeated here.

Here, when the protrusion 24 is inserted into the solder 13 , since the wettability of the conductive base 27 is lower than that of the protrusion 24 , the flow of the solder 13 will be slowed down after the solder 13 flows onto the conductive base 27 .

S213 , as shown in FIG. 11 b , filling the buffer material 30 between the first chip 10 and the second chip 20 .

It should be noted that step S213 is an optional step, for example, in some examples, step S213 may be omitted.

Here, step S213 may refer to the above-mentioned step S112, which will not be repeated here.

The manufacturing method of the chip stack structure provided in the second embodiment has the same technical effect as the manufacturing method of the chip stacking structure provided in the first embodiment, and reference may be made to the above first embodiment, which will not be repeated here. On this basis, since in the second embodiment, before forming the protrusion 24, the conductive base 27 is also formed, and the wettability of the conductive base 27 is worse than that of the protrusion 24 due to the choice of material. The wettability of the conductive base 27 is worse than that of the protrusion 24, so when the solder 13 is welded to the protrusion 24, the conductive base 27 can inhibit the flow of the solder 13, so the phenomenon of tin climbing can be avoided. The short circuit phenomenon caused by the contact of two adjacent solders 13 is eliminated.

The second embodiment also provides a chip stack structure 3, which can be manufactured by using the chip stack structure manufacturing method provided in the above steps S200-S213. The difference between the chip stack structure 3 provided in the second embodiment and the chip stack structure 3 provided in the first embodiment lies in that the chip stack structure 3 provided in the second embodiment adds a conductive base.

As shown in FIG. 12 , the chip stack structure 3 provided by Embodiment 2 includes a first chip 10, and the first chip 10 includes a first substrate 10a and a first conductive portion 100 disposed on the first substrate 10a, the first conductive portion 100 Exposed to the surface of the first chip 10; the chip stack structure 3 also includes a second chip 20; the second chip 20 includes a second substrate 20a and a second conductive portion 200 disposed on the second substrate 20a, and the second conductive portion 200 is exposed on the surface of the second chip 20; the chip stack structure 3 also includes a solder ball 40, the solder ball 40 is arranged between the first conductive part 100 and the second conductive part 200, and the solder ball 40 is connected to the first conductive part 100 and the second conductive part 200 respectively. The conductive portion 200 is in contact, and a conductive intermetallic compound is distributed inside the solder ball 40 . The first chip 10 also includes a first passivation layer 12 disposed on the side of the first conductive portion 100 close to the second chip 20; the first passivation layer 12 includes a first opening, and at least part of the first conductive portion 100 is located on the second chip 20. An opening; the second chip 20 also includes a second passivation layer 22 arranged on the side of the second conductive portion 200 close to the first chip 10; the second passivation layer 22 includes a second opening, the second conductive layer 200 at least partially located in the second opening.

In some examples, the first conductive part 100 includes a first conductive layer 11 and a first seed layer 14 disposed on a side of the first conductive layer 11 away from the first substrate 10a; the second conductive part 200 includes a second conductive layer 21, The second seed layer 25 disposed on the side of the second conductive layer 21 away from the second substrate 20 a and the conductive base 27 disposed on the side of the second seed layer 25 away from the second substrate 20 a.

In other examples, as shown in FIG. 12 , the first conductive part 100 includes a first conductive layer 11, a first seed layer 14 disposed on the side of the first conductive layer 11 away from the first substrate 10a, and a first seed layer 14 disposed on the first seed layer 11. The metal post 16 on the side of the layer 14 away from the first substrate 10a; the second conductive part 200 includes the second conductive layer 21, the second seed layer 25 arranged on the side of the second conductive layer 21 away from the second substrate 20a, and the second seed layer 25 arranged on the second conductive layer 21 The second sublayer 25 is away from the conductive base 27 on the side of the second substrate 20a.

In some examples, as shown in FIG. 12 , the chip stack structure 3 further includes: a buffer material 30 filled between the first chip 10 and the second chip 20 .

In some examples, the distance from the upper surface of the second passivation layer 22, that is, the surface away from the second substrate 20a to the upper surface of the second conductive layer 21, that is, the surface away from the second substrate 20a, is greater than or equal to the height H of the protrusion 24 The sum of the distances from the lower surface of the protrusion 24 , that is, the surface close to the second base 20 a , to the upper surface of the second conductive layer 21 , that is, the surface away from the second base 20 a.

The distance from the surface of the second passivation layer 22 away from the second base 20a to the surface of the second conductive layer 21 away from the second base 20a is greater than or equal to the height of the protrusion 24 and the distance from the surface of the protrusion 24 close to the second base 20a to the second base 20a. In the case of the sum of the distances between the two conductive layers 21 away from the surface of the second substrate 20a, the resulting chip stack structure 3, the upper surface of the second passivation layer 22 is the surface far away from the second substrate 20a to the second conductive layer 21 The distance from the upper surface of the upper surface of the second substrate 20a away from the surface of the second substrate 20a is greater than or equal to the height of the solder ball 40 and the lower surface of the solder ball 40, that is, the surface close to the second substrate 20a, to the upper surface of the second conductive layer 21, that is, away from the second substrate The sum of the distances of the surfaces of 20a.

Embodiment Three

The difference between the third embodiment and the second embodiment in making the chip stack structure 3 is that in the third embodiment, after the step S210 in the second embodiment and before the step S211, a step is added to form a protective layer on the protrusion 24 ; The protective layer covers at least part of the surface of the protrusion 24 .

The third embodiment provides a method for manufacturing a chip stack structure 3, which specifically includes the following steps:

S300, providing a first chip 10, the first chip 10 includes a first substrate 10a, a first conductive layer 11 disposed on the first substrate 10a, and a first passivation layer 12 disposed on the first conductive layer 11; wherein, The first passivation layer 12 includes a first opening, at least part of the first conductive layer 11 is located in the first opening, that is, the first conductive layer 11 is exposed on the surface of the first chip 10 .

S301 , forming a first seed layer 14 on the first passivation layer 12 ; the first seed layer 14 covers the first passivation layer 12 and the first conductive layer 11 .

S302 , forming a first photoresist layer 15 on the first seed layer 14 ; the first photoresist layer 15 includes a first hollow area. Wherein, the projection of the first hollow area on the first substrate 10 a and the projection of the first opening on the first substrate 10 a have overlapping areas.

S303, forming metal pillars 16 in the first hollow area.

It should be noted that step S303 is an optional step, for example, in some examples, step S303 can also be omitted.

S304 , forming solder 13 in the first hollow area; the metal pillar 16 is electrically connected to the solder 13 .

S305 , removing the first photoresist layer 15 , and removing the part of the first seed layer 14 except under the metal pillar 16 .

S306, providing a second chip 20, the second chip 20 comprising a second substrate 20a, a second conductive layer 21 disposed on the second substrate 20a, and a second passivation layer 22 disposed on the second conductive layer 21; wherein , the second passivation layer 22 includes a second opening, at least part of the second conductive layer 21 is located in the second opening, that is, the second conductive layer 11 is exposed on the surface of the second chip 20 .

S307 , forming a second seed layer 25 on the second passivation layer 22 ; the second seed layer 25 covers the second passivation layer 22 and the second conductive layer 21 .

S308 , forming a second photoresist layer 26 on the second seed layer 25 ; the second photoresist layer 26 includes a second hollow area. Wherein, the projection of the second hollow area on the second base 20 a and the projection of the second opening on the second base 20 a have overlapping areas.

S309 , forming a conductive base 27 in the second hollow area, the conductive base 27 is located on the second conductive layer 21 and is electrically connected to the second conductive layer 21 .

S310 , forming a protrusion 24 in the second hollow area; wherein, the wettability of the conductive base 27 is worse than that of the protrusion 24 .

It should be noted that for steps S300-S310, reference may be made to the above-mentioned steps S200-S210, which will not be repeated here.

S311 , as shown in FIG. 13 , forming a protection layer 28 on the protrusion 24 ; the protection layer 28 covers at least part of the surface of the protrusion 24 .

In some examples, the protection layer 28 covers the surface of the bump 24 away from the second chip 20 .

Here, the protective layer 28 may have a single-layer structure or a multi-layer structure.

In some examples, the material of the protective layer 28 includes an inert metal. When the protection layer 28 has a single-layer structure, the material of the protection layer 28 may be one or more of Ni, Au, Co or other inert metals, for example. When the protective layer 28 has a multilayer structure, for example, the protective layer 28 may include a stacked Ni layer and an Au layer or a stacked Ni layer, a Pd (palladium) layer, and an Au layer.

In some examples, the thickness of the protection layer 28 ranges from 0.1 um to 1 um, for example, the thickness of the protection layer 28 may be 0.1 μm, 0.5 μm, 0.8 μm, or 1 μm.

S312 , as shown in FIG. 13 , removing the second photoresist layer 26 , and removing the part of the second seed layer 25 except under the conductive base 27 .

It should be noted that for step S312, reference may be made to the above step S211, which will not be repeated here.

Here, when the material of the protective layer 28 includes an inert metal, during the etching process, the inert metal is not affected by the etching or is less affected by the etching, so after the etching process, the protective layer 28 The size remains the same, or the protective layer 28 shrinks less relative to the protrusion 24 .

S313 , as shown in FIG. 14 , heating the solder 13 and the bump 24 to couple the first chip 10 and the second chip 20 together; wherein, the bump 24 is inserted into the solder 13 .

It should be noted that for step S313, reference may be made to the above step S111, which will not be repeated here.

It should be understood that the wettability of the conductive base 27 is poorer than that of the protrusion 24 due to the selection of the material, so after the protrusion 24 is inserted into the solder 13, the solder 13 has better wettability due to the better wettability of the solder 13 . 13 will wrap around the protrusion 24.

S314 , as shown in FIG. 14 , filling the buffer material 30 between the first chip 10 and the second chip 20 .

It should be noted that step S314 is an optional step, for example, in some examples, step S314 may be omitted.

Here, step S314 may refer to the above-mentioned step S112, which will not be repeated here.

The manufacturing method of the chip stack structure provided in the third embodiment has the same technical effect as the manufacturing method of the chip stacking structure provided in the second embodiment, and reference may be made to the above second embodiment, which will not be repeated here. On this basis, because there is a risk of oxidation on the surface of the bump 24, if the surface of the bump 24 is oxidized, when the bump 24 and the solder 13 are soldered, the welding effect will be poor, so the bump 24 and the solder 13 Before soldering, it is usually necessary to deoxidize the surface of the bump 24 , and in this way, the process of manufacturing the stacked chip structure will be increased. In the third embodiment, since the protective layer 28 is formed on the protrusion 24, the protective layer 28 can prevent the surface of the protrusion 24 from being oxidized, so when the protrusion 24 and the solder 13 are welded, the need for a protective layer 28 on the protrusion 24 can be omitted. The process of deoxidizing the surface can simplify the manufacturing method of the chip stack structure and reduce the production cost.

The third embodiment also provides a chip stack structure 3, which can be manufactured by using the method for manufacturing the chip stack structure provided in the above steps S300-S314. The difference between the chip stack structure 3 provided in the third embodiment and the chip stack structure 3 provided in the second embodiment lies in that a protective layer is added to the chip stack structure 3 provided in the third embodiment.

As shown in FIG. 15 , the chip stack structure 3 provided by Embodiment 3 includes a first chip 10; the first chip 10 includes a first substrate 10a and a first conductive portion 100 disposed on the first substrate 10a, the first conductive portion 100 Exposed to the surface of the first chip 10; the chip stack structure 3 also includes a second chip 20; the second chip 20 includes a second substrate 20a and a second conductive portion 200 disposed on the second substrate 20a, and the second conductive portion 200 is exposed on the surface of the second chip 20; the chip stack structure 3 also includes a solder ball 40, the solder ball 40 is arranged between the first conductive part 100 and the second conductive part 200, and the solder ball 40 is connected to the first conductive part 100 and the second conductive part 200 respectively. The conductive portion 200 is in contact, and a conductive intermetallic compound is distributed inside the solder ball 40 . The chip stack structure 3 further includes: a protection layer 28 disposed inside the solder balls 40 . The first chip 10 also includes a first passivation layer 12 disposed on the side of the first conductive portion 100 close to the second chip 20; the first passivation layer 12 includes a first opening, and at least part of the first conductive portion 100 is located on the second chip 20. An opening; the second chip 20 also includes a second passivation layer 22 arranged on the side of the second conductive portion 200 close to the first chip 10; the second passivation layer 22 includes a second opening, the second conductive layer 200 at least partially located in the second opening.

Wherein, the structure of the first conductive part 100 and the structure of the second conductive part 200 can refer to the second embodiment, which will not be repeated here.

In some examples, as shown in FIG. 15 , the chip stack structure 3 further includes: a buffer material 30 filled between the first chip 10 and the second chip 20 .

It should be noted that after step S314 , during multiple reflow processes, the bumps 24 and the solder 13 will react to form intermetallic compounds. On this basis, the solder 13 may also react with the protection layer 28 to form an intermetallic compound. Therefore, in some examples, the thickness of the protection layer 28 in the manufactured chip stack structure 3 is smaller than the thickness of the protection layer 28 formed in step S311 .

Based on the above, it should be noted that the third embodiment is described by taking the chip stack structure 3 including the conductive base 27 as an example. In other examples, the step of making the conductive base 27 can also be omitted in the manufacturing method of the chip stack structure 3. , the conductive base 27 may not be provided in the chip stack structure 3, and other manufacturing steps and structures are the same as those in the third embodiment, and reference may be made to the third embodiment above.

In addition, the methods for forming the solder 13 , the metal pillar 16 , the conductive base 27 , the protrusion 24 and the protective layer 28 include but are not limited to the methods provided in the first embodiment, the second embodiment and the third embodiment. Taking the formation of the metal pillars 16 as an example, for example, a metal thin film may be formed first, and then the metal thin film may be etched to form the metal pillars 16 .

It should be noted that the first, second and third embodiments above all take the first integrated circuit device 300 as the first chip 10 and the second integrated circuit device 400 as the second chip 20 as an example. The method for fabricating the stacked structure 02 and the integrated circuit stacked structure 02 will be described. In the case where the first integrated circuit device 300 and the second integrated circuit device 400 have other structures, for example, one of the first integrated circuit device 300 and the second integrated circuit device 400 is the first chip 10, and the other is the packaging substrate 4, For another example, one of the first integrated circuit device 300 and the second integrated circuit device 400 is a packaging substrate 4, and the other is a PCB. For the fabrication method of the integrated circuit stack structure 02 and the integrated circuit stack structure 02, reference may be made to the above-mentioned first embodiment. Example 2 and Example 3 will not be repeated here.

In another aspect of the present application, there is also provided a non-transitory computer-readable storage medium for use with a computer, the computer has software for creating and making the above-mentioned integrated circuit stack structure, and the computer-readable storage medium stores the One or more computer readable data structures having control data, such as photomask data, for fabricating the integrated circuit stack structure provided in any one of the illustrations provided above.

The above is only a specific implementation of the application, but the scope of protection of the application is not limited thereto. Anyone familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the application. Should be covered within the protection scope of this application. Therefore, the protection scope of the present application should be determined by the protection scope of the claims.

Claims

A method for manufacturing an integrated circuit stack structure, characterized in that it includes:

forming solder on the first conductive layer exposed on the surface of the first integrated circuit device;

forming bumps on the second conductive layer exposed on the surface of the second integrated circuit device;

heating the solder and the bumps to couple the first integrated circuit device and the second integrated circuit device; wherein the bumps are inserted into the solder.
The manufacturing method according to claim 1, wherein the heating of the solder and the bump comprises:

contacting the solder to the bump;

The solder and the bump are heated, and the solder melts to wrap around at least a portion of the bump.
The manufacturing method according to claim 1 or 2, characterized in that, after the forming of the bump on the second conductive layer exposed on the surface of the second integrated circuit device, before the heating of the solder and the bump , the preparation method also includes:

moving the first integrated circuit device formed with the solder over the second integrated circuit device formed with the bump so that the solder is positioned over the bump.
The manufacturing method according to claim 1, characterized in that, the shape of the protrusion is a cone, a column or a table.
The manufacturing method according to any one of claims 1-4, wherein the first integrated circuit device comprises a first passivation layer disposed on the first conductive layer; wherein the first passivation layer The layer includes a first opening, at least part of the first conductive layer is located in the first opening;

and / or,

The second integrated circuit device includes a second passivation layer disposed on the second conductive layer; wherein the second passivation layer includes a second opening, at least part of the second conductive layer is located in the Describe the second opening.
The manufacturing method according to claim 5, wherein the distance from the upper surface of the second passivation layer to the upper surface of the second conductive layer is greater than or equal to the height of the protrusion and the height of the protrusion The sum of the distances from the lower surface of the second conductive layer to the upper surface of the second conductive layer.
The manufacturing method according to any one of claims 1-6, characterized in that, before forming the bumps on the second conductive layer exposed on the surface of the second integrated circuit device, the manufacturing method further comprises:

forming a conductive pedestal on the second conductive layer exposed on the surface of the second integrated circuit device;

Wherein, the wettability of the conductive base is worse than that of the protrusion, and the projection of the protrusion on the conductive base is located within the boundary of the conductive base.
The manufacturing method according to claim 7, wherein the material of the conductive base includes an inert metal.
The manufacturing method according to any one of claims 1-8, characterized in that, after the bumps are formed on the second conductive layer exposed on the surface of the second integrated circuit device, the heating of the solder and the Before coupling the first integrated circuit device and the second integrated circuit device together, the manufacturing method further includes:

A protective layer is formed on the protrusion; the protective layer covers at least part of the surface of the protrusion.
The manufacturing method according to claim 9, characterized in that, the material of the protective layer includes an inert metal.
The manufacturing method according to any one of claims 1-10, characterized in that, before the solder is formed on the first conductive layer exposed to the surface of the first integrated circuit device, the manufacturing method further comprises:

A metal post is formed on the first conductive layer exposed on the surface of the first integrated circuit device; the metal post is electrically connected to the solder.
The manufacturing method according to any one of claims 1-11, wherein the heating of the solder and the bump couples the first integrated circuit device and the second integrated circuit device After together, described preparation method also comprises:

A buffer material is filled between the first integrated circuit device and the second integrated circuit device.
The manufacturing method according to any one of claims 1-12, wherein the first integrated circuit device is a first chip, and the second integrated circuit device is a second chip;

Alternatively, one of the first integrated circuit device and the second integrated circuit device is a first chip, and the other is a packaging substrate;

Alternatively, one of the first integrated circuit device and the second integrated circuit device is a packaging substrate, and the other is a printed circuit board.
An integrated circuit stack structure, characterized in that it comprises:

a first integrated circuit device including a first conductive portion exposed on a surface of the first integrated circuit device;

a second integrated circuit device including a second conductive portion exposed on a surface of the second integrated circuit device;

Solder balls are disposed between the first integrated circuit device and the second integrated circuit device, the solder balls are respectively in contact with the first conductive part and the second conductive part, and the inside of the solder balls is distributed throughout Conductive intermetallic compounds.
The stacked integrated circuit structure according to claim 14, wherein the first conductive part comprises a first conductive layer and a metal column disposed on a side of the first conductive layer close to the second integrated circuit device.
The integrated circuit stack structure according to claim 14 or 15, wherein the second conductive part comprises a second conductive layer and a conductive layer disposed on the side of the second conductive layer close to the first integrated circuit device. base.
The integrated circuit stack structure according to claim 16, wherein the material of the conductive base comprises an inert metal.
The integrated circuit stack structure according to any one of claims 14-17, further comprising a protective layer disposed inside the solder balls.
The integrated circuit stack structure according to claim 18, wherein the material of the protection layer comprises inert metal.
The integrated circuit stack structure according to any one of claims 14-19, characterized in that the integrated circuit stack structure further comprises: filling between the first integrated circuit device and the second integrated circuit device cushioning material.
The integrated circuit stack structure according to any one of claims 14-20, wherein the first integrated circuit device further comprises: a first passivation layer; the first passivation layer includes a first opening, at least part of the first conductive portion is located in the first opening;

and / or,

The second integrated circuit device further includes: a second passivation layer disposed on a side of the second conductive portion close to the first integrated circuit device; the second passivation layer includes a second opening, the At least part of the second conductive layer is located at the second opening.
The integrated circuit stack structure according to any one of claims 14-21, wherein the first integrated circuit device is a first chip, and the second integrated circuit device is a second chip;

Alternatively, one of the first integrated circuit device and the second integrated circuit device is a first chip, and the other is a packaging substrate;

Alternatively, one of the first integrated circuit device and the second integrated circuit device is a packaging substrate, and the other is a printed circuit board.
An electronic device, characterized by comprising a casing and the integrated circuit stack structure according to any one of claims 14-22.