KR20030041735A - Fabrication and assembly method of image sensor using by flip chip packaging process - Google Patents

Abstract

PURPOSE: A package for CMOS image sensor chip and a fabricating method thereof are provided to reduce a size of the package and a size of a final module by using a flip-chip solder bumping method. CONSTITUTION: A CMOS image sensor chip(110) includes plural exposed electrode pads separated by an insulating layer. A multi-layered lower metal layer is formed on the plural electrode pads. A solder bump(190) is adhered on the multi-layered lower metal layer. An image sensor assembly(270) is formed by mounting a package of the CMOS image sensor chip including the solder bump on a printed circuit board(200) having a plurality of substrate electrode pads. A sealing resin agent(240) is used for sealing the solder bump and a glass plate of an opening portion.

Description

Semiconductor imaging device package and its manufacturing method {Fabrication and assembly method of image sensor using by flip chip packaging process}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image sensor package for a semiconductor imaging device, and more particularly, to a semiconductor imaging device package using flip chip solder bumping and a method of manufacturing the same.

In general, an image sensor chip is also referred to as a solid-state image pickup device, and refers to a device for photographing a subject using an photoelectric conversion device and a charge coupling device to output an electrical signal.

In order to mount such an image sensor chip on a substrate, a packaging operation for mounting the chip in a package body is performed.

1A to 1C, the image sensor module of the conventional semiconductor imaging device 1 includes a lens holder 10, a lens unit 9 attached to the lens holder, and a lower end of the lens holder, as shown in FIG. 1C. An image sensor package 3 or the like.

The dual image sensor package 3 is made of a plastic or ceramic package connected to the lead 7 on the ceramic substrate 6 as shown in FIG. 1B, and the semiconductor imaging device 1 is formed inside the package. It has an image sensor chip, which is electrically connected to the ceramic substrate 6 through gold wire 4 bonding, and the glass plate 5 is bonded with an adhesive 8 to protect it from the external environment.

As described above, the size of the semiconductor imaging device image sensor module is determined by how much the size of the lower camera portion is reduced since the semiconductor imaging device 1 depends entirely on the size and area of the package on which the semiconductor imaging device 1 is mounted.

Therefore, the existing gold wire (4) bonding and plastic molding or a ceramic process package applied to the existing product has the disadvantage that the package size is increased by the gold wire bonding, and also because the manufacturing process time is long, It has a disadvantage that cannot actively respond to the trend of miniaturization of product size.

Accordingly, the present invention provides a new type of package and assembly process that can satisfactorily meet the miniaturization requirements of the lens unit which occupies a large area according to the recent trend of miniaturization of peripheral components for mobile communication devices or PCs. I want to achieve.

The present invention has introduced two important concepts to solve the above problems.

That is, in the present invention, an important issue of the size reduction of the semiconductor image sensor image sensor module is flip chip solder bumping, in which an integrated solder is formed on an electrode pad instead of a conventional gold wire bonding method to reduce the package size. It is to provide the package used.

Another technical problem to be achieved by the present invention is to provide a flip chip assembly process that can prevent surface contamination of the semiconductor imaging device due to flux evaporation that may occur during the reflow process after solder bumping.

Another feature of the present invention is to provide an image sensor module having a novel structure in which the semiconductor imaging device flip chip package manufactured by the above process is applied.

1A to 1C schematically illustrate a semiconductor imaging device and an image sensor module having a plurality of electrode pads according to the prior art.

Figure 2a to 2g shows a preferred embodiment of the present invention, a process diagram showing a process for forming a solder bump in the image pickup device according to the present invention

3A to 3E are flowcharts illustrating a structure of a circuit board for a semiconductor imaging device flip chip package manufactured by the present invention and a process of mounting a package on the circuit board.

4 is a cross-sectional view of a semiconductor imaging device module manufactured according to the present invention.

5 is a schematic explanatory diagram showing a state in which a semiconductor imaging device package manufactured according to the present invention is mounted on a product;

FIG. 6 conceptually compares a size reduction effect of a semiconductor imaging device package manufactured by the present invention with a conventional image sensor package with the same device size; FIG.

Explanation of symbols on the main parts of the drawings

1 semiconductor imaging device 2 electrode pad

3: image sensor package 4: gold wire

5: glass plate 6: ceramic substrate

7: lead 8: adhesive

9: lens unit 10: lens holder

11: module board

100: lower metal layer 110: semiconductor imaging device

120: insulating layer 130: metal adhesive layer

140: intermediate diffusion barrier layer 150: solder bonding layer

160: electrode pad 180: photosensitive material for the plating process

185: photosensitive material for etching 190: solder bump

200: circuit board 210: substrate electrode pad

220: opening 235: insulating layer for the substrate

240: sealing resin 245: glass plate

250: circuit board guide bar 260: module cutting hole

270: image sensor assembly 280: stencil mask

290: Stencil Mask Hole 300: Solder Ball

320: ultrasonic transducer 330: lens unit

340: lens holder 350: module substrate

Embodiment of the semiconductor imaging device 110 image sensor module for achieving the object of the present invention as described above,

A semiconductor imaging device 110 having a plurality of electrode pads 160 separated by an insulating layer 120;

Sequentially forming a metal adhesive layer 130, an intermediate diffusion barrier layer 140, and a solder bonding layer 150 on the exposed electrode pad 160 and the insulating layer 120;

The etching photosensitive material 185 is applied on the solder bonding layer 150 and then exposed and developed to pattern the etching photosensitive material 185 to selectively remain only on the electrode pad 160. and;

Etching the solder bonding layer 150 by applying the remaining etching photosensitive material 185 as a mask;

After removing the residual photosensitive material 185 for etching, the photosensitive material 180 for the plating process is coated on the lower metal layer 100 including the etched solder bonding layer 150, and then exposed and developed. Patterning so that only the etched solder bonding layer (150) region is selectively exposed;

Forming a solder bump (190) by plating a solder on the exposed solder bonding layer (150);

The plated solder bump 190 is fused with the solder bonding layer 150 to form a spherical solder bump 190, and then the solder bump 190 is applied as a mask to the intermediate diffusion barrier layer 140 and the metal. It characterized in that it comprises a step of etching the adhesive layer (130).

In addition, lower metal layers 100 formed on an upper portion of the electrode pad 160 and on a peripheral insulating layer 120 thereof;

The lower metal layers 100 are sequentially formed of an electrode adhesive layer 160, a metal adhesive layer 130, an intermediate diffusion barrier layer 140, and a solder bonding layer 150;

Forming a semiconductor imaging device 110 by fusing a plated solder bump 190 on the solder bonding layer 150;

Fusing the semiconductor imaging device 110 on which the solder bumps 190 are formed to the circuit board 200 on which the substrate electrode pads 210 are formed;

It characterized in that the module is manufactured by applying a sealing resin material 240 around the fused solder bump 190.

The objects and advantages of the preferred embodiments of the present invention will be described below with reference to the accompanying drawings.

2 illustrates a step-by-step process of applying solder bumps to the semiconductor imaging device 110 according to the present invention.

First, referring to FIG. 2A, an insulating layer 120 is formed on a surface of the semiconductor imaging device 110, and then selectively etched to expose a plurality of electrode pads 160 spaced apart from each other. The metal adhesive layer 130, the intermediate diffusion barrier layer 140, and the solder bonding layer 150 are sequentially formed on the substrate.

In this case, the metal adhesive layer 130 may be any one of Ti, Al, or Cr selected from the insulating layer 120 and the electrode pad 160 of the semiconductor imaging device 110 or alloys containing them. The intermediate diffusion barrier layer 140 may be Ni, an alloy thereof, or a Cr-Cu alloy, for the purpose of preventing the solder from reacting with the solder bonding layer 150 at a high temperature to directly contact the metal adhesive layer 130. The solder bonding layer 150 may be Ni, an alloy thereof, Cu, an alloy thereof, or the like as a metal in which the molten solder is well spread and may have excellent adhesion.

In particular, in the present invention, Al or an alloy thereof is used as the metal adhesive layer 130 for the purpose of preventing the surface of the semiconductor imaging device 110 from contamination that may occur during the bumping process and for imparting metallic continuity of the electrode pad of the semiconductor device. , The intermediate diffusion barrier layer 140 is characterized in that composed of TiW or Ti, Ti alloys.

The metal adhesive layer 130 may be formed of any one selected from an Al material, an Al-based alloy material, a Ti material, a Ti-based alloy material, a Cr material, or a Cr alloy material having a thickness of 100 to 5000 kPa.

The intermediate diffusion barrier layer 140 may also be formed of any one selected from a 100-5000 mm thick TiW material and a Ti-based alloy material.

The solder bonding layer 150 may be formed of any one selected from a NiV material, a Ni-based alloy material, a Cu material, a Cu alloy, or an Au material having a thickness of 100 to 5000 kPa.

In addition, the solder bonding layer 150 may be formed by electro- or electroless plating in a limited region using a photosensitive material, and when a plating (electro or electroless) method is applied, a NiV material of 0.1 to 5 um and an Ni-based alloy It is preferable to form one selected from a material, a Cu material, and a Cu alloy material.

In addition, as a process for forming the solder bumps 190 only on the electrode pad 160 or a specific region, as shown in FIG. 2B, an etching photosensitive material 185 is coated on the solder bonding layer 150. Next, after exposure and development, as shown in FIG. 2C, the photosensitive material for etching is selectively patterned so as to remain only on the upper portion of the electrode pad 160, and then applied as a mask to chemically etch the solder bonding layer 150. do.

Therefore, in the region where the solder bonding layer 150 is etched, the intermediate diffusion barrier layer 140 made of TiW, Ti-based alloy, or W-based alloy becomes the uppermost layer.

2D, a photosensitive material 180 for a plating process is coated on the lower metal layer 100 including the solder bonding layer 150 etched as shown in FIG. 2D, and then exposed and developed to expose the etched solder. Only the bonding layer 150 region is patterned to be selectively exposed.

In addition, although not shown in the drawings, the solder bonding layer 150 may be formed by other methods, such that the photosensitive material 180 for the solder plating process may be formed after successively stacking the metal adhesive layer 130 and the intermediate diffusion barrier layer 140. Ni can be formed by electroplating or electroless plating while the area to be plated by solder is opened by application, exposure and development, and the thickness is 0.1 to 5 um.

As shown in FIG. 2E, solder is plated on the exposed solder bonding layer 150 to form solder bumps 190.

As shown in FIG. 2F, when the patterned plating photosensitive material 180 is removed, the uppermost layer of the region where the solder bump 190 is not formed is made of TiW, Ti-based alloy, or W-based alloy. The intermediate diffusion barrier layer 140 has a characteristic of preventing the solder bumps 190 from spreading when the solder bumps are melted.

Therefore, even when the solder bumps 190 are melted as shown in FIG. 2F, the solder bumps do not spread to the intermediate diffusion barrier layer 140 of the TiW material, the Ti-based alloy material, or the W-based alloy material, and the solder bonding layer 150. ) Will be spherical only on the top.

That is, the intermediate diffusion barrier layer 140 of the TiW material, the Ti-based alloy material or the W-based alloy material according to the present invention not only functions as a solder dam, but also is continuously stacked with the metal adhesive layer 130 at the same time. Mechanical stability and thermal stability of the 160 and the convenience of the solder bump 190 process can be provided.

For this reason, in general, the TiW material is applied to the intermediate diffusion barrier layer 140 of Al component at a high temperature of several hundred degrees Celsius or more in the wiring process of the semiconductor imaging device 110, and does not react with solder material such as Sn or Pb at the same time. In addition, since the molten solder is not wet, it is possible to simultaneously perform the role of thermal diffusion prevention and solder dam (the solder is not wet to limit the area of the molten solder).

Lastly, as shown in FIG. 2G, the solder bump 190 is applied as a mask to chemically etch the intermediate diffusion barrier layer 140 and the metal adhesive layer 130, thereby solder bumps according to an exemplary embodiment of the present invention. A semiconductor imaging device 110 having a 190 formed thereon is manufactured.

The semiconductor imaging device wafer of the present invention manufactured by the above processes is selected from only the devices of good products from the electrical test results and placed in a tray of a certain standard.

The semiconductor image pickup device package contained in the tray processes fluorine plasma on the solder bumps 190 to prevent contamination of the surface of the device 110 due to the flux during the assembly process.

Details of the fluorine plasma treatment method are described in US Pat. No. 5,625,815. That is, by exposing the solder bumps 190 to the fluorine plasma, the metal oxide on the surface of the solder ball 500 is simply changed to fluorine oxide.

Fluoride oxide can decompose when reflowed in an inert atmosphere below a certain oxygen partial pressure within a certain time, and has the property that the solder can be melted without flux.

Therefore, if the processed package is placed in a predetermined position with a flip chip bonder equipment and then reflowed under an inert gas (nitrogen or argon) under a certain oxygen partial pressure (20 ppm) or less, the flux is not applied to the circuit board 200. Fusion is possible.

The next process is to assemble a package manufactured by the above process, that is, a package of a semiconductor imaging device 110 in which a solder bump 190 is formed and its surface is fluorine-treated, which is illustrated in FIG. 3.

First, as shown in FIG. 3A, an example of a structural diagram of a circuit board 200 suitable for the present invention is shown.

The circuit board 200 has an opening 220 having a size equal to or larger than that of the image sensing region of the semiconductor imaging device 110 so that light can pass therethrough, and a substrate to which a solder bumped device is bonded is adjacent to an outer portion of the circuit board 200. The electrode pad 210 is present, and the outer side of the electrode pad 210 is a region in which a solder ball 300 to be described later will be mounted for use when the final assembly is mounted on the product circuit board 200. There is a substrate electrode pad 210 having the same size as that for the pad and having a different size. In this case, the substrate electrode pad 210 may be formed of a combination of Cu, Ni, and Au materials.

In addition, since the circuit board portion of the region where the semiconductor imaging device 110 is to be mounted has a step compared to the outside thereof, a protrusion is not generated or minimized even after the semiconductor imaging device package is mounted, so that the solder ball 300 is formed in a later process. It is configured to ensure ease of mounting and assembly process, the shape of which is shown in Figure 3b.

In addition, as shown in FIG. 3C, the circuit board 200 includes two or more package module units for mounting a package in a surface arrangement, and the unit module substrates are separated by module cutting holes 260. Only a part is connected to the circuit board guide bar 250 to facilitate the separation in the final process to facilitate productivity during the post process, such as mounting the solder ball (300).

The package manufactured by the above process is placed on the circuit board 200 at a predetermined position by flip chip bonder equipment, and then reflowed and fused in an inert gas (nitrogen or argon) under a partial oxygen partial pressure (20 ppm).

In addition, in order to improve the mechanical strength and reliability of the solder portion, the encapsulation resin material 240 is applied along the outer portion of the chip to fill and harden around the solder contact portion by capillary action.

The encapsulating resin material 240 is coated with the encapsulating resin material 240 before mounting the semiconductor imaging device 110 on which the solder bumps 190 are formed, and mounting the package on which the solder bumps 190 are formed. , The reflow and the hardening of the encapsulating resin material 240 may be simultaneously performed to shorten the process. The encapsulating resin material 240 prevents a gap between the package and the circuit board 200 and finally serves as a sealing.

Next, the glass plate 245 is adhered to the opening 220 of the opposite side on which the package is mounted for the final sealing of the module in which the image sensor assembly 270 is described later. For this purpose, the inside of the sealing area is sealed in an inert atmosphere by performing in an inert gas atmosphere.

Next, as shown in Figures 3c to 3e as a process for mounting the solder ball 300 to be used to mount the product to complete the final module.

At this time, the solder ball 300 used is characterized in that the flux is not used by using the fluorine plasma treatment described above, and the solder ball 300 which has been subjected to the fluorine plasma treatment in advance is used.

As shown in FIG. 3D, a plurality of solder balls are mounted on the module by arranging the stencil masks 280 in which the plurality of stencil mask holes 290 are drilled in the same position as the place where the solder balls 300 are to be placed and mounted on the module. Seat 300.

At this time, the size of the stencil mask hole 290 should be more than 110% of the diameter of the solder ball 300, the thickness of the stencil mask 280 should be less than 80% of the diameter of the solder ball (300).

3E shows that each of the solder balls 300 is pressed using the ultrasonic transducer 320 so that the solder balls 300 are not separated from the substrate electrode pad 210. When the solder balls 300 are reflowed, the solder balls 300 are solder balls. 300 is formed to complete the manufacturing process of the image sensor assembly 270 module according to the present invention, which is shown in FIG.

As another example, the mounting process can be shortened by not reflowing the solder ball 300 mounted on the surface of the fluorine in the above process and reflowing without directly fluxing the product after mounting on the product.

Another solder ball mounting method may employ a general process, such that flux is applied using a mask similar to the stencil mask 280 of FIG. 3C, and then the solder ball 300 again using a stencil mask 280 or equipment. Mounting and reflowing can also be used to form the final solder ball 300.

As described above, the semiconductor image pickup device package and the assembly method thereof according to the present invention have been described with reference to the illustrated drawings. However, the present invention is not limited thereto by the embodiments and drawings disclosed herein, but the scope of the present invention is within the scope of the present invention. Of course, various modifications can be made by those skilled in the art.

As described above, the image sensor assembly 270 manufactured by the semiconductor imaging device package and the manufacturing method thereof according to the present invention is an image sensor package 3 manufactured using a conventional gold wire bonding method as shown in FIG. 6. ), It minimizes the size of the package and ultimately significantly reduces the size of the final module.

In addition, according to the present invention, since the semiconductor image sensor package 110 is manufactured in a batch process, the production cost may be reduced.

In addition, the intermediate diffusion barrier layer 140 of the metal used as the lower metal layer 100 of the solder bump 190 used in the flip chip package process of the present invention is TiW or Ti-based alloy material or W Since the intermediate diffusion barrier layer 140 serves as a solder dam (the role of limiting the area of the molten solder because the solder is not wet), the intermediate diffusion barrier layer 140 is not etched before solder reflow, so that the surface of the semiconductor imaging device 110 is formed. Can be prevented from contamination by solder reflow.

Meanwhile, when the semiconductor imaging device 110 package in which the solder bumps 190 are formed is reflowed using fluorine plasma treatment on the solder surface when the semiconductor imaging device 110 package is mounted on the circuit board 200, contamination due to no flux is prevented. There are many special advantages, such as being able to.

Claims (10)

In the semiconductor imaging device 110 in which a plurality of electrode pads 160 spaced apart from the insulating layer 120 are exposed, A lower metal layer 100 formed in multiple layers on the electrode pads 160; A solder bump 190 fused to the lower metal layer 100; The image sensor assembly 270 in which the package of the semiconductor imaging device 110 having the solder bumps 190 formed thereon is fused to a circuit board 200 having a plurality of substrate electrode pads 210 separated by a substrate insulating layer 235. )Wow; A semiconductor imaging device package comprising a structure in which a circumference of solder bumps 190 of a fused package is protected and sealed with an encapsulating resin material 240 and sealed with an opposite opening glass plate 245. In the semiconductor imaging device 110 having a plurality of electrode pads 160, Exposing the electrode pads 160 by being spaced apart from the insulating layer 120; Forming a metal adhesive layer (130), an intermediate diffusion barrier layer (140), and a solder bonding layer (150) on top of the exposed electrode pad (160) and the insulating layer (120); Applying a photosensitive material (185) for etching on the solder bonding layer (150), and then exposing and developing the photosensitive material so that the photosensitive material remains selectively only on the electrode pad (160); Etching the solder bonding layer 150 by applying the remaining photosensitive material 185 as a mask; Removing the remaining photosensitive material (185); After coating the photosensitive material 180 for the plating process on the solder bonding layer 150, only the solder bonding layer 150 remaining after etching among the lower metal layers 100 on the electrode pad is exposed and developed. Patterning such that it is selectively exposed; Plating a solder on the exposed solder bonding layer (150); Removing the patterned plating photosensitive material 180 and then fusion welding the plated solder with the solder bonding layer 150 to form solder bumps 190; Etching the remaining lower metal layer 100 by applying the fused solder bumps 190 as a mask; Performing a fluorine treatment on the manufactured spherical solder bumps 190; Mounting and fusion of the completed package on the circuit board 200; Applying a sealing resin material 240 to the solder contact portion and sealing the glass plate 245 in the opposite opening; And Method for manufacturing a semiconductor imaging device package comprising the step of mounting a solder ball (300), in order to connect with the final product in the manufactured assembly. The method of claim 2, The metal adhesive layer 130 is a semiconductor imaging device package manufacturing method, characterized in that formed of any one selected from Al, Al-based alloy material, Ti material, Ti-based alloy material, Cr material or Cr alloy material having a thickness of 100 ~ 5000Å. The method of claim 2, The intermediate diffusion barrier layer 140 is a semiconductor imaging device package manufacturing method, characterized in that formed of any one selected from 100 to 5000 Å thick TiW material, Ti-based alloy material. The method according to claim 2 or 4, The intermediate diffusion barrier layer 140 is inserted between the metal adhesive layer 130 and the solder bonding layer 150 to prevent the mutual diffusion reaction between the metal adhesive layer 130 and the solder bonding layer 150 at a high temperature of 100 ° C. or higher. In addition, the semiconductor imaging device package manufacturing method characterized in that the molten solder is formed of an alloy material containing TiW or Ti so as not to get wet. The method of claim 2, The solder bonding layer 150 is a semiconductor imaging device package manufacturing method, characterized in that formed of any one selected from 100 to 5000V thick NiV material, Ni-based alloy material, Cu material, Cu alloy, Au material. The method of claim 2, In forming the solder bonding layer 150, after coating the photosensitive material 180 for the plating process on the intermediate diffusion barrier layer 140 and opening the area to be soldered, Ni to a thickness of 0.1 ~ 5um Method for manufacturing a semiconductor imaging device package, characterized in that the electroless or electroless plating The method of claim 2, An opening 220 having a size greater than or equal to an image sensing region of the semiconductor imaging device 110 is formed on the circuit board 200 on which the semiconductor imaging device 110 on which the solder bumps 190 are formed is to be mounted. The semiconductor imaging device package manufacturing method characterized in that it has a plurality of substrate electrode pads (210) on which the solder bumps (190) of the semiconductor imaging device (110) are placed. The method of claim 2, The circuit board 200 has a step where the area in which the package of the semiconductor imaging device 110 on which the solder bumps 190 are formed is mounted has a step so that the height after the package is mounted is equal to or lower than the height of the circuit board 200. Semiconductor imaging device package manufacturing method. The method of claim 2, Before or after reflowing the solder bumps 190 formed by the plating, the surface of the solder is treated with fluorine plasma to mount on the circuit board 200 without using flux to prevent contamination of the semiconductor imaging device 110. A semiconductor imaging device package manufacturing method.