KR20160026445A - Method and apparatus for refreshing memory - Google Patents

Method and apparatus for refreshing memory Download PDF

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Publication number
KR20160026445A
KR20160026445A KR1020140115368A KR20140115368A KR20160026445A KR 20160026445 A KR20160026445 A KR 20160026445A KR 1020140115368 A KR1020140115368 A KR 1020140115368A KR 20140115368 A KR20140115368 A KR 20140115368A KR 20160026445 A KR20160026445 A KR 20160026445A
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KR
South Korea
Prior art keywords
refresh
dram row
dram
period
read command
Prior art date
Application number
KR1020140115368A
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Korean (ko)
Inventor
정성우
공영호
Original Assignee
고려대학교 산학협력단
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 고려대학교 산학협력단 filed Critical 고려대학교 산학협력단
Priority to KR1020140115368A priority Critical patent/KR20160026445A/en
Publication of KR20160026445A publication Critical patent/KR20160026445A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)

Abstract

The present invention relates to a method and an apparatus for refreshing a memory using a refresh effect of a read command. The method for refreshing the memory according to an embodiment of the present invention comprises the steps of: separating a first DRAM row from a second DRAM row considering a measured data retention period and a refresh cycle to be set; transmitting a read command to the first DRAM row by a command transmission cycle shorter than the refresh cycle; and refreshing the second DRAM row by the refresh cycle.

Description

[0001] METHOD AND APPARATUS FOR REFRESHING MEMORY [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a refresh method and apparatus for a DRAM, and more particularly, to a method and apparatus for refreshing a memory using a refresh effect of a read command.

DRAM is a memory device that has been used for a long time as a main memory of a computer. Demand for DRAM memory capacity has also increased sharply with recent dramatic performance advances in processors. In DRAM, there is a feature that a refresh command must be periodically executed to maintain stored data. In the conventional DRAM chip, the refresh cycle is fixed to 64 ms, and the same refresh cycle is applied to all the DRAM rows. Korean Patent Publication No. 2001-0029624 discloses a related prior art.

However, since all DRAM rows do not have the same data retention time, using a conventional single refresh period is inefficient in terms of performance / energy. Especially, the energy due to the refreshment occupies the largest portion of the total energy consumption.

Moreover, as the capacity increases, the proportion of refresh energy in the total DRAM energy is increasing.

In order to reduce the energy consumption of the DRAM, it is necessary to study a technique for efficiently performing refreshing.

An object of the present invention is to provide a memory refresh method and apparatus capable of reducing energy consumption of a memory by utilizing a refresh effect of a read command of a memory.

According to an aspect of the present invention, there is provided a method of controlling a data transmission method, the method comprising: dividing a first data stream into a first data stream and a second data stream by considering a measured data retention time and a refresh period to be set; Transmitting a read command to the first DRAM row at a command transmission period shorter than the refresh period; And refreshing the second stream of DRAMs with the refresh period.

According to an embodiment of the present invention, a profiling unit divides a first stream into a first stream and a second stream by considering a measured data retention time and a refresh period to be set. A read command unit for transmitting a read command to the first DRAM row at a command transmission period shorter than the refresh period; A refresh unit for refreshing the second DRAM row in the refresh period; And a control unit for controlling the profiling unit, the read command unit, and the refresh unit.

The method and apparatus for refreshing a memory according to an embodiment of the present invention can reduce the number of refreshes much more than the existing refresh method by efficiently setting the refresh period in consideration of the data retention time of memory rows.

In addition, according to an embodiment of the present invention, energy consumption of the memory can be greatly reduced.

1 is a block diagram showing a memory refreshing apparatus according to an embodiment of the present invention.
2 is a diagram for explaining a memory refresh method according to an embodiment of the present invention.
3 is a flow diagram illustrating a method of refreshing memory associated with an embodiment of the present invention.
4 is a flow diagram illustrating a method for transmitting a read command in a method of refreshing memory associated with an embodiment of the present invention.
5 is a graph for comparing the performance of the memory refresh method and the conventional refresh method according to an embodiment of the present invention.
FIG. 6 is a graph for comparing energy consumption of a memory refresh method and an existing refresh method according to an embodiment of the present invention.

Hereinafter, a method and an apparatus for refreshing a memory according to an embodiment of the present invention will be described with reference to the drawings.

As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. In this specification, the terms "comprising ", or" comprising ", etc. should not be construed as necessarily including the various elements or steps described in the specification, Or may be further comprised of additional components or steps.

The refresh method associated with an embodiment of the present invention can be utilized not only for DRAM (DRAM) memory, but also for volatile memories that require embedded DRAM or refresh. In the following embodiments, a DRAM will be described as an example.

1 is a block diagram showing a memory refreshing apparatus according to an embodiment of the present invention.

The refresh device 100 may include a profiling unit 110, a buffer 120, a read instruction unit 130, a refresh unit 140, and a control unit 150.

The profiling unit 110 may profile the data retention time from the DRAM Rows of the DRAM banks. The profiling unit 110 can select the Weak Row considering the measured data retention time and a predetermined refresh period (e.g., a period longer than the existing 64 ms). For example, DRAM rows where data retention time is shorter than the refresh period (a period longer than the existing 64 ms) can be called Weak Row.

The buffer 120 may store the address of the Weak Row.

The read command unit 130 may transmit a read command to the Weak Row every command transmission period. The instruction transmission period is shorter than the refresh period. The Weak Row may be divided into a plurality of groups in consideration of data holding time.

The refresh unit 140 may refresh the DRAM rows that have not been sorted by Weak Row into the refresh period.

The control unit 150 may control the profiling unit 110, the buffer 120, the read command unit 130, and the refresh unit 140 as a whole.

FIG. 2 is a diagram for explaining a memory refresh method according to an embodiment of the present invention, and FIG. 3 is a flowchart illustrating a memory refresh method according to an embodiment of the present invention.

As shown in FIG. 2, the refresh device 100 may be a DRAM controller. The refresh device 100 may apply the refresh effect by profiling the data holding time from the DRAM Row of all the DRAM banks of the DRAM 200. [

First, the refresh device 100 may profile the data retention time from DRAM rows of DRAM banks (S310). The refresh device 100 can measure the data retention time of all DRAM Row's for data retention time profiling. The data retention time measurement may be performed by writing 1 to all the DRAM rows at the boot time and recording the time at which the data disappears without refreshing.

The refresh device 100 selects the DRAM row having a shorter data holding time than the refresh period to be set (for example, a period longer than the existing 64 ms) by Weak Row, and stores the corresponding Weak row address, (A necessary refresh cycle) for distinguishing the refresh cycle from the set refresh cycle and the refresh cycle set for convenience (S320).

If you set the refresh period to 192ms, DRAM rows with shorter data retention times than 192ms will be Weak Row. In the refresh device 100, the Weak Rows may be grouped into a plurality of groups per section and stored in the buffer 120 (S330). For example, the Weak Row may be divided into 64 ms, 128 ms, 192 ms, etc. in units of 64 ms. Therefore, the DRAM Row having the data retention time of 64 ms to 128 ms in the weak row can be grouped into the first group, and the DRAM Row having the data retention time of 128 ms to 192 ms in the weak row can be grouped into the second group.

The refresh device 100 may transmit a read command to the corresponding Weak Row at the required refresh cycle using the Weak Row address stored in the buffer 120 at step S340. Also, when the Weak Row is divided into a plurality of groups, the necessary refresh cycles are different for each group. For example, the required refresh period for the first group having a data retention time of 64 ms to 128 ms may be shorter than that of the second group having a data retention time of 128 ms to 192 ms. The required refresh period may be performed through counting of a refresh counter. A detailed description thereof will be given later with reference to FIG.

In the refresh device 100, the Weak Rows may be refreshed by the refresh effect of the Read command, and the refresh may be performed in the refresh cycles (e.g., 192 ms) set in the remaining Rows (S350).

4 is a flow diagram illustrating a method for transmitting a read command in a method of refreshing memory associated with an embodiment of the present invention.

First, the refresh device 100 may initialize a refresh counter corresponding to each Weak Row to transmit a read command (S410). If the Weak Row is divided into multiple groups, each group can have an initial value of a different Refresh Counter. For example, Weak Rows with a data retention time of 64 ms to 128 ms may have an initial value of 2 as a Refresh Counter when the initial value of the refresh counter is 1 and the data retention time is 128 ms to 192 ms.

After waiting for time t1 (for example, 64 ms), the refresh counter is decremented by one (S420, S430). That is, when t1 is 64 ms, the refresh counter is decremented by 1 every 64 ms.

When the value of the refresh counter is 0, the refresh device 100 can transmit a read command to the corresponding Weak Row (S440, S450). And immediately the Refresh Counter is initialized to its initial value. Weak Rows have the effect of being refreshed through the transfer of a read command, so that weak rows can hold data. In addition, the remaining DRAM rows other than the Weak row can be set to have a longer refresh period than that of the conventional DRAM row (64 ms), so that the number of refresh times can be greatly reduced and data can be maintained.

5 is a graph for comparing the performance of the memory refresh method and the conventional refresh method according to an embodiment of the present invention.

The graph shown is a result of comparing the refresh performance based on the existing refresh period (64 ms). When the existing refresh period (64 ms) is used, only the refresh operation is performed. When the other refresh periods (128 ms, 192 ms, 256 ms, 320 ms) are used, the result of using the refresh and the read command together.

As shown, several refresh periods can be simulated to obtain refresh cycles with optimal performance. In the graph shown, 256 ms is the optimum refresh period.

FIG. 6 is a graph for comparing energy consumption of a memory refresh method and an existing refresh method according to an embodiment of the present invention.

Dynamic and Leakage represent energy consumption that occurs regardless of refresh, and Refresh represents energy consumption by refresh. 6, it can be seen that the refresh energy consumption according to the embodiment of the present invention is reduced by an average of 49.2% as compared with the conventional method (using 64 ms as the refresh period).

As described above, the memory refresh method and apparatus according to an embodiment of the present invention effectively sets the refresh period in consideration of the data retention time of memory rows, thereby significantly reducing the number of refresh times compared to the conventional refresh method Can be reduced. In addition, according to an embodiment of the present invention, energy consumption of the memory can be greatly reduced.

The above-described refresh method may be implemented in the form of a program command that can be executed through various computer means and recorded in a computer-readable recording medium. At this time, the computer-readable recording medium may include program commands, data files, data structures, and the like, alone or in combination. On the other hand, the program instructions recorded on the recording medium may be those specially designed and configured for the present invention or may be available to those skilled in the art of computer software.

The computer-readable recording medium includes a magnetic recording medium such as a magnetic medium such as a hard disk, a floppy disk and a magnetic tape, an optical medium such as a CD-ROM and a DVD, a magnetic disk such as a floppy disk, A magneto-optical media, and a hardware device specifically configured to store and execute program instructions such as ROM, RAM, flash memory, and the like.

The recording medium may be a transmission medium such as a light or metal line, a wave guide, or the like including a carrier wave for transmitting a signal designating a program command, a data structure, and the like.

The program instructions also include machine language code, such as those generated by the compiler, as well as high-level language code that can be executed by a computer using an interpreter or the like. The hardware devices described above may be configured to operate as one or more software modules to perform the operations of the present invention, and vice versa.

The above-described memory refresh method and apparatus The configuration and method of the above-described embodiments are not limitedly applied, but the embodiments may be modified so that all or some of the embodiments are selectively combined .

100: refresh device
110: Profiling section
120: buffer
130:
140: Refresh section
150:
200: Dirham

Claims (10)

Dividing the data into a first DRAM row and a second DRAM row in consideration of a measured data holding time and a refresh period to be set;
Transmitting a read command to the first DRAM row at a command transmission period shorter than the refresh period; And
And refreshing the second DRAM row with the refresh period. 2. The method of claim 1, wherein dividing the first stream into a first stream and a second stream comprises:
Selecting a first DRAM row having a data holding time shorter than the refresh period by the first DRAM row. 3. The method of claim 2,
Wherein the first group of DRAMs is divided into a plurality of groups according to the measured data retention time and the first group having a shorter average data retention time is smaller than the second group having a relatively longer average data retention time, And the period is short. 3. The method of claim 2, wherein the step of transmitting the read command comprises:
Counting down an initial value set in consideration of a data holding time by a predetermined value at predetermined time intervals; And
And when the counted down value reaches a predetermined value, initializing the counted down value to the initial value at the same time as transmitting the read command. 3. The method of claim 2, wherein the refresh method of the memory
Further comprising the step of storing an address of the first DRAM row. A profiling unit which divides the first and second DRAM rows into a first DRAM row and a second DRAM row in consideration of a measured data holding time and a refresh period to be set;
A read command unit for transmitting a read command to the first DRAM row at a command transmission period shorter than the refresh period;
A refresh unit for refreshing the second DRAM row in the refresh period; And
And a control unit for controlling the profiling unit, the read instruction unit, and the refresh unit. 7. The apparatus of claim 6, wherein the profiling portion
Wherein the first DRAM row selects a DRAM row in which the data holding time is shorter than the refresh period. 8. The method of claim 7,
Wherein the first group of DRAMs is divided into a plurality of groups according to the measured data retention time and the first group having a shorter average data retention time is smaller than the second group having a relatively longer average data retention time, And the period is short. 8. The apparatus of claim 7, wherein the read command unit
The initial value set in consideration of the data holding time is counted down by a predetermined value at predetermined time intervals,
And when the counted value reaches a predetermined value, transmits the read command and initializes the counted-down value to the initial value. The memory device according to claim 2, wherein the refresh device
And a buffer for storing an address of the first DRAM row.
KR1020140115368A 2014-09-01 2014-09-01 Method and apparatus for refreshing memory KR20160026445A (en)

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