KR20160008944A - Light emitting diode having polyhedron having upper width narrower than lower width and method for fabricating the same - Google Patents

Abstract

Provided are a light emitting diode and a manufacturing method thereof. The light emitting diode comprises a substrate and a polyhedron which is arranged on the substrate and has an upper width narrower than a lower width. A first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer are successively arranged on the polyhedron. The first conductivity type semiconductor layer is electrically connected to a first electrode. The second conductivity type semiconductor layer is electrically connected to a second electrode.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting diode including a polyhedron having a narrower upper width than a lower width and a method of manufacturing the light emitting diode having a polyhedron having an upper width narrower than a lower width,

The present invention relates to a semiconductor device, and more particularly, to a photoelectric conversion element.

The photoelectric conversion element refers to an element that can convert light energy into electric energy or convert electric energy into light energy. The photoelectric conversion device includes a solar cell that converts solar energy into electrical energy, and a light emitting diode that converts electrical energy into optical energy.

There have been studies to use nanowires to improve the efficiency of such photoelectric conversion devices (JP Publication No. 2009-59740). However, it is known that the improvement of the efficiency of a photoelectric conversion device using a nanowire is not sufficient.

Accordingly, an object of the present invention is to provide a photoelectric conversion element with improved photoelectric conversion efficiency.

The technical objects of the present invention are not limited to the technical matters mentioned above, and other technical subjects not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a light emitting diode. The light emitting diode includes a substrate and a polyhedron disposed on the substrate and having a narrower top width than a bottom width. The first conductivity type semiconductor layer, the active layer, and the second conductivity type semiconductor layer are sequentially disposed on the polyhedron. The first electrode is electrically connected to the first conductive type semiconductor layer. And the second electrode is electrically connected to the second conductivity type semiconductor layer.

The first conductive semiconductor layer, the active layer, and the second conductive semiconductor layer may be compound semiconductor layers. The polyhedron may be a crystalline silicon polyhedron, and the first conductivity type semiconductor layer, the active layer, and the second conductivity type semiconductor layer may be epitaxial layers.

The polyhedron may have a sharp apex or corner at its top. The polyhedron may have a plurality of crystal faces. The angle formed by each crystal plane of the polyhedron with the surface of the substrate may be reduced toward the upper part.

In one embodiment, the polyhedron is a silicon polyhedron, and the polyhedron may have sharp apexes having four {111} faces and four {111} faces on top of the polyhedron. In this case, the first conductive semiconductor layer may be a GaN layer grown in the [0002] direction.

According to another aspect of the present invention, there is provided a light emitting diode. The light emitting diode includes a substrate and a polyhedron disposed on the substrate and having a plurality of crystal faces. The first conductivity type semiconductor layer, the active layer, and the second conductivity type semiconductor layer are sequentially disposed on the polyhedron. The first electrode is electrically connected to the first conductive type semiconductor layer. And the second electrode is electrically connected to the second conductivity type semiconductor layer.

The angle formed by each crystal plane of the polyhedron with the surface of the substrate may be reduced toward the upper part. The polyhedron may be a silicon polyhedron having crystallinity, and the first conductive semiconductor layer, the active layer, and the second conductive semiconductor layer may be compound semiconductor epitaxial layers.

According to another aspect of the present invention, there is provided a method of manufacturing a light emitting diode. First, a crystalline substrate is provided. The crystalline substrate is etched to form pillars. A base semiconductor layer is epitaxially grown on the pillars to form a crystalline polyhedron. A first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer are formed on the crystalline polyhedron. A first electrode electrically connected to the first conductive type semiconductor layer is formed. And a second electrode electrically connected to the second conductive semiconductor layer is formed.

Before growing the base semiconductor layer epitaxially, the pillar may be hydrogen annealed. The pillar may be etched using anisotropic etching. The pillar may be etched using the isotropic etching method and then the isotropic etching method.

The substrate may be a silicon single crystal substrate. The base semiconductor layer may be a silicon layer. In this case, the substrate may be a substrate grown in a <100> direction, a <110> direction, or a <111> direction. In one embodiment, the substrate is a substrate grown in a <100> direction, and the first conductivity type semiconductor layer, the active layer, and the second conductivity type semiconductor layer may be grown epitaxially.

As described above, according to the present invention, a photoelectric conversion element to which a polyhedron having a narrower top width than a bottom width is applied can improve the photoelectric conversion efficiency due to the structural characteristics of the polyhedron.

FIGS. 1A, 2A, and 3A are perspective views illustrating a method of fabricating a crystalline polyhedron according to an exemplary embodiment of the present invention. Referring to FIG.
Figures 1B, 2B and 3B are cross-sectional views taken along the cutting lines II 'of Figures 1A, 2A, and 3A.
Figures 4A, 4B, and 4C are schematic diagrams illustrating crystalline polyhedrons in accordance with one embodiment of the present invention.
5 is a cross-sectional view illustrating a photoelectric conversion device according to an embodiment of the present invention.
6 is a cross-sectional view illustrating a photoelectric conversion device according to another embodiment of the present invention.
7A is a photograph of the crystalline polyhedrons obtained during the production process according to Production Example 1.
FIG. 7B is a SEM photograph (a, c) and a TEM photograph of the crystalline polyhedrons according to Production Example 1 of the crystalline polyhedron. FIG.
8A, 8B and 8C are SEM photographs of the crystalline polyhedrons according to Production Examples 1 to 3, respectively.
9 is a graph showing the light absorption efficiency of a crystalline polyhedron, a cylindrical silicon pillar, a rectangular parallelepiped silicon wall, and a planar silicon substrate according to Production Example 1 of the crystalline polyhedron.
10 is a graph showing the light absorption efficiency of a crystalline polyhedron, a cylindrical silicon pillar, a rectangular parallelepiped silicon wall, and a planar silicon substrate according to Production Example 1 of the crystalline polyhedron.
11 is a graph showing the absorption rate of the crystalline polyhedrons according to Manufacturing Example 1 according to the angle of incidence of light.
12 is a graph showing the current density according to the voltage of the solar cell using the crystalline polyhedrons according to Production Example 1. FIG.
13 is a graph comparing light extraction efficiencies of light emitting diodes having various shapes.
14 is a graph comparing light extraction efficiencies of light emitting diodes having various shapes.
FIG. 15 is a graph (a) showing the light extraction efficiency according to the height variation of the n-type GaN layer of the planar light emitting diode and the crystalline polyhedron light emitting diode, (B) showing the degree of improvement in light extraction efficiency.
16A, 16B and 16C are SEM (Scanning Electron Microscope) photographs of the upper surface, the inclined upper surface, and the cross section of the specimen according to the nitride film growth example, respectively.
17 is an SEM photograph of the upper surface of the crystalline polyhedron before formation of the nitride film and an SEM photograph of the upper surface of the sample after growing the nitride film.
18 shows TEM (transmission electron microscope) photographs and FFT (Fourier transform) image analysis showing a cross section of the specimen in the first direction according to the nitride film growth example.
FIG. 19 shows a TEM photograph and an FFT image analysis showing a section of the specimen according to the nitride film growth example cut in the second direction.
20 shows a TEM photograph and a FFT image analysis showing a cross section of a specimen according to a comparative example of nitride film growth.
21A and 21B are cross-sectional views illustrating a photoelectric conversion element according to another embodiment of the present invention.
22 is a plan view schematically showing the upper surface of the unit cell U shown in Fig. 16B.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. In the drawings, where a layer is referred to as being "on" another layer or substrate, it may be formed directly on another layer or substrate, or a third layer may be interposed therebetween.

FIGS. 1A, 2A, and 3A are perspective views illustrating a method of fabricating a crystalline polyhedron according to an exemplary embodiment of the present invention. Referring to FIG. Figures 1B, 2B and 3B are cross-sectional views taken along the cutting lines I-I 'of Figures 1A, 2A, and 3A.

Referring to FIGS. 1A and 1B, a substrate S may be provided. The substrate S may be a crystalline substrate, specifically, a single crystal substrate, or a single crystal semiconductor substrate. As an example, the substrate S may be a silicon single crystal substrate.

The substrate S may be etched to form a plurality of pillars 10 regularly arranged. The substrate S may be etched by a photolithography method or a dry etching method. The dry etching may be reactive ion etching (RIE) capable of anisotropic etching. The height of the pillars 10 in the vertical direction is higher than the width of the pillars 10, that is, the aspect ratio may exceed one. As an example, the aspect ratio of the pillars 10 may be 1 to 30. [

Thereafter, the substrate on which the pillars 10 are formed may be further subjected to isotropic dry etching. In this case, the diameter of the pillars 10 can be reduced, and the side surface can have a slight inclined surface.

Referring to FIGS. 2A and 2B, the pillars 10 can be hydrogen annealed. At this time, hydrogen annealing may mean thermal annealing in a hydrogen atmosphere. The hydrogen anneal can be conducted at a pressure of about 10 to about 100 Torr, at a temperature of about 800 to about 1200 DEG C for about 1 to 30 minutes. More specifically, the hydrogen annealing can be conducted at a pressure of about 20 to 60 Torr, at a temperature of about 1000 to 1100 DEG C for about 1 to 10 minutes.

This hydrogen annealing may etch the edges of the pillars 10 so that the pillars 10 have rounded edges 10T. However, this hydrogen annealing process is not a necessary process, and this hydrogen annealing process may be omitted if the pillars 10 are formed thin enough to have a sufficiently narrow upper surface.

Referring to FIGS. 3A and 3B, the semiconductor layer may be epitaxially grown on the substrate including the pillars 10 to form the crystalline polyhedron 15. FIG. The crystalline polyhedron 15 is a structure surrounded by a plurality of different crystal facets and may have a narrower upper width than a lower width. Specifically, the angle formed by each side of the crystalline polyhedron 15 with the substrate surface may be reduced toward the upper side. The crystalline polyhedrons 15 may be formed because the growth rates of the crystalline polyhedrons 15 are different from each other in the epitaxial process.

The semiconductor layer may be the same material or different material as the pillars 10. In other words, the semiconductor layer may be grown homoepitaxially on the pillars 10, and the semiconductor layer may be grown heteroepitaxially on the pillars 10. In particular, the semiconductor layer and the pillars 10 may all be silicon. Alternatively, the semiconductor layer may be GaN, or AlN, and may be one of a semiconductor material consisting of element IV-group semiconductors and alloys thereof, and a compound semiconductor, and the pillars 10 may be silicon.

The semiconductor layer may be epitaxially grown and the semiconductor layer may be doped. As an example, the semiconductor layer may be doped p-type.

The epitaxial growth of the semiconductor layer and the formation of the crystalline polyhedron 15 can be performed by metal organic chemical vapor deposition (MOCVD), chemical vapor deposition (CVD), plasma chemical vapor deposition May be performed using various deposition or growth methods including plasma enhanced chemical vapor deposition (PECVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE) .

Figures 4A, 4B, and 4C are schematic diagrams illustrating crystalline polyhedrons in accordance with one embodiment of the present invention.

Referring to FIG. 4A, a crystalline polyhedron 15 is shown. The crystalline polyhedron 15 is formed by etching a silicon substrate S grown in a <100> direction to form a silicon pillar 10, optionally hydrogen-annealing the pillar 10, Can be obtained by homoepitaxially growing the silicon semiconductor layer on the silicon substrate 10.

The crystalline polyhedron 15 may have a narrower upper width than the lower width. Further, it may have a cone shape whose width gradually decreases from the lower part to the upper part. In other words, the angle formed by the facets of the crystalline polyhedron 15 with the substrate surface can be reduced toward the upper part. For example, the crystalline polyhedron 15 may have a first surface F3, a second surface F2, and a third surface F1 in a direction from the bottom to the top, May be reduced from the first surface F3 to the second surface F2 and from the second surface F2 to the third surface F1. As an example, the third surface F1 may be a {111} surface and the angle with the substrate surface may be about 55 degrees. In addition, the crystalline polyhedron 15 may have a sharp apex T at the top of which crystal faces, specifically, four third faces F1 meet.

Referring to FIG. 4B, a crystalline polyhedron 15 having a shape different from that shown in FIG. 4A is shown. The crystalline polyhedron 15 is formed by etching a silicon substrate S grown in a <110> direction to form a silicon pillar 10, optionally hydrogen-annealing the pillar 10, Can be obtained by homoepitaxially growing the silicon semiconductor layer on the silicon substrate 10.

The crystalline polyhedron 15 may have a narrower upper width than the lower width. Further, it may have a cone shape whose width gradually decreases from the lower part to the upper part. In other words, the angle formed by each crystal facet of the crystalline polyhedron 15 with the substrate surface can be reduced toward the upper part. As an example, the crystalline polyhedron 15 may have a first surface F6, a second surface F5, and a third surface F4 from the bottom to the top, May be reduced from the first surface F6 to the second surface F5 and from the second surface F5 to the third surface F4. As an example, the third surface F4 may be a {111} surface and an angle between the third surface F4 and the substrate surface may be about 35 degrees. Also, the second surface F5 may be a {113} surface and an angle between the second surface F5 and the substrate surface may be about 65 degrees. In addition, the crystalline polyhedron 15 may have a sharp edge T at the uppermost part, in which crystal faces, specifically, two third faces F4 are formed.

Referring to Fig. 4C, a crystalline polyhedron 15 having another form is shown. The crystalline polyhedron 15 is formed by etching a silicon substrate S grown in a <111> direction to form a silicon pillar 10, optionally hydrogen-annealing the pillar 10, Can be obtained by homoepitaxially growing the silicon semiconductor layer on the silicon substrate 10.

The crystalline polyhedron 15 may have a narrower upper width than the lower width. Further, it may have a cone shape whose width gradually decreases from the lower part to the upper part. In other words, the angle formed by the facets of the crystalline polyhedron 15 with the substrate surface can be reduced toward the upper part. For example, the crystalline polyhedron 15 may have a first surface F8 and a second surface F7 from the bottom to the top, and the angle formed by the respective surfaces with the substrate surface may be a first surface F8) to the second surface (F7). For example, the second surface F7 may be a {111} surface and an angle between the first surface F8 and the substrate surface may be about 71 degrees, the first surface F8 may be a {311} . In addition, the crystalline polyhedron 15 may have a very narrow surface area T on the uppermost surface, in particular three third faces F7.

4A, 4B, and 4C differs in that the crystallographic planes revealed on the surface of the etched and hydrogen annealed pillars are different and also due to the different growth rates of the crystal planes during the epitaxy process can do.

5 is a cross-sectional view illustrating a photoelectric conversion device according to an embodiment of the present invention.

Referring to Fig. 5, a solar cell which is one type of photoelectric conversion element is shown. The solar cell has the polyhedron 15 disposed on the substrate S. The polyhedron 15 may be formed using the method described with reference to Figs. 1A, 2A, and 3A, and may be any one of the polyhedrons 15 described with reference to Figs. 4A, 4B, have.

The polyhedron 15 may have a narrower upper width than a lower width. In addition, the polyhedron 15 may be a structure surrounded by a plurality of different crystal facets. Further, the angle formed between the crystal faces of the polyhedron 15 and the surface of the substrate may be reduced toward the upper part. In addition, the polyhedron 15 may have a sharp apex (T in FIG. 4A) or a sharp edge (T in FIG. 4B) at its top. In addition, the polyhedron 15 may be a silicon polyhedron having crystallinity.

The polyhedron 15 may be a semiconductor having a first conductivity type. The first conductivity type may be p-type. Alternatively, an additional first conductive semiconductor layer may be formed on the polyhedron 15. The first conductive semiconductor layer may be epitaxially grown and doped with a first conductive dopant.

The second conductivity type semiconductor layer 25 may be epitaxially grown on the polyhedron 15. In other words, the second conductive semiconductor layer 25 may be an epi layer, specifically a silicon epi layer. In this case as well, the second conductivity type semiconductor layer 25 can be grown and doped with the second conductivity type dopant. The second conductivity type may be n-type. Alternatively, the second conductivity type semiconductor layer 25 may be formed by implanting a second conductivity type dopant into the polyhedron 15 by ion implantation or the like. The second conductivity type semiconductor layer 25 may have a thickness of 10 nm to 1000 nm, specifically, a thickness of 40 nm to 100 nm.

The sum of the thickness of the second conductivity type semiconductor layer 25 or the thickness of the first conductivity type semiconductor layer and the thickness of the second conductivity type semiconductor layer 25 when the first conductivity type semiconductor layer is formed, 15). &Lt; / RTI &gt; As a result, after the second conductive semiconductor layer 25 is formed, the resultant shape may still be similar to that of the polyhedron 15.

A PN junction 20 may be formed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer 25 formed on the polyhedron 15 or on the polyhedron 15.

A light-transmitting electrode layer (not shown) may be further formed on the second conductive semiconductor layer 25, but the present invention is not limited thereto. The light-transmitting electrode layer may be a carbon nanotube layer, a graphene layer, a transparent conductive oxide layer, or a metal layer, and may be formed by coating, thermal evaporation, electron beam evaporation, or sputtering.

Thereafter, a first electrode 30 may be formed on the lower portion of the substrate S, and a second electrode 40 may be formed on the second-type semiconductor layer 25. However, the position of the first electrode 30 is not limited to this, and any position can be used as long as the first electrode 30 can be electrically connected to the polyhedron 15 or the first conductivity type semiconductor layer (not shown).

When the solar cell is irradiated with sun light, for example, the PN junction 20 absorbs a photon to generate an electron-hole pair, and the electron-hole pair is separated, The holes are transferred to the first electrode 30 to produce electricity. At this time, the polyhedron 15 protruding upward causes irregular reflection of the incident light, so that the reflectance of the light can be greatly reduced. In addition, the surface area of the PN junction 20 can be greatly improved, The shape of the narrow polyhedron 15 allows the light to be irradiated to the PN junction 20 located on the upper portion of the polyhedron 15 as well as the PN junction 20 located on the lower portion, . In addition, the shape of the polyhedron 15 having a narrow width toward the top may be such that when the angle formed by the light with respect to the substrate surface is reduced, for example, when it is obliquely irradiated with respect to the substrate surface as morning light or evening sunlight , The light can be vertically incident on the PN junction portion 20 on the lower portion, so that the photoelectric conversion efficiency may not be greatly affected by the incident angle of light.

In addition, since each side of the polyhedron 15 is a crystal plane and the first semiconductor layer or the second semiconductor layer 25 formed epitaxially on the crystal faces also has a low defect density and crystal quality can be improved, the PN junction ( Electron-hole pair generation and separation can be performed more efficiently.

6 is a cross-sectional view illustrating a photoelectric conversion device according to another embodiment of the present invention.

Referring to Fig. 6, there is shown a light emitting diode which is another kind of photoelectric conversion element. The light emitting diode has a polyhedron 55 disposed on the substrate S. The polyhedron 55 may be formed using the method described with reference to Figs. 1A, 2A, and 3A, and may be any one of the polyhedrons 15 described with reference to Figs. 4A, 4B, have.

The polyhedron 55 may have a narrower top width than a bottom width. In addition, the polyhedron 55 may be a structure surrounded by a plurality of different crystal facets. Further, the angle formed between the crystal faces of the polyhedron 55 and the surface of the substrate may be reduced toward the upper portion. In addition, the polyhedron 55 may have a sharp apex (T in FIG. 4A) or a sharp corner (T in FIG. 4B) at its top. In addition, the polyhedron 55 may be a silicon polyhedron having crystallinity.

An element layer can be formed on the polyhedron 55. The device layer may be a first conductive type semiconductor layer 61, an active layer 65, and a second conductive type semiconductor layer 67 which are sequentially stacked. The first conductivity type semiconductor layer 61, the active layer 65 and the second conductivity type semiconductor layer 67 may be formed by stacking compound semiconductor layers, specifically III-V compound semiconductor layers, Semiconductor layers can be formed. The III-V compound semiconductor layers may be GaAlAs-based, AlGaIn-based, AlGaInP-based, AlGaInPAs-based, or GaN-based semiconductor layers as an example.

The first conductive semiconductor layer 61 may be a nitride-based semiconductor layer doped with an n-type dopant. For example, the first conductive semiconductor layer 61 may include an n-type dopant such as In _x Al _y Ga _1-xy N (0? _X <1, 0? Y <Lt; RTI ID = 0.0 &gt; Si. &Lt; / RTI &gt; The active layer 65 may be a layer of In _x Al _y Ga _1-xy N (0? _X <1, 0? Y <1, 0? _X + y <1) and may have a single quantum well structure or a multi quantum well structure multi-quantum well (MQW). For example, the active layer 65 may have a single quantum well structure of an InGaN layer or an AlGaN layer, or a multiple quantum well structure of a multi-layer structure of InGaN / GaN, AlGaN / (In) GaN, or InAlGaN / . The second conductive semiconductor layer 67 may be a semiconductor layer doped with a p-type dopant. For example, the second conductivity type semiconductor layer 67 may have a p-type conductivity in the In _x Al _y Ga _1-xy N (0 x <1, 0 y <1, 0 x + y < It may be a layer doped with Mg or Zn as a fund.

When the surface of the polyhedron 55 and the first conductivity type semiconductor layer 61 have different lattice constants, the surface of the polyhedron 55 before forming the first conductivity type semiconductor layer 61 And a buffer layer (not shown) for relieving the lattice mismatch between the first conductive semiconductor layer 61 and the first conductive semiconductor layer 61. This buffer layer may be an AlN layer. However, the material of the buffer layer is not limited thereto.

The sum of the thicknesses of the first conductivity type semiconductor layer 61, the active layer 65 and the second conductivity type semiconductor layer 67 as well as their thicknesses is greater than the height of the polyhedron 55 Can be low. As a result, the shape of the resulting product after each of these layers is formed may be similar to that of the polyhedron 55.

The first conductive semiconductor layer 61, the active layer 65 and the second conductive semiconductor layer 67 may be epitaxially grown epitaxial layers. Specifically, the first conductive semiconductor layer 61, the active layer 65, Chemical vapor deposition (MOCVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy Hydride Vapor Phase Epitaxy (HVPE), and the like.

A light-transmitting electrode layer (not shown) may be further formed on the second conductive semiconductor layer 67, but the present invention is not limited thereto. The light-transmitting electrode layer may be a carbon nanotube layer, a graphene layer, a transparent conductive oxide layer, or a metal layer, and may be formed by coating, thermal evaporation, electron beam evaporation, or sputtering.

Thereafter, a first electrode 70 may be formed under the substrate S, and a second electrode 80 may be formed on the second conductive type semiconductor layer 67. However, the position of the first electrode 70 is not limited to this, and any position that can be electrically connected to the first conductivity type semiconductor layer 61 is possible.

When a forward electric field is applied to such a light emitting diode, electrons and holes are injected into the active layer 65, and electrons injected into the active layer 65 recombine with holes to emit light. At this time, the surface area of the active layer 65 can be greatly increased due to the polyhedrons 55 protruding upward, and the upper portion of the polyhedron 55 due to the shape of the polyhedron 55 having a narrower upper width than the lower width, The light emitted from the active layer 65 located on the lower portion as well as the light emitted from the active layer 65 located on the light emitting layer 65 can be extracted to the outside. The first conductivity type semiconductor layer 61, the active layer 65, and the second conductivity type semiconductor layer 67, which are epitaxially grown on the crystal faces, are formed on the crystal faces of the polyhedrons 55, Since the defect density is low and crystal quality can be improved, the photoelectric extraction efficiency can also be improved.

On the other hand, in the case where the upper width is narrower than the lower width of the polyhedron 55, the forward electric field can be concentrated on the upper portion of the polyhedron 55, It is possible to increase the amount of light emitted from the active layer 65 located in the light emitting layer. Thereby, the effect of concentrating the light on the front surface may be obtained.

In addition, it is expected that various colors of light can be realized by changing the voltage applied to the light emitting diode. This is because a variety of luminescent colors can be realized according to the applied electric field while varying the current path and the equipotentio plane according to the structural features of the polyhedron 55. This is difficult to implement in planar light emitting diodes.

Hereinafter, preferred examples will be given to facilitate understanding of the present invention. It should be understood, however, that the following examples are for the purpose of promoting understanding of the present invention and are not intended to limit the scope of the present invention.

&Lt; Preparation Example 1: Preparation of crystalline polyhedra &

The silicon substrate grown in the <100> direction was etched using reactive ion etching (RIE) to form silicon pillars. Then, the silicon pillars were subjected to isotropic dry etching again to form inclined surfaces on the side surfaces of the silicon pillars, and the substrate on which the silicon pillars were formed was hydrogen annealed at a temperature of 1050 DEG C and a pressure of 40 Torr for about 10 minutes to round the corners of the silicon pillars Change. Then, the edge is SiH ₂ Cl ₂ the substrates are formed of a round silicon pillar in a load in the epi-reactor (Epi-Reactor) and the chamber (dichlorosilane; DCS) 370sccm, HCl 110sccm, B 2 H 6 (diborane, 1% balanced in H2 ) Of 110 sccm and H _{2 20} slm, the deposition was carried out at a temperature of 1050 ° C and a pressure of 60 Torr for about 5 minutes to epitaxially grow the semiconductor layer on the silicon pillars.

&Lt; Preparation Example 2: Preparation of crystalline polyhedra &

A crystalline polyhedron was prepared in the same manner as in Production Example 1 except that a crystalline polyhedron was used using a silicon substrate grown in the <110> direction.

&Lt; Preparation Example 3: Preparation of crystalline polyhedra >

A crystalline polyhedron was prepared in the same manner as in Production Example 1, except that a crystalline polyhedron was used using a silicon substrate grown in the <111> direction.

7A is a photograph of the crystalline polyhedrons obtained during the production process according to Production Example 1.

Referring to FIG. 7A, after the isotropic dry etching is completed, it is confirmed that the silicon pillars a having an average width of about 1 μm and a height of about 15 μm are formed. After the hydrogen annealing, the edges of the silicon pillars are rounded (B) can be confirmed. Further, it can be seen that the crystalline polyhedron (c) is formed after the semiconductor layer is epitaxially grown on the silicon pillars. The lowermost width of the crystalline polyhedron (c) was 7 mu m on average and the average height was 11 mu m.

FIG. 7B is a SEM photograph (a, c) and a TEM photograph of the crystalline polyhedrons according to Production Example 1 of the crystalline polyhedron. FIG.

Referring to FIG. 7 (b), the crystalline polyhedrons were cut along the red frame of FIG. 7 (a) and subjected to TEM analysis. As a result, four crystal planes having <100> .

8A, 8B and 8C are SEM photographs of the crystalline polyhedrons according to Production Examples 1 to 3, respectively.

8A, 8B, and 8C, it can be seen that crystalline polyhedrons having different shapes are produced when the crystal growth direction of the silicon substrate is different.

9 is a graph showing the light absorption efficiency of a crystalline polyhedron, a cylindrical silicon pillar, a rectangular parallelepiped silicon wall, and a planar silicon substrate according to Production Example 1 of the crystalline polyhedron. At this time, the silicon pillars of the cylindrical shape had a width of 3.5 mu m and a height of 11 mu m, and the rectangular parallelepiped silicon walls had a width of 3.5 mu m and a height of 11 mu m, and the crystalline polyhedron formed according to Production Example 1 In the state assumed to have a height of 11 mu m, the light absorption efficiency was calculated by computer simulation. At this time, it was assumed that light of AM 1.5G was irradiated.

) 절대적으로는 약 33% 이상 크게 증가한 것을 알 수 있다. Referring to FIG. 9, a cylindrical silicon pillar (represented by Si microwire, absorbable surface area of 170 占 퐉 ² ) and a rectangular parallelepiped silicon wall (represented by Si microwall, absorbable surface area of 203 占 퐉 ² ) The total light absorption rate at the wavelength was about 67.6% and about 71.6%, respectively, which was higher than the light absorption rate (61.4%) of the flat silicon substrate (absorption surface area 49 μm ² ). This is presumably due to an increase in surface area. On the other hand, the crystalline polyhedron according to Production Example 1 (represented by Si microcone, absorbable surface area 152.1 mu m &lt; ² &gt;) had an overall light absorptivity of about 95% at a wavelength of 300 nm to 1100 nm, 1.5 times or more (

) And it is absolutely increased by about 33% or more.

The crystalline polyhedrons according to Preparation Example 1 (represented by Si microconsamples with an absorbable surface area of 152.1 탆 ² ) were obtained by using a cylindrical silicon pillar (represented by Si microwire, absorbable surface area 170 탆 ² ) and a rectangular silicon wafer The absorbed surface area was found to be 1.3 to 1.4 times higher than the absorbable surface area of 203 μm ² ). The reason for this is presumed to be that the crystalline polyhedrons produced in the present invention have a plurality of crystal planes and also have a graded refractive index superior in light scattering effect due to sharp shape and more complex than other structures.

10 is a graph showing the light absorption efficiency of a crystalline polyhedron, a cylindrical silicon pillar, a rectangular parallelepiped silicon wall, and a planar silicon substrate according to Production Example 1 of the crystalline polyhedron. At this time, the silicon pillars in the cylindrical form had a width of 3 mu m and a height of 11 mu m, and the rectangular parallelepiped silicon walls had a width of 3.5 mu m and a height of about 7.4 mu m, Lt; RTI ID = 0.0 &gt; 11 &lt; / RTI &gt; At this time, it was assumed that light of AM 1.5G was irradiated.

Referring to Figure 10, (shown as Si microwire, absorbent surface area can 152.7㎛ ²⁾ a cylindrical-shaped silicon pillar and the cuboid-type silicon month (shown as Si microwall, absorbent surface area can 152.6㎛ ²⁾ is at a wavelength of 300㎚ to 1100㎚ It can be seen that the total light absorption rate is about 66.7% and about 69.8%, respectively, which is higher than the light absorption rate of the flat silicon substrate 61.4%. However, the crystalline polyhedron according to Production Example 1 (represented by Si microcone, absorbable surface area of 152.1 탆 ² ) had a total light absorption rate of about 95% at a wavelength of 300 nm to 1100 nm and exhibited a cylindrical silicon pillar Surface area of 152.7 μm ² ) and a rectangular surface area (expressed as Si microwall, absorbable surface area 152.6 μm ² ). It was also presumed that the crystalline polyhedrons produced in the present invention have a refractive index with a high degree of light scattering due to a sharp shape with a plurality of crystal planes and a complicated difference from other structures.

11 is a graph showing the absorption rate of the crystalline polyhedrons according to Manufacturing Example 1 according to the angle of incidence of light.

11, the planar silicon substrate is a crystalline polyhedron according to Production Example 1 (represented by Si microcone) in which light absorption rate is greatly reduced as the incident angle increases, Absorbing rate. &Lt; / RTI &gt; This indicates that, in the case of a solar cell employing a crystalline polyhedron, even if the angle of the sun varies in the daytime, it can exhibit a constant light absorption rate even in the morning or evening time.

12 is a graph showing the current density according to the voltage of the solar cell using the crystalline polyhedrons according to Production Example 1. FIG. The solar cell had a structure in which an n-type semiconductor layer was formed to a thickness of about 100 nm on a crystalline polyhedron having a p-type according to Production Example 1, a first electrode was formed under the substrate, Electrodes were formed, and the current density according to the voltage was obtained through experiments.

12, the open circuit voltage (Voc) of the solar cell manufactured according to Production Example 2 is 594 mV, the short circuit current density (Jsc) is 34.1 mA / cm ² , the filling constant the fill factor FF is 0.687 and the power conversion efficiency is 13.9% when the input power density Ps is 100 mW / cm ² . Considering that a flat silicon solar cell having an antireflection film exhibits a power conversion efficiency of about 12.0%, it can be seen that a solar cell formed on a crystalline polyhedron exhibits excellent performance.

13 is a graph comparing light extraction efficiencies of light emitting diodes having various shapes. At this time, a flat silicon substrate, a silicon pillar of a cylindrical shape having a width of 3.5 mu m and a height of 11 mu m, a silicon wall of a rectangular parallelepiped shape having a width of 3.5 mu m and a height of 11 mu m, (Represented by planar), a silicon pillar light emitting diode (obtained by dividing the p-type GaN layer by 100 nm) obtained by forming an n-type GaN layer of 1000 nm, an MQW layer of 125 nm and a p- light extraction diode (represented by microwire), silicon monolayer (represented by microwall), and crystalline polyhedral light-emitting diode (represented by microcone) were obtained through computer simulation.

Referring to FIG. 13, a crystalline polyhedral light emitting diode (represented by a microcone) is compared to a planar light emitting diode (represented by planar), a silicon pillar light emitting diode (represented by microwire), and a silicon monochromatic light emitting diode The efficiency is remarkably improved. It was predicted that the crystalline structure of the crystalline polyhedra contributed to the emission of light because of its distinctive structure.

14 is a graph comparing light extraction efficiencies of light emitting diodes having various shapes. At this time, a flat silicon substrate, cylindrical pillar silicon cylinders having various widths of 0.5 to 3.5 mu m and a height of 11 mu m, and a crystalline polyhedron having a height of 11 mu m formed according to Production Example 1, (Planar), silicon pillar light emitting diodes having various widths (D = 0.5 μm, 1 μm (thickness)) obtained by forming a p-type GaN layer, a 125 nm MQW layer, , 2 탆, 3 탆, and 3.5 탆), and a crystalline polyhedral light-emitting diode (represented by microcone) were obtained through computer simulation.

Referring to FIG. 14, it can be seen that the maximum value of the light extraction efficiency increases as the diameter of the silicon pillar in the silicon pillar light emitting diodes decreases. However, even a light emitting diode having a silicon pillar having a diameter of 0.5 탆 shows a lower light extraction efficiency than a crystalline polyhedral light emitting diode.

FIG. 15 is a graph (a) showing the light extraction efficiency according to the height variation of the n-type GaN layer of the planar light emitting diode and the crystalline polyhedron light emitting diode, (B) showing the degree of improvement in light extraction efficiency. At this time, the n-type GaN layer, the 125-nm MQW layer, and the 500-nm p-type GaN layer were formed on a silicon substrate and a crystalline polyhedron having a height of 11 탆 according to Production Example 1, The light extraction efficiency for a planar light-emitting diode (denoted as planar) and a crystalline polyhedral light-emitting diode (denoted as microcone) was obtained through computer simulation while varying the height of the n-type GaN layer.

Referring to FIG. 15 (a), it is shown that the crystalline polyhedral light emitting diode exhibits much better light extraction efficiency than a general flat panel light emitting diode. The planar light emitting diode has a low light extraction efficiency of about 4.5% or less irrespective of the thickness of the n-type GaN layer. However, in the crystalline polyhedral light emitting diode, the total light extraction efficiency of 9% or more and the thickness of the n- , It is confirmed that the maximum efficiency is 14%, which indicates that the crystalline polyhedral light-emitting diode can be more than three times more efficient than the conventional planar light-emitting diode.

Referring to FIG. 15 (b), it can be seen that the light extracting efficiency of the crystalline polyhedral light emitting diode can be improved compared to the planar light emitting diode even if the position of the dipole source is changed.

&Lt; Example of nitride film growth &

TMA (trimethylaluminium) gas, NH ₃ gas, TMG (trimethylgallium) gas and NH ₃ gas were supplied to the crystalline silicon polyhedron according to Production Example 1, and MOCVD was used to form an AlN / GaN multi- (The bottom region was an AlN buffer layer of 20 nm), and then a TMG gas and an NH ₃ gas were supplied, and a GaN layer of about 1 탆 was formed by MOCVD.

&Lt; Comparative Example of Nitride Film Growth &

A buffer layer and a GaN layer were formed using the same method as in the nitride film growth example except that a [111] silicon substrate was used instead of the crystalline silicon polyhedron.

16A, 16B and 16C are SEM (Scanning Electron Microscope) photographs of the upper surface, the inclined upper surface, and the cross section of the specimen according to the nitride film growth example, respectively. 17 is an SEM photograph of the upper surface of the crystalline polyhedron before formation of the nitride film and an SEM photograph of the upper surface of the sample after growing the nitride film. 16C is a cross-sectional view taken along line I-I 'of FIG. 16B.

Figure 16a, Figure 16b, Figure 16c, and Referring to Figure 17, the crystallinity of the polyhedron (55), mainly the upper part, especially, {111} surface of the crystalline polyhedron (see Fig. 7b, F ₁₎ of the nitride film on the (NL) (Fig. 16C). That is, it can be seen that the nitride film (NL) is mainly grown from the {111} plane (F ₁ ) of the crystalline polyhedron. The nitride film NL according to the nitride film growth example has a shape of a polyhedron having an upper width narrower than the lower width similarly to the crystalline polyhedron 55, and further, the uppermost portion of the nitride film NL has a pointed vertex or corner Able to know. Specifically, the nitride film NL grown on the crystalline polyhedron 55 has a ridge R formed on the {111} plane F ₁ of the crystalline polyhedron, and the {111 And a valley (V) formed on an edge (E) between the surfaces. Further, the ridges R of the nitride film NL are connected to each other above the crystalline polyhedrons 55 adjacent to each other. At this time, the surface of the nitride film exposed between the ridge and the valley may be the {0002} surface.

18 shows a transmission electron microscope (TEM) image and an FFT (Fourier transform) image analysis showing a section of the specimen in the first direction according to the nitride film growth example, FIG. 19 shows the specimen according to the nitride film growth example in the second direction FIG. 20 shows a TEM photograph and an FFT image analysis showing a cut section of a specimen according to a nitride film growth comparative example. FIG. In this case, the first direction is I-I 'in FIG. 16B or FIG. 17, and the second direction is II-II' in FIG. 16B or 17.

Referring to FIG. 18, a multi-buffer layer (denoted by AIN) and a GaN layer, which are nitride films NL, are sequentially formed on the edge E where adjacent {111} faces of the crystalline polyhedron 55 meet, It can be seen that the buffer layer has a thickness of about 0.2 mu m and the GaN layer has a thickness of about 0.4 mu m. It can also be seen that GaN is grown in the <0002> direction. On the other hand, the surface of the nitride film NL on the edge E where the adjacent {111} faces of the crystalline polyhedron 55 meet is the valley V of FIG. 16B.

19, a multi-buffer layer (denoted by AIN), which is a nitride film NL, and a GaN layer are sequentially formed on the {111} planes F ₁ of the crystalline polyhedron 55, and the multi- And the GaN layer has an average thickness of about 1 mu m (maximum height of 1.7 mu m). It can also be seen that GaN is grown in the <0002> direction. On the other hand, the surface of the nitride film NL formed on the {111} planes F ₁ of the crystalline polyhedr 55 corresponds to the ridge portion of FIG. 16B.

20, a nitride film formed on a [111] silicon substrate having a flat plate shape includes a multi-buffer layer (denoted by AIN) and a GaN layer, wherein the multi-buffer layer has a thickness of about 0.6 mu m and the GaN layer has a thickness of about 1 Mu m. &Lt; / RTI > It can also be seen that GaN is grown in the <0002> direction.

The following Table 1 shows the cross section of the specimen according to the nitride film growth example in the first direction (the cross section shown in Fig. 18), the cross section of the specimen according to the nitride film growth example in the second direction Shows the total dislocation density (TDD) obtained from the cross section of the specimen (cross section shown in Fig. 20) according to the example.

TDD Nitride film growth comparative example
Contrast Reduced TDD Section of the specimen according to the nitride film growth example cut in the first direction
(Section shown in Fig. 18) 7.78 × 10 ⁸ cm ^-2 0.69 The cross section cut in the second direction (cross section shown in Fig. 19) of the specimen according to the nitride film growth example, 3.4 × 10 ⁸ cm ^-2 0.30 Growth of nitride film According to the comparative example,
(Section shown in Fig. 20) 1.125 × 10 ⁹ cm ^-2 One

Referring to Table 1, the total dislocation density of the nitride film formed on the crystalline silicon polyhedron is significantly reduced to 0.3 to 0.69 times that of the nitride film formed on the [111] silicon substrate having the flat plate shape, A high-quality nitride film is formed.

21A and 21B are cross-sectional views illustrating a photoelectric conversion element according to another embodiment of the present invention. At this time, Figs. 21A and 21B may correspond to cross-sections taken along lines I-I 'and II-II' in Fig. 16B. 22 is a plan view schematically showing the upper surface of the unit cell U shown in Fig. 16B. The photoelectric conversion element according to this embodiment can be similar to the photoelectric conversion element described with reference to Fig. 6, except for the following.

21A, 21B, and 22, a light emitting diode which is another kind of photoelectric conversion element is shown. The light emitting diode has a polyhedron 55 disposed on the substrate S. The polyhedron 55 may be formed using the method described with reference to FIGS. 1A, 2A, and 3A, or may be the polyhedron 15 described with reference to FIG. 4A, but not limited thereto, Or may be a polyhedron described with reference to FIGS.

An element layer DL may be formed on the polyhedron 55. The device layer DL may be a buffer layer 60, a first conductive semiconductor layer 61, an active layer 65, and a second conductive semiconductor layer 67 which are sequentially stacked. The first conductivity type semiconductor layer 61, the active layer 65 and the second conductivity type semiconductor layer 67 may be formed by stacking compound semiconductor layers, specifically III-V compound semiconductor layers, Semiconductor layers can be formed. The III-V compound semiconductor layers may be GaAlAs-based, AlGaIn-based, AlGaInP-based, AlGaInPAs-based, or GaN-based semiconductor layers as an example.

The first conductive semiconductor layer 61 may be a nitride-based semiconductor layer doped with an n-type dopant. For example, the first conductive semiconductor layer 61 may include an n-type dopant such as In _x Al _y Ga _1-xy N (0? _X <1, 0? Y <Lt; RTI ID = 0.0 &gt; Si. &Lt; / RTI &gt; The active layer 65 may be a layer of In _x Al _y Ga _1-xy N (0? _X <1, 0? Y <1, 0? _X + y <1) and may have a single quantum well structure or a multi quantum well structure multi-quantum well (MQW). For example, the active layer 65 may have a single quantum well structure of an InGaN layer or an AlGaN layer, or a multiple quantum well structure of a multi-layer structure of InGaN / GaN, AlGaN / (In) GaN, or InAlGaN / . The second conductive semiconductor layer 67 may be a semiconductor layer doped with a p-type dopant. For example, the second conductivity type semiconductor layer 67 may have a p-type conductivity in the In _x Al _y Ga _1-xy N (0 x <1, 0 y <1, 0 x + y < It may be a layer doped with Mg or Zn as a fund.

The buffer layer 60 may be formed on the surface of the polyhedron 55 and the surface of the first conductivity type semiconductor layer 61 in the case where the surface of the polyhedron 55 and the first conductivity type semiconductor layer 61 have different lattice constants. ), Which buffer layer may be an AlN layer, specifically an AlN / GaN multi-buffer layer. However, the material of the buffer layer is not limited thereto.

The element layer DL may be similar in shape to the nitride film described with reference to Figs. 16A, 16B, 16C, and 17. Specifically, the element layer has a shape of a polyhedron whose top width is narrower than that of the bottom width, similar to the polyhedron 55, and further, the top of the element layer can have sharp apexes or corners. Specifically, when the polyhedron 55 is a polyhedron described with reference to FIG. 4A, the element layer DL grown on the upper surface of the polyhedron 55 is a ridge formed on the {111} face F ₁ of the polyhedron 55 , R), and may have a valley (V) formed on an edge (E) between the {111} faces of the polyhedron. In addition, the ridges R of the element layer DL may be connected to each other at the upper portion of the adjacent polyhedrons 55. [ On the other hand, at least the first conductivity type semiconductor layer 61 may be a layer grown in the [0002] direction.

Thereafter, a first electrode 70 may be formed on the lower portion of the substrate S, and a second electrode (not shown) may be formed on the second conductive type semiconductor layer 67.

When a forward electric field is applied to such a light emitting diode, electrons and holes are injected into the active layer 65, and electrons injected into the active layer 65 recombine with holes to emit light. At this time, the surface area of the active layer 65 can be greatly increased due to the polyhedrons 55 protruding upward, and the upper portion of the polyhedron 55 due to the shape of the polyhedron 55 having a narrower upper width than the lower width, The light emitted from the active layer 65 located on the lower portion as well as the light emitted from the active layer 65 located on the light emitting layer 65 can be extracted to the outside. The first conductivity type semiconductor layer 61, the active layer 65, and the second conductivity type semiconductor layer 67, which are epitaxially grown on the crystal faces, are formed on the crystal faces of the polyhedrons 55, Since the defect density is low and crystal quality can be improved, the photoelectric extraction efficiency can also be improved.

On the other hand, in the case where the upper width is narrower than the lower width of the polyhedron 55, the forward electric field can be concentrated on the upper portion of the polyhedron 55, It is possible to increase the amount of light emitted from the active layer 65 located in the light emitting layer. Thereby, the effect of concentrating the light on the front surface may be obtained.

In addition, it is expected that various colors of light can be realized by changing the voltage applied to the light emitting diode. This is because a variety of luminescent colors can be realized according to the applied electric field while varying the current path and the equipotentio plane according to the structural features of the polyhedron 55. This is difficult to implement in planar light emitting diodes.

Table 2 below shows the light extraction efficiency of the light emitting diode shown in Figs. 16B, 21A, 21B, and 22. In this case, the buffer layer 60 is formed of an AlN / GaN multi-buffer layer, the n-type GaN layer having a thickness of 350 nm to 2 m according to the position of the first conductivity type semiconductor layer 61, Layer, the second conductivity type semiconductor layer 67 was a p-type GaN layer of 250 nm, and the light extraction efficiency was obtained through computer simulation. On the other hand, as shown in Fig. 22, the position of the dipole was changed to (1), (2), (3), and (4).

Dipole location ① Branch ② Branch ③ Point ④ Branch Light extraction efficiency
(@ 450 nm) 6.8% 7.2% 8.0% 4.1% Improvement of planar light emitting diode contrast 2.1 times 2.2 times 2.5 times 1.3 times Light extraction efficiency (@ 450 nm) of a planar light emitting diode having the same layer configuration: 3.25%

Referring to Table 2, It can be seen that the light emitting diode formed on the crystalline silicon polyhedron emits the wavelength of about 450 nm, that is, the wavelength of the blue light region, with a light extraction efficiency of about 4.1 to 8.0%. In addition, it shows that the light extraction efficiency is much better than that of a planar light emitting diode at 450 nm. Also, it can be seen that the light extraction efficiency of the light emitting diode formed on the crystalline silicon polyhedron is improved compared to the planar light emitting diode even if the position of the dipole source is changed.

While the present invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (21)

Board;
A polyhedral disposed on the substrate and having a top width narrower than a bottom width;
A first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer sequentially disposed on the polyhedron;
A first electrode electrically connected to the first conductive semiconductor layer; And
And a second electrode electrically connected to the second conductive type semiconductor layer. The method according to claim 1,
Wherein the first conductive semiconductor layer, the active layer, and the second conductive semiconductor layer are compound semiconductor layers. 3. The method according to claim 1 or 2,
Wherein the polyhedron is a crystalline silicon polyhedron,
Wherein the first conductivity type semiconductor layer, the active layer, and the second conductivity type semiconductor layer are epi layers. The method according to claim 1,
Wherein the polyhedron has a pointed vertex or corner at its top. The method according to claim 1,
Wherein the polyhedron has a plurality of crystal planes. 6. The method of claim 5,
Wherein an angle between each of the crystal planes of the polyhedron and the surface of the substrate is reduced toward the top. 6. The method of claim 5,
The polyhedron is a silicon polyhedron,
Wherein the polyhedron has sharp apexes in which four {111} planes and four {111} planes meet. 8. The method of claim 7,
Wherein the first conductivity type semiconductor layer is a GaN layer grown in a [0002] direction. Board;
A polyhedral disposed on the substrate and having a plurality of crystal faces; And
A first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer sequentially disposed on the polyhedron;
A first electrode electrically connected to the first conductive semiconductor layer; And
And a second electrode electrically connected to the second conductive type semiconductor layer. 10. The method of claim 9,
Wherein an angle between each of the crystal planes of the polyhedron and the surface of the substrate is reduced toward the top. 10. The method of claim 9,
Wherein the polyhedron is a silicon polyhedron having crystallinity,
Wherein the first conductive semiconductor layer, the active layer, and the second conductive semiconductor layer are compound semiconductor epitaxial layers. 10. The method of claim 9,
The polyhedron is a silicon polyhedron,
Wherein the polyhedron has sharp apexes in which four {111} planes and four {111} planes meet. 13. The method of claim 12,
Wherein the first conductivity type semiconductor layer is a GaN layer grown in a [0002] direction. Providing a crystalline substrate;
Etching the crystalline substrate to form a pillar;
Epitaxially growing a base semiconductor layer on the pillar to form a crystalline polyhedron;
Forming a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer on the crystalline polyhedron;
Forming a first electrode electrically connected to the first conductive semiconductor layer; And
And forming a second electrode electrically connected to the second conductive type semiconductor layer. 15. The method of claim 14,
Before epitaxially growing the base semiconductor layer,
And hydrogen annealing the pillar. &Lt; RTI ID = 0.0 &gt; 21. &lt; / RTI &gt; 15. The method of claim 14,
Wherein the pillar is etched using an anisotropic etching method. 17. The method of claim 16,
Wherein the pillar is etched by performing the isotropic etching method and then performing the isotropic etching method. 15. The method of claim 14,
Wherein the substrate is a silicon single crystal substrate. 19. The method of claim 18,
Wherein the base semiconductor layer is a silicon layer. The method of claim 18 or 19, wherein the substrate is a substrate grown in a <100> direction, a <110> direction, or a <111> direction. 21. The method of claim 20,
The substrate is a substrate grown in the <100> direction,
Wherein the first conductivity type semiconductor layer, the active layer, and the second conductivity type semiconductor layer are epitaxially grown.

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