KR20160002973A - Led pattern wafer, led epitaxial wafer, and production method for led epitaxial wafer - Google Patents

Abstract

The pattern wafer 10 for LED has a concavo-convex structure (A) 20 having at least a part of the main surface thereof arranged substantially symmetrically n times, and at least a part of the concave- convex structure (A) Of the concave and convex structure (A) 20 with respect to the crystal axis direction of the convexo-concave structure (A) 20 satisfies 0 ° <? (180 / n) Is a corner portion whose radius of curvature is greater than zero. The first semiconductor layer 30, the light-emitting semiconductor layer 40 and the second semiconductor layer 50 are stacked in this order on the concave-convex structure (A) 20 to constitute the LED epitaxial wafer 100 . It is possible to provide pattern wafers for LEDs and epitaxial wafers for LEDs with improved cracking and internal quantum efficiency (IQE).

Description

TECHNICAL FIELD [0001] The present invention relates to a pattern wafer for LED, an epitaxial wafer for LED, and a method for manufacturing an epitaxial wafer for LED (LED PATTERN WAFER, LED EPITAXIAL WAFER, AND PRODUCTION METHOD FOR LED EPITAXIAL WAFER)

The present invention relates to a patterned wafer for LED, an epitaxial wafer for LED, and a method for manufacturing an epitaxial wafer for LED.

Semiconductor light emitting device chips, for example, LED chips generally include an LED epitaxial wafer in which a first semiconductor layer, a light emitting semiconductor layer, and a second semiconductor layer, which are light emitting diode structures, are successively layered and grown on a wafer for LED, Forming an electrode on the second semiconductor layer and the first semiconductor layer, respectively, and then forming the chip on the chip. The emission of the LED can be recognized by extracting the emitted light generated by the recombination of the holes and electrons injected from the respective semiconductor layers to the outside of the LED chip. On the other hand, in general, a structure is adopted in which luminescent light is extracted from the side of the transparent electrode on the second semiconductor layer or the side of the wafer for LED, but it is also possible to remove the LED wafer and extract the luminescent light from the first semiconductor layer side have.

(EQ), internal quantum efficiency (IQE), and optical extraction efficiency (EQE), which determine the external quantum efficiency (EQE) LEE) (Light Extraction Efficiency). Among them, the internal quantum efficiency (IQE) depends on the dislocation density due to the lattice mismatch of the semiconductor crystal (for example, Non-Patent Document 1). The light extraction efficiency (LEE) is improved by destroying the waveguide mode inside the semiconductor layer by light scattering by the concave-convex structure of the patterned wafer for LED (for example, Patent Document 1). Further, the electron injection efficiency (EIE) is improved by reducing the interface resistance between the second semiconductor layer and the transparent conductive layer composed of an oxide such as ITO, ZnO, In ₂ O ₃ or SnO ₂ .

The external quantum efficiency (EQE) of the LED is determined by the three factors described above, but the internal quantum efficiency (IQE) means the efficiency with which the LED emits light. The patterned wafer for LED includes a first semiconductor layer, If a semiconductor layer and a second semiconductor layer are formed to manufacture an epitaxial wafer for LED, a great improvement can not be expected. That is, in order to manufacture an LED that realizes a high external quantum efficiency (EQE), it is necessary to at least improve the internal quantum efficiency (IQE).

In this background, in order to significantly improve the internal quantum efficiency (IQE), an LED manufactured by forming a semiconductor layer on the concave-convex structure of a patterned wafer for LED in which a concave-convex structure is previously formed on the surface of the wafer for LED has been proposed (See, for example, Non-Patent Document 2).

Patent Document 1: JP-A-2009-200514

Non-Patent Document 1: IEEE photo. Tech. Lett., 20, 13 (2008) Non-Patent Document 2: J. Appl. Phys., 103, 014314 (2008)

However, when the concave-convex structure is formed on the wafer for LED in order to improve the internal quantum efficiency (IQE), the growth property of the semiconductor layer is not stabilized, and accordingly, the flatness of the concave-convex structure by the semiconductor layer is not satisfactorily made, There is a problem that a crack is generated in the layer. The generation of such a crack significantly lowers the light emitting diode characteristics of the epitaxial wafer for LED, and increases the defect rate of the LED chip.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and it is an object of the present invention to provide a patterned wafer for LED which can form a semiconductor layer with improved internal quantum efficiency (IQE) And an object thereof is to provide an epitaxial wafer for LEDs with improved efficiency (IQE) and a manufacturing method thereof.

The patterned wafer for LED according to the present invention comprises a concavo-convex structure (A) having at least a part of a main surface substantially symmetrical with n times, at least a part of the convexo-concave structure (A) The rotational shift angle? Of the array axis A of the concave-convex structure A with respect to the direction of the pattern wafer axis satisfies 0 ° <? (180 / n) 占 and the convex- Is a corner section having a radius of curvature of more than 0.

The epitaxial wafer for LED of the present invention is characterized in that at least a first semiconductor layer, a light-emitting semiconductor layer, and a second semiconductor layer are laminated in this order on the main surface of the patterned wafer for LEDs on which the concavoconvex structure A is formed .

Further, the method for manufacturing an epitaxial wafer for LED of the present invention includes the steps of preparing a patterned wafer for LED, optically inspecting the prepared patterned wafer for LED, using the patterned wafer for LED, And a step of producing an epitaxial wafer.

According to the present invention, the internal quantum efficiency (IQE) is improved by dispersing the dislocations generated in the semiconductor layer by the concavo-convex structure (A) of the patterned wafer for LED and reducing the density. Simultaneously, by setting the rotation shift angle (?) Between the crystal axis of the pattern wafer for LED and the arrangement axis A of the concave-convex structure (A) within a predetermined range, cracks occurring in the semiconductor layer can be suppressed. That is, an epitaxial wafer for LEDs having good light emitting diode characteristics can be manufactured. Thus, an LED chip having a high external quantum efficiency (EQE) can be efficiently manufactured.

Fig. 1 is a schematic diagram for explaining the rotation shift angle? Made by the crystal axis of the patterned wafer 1 for LED and the arrangement axis A of the concavo-convex structure A according to the present embodiment.
Fig. 2 is a schematic diagram showing an arrangement example of the concavo-convex structure A having three or more symmetries in the pattern wafer 1 for LED according to the present embodiment.
Fig. 3 is a schematic diagram showing an arrangement example of the concavo-convex structure A having three or more symmetries in the pattern wafer 1 for LED according to the present embodiment.
Fig. 4 is a schematic diagram for explaining crystal axes of the crystal lattice in the main surface of the patterned wafer for LED 1 according to the present embodiment.
5 is a schematic diagram showing a surface observation image when the film formation is stopped in the nucleus growth step when the semiconductor layer is formed on the surface of the patterned wafer 1 for LED.
6 is a graph showing the relationship between the rotational shift angle? When the semiconductor layer is grown on the patterned wafer 1 for LED, the size of the bottom of the concave portion contributing to the growth of the semiconductor layer and the density of the convex portion As shown in FIG.
7 is a graph showing the relation between the duty, the size of the concave bottom portion contributing to the growth of the semiconductor layer, and the density of the convex portion through which the growing semiconductor layer passes, when the semiconductor layer is grown on the patterned wafer 1 for LED Fig.
Fig. 8 is a graph showing the relationship between the rotation shift angle? And the duty shown in Figs. 6 and 7. Fig.
9 is a graph showing the relationship between the average spacing Pave of the concavo-convex structure A of the patterned wafer 1 for LED and the duty according to the present embodiment.
FIG. 10A is a scanning electron micrograph showing an example of the cross-sectional shape of the convex portion of the concavo-convex structure A according to the present embodiment, and FIG. 10B is a schematic view showing a part of FIG. 10A.
11 is a scanning electron micrograph showing an example of the undoped first semiconductor layer according to the present embodiment.
FIG. 12A is a scanning electron micrograph showing a crack, and FIG. 12B is a schematic diagram showing a part of FIG. 12A.
13 is a graph showing the relationship between the crack density and the half width (FWHM) of the rocking curve.
14 is a graph showing the relationship between the crack density and the dark density obtained from the image obtained by the evaluation of the cathode luminescence (CL).
15 is a scanning electron micrograph showing an example of the cross-sectional shape of the convex portion of the concavo-convex structure A according to the present embodiment.
16 is a graph showing the relationship between the average spacing (Pave) of the concavo-convex structure A of the patterned wafer for LED 1 according to the present embodiment and the duty.
17 is a graph showing the relationship between the average spacing (Pave) of the concavo-convex structure A of the patterned wafer 1 for LED and the duty according to the present embodiment.
18 is an explanatory view showing the relationship between the concavo-convex structure G and the non-G region in the patterned wafer 1 for LED according to the present embodiment.
Fig. 19 is a schematic diagram showing an outline shape formed by the concavo-convex structure G region in the patterned wafer 1 for LED according to the present embodiment.
20 is a schematic plan view showing a state in which the patterned wafer 1 for LED according to the present embodiment is observed from its surface.
21 is a schematic plan view showing a state in which the patterned wafer 1 for LED according to the present embodiment is observed from the surface.
22 is a schematic cross-sectional view showing an example of an epitaxial wafer for LED according to the present embodiment.
23 is a schematic cross-sectional view showing another example of the epitaxial wafer for LED according to the present embodiment.
24 is a schematic cross-sectional view showing another example of the epitaxial wafer for LED according to the present embodiment.
25 is a schematic cross-sectional view showing the LED chip according to the present embodiment.
26 is a schematic cross-sectional view showing another example of the LED chip according to the present embodiment.
27 is a schematic cross-sectional view showing an example of the patterned wafer 2 for LED according to the present embodiment.
28 is a schematic cross-sectional view showing another example of the patterned wafer 2 for LED according to the present embodiment.
29 is a schematic diagram showing the concavo-convex structure of the patterned wafer 2 for LED according to the present embodiment.
30 is a schematic cross-sectional view showing another example of the patterned wafer 2 for LED according to the present embodiment.

Hereinafter, one embodiment of the present invention (hereinafter abbreviated as &quot; embodiment &quot;) will be described in detail. On the other hand, the present invention is not limited to the following embodiments, but various modifications may be made within the scope of the present invention.

The patterned wafer 1 for LED according to the present embodiment has a concavo-convex structure A having a substantially symmetrical arrangement n times on its main surface, and at least a part of the concave- The rotational shift angle? Of the array axis A of the concavoconvex structure A with respect to the direction of the crystal axis of the pattern wafer 1 for LED 1 satisfies 0 ° <? (180 / n) Is a corner portion whose radius of curvature is greater than zero.

According to this configuration, cracks generated in the semiconductor layer to be formed on the main surface on which the concavo-convex structure A of the patterned wafer for LED 1 is formed can be suppressed. At the same time, dislocations generated with respect to the semiconductor layer can be dispersed and the density thereof can be reduced. Therefore, it is possible to improve the internal quantum efficiency (IQE) of the epitaxial wafer for LEDs using the patterned wafer 1 for LEDs, and to improve the yield when manufacturing the patterned wafer 1 for LEDs. Further, cracks in the semiconductor layer of the LED epitaxial wafer can be suppressed, so that the defect rate of the LED chip can be reduced.

First, the convex portion of the concavo-convex structure A of the pattern wafer for LED 1 is a corner portion having a radius of curvature of more than 0. Therefore, when forming the semiconductor layer on the concavo-convex structure A of the patterned wafer 1 for LED, the semiconductor layer can be grown on the basis of the concave bottom of the concavo-convex structure. That is, the semiconductor layer grows preferentially from the concave bottom of the concavo-convex structure. Then, the concavo-convex structure A formed on the patterned wafer 1 for LEDs has an arrangement that is substantially n times symmetrical. Therefore, when attention is paid to the initial growth step of the semiconductor layer to be formed on the patterned wafer 1 for LED, the nucleation of the semiconductor layer can be uniformly dispersed, and the unevenness of the nucleation can be balanced. Here, the unevenness of nucleation is that the semiconductor layer partially rises by nucleation. That is, it is possible to disperse the semiconductor layer of the partially growing nucleation step. The arrangement axis A of the concavoconvex structure A is arranged in a predetermined range of the rotational shift angle Θ with reference to the crystal axis direction of the LED pattern wafer 1 in the main surface of the pattern wafer for LED 1 I am shifting within. Thus, the size of the concave bottom portion of the concavo-convex structure contributing greatly to the initial growth of the semiconductor layer can be increased. At the same time, it is possible to reduce the number of protrusions of the concave-convex structure through which the growing semiconductor layer passes when viewed from the growth direction of the semiconductor layer. As described above, the coalescence (cohesion) of the growing nuclei when the semiconductor layer is grown becomes good, and cracks in the semiconductor layer can be suppressed. At the same time, at the time of the coalescence, the direction of the electric potential in the semiconductor layer changes in the in-plane direction of the patterned wafer 1 for LED. As a result, collisions between the potentials are effectively induced, so that the internal quantum efficiency IQE is improved. That is, since the semiconductor layer with improved internal quantum efficiency (IQE) can be obtained in a state in which cracks are suppressed, it is possible to manufacture an epitaxial wafer for LED having good light emitting diode characteristics, ) Can be manufactured efficiently.

In the patterned wafer 1 for LED according to the present embodiment, the average spacing Pave of the concavo-convex structure A preferably satisfies 50 nm? Pave? 1500 nm.

In this case, both the improvement effect of the internal quantum efficiency (IQE) and the crack suppression effect are increased. Firstly, when the average spacing Pave satisfies the above range, the density of the concave portion of the concavoconvex structure A is improved, so that the frequency of incorporation of the growing semiconductor layers described above can be increased. In other words, since the potential in the semiconductor layer can improve the frequency of changing its traveling direction, the potential reduction effect becomes larger, thereby effectively improving the internal quantum efficiency IQE. Furthermore, the size of the concave bottom portion of the concave-convex structure contributing greatly to the initial growth of the semiconductor layer can be made to fall within a predetermined range. As a result, the nucleation of the semiconductor layer at the bottom of the concave portion of the concave-convex structure A can be satisfactorily maintained. Therefore, the effect of suppressing cracks in the semiconductor layer is increased as the array axis A of the concavoconvex structure A shifts within a predetermined range by the rotational shift angle?.

In the patterned wafer 1 for LEDs according to the present embodiment, the duty ratio (? Ave / Pave) between the average width? Ave of the convex bottom portions of the concavoconvex structure A and the average spacing Pave , The rotation shift angle? Preferably satisfies the range of atan (duty / 2)??? (180 / n) degrees.

In this case, the internal quantum efficiency (IQE) improvement effect and the crack suppression effect on the semiconductor layer become larger together. The size of the concave bottom portion of the concavo-convex structure A contributing greatly to the initial growth of the semiconductor layer can be made smaller than the size of the bottom portion of the concave portion A in the in-plane direction of the LED pattern wafer 1, The size of the surface on which the growth rate of the semiconductor layer is high becomes large because it can be largely held in the direction substantially perpendicular to the growth direction. Thus, when focusing on the coalescence of the growing semiconductor layers, the interfacial area between the coalescing semiconductor layers becomes larger. Further, since the number of convex portions of the concave-convex structure A across which the semiconductor layer is grown at a high speed can be reduced, the degree of coalescence of the growing semiconductor layers becomes good. From the above, the internal quantum efficiency IQE is further improved, and cracks occurring in the semiconductor layer are effectively suppressed.

In the patterned wafer for LED according to the present embodiment, it is preferable that the patterned wafer for LED 1 is a sapphire wafer, a silicon wafer, a silicon carbide wafer or a gallium nitride wafer.

According to this configuration, since it is possible to more effectively exhibit the improvement of the internal quantum efficiency (IQE), the suppression of cracks in the semiconductor layer and the shortening of the production time, the LED chips having a high internal quantum efficiency (IQE) Production time can be shortened.

The epitaxial wafer for LED according to the present embodiment is characterized in that at least the first semiconductor layer, the light-emitting semiconductor layer, and the second semiconductor layer are formed on the main surface on which the concave-convex structure A of the patterned wafer for LED 1 is formed, As shown in FIG.

According to this structure, it is possible to manufacture an epitaxial wafer for LED having a semiconductor layer, which is a light emitting diode structure having a high internal quantum efficiency (IQE) with suppressed cracks, from the principle already described.

In the epitaxial wafer for LED according to the present embodiment, the distance (Hbun) between the surface of the LED pattern wafer 1 on the light emitting semiconductor layer side and the surface of the light emitting semiconductor layer on the first semiconductor layer side, (Hbun / Have) to the average height (Have) of the concave-convex structure (A) preferably satisfy 2? Hbun / Have?

According to this configuration, it is possible to efficiently manufacture an epitaxial wafer for LED having a high internal quantum efficiency (IQE) with suppressed cracks. The crystallinity of the first semiconductor layer can be increased and the crack can be suppressed by the previously described principle by the concavo-convex structure A formed on the main surface of the patterned wafer 1 for LED. Particularly, when the ratio (Hbun / Have) is 2 or more, the degree of planarization of the concave-convex structure (A) by the first semiconductor layer is improved. As a result, the deposition precision of the light emitting semiconductor layer and the second semiconductor layer provided on the first semiconductor layer can be effectively improved. As a result, it is possible to reflect the performance of the first semiconductor layer having a small potential as a semiconductor to the light emitting semiconductor layer and the second semiconductor layer in a state where the cracks are suppressed, and the internal quantum efficiency IQE A semiconductor layer (including a first semiconductor layer, a light-emitting semiconductor layer, and a second semiconductor layer), which is a high light-emitting diode structure, can be obtained. In addition, when the ratio (Hbun / Have) is 300 or less, in addition to the above effect, warping of the pattern wafers 1 for LED can be suppressed, and the LED chip efficiency can be improved. From the above, it is possible to form a semiconductor layer having a high internal quantum efficiency (IQE) in which cracks are suppressed by satisfying the predetermined ratio Hbun / Have, and at the same time, the patterned wafer 1 for a semiconductor film, It is possible to manufacture a highly efficient LED chip with high production efficiency. In particular, even when the size of the patterned wafer for LED 1 is 6 inches or more in diameter, warping of the epitaxial wafer for LEDs can be effectively suppressed. Thus, by using the patterned wafer for LED 1 of the present invention with a size of 6 inches or larger, it is possible to reduce the thickness of the patterned wafer 1 for LEDs and effectively suppress the warping of the epitaxial wafer for LEDs . In particular, by reducing the thickness of the patterned wafer for LED 1, the amount of patterned wafer for LEDs can be reduced, i.e., the environmental fitness can be increased. In addition, since heat accumulation on the patterned wafer 1 for LED can be suppressed, temperature management during the formation of the semiconductor layer becomes easy.

In the epitaxial wafer for LED according to the present embodiment, the first semiconductor layer includes a non-doped first semiconductor layer and a doped first semiconductor layer which are sequentially laminated from the patterned wafer for LED 1, The distance Hbu between the surface of the patterned wafer 1 on the side of the light emitting semiconductor layer and the surface of the undoped first semiconductor layer on the side of the first doped semiconductor layer and the average height Have of the concave- It is preferable that the ratio (Hbu / Have) satisfies 1.5? Hbu / Have? 200.

According to this configuration, it is possible to efficiently manufacture an epitaxial wafer for LED having a high internal quantum efficiency (IQE) with suppressed cracks. The crystallinity of the undoped first semiconductor layer can be increased and the crack can be suppressed by the previously described principle by the concavo-convex structure A formed on the main surface of the patterned wafer 1 for LED. Particularly, when the ratio (Hbu / Have) is 1.5 or more, the degree of planarization of the uneven structure (A) by the undoped first semiconductor layer is improved. Thus, the deposition precision of the first doped first semiconductor layer, the light emitting semiconductor layer, and the second semiconductor layer formed on the undoped first semiconductor layer can be effectively improved. Therefore, it is possible to reflect the crystallinity of the undoped first semiconductor layer having a small potential to the doped first semiconductor layer, the light-emitting semiconductor layer, and the second semiconductor layer in a state of suppressing cracks, An epitaxial wafer for LED having a high internal quantum efficiency (IQE) can be obtained while shortening the production time. In addition, when the ratio (Hbu / Have) is 200 or less, warpage of the patterned wafer 1 for LED can be suppressed in addition to the above effects, and the LED chip efficiency can be improved. From the above, it is possible to form a semiconductor layer having a high internal quantum efficiency (IQE) whose cracks are suppressed by satisfying a predetermined range of the ratio Hbu / Have, and at the same time, The warpage can be suppressed, so that a high efficiency LED chip can be produced with high production efficiency. In particular, even when the size of the patterned wafer for LEDs is 6 inches or more in diameter, warping of the epitaxial wafer for LEDs can be effectively suppressed. Thus, by using the patterned wafer for LED 1 of the present invention with a size of 6 inches or larger, it is possible to reduce the thickness of the patterned wafer 1 for LEDs and effectively suppress the warping of the epitaxial wafer for LEDs . In particular, by reducing the thickness of the patterned wafer for LED 1, the amount of patterned wafer for LEDs can be reduced, i.e., the environmental fitness can be increased. In addition, since heat accumulation on the patterned wafer 1 for LED can be suppressed, temperature management during the formation of the semiconductor layer becomes easy.

In the epitaxial wafer for LED according to the present embodiment, the first semiconductor layer, the light-emitting semiconductor layer, and the second semiconductor layer may be a III-V family semiconductor. In the epitaxial wafer for LED according to the present embodiment, the first semiconductor layer, the light-emitting semiconductor layer, and the second semiconductor layer may be GaN-based semiconductor.

The method for manufacturing an epitaxial wafer for LED according to the present embodiment includes a step of preparing the LED pattern wafer 1, a step of optically inspecting the prepared LED pattern wafer 1, And a step of producing the epitaxial wafer for LED described above by using the patterned wafer 1 for patterning.

According to this configuration, since the rotational shift angle? Of the array axis A of the concavoconvex structure A can be measured, the light emitting diode characteristics of the LED epitaxial wafer can be predicted without manufacturing the epitaxial wafer for LED, So that it can be filtered. Therefore, the yield of the epitaxial wafer for LED can be improved.

In the method of manufacturing an epitaxial wafer for LED according to the present embodiment, the step of preparing the pattern wafers 1 for LED is performed by a transfer method using a mold having a fine pattern on its surface, Is satisfied.

By employing the transfer method for manufacturing the concavoconvex structure A, the patterned wafer 1 for LEDs satisfying the above-described range of the rotational shift angle (?) Can be manufactured without using an excessive apparatus or a control mechanism . Particularly, by employing the transfer method, the patterned wafer 1 for LEDs having a diameter of 6 inches or more, which is difficult to manufacture, can be manufactured with high precision and efficiency.

Hereinafter, the patterned wafer 1 for LED, the epitaxial wafer for LED, and the manufacturing method thereof will be described in detail in this order.

<< Pattern Wafer for LED (1) >>

The patterned wafer for LED according to the present embodiment has a patterned wafer for LED 1 capable of forming a high quality semiconductor layer with suppressed cracks and particularly capable of improving internal quantum efficiency IQE, And includes both the pattern wafers 2 for LEDs, which impart a high light extraction efficiency (LEE) to the wafer 1 as a further function. In the following description, description will be given starting from the patterned wafer 1 for LED, and the description of the patterned wafer for LED 2 will be mainly described with attention paid to the elements to be added.

The patterned wafer 1 for LED according to the present embodiment has a concavo-convex structure A on its surface. The concavo-convex structure (A) may be formed by machining a single-sided surface of the wafer for LED, or may be formed separately on one surface of the wafer for LED. That is, the material constituting the wafer for LED and the material constituting the concavo-convex structure (A) may be the same or different. Here, the concave-convex structure (A) has a substantially symmetrical arrangement of n times, and indicates that the direction of the arrangement axis A of the concave-convex structure (A) and the direction of the crystal axis within the plane of the LED wafer shift within a predetermined range . This shift amount is called a rotation shift angle?.

 &Lt; Rotation shift angle?

First, the rotation shift angle? Will be described. On the other hand, the arrangement axis A of the concavo-convex structure A and the crystal axes of the pattern wafers 1 for LED will be described later. The rotation shift angle? Is defined as the minimum rotation angle of the arrangement axis A of the concavo-convex structure A with reference to the crystal axis of the pattern wafer 1 for LED. Fig. 1 is a schematic diagram for explaining the rotation shift angle? Made by the crystal axis of the patterned wafer 1 for LED and the arrangement axis A of the concavo-convex structure A according to the present embodiment. 1A, only one alignment axis A (represented by AXa in Fig. 1A) and a crystal axis (represented by AXc in Fig. 1A) are shown for simplification. 1A, the minimum angle when the crystal axis AXc is rotated until it overlaps with the array axis AXa is the rotation shift angle? When the intersection point of the crystal axis AXc and the array axis AXa is the center point.

Next, a case in which a plurality of crystal axes and arrangement axes A are considered will be described with reference to Fig. 1B. 1B is a drawing of three crystal axes (denoted by AXc1, AXc2 and AXc3 in Fig. 1B) and an array axis A (denoted by AXa1, AXa2 and AXa3 in Fig. 1B) together for convenience. For example, it is a case in which a concavoconvex structure A having a six-fold symmetry arrangement is formed on an LED wafer having a crystal axis of six times symmetry. In this case, one crystal axis is selected first. For example, suppose that the crystal axis AXc1 is selected. Then, the crystal axis AXc1 is rotated to record the angle of overlap with the array axis A. [ For example, a small angle when overlapping the array axis AXa3 is an angle? A, and a small angle when overlapping the array axis AXa1 is an angle? B. The minimum of these angles is the rotation shift angle?. On the other hand, the above definition is also established by reversing the arrangement axis A and the crystal axis. That is, it is defined in the same manner by rotating the array axis A to the minimum angle at the time of overlapping the crystal axis.

<Array axis>

Next, the array axis A will be described. The array axis A is an axis for determining the arrangement direction of the concavoconvex structure A. The arrangement of the concave-convex structure (A) has substantial n-fold symmetry. In the present specification, &quot; n-times symmetry &quot; means &quot; rotational symmetry &quot;. Therefore, n is a positive integer of 2 or more. By observing the concave-convex structure (A) from its surface by, for example, a scanning electron microscope or an atomic force microscope, the arrangement of the concavo-convex structure (A) can be confirmed. Therefore, the array axis A has the property of overlapping the same or different array axis A by rotation of (360 / n) degrees. Here, the array axis A is defined separately for the case where n is symmetrical n times, and when n is two or more.

First, in the case of two symmetries, it is an arrangement symmetrical with respect to any one axis. At this time, the array axis A is defined as an axis perpendicular to the axis. For example, in the case of the concave-convex structure A in which a plurality of mutually parallel lines are arranged, the line segment perpendicular to the line is symmetrical twice, and therefore, the array axis A is a line segment parallel to the line. Further, in the case of an arrangement in which a regular square array or a square dish array is uniaxially stretched, an orthogonal array or a square dish array is periodically (for example, in a sinusoidal wave) modulation in the uniaxial direction, Direction, and therefore, the array axis A is a line segment parallel to the stretching direction or the modulation direction. Also, in the case where the intervals of a plurality of lines are periodically modulated (for example, on a sine wave), the line segments in the direction parallel to the plurality of lines become the array axis A. Further, in the case of an arrangement in which the orthorhombic array or the square array is elongated in mutually perpendicular biaxial directions at different elongation ratios in the respective axial directions, it is symmetrical twice in the direction perpendicular to any elongation direction, A is a line segment parallel to the stretching direction. In the case of an arrangement in which the regular square array and the square array are modulated in mutually perpendicular biaxial directions with different modulation periods in the respective axial directions, the arrangement is symmetrical twice in the direction perpendicular to any modulation direction, Is a line segment parallel to the modulation direction.

On the other hand, in the case of an array having three or more symmetries, the convex portion of the concavoconvex structure A or the axis which is the closest to each other in the concave portions is defined as the array axis A. Herein, the closest direction is the direction of a line segment connecting the central portions of the nearest convex portion, or the direction of a line connecting the centers of the concave portion closest to each other. 2 is a schematic diagram showing an arrangement example of the concavo-convex structure A having three or more symmetries in the pattern wafer 1 for LED according to the present embodiment. For example, it can be obtained by observing the surface side of the patterned wafer 1 for LED with the concavo-convex structure A by a scanning electron microscope or an atomic force microscope. Fig. 2 shows a case where the concavo-convex structures A are arranged substantially in the right sideward direction. The positive rectangular array is a four-symmetrical array. That is, when any axis is arbitrarily set, the axis is rotated by (360 / n) ° = (360/4) ° to overlap another symmetry axis. Here, the arrangement axis A is the closest direction of the convex portion or the concave portion of the concavo-convex structure A. In Fig. 2, the center of the convex portion closest to the convex portion (or concave portion, hereinafter the same) having the center indicated by the symbol A is as indicated by the symbols a, b, c and d in Fig. 2A. That is, the direction parallel to any of the line segment A-a, line segment A-b, line segment A-c, and line segment A-d connecting the center A and the other centers is the arrangement axis AXa.

Fig. 3 is a schematic diagram showing an arrangement example of the concavo-convex structure A having three or more symmetries in the pattern wafer 1 for LED according to the present embodiment. For example, it can be obtained by observing the surface side of the patterned wafer 1 for LED with the concavo-convex structure A by a scanning electron microscope or an atomic force microscope. Fig. 3 shows a case where the concave-convex structures A are arranged substantially in a meat-processing chamber. The meat arrangement is a six-fold symmetrical arrangement. That is, when an arbitrary axis is arbitrarily set, the axis is rotated by (360 / n) ° = (360/6) degrees to overlap another symmetry axis. Here, the arrangement axis A is the closest direction of the convex portion or the concave portion of the concavo-convex structure A. In Fig. 3, the center of the convex portion closest to the convex portion (or concave portion, hereinafter the same) having the center indicated by A is expressed by symbols a, b, c, d, e, The same. That is, the direction parallel to the line segment A-a, line segment A-b, line segment A-c, line segment A-d, line segment A-e, and line segment A-f connecting the center A and other centers is the arrangement axis AXa.

In addition, for example, in the four-fold symmetry arrangement described above, a case where the interval between mutually perpendicular biaxial convex portions or concave portions is modulated periodically (for example, on a sinusoidal wave) is also an arrangement of four times symmetry. Further, in the above-described four-fold symmetry arrangement, when the intervals of the convex portions or concave portions placed on the axis of the pitch of 60 DEG with respect to any axis periodically change (for example, on a sinusoidal wave) do. In addition, for example, in the six-fold symmetry arrangement described above, when the intervals of the mutually perpendicular biaxial convex portions or concave portions are periodically (for example, subjected to a sinusoidal wave), the arrangement is symmetrical four times. In addition, in the six-fold symmetry arrangement described above, even when the intervals of the convex portions or the concave portions placed on the axis of the pitch of 60 DEG with respect to any axis periodically change (for example, on a sinusoidal wave) do.

As described above, there is at least one arrangement axis A, and by applying the definitions already described, the rotation shift angle? Can be obtained.

&Lt; Crystallization axis &

Next, the crystal axes will be described. The crystal axis is the closest direction of the lattice point of the crystal lattice in the plane parallel to the main surface of the patterned wafer 1 for LED. Fig. 4 is a schematic diagram for explaining crystal axes of the crystal lattice in the main surface of the patterned wafer for LED 1 according to the present embodiment. Fig. 4 shows the case where the crystal lattice in the plane parallel to the main surface of the wafer for LED is a meat crystal lattice, and the lattice intersection is marked and emphasized. The crystal axis is the closest direction of the lattice point. For example, in Fig. 4, the intersection closest to the intersection represented by the symbol A is as indicated by the symbols a, b, c, d, e, and f. That is, the direction parallel to any one of the line segment A-a, line segment A-b, line segment A-c, line segment A-d, line segment A-e, and line segment A-f connecting the intersection A and the other intersection point is the crystal axis. The arrangement of the crystal lattices observed in the plane parallel to the main surface of the patterned wafer for LED 1 can be determined by arranging the crystal lattices in a hexagonal arrangement, a rectangular arrangement, a hexagonal arrangement, An arrangement in which the hexagonal arrangements extend in mutually opposite directions of the biaxial directions, and arrangements in which the four directions are elongated in the directions of the biaxially orthogonal directions. For any crystal lattice arrangement, the crystal axes herein are defined by applying the above definition. For example, when the pattern wafer 1 for LED is monocrystalline sapphire and its principal plane is c-plane, m-plane or r-plane, the crystal axes are respectively a-axis, c-axis or n-axis.

<array of symmetry>

The concavo-convex structure A formed on the pattern wafer 1 for LEDs has an arrangement that is substantially n times symmetrical. Therefore, when attention is paid to the initial growth step of the semiconductor layer to be formed on the patterned wafer 1 for LED, the nucleation of the semiconductor layer can be uniformly dispersed, and the unevenness of the nucleation can be balanced. Here, the unevenness of nucleation is that the semiconductor layer partially rises by nucleation. That is, it is possible to disperse the semiconductor layer of the partially growing nucleation step.

5 is a schematic diagram showing a surface observation image when the film formation is stopped in the nucleus growth step when the semiconductor layer is formed on the surface of the patterned wafer 1 for LED. In FIGS. 5A and 5B, the symbol X represents the position of the semiconductor layer in the partially growing nucleation step. FIG. 5A schematically shows a state in which a semiconductor layer X of a nucleus growth step partially rising is dispersed in the patterned wafer 1 for LED according to the embodiment of the present invention. On the other hand, FIG. 5B shows a case where there is a bias in the semiconductor layer X in the nucleus growth stage, which partially protrudes, in the patterned wafer 1 for LED having a low rotational symmetry in the arrangement of the concavoconvex structures A . In the patterned wafer 1 for an LED according to the embodiment of the present invention, the unevenness structure A has a substantially n-fold symmetry, so that the dispersibility of the semiconductor layer X in the nucleus growth stage partially rising is increased . As a result, portions where coalescence (adhesion) of the growing semiconductor layers occur is also dispersed. That is, the stress concentration points inside the semiconductor layer are dispersed, and the collision sites between the potentials are dispersed. Therefore, cracks in the semiconductor layer are suppressed, and the internal quantum efficiency (IQE) is effectively improved. On the other hand, the term &quot; crack &quot; In the case of forming the semiconductor layer with respect to the concavo-convex structure (A) of the patterned wafer for LED (1), it is observed that the growth of the semiconductor layer is stopped during the facet formation process. At this time, when the facets have an n-angular shape represented by, for example, a hexagonal shape, and when attention is paid to two adjacent n-angular concave portions, cracks entering in the direction orthogonal to the sides and sides of the n-angular concave portions , &Lt; / RTI &gt; as defined herein.

As described above, the rotation shift angle? Is set such that the crystal axis of the patterned wafer 1 for LED and the rotation (rotation) in the plane parallel to the main surface of the LED pattern wafer 1 on the arrangement axis A of the concave- Direction. This rotation shift angle? Satisfies 0 deg. &Lt; / = (180 / n) deg. On the other hand, &quot; n &quot; is the rotational symmetry order of the concavo-convex structure (A) constituting the array of symmetrical n times and is the same as described above. For example, when the concavoconvex structure A is six times symmetrical, the rotation shift angle? Is more than 0 degrees and less than 30 degrees. When the rotation shift angle? Satisfies the above range, the size of the concave bottom portion of the concavo-convex structure A contributing greatly to the initial growth of the semiconductor layer can be increased. At the same time, it is possible to reduce the number of convex portions of the passing convexo-concave structure A of the semiconductor layer having a high growth speed. Therefore, the initial growth of the semiconductor layer becomes good. Then, when the sides of the facets to be formed face each other, the parallelism between the sides becomes better, and cracks are suppressed.

<More preferable range of the rotation shift angle?

A more preferable range of the rotation shift angle? Can be considered as follows. First, improvement of the internal quantum efficiency (IQE) and improvement of cracks are effective, and it is effective to increase the frequency of coalescence of the growing semiconductor layers and to disperse the coalescence sites. Also, considering the step before the semiconductor layers are combined, it is necessary to maintain the nucleation of the semiconductor layer at a satisfactory level while maintaining good nucleation performance. In order to realize these, it is considered effective to increase the size of the concave portion of the concavo-convex structure A to which the nuclei of the semiconductor layer are attached and to reduce the number of convex portions of the concavo-convex structure A that crosses when the semiconductor layer grows . At the same time, it is important to increase the parallelism between sides of the facets to be formed.

6 is a graph showing the relationship between the rotational shift angle? When the semiconductor layer is grown on the patterned wafer 1 for LED, the size of the bottom of the concave portion contributing to the growth of the semiconductor layer and the density of the convex portion As shown in FIG. 6 is a graph showing the relationship between the size of the concave bottom portion contributing to the growth of the semiconductor layer (hereinafter, simply referred to as the size L of the bottom portion of the concave portion) given by the rotational shift angle? ) And the density of the convex portion through which the growing semiconductor layer passes (hereinafter, simply referred to as the density D of the convex portion) is calculated. 6, the horizontal axis represents the rotational shift angle?, The vertical axis on the left represents the size L of the concave bottom portion, and the vertical axis on the right represents the density D of the convex portion. The influence of the plot of the black circle (●) on the size (L) of the concave bottom portion and the influence of the plot of the black square (■) on the density (D) of the convex portion are respectively shown. In Fig. 6, the size L of the concave bottom portion and the density D of the convex portions are all normalized to 1 when the rotational shift angle? Is 0 °.

It can be seen from Fig. 6 that as the rotational shift angle? Increases, the size L of the concave portion of the concavo-convex structure A effective for attachment of nuclei and growth thereof increases. In particular, even when the maximum shift point angle θ is maximized when the rotation shift angle θ is increased and the maximum shift point angle θ is maximized, the size L of the recessed portion is larger than when the rotation shift angle θ is 0 ° . On the other hand, it can be seen that as the rotational shift angle? Increases, the density D of the convex portion, which adversely affects the growth of the semiconductor layer and the coalescence of the growing semiconductor layers, is reduced. The density D of the convex portion is smaller than that in the case where the rotational shift angle? Is 0 占 even when the rotational shift angle? Is maximum, especially when the rotational shift angle? .

From the above, it is preferable that the rotation shift angle? Is not less than 1 degree, more preferably not less than 3 degrees, and most preferably not less than 5 degrees in order to effectively suppress the cracks and increase the internal quantum efficiency IQE . In this case, particularly, the density D of the convex portion is greatly reduced, so that the growth property of the semiconductor layer is stabilized and the crack suppressing effect is increased. Further, the rotation shift angle? Is preferably 7.5 ° or more, more preferably 10 ° or more, and most preferably 14 ° or more. In this case, the inner quantum efficiency (IQE) can be further improved since the size of the concave portion of the concavo-convex structure A that is effective for attachment of nuclei of the semiconductor layer and growth thereof can be increased while maintaining the above- . On the other hand, when the rotation shift angle? Is (180 / n) degrees, the amount of directional change of the stress that can be changed by the shift amount between the crystal axis and the arrangement axis A becomes the maximum, and the relaxed stress is made n times It is considered that the structure (A) has the highest effect of rotationally connecting in a vector manner, so that the stress relaxation effect is further increased, and accordingly, the warpage reduction becomes more remarkable.

When the following relationship is satisfied with respect to the convex portion of the concavo-convex structure A, the rotational shift angle? Further enhances the crack suppressing effect and the internal quantum efficiency IQE improving effect. The rotational shift angle? Is set to atan (duty / 2) 占 when using the duty which is the ratio (? Ave / Pave) of the average width? Ave of the convex bottom portion of the concavoconvex structure A to the average spacing Pave (180 / n) deg.. On the other hand, the average width (? Ave), the average spacing (Pave) and the duty of the bottom portion of the convex portion will be described later.

In this case, the internal quantum efficiency (IQE) improvement effect and the crack suppression effect on the semiconductor layer become larger together. The size L of the bottom portion of the concave portion contributing to the initial growth of the semiconductor layer satisfies the following relationship within the plane of the patterned wafer for LED 1 in the growth direction of the semiconductor layer The size of the surface of the semiconductor layer where the growth rate of the semiconductor layer is high becomes large. Thus, when focusing on the coalescence of the growing semiconductor layers, the interfacial area between the coalescing semiconductor layers becomes larger. Furthermore, since the number of convex portions of the concave-convex structure across which the semiconductor layer is grown at a high speed can be reduced, the degree of coalescence of the growing semiconductor layers becomes good. From the above, the internal quantum efficiency IQE is further improved, and cracks occurring in the semiconductor layer are effectively suppressed.

The relation between the duty and the rotation shift angle? Is obtained by thinking as follows. First, as for the improvement of the internal quantum efficiency (IQE) and the improvement of the crack, it is effective to increase the frequency of coalescence of the growing semiconductor layers and to disperse the coalescence sites. Also, considering the step before the semiconductor layers are combined, it is necessary to maintain the nucleation of the semiconductor layer at a satisfactory level while maintaining good nucleation performance. In order to realize these, it is considered effective to increase the size of the concave portion of the concavo-convex structure A to which the nuclei of the semiconductor layer are attached and to reduce the number of convex portions of the concavo-convex structure A that crosses when the semiconductor layer grows .

7 shows the relationship between the duty, the size of the concave bottom portion contributing to the growth of the semiconductor layer, and the density of the convex portion through which the growing semiconductor layer passes when the semiconductor layer is grown on the patterned wafer 1 for LED Respectively. Fig. 7 shows the results of calculation of the influence of the duty on the size L of the bottom of the concave portion and the density D of the convex portion, taking the case in which the concave-convex structure A is symmetric six times. In Fig. 7, the abscissa represents the duty, the ordinate on the left represents the size L of the concave bottom portion, and the ordinate on the right represents the density D of the convex portion. The influence of the plot of the black circle (●) on the size (L) of the concave bottom portion and the influence of the plot of the black square (■) on the density (D) of the convex portion are respectively shown. 7, the size L of the bottom portion of the concave portion and the density D of the convex portion are all normalized to 1 when the duty is zero, that is, when the concavoconvex structure A is absent.

7, it can be seen that as the duty increases, the size L of the concave portion of the concavo-convex structure A effective for attachment of nuclei and growth thereof increases. On the other hand, it can be seen that as the duty increases, the density D of the convex portion, which functions adversely to the growth of the semiconductor layer and the coalescence of the growing semiconductor layers, decreases.

6 and 7, the parameters on the abscissa are different from each other, and the behavior on the influence on the size L of the concave bottom portion and on the density D of the convex portion are similar. From this relationship, the relationship between the horizontal shift rotation angle (?) And the duty ratio of each horizontal axis in Figs. 6 and 7 is obtained, and the rotation shift angle? = Atan (duty / 2) deg. As described above, as the duty increases, the rotation shift angle? Is given as?? Atan (duty / 2)? Since the nucleation, growth, and coalescence of the semiconductor layer effectively occur.

That is, when the duty of the concavoconvex structure A is determined, the rotation shift angle? Is in a range of not less than a predetermined value and not more than (180 / n) degrees, Further, since the semiconductor layers to be grown are better combined, an epitaxial wafer for LED having a high internal quantum efficiency (IQE) with suppressed cracks can be obtained. Fig. 8 is a graph showing the relationship between the rotation shift angle? And the duty shown in Figs. 6 and 7. Fig. For example, taking the case in which the concavoconvex structure A is symmetrical six times, the shaded area in FIG. 8 is the most preferable range of the rotational shift angle?. In Fig. 8, the abscissa is the duty and the ordinate is the rotation shift angle?. The plot in FIG. 8 is atan (duty / 2) degrees, and the upper portion in the vertical axis direction than this curve is the most preferable range of the rotation shift angle?.

On the other hand, if the size L of the bottom portion of the concave portion of the concavoconvex structure A is too small, nucleation of the semiconductor layer is inhibited, and growth of the semiconductor layer is hindered. The size of the bottom of the concave portion of the concavoconvex structure A can be expressed by using an average interval (Pave) and a duty. The lower limit of the size of the bottom of the concave portion of the concavo-convex structure (A) can be estimated from the size of the nucleus of the semiconductor layer. More specifically, regarding the RAMP process after forming the low-temperature buffer layer to be described later on the patterned wafer 1 for LED, the travel distance of the nucleus which re-diffuses in the RAMP process is approximately 80 nm. Thus, by setting the size L of the bottom of the concave portion to 80 nm or more, the nuclei adhering to the side surface of the convex portion can be suppressed, and the crystal quality is improved. From the above, the upper limit value of the duty is determined, and is calculated as duty? 1 - (Y / Pave). Here, it is preferable that Y = 50 nm, and Y = 80 nm is most preferable. That is, it is preferable to satisfy the range of the duty lower than the curve shown in Fig. 9 is a graph showing the relationship between the average interval (Pave) of the concavo-convex structure (A) of the patterned wafer for LED 1 according to the present embodiment and the duty. 9, the abscissa represents the average interval (Pave) of the concavo-convex structure (A), and the ordinate represents the duty. In FIG. 9, the plot of black triangle () is the preferred case where the Y of formula 1 - (Y / Pave) is 50 nm, and the plot of black diamond () . On the other hand, with respect to the expression of the above-described duty, the dimension of Pave is nanometer.

The nucleation of the semiconductor layer becomes good as described above by satisfying the concavoconvex structure A in the range below the curve shown in Fig. Here, since the rotational shift angle? Is satisfied, the nucleation is good, the coalescence frequency of the grown semiconductor layers is high, and the coalesced portions can be dispersed, so that the internal quantum efficiency IQE, The high semiconductor layer can be obtained.

The crack, which is one of the effects of the rotation shift angle? Described above, will be described in more detail including the results of actual examination. First, a C-face sapphire wafer of 6 inches in diameter was used as a wafer for an LED. The main surface of the LED wafer was processed using a nano-processed sheet method described later to obtain a patterned wafer 1 for LED. Here, the rotation shift angle? Was controlled by tilting the nano-processed sheet from the normal line by inclining with reference to the normal to the orientation flat of the LED wafer. In other words,? =?. In addition, since the accuracy of resolution of the bonding is 1 to 2 degrees, the rotational shift angle (?) Includes an error of? 1 占. The arrangement of the concavo-convex structure (A) of the pattern wafer for LED (1) That is, the concavo-convex structure (A) is a six-fold symmetrical arrangement. In addition, the shape of the convex portion of the concavoconvex structure A was confirmed by scanning electron microscope observation of the cross section of the pattern wafer 1 for LED. The results are shown in Fig. 10A is a scanning electron micrograph showing an example of the cross-sectional shape of the convex portion of the concavo-convex structure A according to the present embodiment. 10B is a schematic diagram showing a part of FIG. 10A. It can be seen from Fig. 10 that there is no flat table top at the top of the convex portion, and curved lines slightly upward convex cross each other, thereby forming the cross-sectional shape of the convex top portion.

A 10 nm low-temperature buffer layer was formed on the patterned wafer (1) for LED fabricated. Subsequently, gallium nitride was deposited as a non-doped first semiconductor layer to be described later to form a facet. This facet was taken out of the chamber during the formation of the facets, and the surface of the gallium nitride film was observed with a scanning electron microscope. The results are shown in Fig. 11 is a scanning electron micrograph showing an example of the undoped first semiconductor layer according to the present embodiment. Figure 11 is a view of 2500 times magnification. It can be seen from Fig. 11 that the relationship between the plurality of facets formed and the gallium nitride layer is random. Here, FIG. 12 shows an image obtained by enlarging the cracks observed in the observation image of FIG. 11. 12A is a scanning electron micrograph showing a crack. 12B is a schematic diagram showing a part of FIG. 12A. It can be seen from Fig. 12 that cracks are generated in the direction perpendicular to the sides of the hexagonal gallium nitride layer at the positions opposite to the side of the hexagonal shape when attention is paid to the hexagonal opening portions of the growing gallium nitride . Cracks in this specification refer to such nanoscale cracks.

As the number of cracks was measured and quantified from the scanning electron microscopic image, as the rotation shift angle? Was changed to 0 占 2 占 7.5 占 15 占 22.5 占 and 30 占, 72 × 10 was changed to ⁹ / ㎠, 70 × 10 ⁹ / ㎠, 57 × 10 ⁹ / ㎠, 51 × 10 ⁹ / ㎠, 43 × 10 ⁹ / ㎠ and 41 × 10 ⁹ / ㎠ . That is, it was found that as the rotational shift angle? Increases, the crack density decreases. Further, when this reduction degree is compared, it is found that the decrease in the crack density is remarkable in the region where the rotation shift angle? Is more than 2 degrees. This is because the control of the rotation shift angle? Is about 占 1 占 and the rotation of the concavo-convex structure (A) of a slight degree of 1 to 2 占 is caused by the error of the film formation control from the viewpoint of the gallium nitride film do.

Then, the influence on the semiconductor layer due to the reduction of the crack was confirmed. A non-doped first semiconductor layer was formed on the sample subjected to the crack measurement, and the surface of the gallium nitride layer was planarized. In this state, the X-ray rocking curve method of inflation was applied to obtain a rocking curve, and the full width at half maximum (FWHM) was evaluated. The results are shown in Fig. 13 is a graph showing the relationship between the crack density and the half width (FWHM) of the rocking curve. 13, the axis of abscissas is the crack density, and the axis of ordinates is the half width (FWHM) of the rocking curve. From Fig. 13, it can be seen from Fig. 13 that the crack density is 102 x 10 ⁹ / cm 2, 71 10 ⁹ / cm 2, 56 10 ⁹ / cm 2, 52 10 ⁹ / cm 2, 44 10 ⁹ / As the FWHM decreases to ⁹ / cm 2, the FWHM decreases to 673, 671, 644, 630, 600 and 590. Particularly, in the region where the crack density is 70 × 10 ⁹ / cm 2 or less, the numerical value of the FWHM is effectively reduced. That is, it has been found that the crystal uniformity of the semiconductor layer is improved by decreasing the crack density, particularly by setting the crack density to 70 × 10 ⁹ / cm 2 or less.

Further, an n-type gallium nitride layer was formed as a first doped semiconductor layer on the sample used for the measurement of the rocking curve. A cathode luminescence (CL) evaluation was performed on this sample. Here, CL is a method of evaluating light generated by irradiating an electron beam, and is an evaluation equivalent to a transition from the bottom of the conduction band to the vicinity of the top of the valence band. Therefore, the determination information such as crystal defects, carrier concentration, stress, . The results are shown in Fig. 14 is a graph showing the relationship between the crack density and the dark density obtained from the image obtained by the evaluation of the cathode luminescence (CL). In Fig. 14, the abscissa indicates the density of cracks, and the ordinate indicates the density of darkness obtained from the image obtained by CL. As can be seen from Fig. 14, as the crack density decreases to 102 x 10 ⁹ / cm 2, 71 10 ⁹ / cm 2, 52 10 ⁹ / cm 2, 44 10 ⁹ / cm 2 and 40 10 ⁹ / , The CL darkening densities decrease to 5.51 x 10 ⁸ / cm 2, 5.52 x 10 ⁸ / cm 2, 4.89 × 10 ⁸ / cm 2, 4.44 × 10 ⁸ / cm 2 and 4.34 × 10 ⁸ / cm 2. Particularly, in the region where the crack density is 71 × 10 ⁹ / cm 2 or less, the value of the CL darkness density is effectively reduced. In other words, it can be seen that the crystal quality is greatly improved by reducing the crack density to 71 × 10 ⁹ / cm 2 or less.

From the above, it is possible to effectively reduce the crack density by exceeding the rotation shift angle [theta] by more than 0 DEG, preferably by 2 DEG. Thus, the crystal uniformity of the undoped first semiconductor layer is effectively improved. Further, the crystal quality of the doped first semiconductor layer can be improved. These improvements in crystal uniformity and crystal quality are factors that improve the internal quantum efficiency (IQE) and improve the long-term reliability of the semiconductor light emitting device. Therefore, by controlling the crack density by the rotation shift angle? , It is estimated that the light emitting performance and long-term reliability of the semiconductor light emitting device can be improved at the same time.

On the other hand, the above result shows that the same tendency can be obtained with respect to the shape of the convex portion shown in Fig. 15 although the magnitude of the absolute value of the numerical value is changed. 15 is a scanning electron micrograph showing an example of the cross-sectional shape of the convex portion of the concavo-convex structure A according to the present embodiment. The scanning electron microscope image shown in Fig. 15 is an observation image of the cross section of the patterned wafer 1 for LED. From Fig. 15, it can be seen that the shape of the convex portion used in the examination is a lens type, so that the curve of the convex portion crossing each other slightly crosses the shape of making the cross-sectional shape of the top portion. From this, it is considered that the effect of the above-described rotational shift angle (?) Described above can be realized by adopting the convex portion which is a corner portion having a radius of curvature of more than 0.

It has already been described that it is important that the convex portion of the concavoconvex structure A is a corner having a radius of curvature of more than 0. Here, when there is a flat portion at the convex portion of the concavoconvex structure A, in other words, even in the case of the table top structure, the disadvantage of the table top structure can be suppressed by combining with the rotational shift angle? It was suggested. First, the disadvantage of the table top structure is that it is difficult to reduce the potential by the semiconductor layer grown on the table top. That is, it is difficult to reduce the dislocation density of the semiconductor layer, and the internal quantum efficiency IQE tends to decrease. Here, although the mechanism is not clear, it is known that the reduction amount of the internal quantum efficiency (IQE) by the table top tends to be small in the range where the rotation shift angle? Is more than 10 ° (180 / n) I could. That is, the degree of reduction of the internal quantum efficiency IQE is reduced. On the other hand, in the case of the table top structure, the light scattering property with respect to the emitted light is improved by the large volume of the convex portion, so that the light extraction efficiency (LEE) can be further improved. As a result, by using the pattern wafers 1 for LEDs including the concavo-convex structure A in which the top of the convex portion is in the form of a table top and the rotational shift angle? Is more than 10 ° (180 / n) High-efficiency LEDs can be manufactured. This effect was more remarkable in the region where the rotation shift angle was not less than 15 degrees (180 / n) degrees. The size of the table top was tested to be 20 nm, 50 nm, 100 nm, 300 nm, and 500 nm. In the case of 300 nm and 500 nm, Was improved. This is presumably due to the fact that the re-diffusion distance of the nuclei in the RAMP process after the formation of the low-temperature buffer layer is about 80 nm. From the above, it has been suggested that the angular portion with the radius of curvature of more than 0, which is referred to in this specification, is not inconsistent even if the size of the table top is 100 nm or less. As described above, convex portions of the concavoconvex structure A are formed by the corner portions having a radius of curvature of more than 0 including the table top size of 100 nm or less, and the rotational shift angle? ) ° or less, preferably 15 ° or more and (180 / n) ° or less, is used as the LED pattern wafer 1, the LED of high efficiency can be easily manufactured.

From the above, it is possible to reduce the cracks to the semiconductor layer by controlling the shape of the convex portion of the concave-convex structure A and the rotation shift angle?. In addition, the internal quantum efficiency (IQE) can be increased, and the emission characteristic of the semiconductor light emitting element can be improved. Further, the long-term reliability of the semiconductor light emitting device can be improved. Here, the external quantum efficiency (EQE) of the LED can be further improved by improving the light extraction efficiency (LEE) which is another major problem of the LED by the concavo-convex structure (A). The reason why the light extraction efficiency (LEE) of the LED is kept low is because the semiconductor layer having a high refractive index is sandwiched by a medium having a relatively low refractive index. In this case, the light is guided through the medium having a high refractive index. By this waveguide, the emitted light is absorbed and lost as heat before being extracted to the outside of the LED. That is, in order to improve the light extraction efficiency (LEE), it is necessary to disturb the mode of emitted light to be guided. Here, it is understood that the duty needs to be larger than a predetermined value in consideration of the fact that the propagation direction of the emitted light is effectively disturbed and the waveguide mode is broken to improve the light extraction efficiency (LEE). This was calculated by the three-dimensional RCWA method and the two-dimensional FDTD method. That is, it is preferable that the duty ≥ (3.47 × 10 ^-8 ) Pave ² + Z is satisfied. Here, since the mode number and the diffraction intensity of the optical diffraction by the concavo-convex structure (A) increase in the order of Z, 0.5, 0.6 and 0.65, the effect of disturbing the waveguide mode is increased and the light extraction efficiency (LEE) is also improved . That is, it is preferable that the range of the duty that is located above the curve shown in Fig. 16 is satisfied. On the other hand, in the above equation for determining the duty to further improve the light extraction efficiency (LEE), the dimension of Pave is nanometer.

16 is a graph showing the relationship between the average spacing (Pave) of the concavo-convex structure A of the patterned wafer 1 for LED and the duty according to the present embodiment. 16, the abscissa indicates the average interval (Pave) of the concavo-convex structure (A), and the ordinate indicates the duty. In FIG. 16, a plot of black triangles () is the preferred case where Z of formula D &gt; (3.47 x 10 ^-8 ) Pave ² + Z is 0.5 and plots of black diamonds (x) And the plot of the black circle (&amp; cir &amp;) is the most preferable case where Z is 0.65.

When the concavoconvex structure A is satisfied in the range of the curve or more shown in Fig. 16, the intensity and mode number of the optical diffraction increase as described above, and the light extraction efficiency LEE is improved.

(A) satisfying the range of the rotational shift angle (?) And satisfying the relation of the average interval (Pave) and the duty shown in FIG. 17 as described above and the internal quantum efficiency IQE) can be manufactured, the efficiency of light emission itself is improved. At the same time, since the light emitted efficiently is extracted to the outside of the LED by the improved light extraction efficiency (LEE), the external quantum efficiency (EQE) becomes large. That is, an LED chip having a high external quantum efficiency (EQE) can be manufactured with a low defect efficiency. In addition, the crack density of the semiconductor layer in the LED chip is also reduced, so that the service life is prolonged.

17 is a graph showing the relationship between the average spacing (Pave) of the concavo-convex structure (A) of the patterned wafer for LED 1 according to the present embodiment and the duty. 17, the abscissa represents the average interval (Pave) of the concavo-convex structure (A), and the ordinate represents the duty. In FIG. 17, plots of black triangles (), black diamonds () and black circles () are curves determined from the viewpoint of improvement of light extraction efficiency (LEE), and the previously described duty ≥ (3.47 × ^10-8 ) And Z of the equation expressed by Pave ² + Z are 0.5, 0.6, and 0.65, respectively. On the other hand, a plot of an asterisk and a black square (I) is a curve determined from the viewpoint of internal quantum efficiency (IQE) and cracks, and Y of the equation expressed by the duty ≤1- (Y / Pave) 50 nm and 80 nm. That is, if the concavo-convex structure A satisfies the range of 1- (Y / Pave)? Duty? (3.47 占^10-8 ) Pave ² + Z, the semiconductor light emitting device having the above- And the like.

&Lt; Condensation structure (A) >

Next, the concavo-convex structure A will be described. The convex portion of the concavo-convex structure (A) is constituted by a corner portion whose convex portion has a radius of curvature of more than 0. Here, each part having a radius of curvature of more than 0 means that the upper surface of the convex portion of the concave-convex structure A is formed of a curved surface. For example, a conical body, a lens-shaped body, a dome-shaped body, a cone-shaped body, and a shell body having rounded ends may be cited and include the shape shown in Fig.

As described above, since the convex portion of the concavo-convex structure A of the pattern wafer 1 for LEDs is constituted by the corner portions having a radius of curvature greater than 0, improvement of the internal quantum efficiency IQE and suppression of cracks can be realized at the same time. In addition, when forming the semiconductor layer on the concavo-convex structure A of the patterned wafer for LED 1, the semiconductor layer can be preferentially grown from the bottom of the concave portion of the concave-convex structure A. In other words, it is possible to suppress the growth of the semiconductor layer from above the convex portion of the concave-convex structure A. That is, the initial conditions for the attachment and growth of the nuclei of the semiconductor layer to the concave portions of the concave-convex structure (A) and the coalescence of the growing semiconductor layers can be provided.

Here, when the concavoconvex structure A satisfies the previously described rotational shift angle?, The semiconductor layer is preferentially grown from the concave portion of the concave-convex structure A and the coalescence of the growing semiconductor layers is effectively dispersed It is possible to reduce the dislocation and also to suppress the cracks. This effect becomes conspicuous by satisfying the relationship between the rotation shift angle? And duty as described with reference to Fig. It becomes more significant by satisfying the relationship between the duty and the average interval (Pave) described with reference to FIG. Moreover, the light extraction efficiency LEE can be improved at the same time by satisfying the relationship of the average interval Pave and the duty described with reference to FIG.

As described above, since the convex portion of the concavo-convex structure A is constituted by the corner portion having the radius of curvature of more than 0, the range of the rotational shift angle? Is satisfied and the internal quantum efficiency IQE is effectively improved, Cracks can be suppressed.

From the viewpoint that the effect based on the above-mentioned principle is well expressed and the improvement of the internal quantum efficiency (IQE) and the reduction of the crack are both made better, the convex portion of the concave- convex structure (A) It is preferable that the diameter becomes smaller along the direction toward the center. This makes it possible to reduce the stress generated in the vicinity of the top of the convex portion of the concavo-convex structure A toward the semiconductor layer. That is, since the stress applied from the concavo-convex structure A to the semiconductor layer to be grown can be reduced, the residual stress generated in the semiconductor layer can be reduced. As a result, the crack suppressing effect on the semiconductor layer becomes large.

It is preferable that the convex portion side surface portion connecting the convex portion top portion and the concave portion bottom portion has an inclination angle of two or more steps and a radius of curvature of the point where the inclination changes is more than 0 and forms a curved surface. In this case, before the stable growth surface of the semiconductor layer reaches the top of the convex portion, the strain applied to the semiconductor layer can be made to have a gradient, so that the crack suppressing effect becomes greater.

Furthermore, it is preferable that the concavoconvex structure A is constituted by a plurality of independent convex portions and a continuous concave portion, because the above effects can be further exerted. In this case, the size of the bottom portion of the concave portion can be relatively increased as compared with the case where the concavoconvex structure A is formed by a plurality of independent concave portions and continuous convex portions. That is, since the growth property of the semiconductor layer from the concave bottom portion described above can be made better, the internal quantum efficiency IQE can be improved and the crack can be suppressed.

Further, the bottom of the concave portion has a flat surface, whereby the effect of improving the internal quantum efficiency IQE is further enhanced. This is because the initial state of growth of the semiconductor layer growing at the bottom of the concave portion of the concave-convex structure A can be well maintained, and the effect of the potential dispersion by the concave-convex structure A can be further exerted.

The average interval Pave of the concavo-convex structure A is not particularly limited because it can be selected from the viewpoint of balance between the internal quantum efficiency IQE and the light extraction efficiency LEE. For example, 200 nm, 300 nm, The patterned wafer 1 for LEDs having the concavo-convex structure (A) of 500 nm, 700 nm, 1200 nm, 1500 nm, 2500 nm and 5000 nm was manufactured and the above-described effects were confirmed. From the viewpoint of effectively improving the external quantum efficiency (EQE) of the LED, it is necessary to necessarily improve the internal quantum efficiency (IQE). From this viewpoint, it is preferable that the average interval (Pave) satisfies 50 nm? Pave? 1500 nm. When the average spacing Pave is 1500 nm or less, the density of the concave portion of the concavoconvex structure A is improved, and the frequency of incorporation of the growing semiconductor layers as described above can be increased. In other words, since the potential in the semiconductor layer can improve the frequency of changing its traveling direction, the effect of reducing the potential is increased, thereby effectively improving the internal quantum efficiency IQE. On the other hand, when the average spacing Pave is 50 nm or more, the size of the concave bottom portion of the concave-convex structure A contributing greatly to the initial growth of the semiconductor layer can be ensured. As a result, the nucleation of the semiconductor layer at the bottom of the concave portion of the concave-convex structure A can be satisfactorily maintained. Therefore, the effect of suppressing cracks in the semiconductor layer is increased as the array axis A of the concavoconvex structure A shifts within a predetermined range by the rotational shift angle?. Particularly, from the viewpoint of satisfactorily maintaining the nucleation and nucleus growth of the semiconductor layer, the average interval (Pave) is preferably 100 nm or more, more preferably 200 nm or more, and most preferably 300 nm or more.

It is also possible to improve the density of the concave portion of the concave-convex structure A, improve the frequency of incorporation of the growing semiconductor layers, disperse the coalescing portion, improve the internal quantum efficiency IQE effectively, , It is preferably 1200 nm or less, more preferably 1000 nm or less, and most preferably 950 nm or less. On the other hand, by satisfying the relation between the average interval (Pave) and the duty as already described with reference to Figs. 9, 16 and 17, the crack suppressing effect and the internal quantum efficiency (IQE) LEE) can be further improved.

<Average interval (Pave)>

The average spacing Pave is measured at substantially the same site as the sample used when calculating the average height (Have) of the concavo-convex structure described in the following << semiconductor light emitting device >>. Alternatively, the patterned wafer for LED 1 can be measured. The average interval Pave of the concavo-convex structure A is determined according to the following definition irrespective of the arrangement of symmetry of n times in the concave-convex structure A. [ A distance P _A1B1 between the center of a convex portion A1 and the center of the convex portion B1 closest to the convex portion A1 is defined as a distance P. The average interval (Pave) is calculated according to the following definition. (1) Any ten convex portions A1, A2, ... Select A10. (2) Measure the interval P _AMBM between the convex portion AM and the convex portion (BM) closest to the convex portion AM (1 M 10). (3) For the convex portions A1 to A10, the interval P is measured as in (2). (4) The average values of the intervals P _A1B1 to P _A10B10 are defined as an average interval (Pave). On the other hand, the above definition does not depend on the n-fold symmetry of the concavo-convex structure (A). That is, even when a plurality of convex portions are isolated by a continuous concave portion, even if a plurality of grass-shaped bodies are line-and-space structures isolated by a plurality of grass-shaped bodies, an arrangement in which an orthogonal array is uniaxially or biaxially stretched . On the other hand, in the case of a structure in which a plurality of concave portions are spaced apart by a continuous convex portion, the center of the convex portion is rewritten as the center of the concave opening portion, whereby the average interval Pave can be defined. In addition, when the length of the cumulus shaped body is very long and the end portion can not be observed by observing a scanning electron microscope or an atomic force microscope, or when there is no end portion, the center of the convex portion in these observation images , And is used as the center of the convex portion.

&Lt; Average width (? Ave) of the bottom of the convex portion>

The average width [phi] ave is measured at approximately the same site as the sample used when calculating the average height (Have) of the concavo-convex structure explained in the following << semiconductor light emitting device >>. Alternatively, it is measured with respect to the patterned wafer 1 for LED. The average width (? Ave) of the concave-convex structure (A) is determined according to the following definition irrespective of the arrangement of symmetry of the concave-convex structure (A) n times. The distance? _A1 when the distance XY between a point X on the outer periphery of the contour and the other point Y on the outer periphery of the contour becomes the maximum in the contour shape of the bottom portion of the convex portion _{A1 is set} to be the bottom Is defined as the width (?) Of the negative. The average width (? Ave) is calculated according to the following definition. (1) Any ten convex portions A1, A2 ... Select A10. (2) Measure the width? _AM of the bottom of the convex portion with respect to the convex portion AM (1? M? 10). (3) Regarding the convex portions A1 to A10, the width? Of the bottom portion of the convex portions is measured in the same manner as in (2). (4) The average value of the upper and lower limits of the widths _A1 to _A10 of the bottom of the convex portion is defined as the average width (? Ave). On the other hand, when the aspect ratio of the contour of the bottom of the convex portion is 1.5 or more, the width? Of the bottom of the convex portion is the shortest distance between the point X and the other point Y on the outer periphery of the contour of the bottom portion of the convex portion Is defined.

<Duty>

The duty is defined as the ratio (? Ave / Pave) of the average width (? Ave) to the average spacing (Pave).

&Lt; Arrangement of concave and convex structure (A)

The patterned wafer 1 for LED according to the present embodiment has the concavo-convex structure A described above on a part or the entire surface of the patterned wafer 1 for LED. On the other hand, the more detailed shape and arrangement of the concavo-convex structure (A), the manufacturing method and materials will be described in the following << semiconductor light emitting device >>. That is, even if the front surface of the LED pattern wafer 1 is covered with the concavo-convex structure A described above, a concave-convex structure A may be formed on a part of the surface of the LED pattern wafer 1. [ In the following description, the concavo-convex structure A is referred to as a concavo-convex structure G and the concavo-convex structure that does not correspond to the concavo-convex structure A is referred to as a concavo-convex structure B.

The patterned wafer 1 for LEDs has a concavo-convex structure G at least in part. That is, the surface of the patterned wafer 1 for LED may be partially or wholly covered by the concavo-convex structure G. Here, a region not covered by the concavo-convex structure G is called a &quot; non-G region &quot;. Here, the non-G region is composed of the uneven structure B and / or the flat portion. Even when a non-G region is formed on a part of the surface of the patterned wafer for LED 1, since the effect described above can be exhibited in the region covered with the uneven structure G, the internal quantum efficiency IQE ) Can be formed. Further, the light extraction efficiency LEE can be improved at the same time by satisfying the relationship between the average interval Pave and duty as described with reference to Figs. 16 and 17. Fig.

(?) If the concavo-convex structure G formed on the surface of the pattern wafer 1 for LED is formed at least in a region having an area of 10 Pave 占 10 Pave using the average spacing Pave, So that it is preferable. That is, the concavo-convex structure G may be formed in the pattern wafer 1 for LEDs at least in the range of 10 Pave × 10 Pave. That is, for example, when the surface of the patterned wafer 1 for LED is observed using a scanning electron microscope or an atomic force microscope, a region having an area of 10 Pave × 10 Pave is formed by the concave- . In particular, it is preferable to satisfy the ratio or size of the concavo-convex structure G described below by totaling the concavo-convex structure G filling the region having the area of 10 Pave 占 10 Pave. That is, a range having an area of 10 Pave × 10 Pave is formed by the concavo-convex structure (G), and a plurality of such ranges can be provided. Particularly, by satisfying 20 Pave × 20 Pave or more, and more preferably, 25 Pave × 25 Pave or more, it is possible to improve the adhesion of nuclei of the semiconductor layer by the uneven structure G, the nucleation, Which is remarkable. Also in this case, it is preferable that the ratio or the size of the concavo-convex structure G described below is satisfied by the totalization of the concavo-convex structure G. Further, since the region having an area of 50 Pave 占 50 Pave or more, more preferably 75 Pave 占 7 PaveP or more is constituted by the concavoconvex structure G, even in the region G adjacent to the region covered with the concavoconvex structure G, Nucleation of the semiconductor layer, nucleation, and coalescence of the growing semiconductor layers become favorable, and cracks are suppressed and the internal quantum efficiency (IQE) is improved. This effect is exerted more than 100 Pave × 100 Pave, 150 Pave × 150 Pave or more, and 450 Pave × 450 Pave or more. Also in these cases, it is preferable that the ratio or the size of the concavo-convex structure G described below is satisfied by the totalization of the concavo-convex structure G.

(β) When a non-G region is formed in a region covered with the uneven structure G, the ratio of the non-G region is preferably not more than 1/5 of the unevenness structure G. Thus, the effect of the concavo-convex structure G can be exhibited. More preferably 1/10 or less, more preferably 1/25 or less, and most preferably 1/50 or less from the viewpoint of exerting the same effect. On the other hand, by satisfying 1/100 or less, it is possible to further improve the suppression of cracks and the improvement of the internal quantum efficiency (IQE). Particularly, satisfying 1/500 or less, more preferably 1/1000 or less, is preferable because the uniformity of emitted light emitted from inside the LED is improved. From the same viewpoint, it is preferably 1/10000 or less, more preferably 1/100000 or less, and more preferably 1/1000000 or less. On the other hand, the lower limit value is not particularly limited, and it is preferable that the smaller the value, the closer the value is to 0, the more remarkable the effect of the concave-convex structure G becomes.

(γ) The ratio of the concavo-convex structure G to the surface of the pattern wafer for LED 1 may vary depending on the external shape and size of the LED chip, but if it is 0.002% or more, So that it is possible to exhibit the effect. Particularly, since the LED pattern wafers 1 are provided with the concavo-convex structure G of not less than 0.02%, and more preferably not less than 0.2%, the dispersibility of dislocations in the semiconductor layer is improved, so that the uniformity of the internal quantum efficiency IQE . In addition, since the dispersibility of the coalesced portion of the growing semiconductor layer is improved, the crack suppressing effect is increased. In addition, by including the patterned wafer 1 for LED in the recessed and projected structure G of 2.3% or more, and more preferably 10% or more, the above effects can be further exerted. In addition, when the ratio is 20% or more, the in-plane uniformity of the semiconductor layer to be formed on the patterned wafer 1 for LED is improved, and the improvement degree of the internal quantum efficiency IQE is equalized in the plane of the patterned wafer 1 for LED , The yield of obtaining a highly efficient LED chip is improved. From the viewpoint of exerting this effect, the concavoconvex structure G preferably includes 30% or more, more preferably 40% or more, and most preferably 50% or more. In addition, when the concavoconvex structure G includes 60% or more of the concavoconvex structure G, propagation of the effect of the concave and convex structure G on the non-G area is improved. That is, since the effect of the nucleation of the semiconductor layer by the concavo-convex structure G, the nucleation, and the effect of the coalescence of the growing semiconductor layers is propagated to the non-G regions, the improvement of the internal quantum efficiency (IQE) And the effect of crack improvement is also increased. From the viewpoint of achieving the above effect, the uneven structure G is preferably contained in an amount of 70% or more, more preferably 80% or more, and most preferably 90% or more. On the other hand, when the surface of the patterned wafer for LED 1 is substantially filled with the concavo-convex structure G when the concave-convex structure G is contained in an amount of 98% or more, in other words, Is equalized in the plane of the wafer 1, so that the degree of improvement of the internal quantum efficiency IQE is promoted. That is, the characteristic distribution curve of a plurality of LED chips made of an epitaxial wafer for LED becomes sharper.

(隆) The concavo-convex structure G included in the surface of the pattern wafer 1 for LED is preferably 0.0025 x 10 ^-6 m 2 or more. By satisfying this range, the light emission output of the LED chip becomes large. This can be determined from the collision probability between the light emitting beam guiding the inside of the LED chip and the concavo-convex structure G, though it may vary depending on the size and appearance of the LED chip. In addition, when this range is satisfied, the initial growth of the semiconductor layer to be formed on the concave-convex structure G becomes good. That is, the nucleation of the semiconductor layer and the rate of nucleation can be lowered by the uneven structure G, so that the potential is reduced and the internal quantum efficiency IQE is improved. The concavo-convex structure G included in the surface of the LED pattern wafer 1 is preferably 0.01 x 10 ^-6 m2 or more, more preferably 0.04 x 10 ^-6 m2 or more , And most preferably 0.09 x 10 ^-6 m 2 or more. Further, since the in-plane uniformity of the semiconductor layer to be formed on the patterned wafer 1 for LED is improved by 0.9 × 10 ^-6 m 2 or more, the rate at which cracks are suppressed is increased, and the yield of obtaining the semiconductor light emitting device is improved. From the viewpoint of exerting the above effect, it is more preferably 9 10 ^-6 m 2 or more, and most preferably 90 10 ^-6 m 2 or more. On the other hand, the transmittance of the concavo-convex structure (G) effect on the non-G region is improved by setting it to 900 × 10 ^-6 m 2 or more, more preferably 1.8 × 10 ^-3 m 2 or more. That is, by propagating the effect that the adhesion of the nuclei of the semiconductor layer by the concavo-convex structure G, the growth of the nuclei, and the coalescence of the growing semiconductor layers can appropriately be propagated to the G region, the internal quantum efficiency The degree of improvement of IQE and the degree of reduction of cracks are also increased. In particular, a good LED can be obtained even when the outer edge portion of the patterned wafer for LED 1 is used, by using 3.6 x 10 ^-3 m 2 or more, more preferably 7.5 x 10 ^-3 m 2 or more. One or more of the concavo-convex structure G that satisfies the size of the concavo-convex structure G as described above is formed on the surface of the patterned wafer 1 for LED, whereby a substrate for LEDs capable of manufacturing a high- Can be obtained. On the other hand, it is also possible to form a plurality of concave-convex structures G satisfying the size of the concavo-convex structure G described above. In this case, at least one concave-convex structure G satisfies the above-mentioned size. In particular, it is preferable that 50% or more of the number of the concavo-convex structures (G) satisfy the above-described range, and 100% is most preferable to the above range.

The arrangement relationship of the uneven structure (G) and the non-G region is not particularly limited as long as the above content is satisfied. The arrangement relationship between the concavoconvex structure G and the non-G area is exemplified by the arrangement described below when the concave-convex structure G and the non-G area are considered. On the other hand, the concavo-convex structure G is an assembly of the concavo-convex structure G satisfying at least one of?,?,? And? Described above, that is, the concavo-convex structure G region. 18, when the non-G region 502 is formed in the uneven structure (G) region 501, the non-G region 502, when the ratio described in the above-mentioned? Is satisfied, , And regularity and irregularity are not limited. 18 is an explanatory view showing the relationship between the concave-convex structure G and the non-G area in the patterned wafer 1 for LED according to the present embodiment. 18A and 18B, a plurality of non-G regions 502 having an irregular outline are arranged in the uneven structure (G) region 501. 18C, a grating-type non-G region 502 is formed in the concavo-convex structure (G) region 501. 18D, a plurality of substantially non-G regions 502 are formed in the concavo-convex structure (G) region 501. As shown in Fig.

The contour shape produced by the concavo-convex structure (G) region 501 is not particularly limited. That is, the interface shape between the uneven structure (G) region 501 and the non-G region 502 is not limited. For example, the interface shape between the uneven structure (G) region 501 and the non-G region 502 is an n-type (n? 3) or a non-n-type (n? 3) And the like. The n-square may or may not be an n-square.

Fig. 19 is a schematic diagram showing an outline shape formed by the concavo-convex structure G region in the patterned wafer 1 for LED according to the present embodiment. For example, a quadrangular shape may be a quadrilateral (square), a rectangle, a parallelogram, a trapezoid, or a shape in which at least one pair of opposed sides of the quadrilateral are non-planar. Incidentally, when n is 4 or more in the n-type (n? 3), it includes a shape as shown in Figs. 19A to 19D. 19A is a quadrangle, Fig. 19B is a hexagon, Fig. 19C is an octagon, and Fig. 19D is a hexagon. The non-n-angular shape may be a structure including angular portions having a radius of curvature of more than 0, for example, a circle, an ellipse, a shape having the above-described n-angular rounding (a shape in which the radius of curvature of the n- (N &amp;ge; 3) described above including a rounded corner (a region having a radius of curvature of more than 0). For this reason, for example, the shapes illustrated in Figs. 19E to 19H are included. On the other hand, the outline shape of the non-G region can adopt a shape exemplified as an outline shape of the set of the concave-convex structures G described above.

First, a state in which the uneven structure (G) region 501 is surrounded or interposed between the non-G regions 502 can be mentioned. 20 is a schematic plan view showing a state in which the patterned wafer 1 for LED according to the present embodiment is observed from its surface. 20A to 20F show a state in which the concavo-convex structure (G) region 501 is surrounded by the non-G region 502. Fig. As shown in Fig. 20A, a concave and convex structure G area 501 may be formed on the surface of the pattern wafers 1 and 500 for the LED, and the outside thereof may be constituted by the non-G area 502. [ The concave and convex structure (G) region 501 preferably satisfies the above-described ratio. In addition, it is preferable that the concavo-convex structure (G) region 501 satisfies the above-described size. As shown in FIG. 20B or 20C, a plurality of concavo-convex structure (G) regions 501 are arranged on the surface of the patterned wafer for LED 1 (500) And the outside of the concave and convex structure (G) region 501 may be filled with the non-G region 502. [ In this case, it is preferable that the ratio described above is satisfied with respect to the total area of the concavo-convex structure (G). Further, it is preferable that at least one concavo-convex structure G satisfies the previously described size, and it is more preferable that all the concavo-convex structure G satisfy the previously described size. When several concave and convex structures G are formed, the concave and convex structure G regions 501 may be regularly arranged as shown in Fig. 20C or irregularly arranged as shown in Fig. 20D. Examples of the regular arrangement include a rectangular array, a hexagonal array, an arrangement in which these arrangements are uniaxially stretched, an arrangement in which these arrangements are stretched in a biaxial direction, and the like. 20A to 20D, the outline shape of the concavo-convex structure (G) region 501 is described as a circle, but a shape of indefinite shape as shown in Fig. 20E may also be employed. For example, the outer shape of the concavo-convex structure (G) region 501 may be a shape having an n-type (n? 3), an angled n-type (n? 3), a circle, an ellipse, a linear, a star, . 20F, the concavo-convex structure G region 501 is surrounded by the non-G region 502, the outer circumference thereof is surrounded by the concavo-convex structure G region 501, The non-G area 502 may be surrounded. 20A to 20D, the concavo-convex structure (G) region 501 is described as being circular, but the contour shape formed by the concavo-convex structure (G) region 501 is not limited to the shape described with reference to Fig. 19 .

21 is a schematic plan view showing a state in which the patterned wafer 1 for LED according to the present embodiment is observed from the surface. 21 shows a case where the concavo-convex structure (G) area 501 is sandwiched by the non-G area 502. Fig. As shown in Figs. 21A and 21B, even when the uneven structure G region 501 is formed on the surface of the LED pattern wafers 1 and 500 and the outer side is constituted by the non-G region 502 good. It is preferable that the concave-convex structure G satisfies the above-mentioned ratio. In addition, it is preferable to satisfy the size already described. As shown in Fig. 21C, a plurality of concavo-convex structure (G) regions 501 are disposed on the surface of the pattern wafers 1 and 500 for LED, The outside of the structure (G) region 501 may be filled with the non-G region 502. [ In this case, it is preferable that the ratio described above is satisfied with respect to the total area of the concavo-convex structure (G). Further, it is preferable that at least one concavo-convex structure G satisfies the previously described size, and it is more preferable that all the concavo-convex structure G satisfy the previously described size. Also, as shown in FIG. 21D, the concavo-convex structure (G) region 501 may be arranged so as to continuously contain the non-G region 502 therein. In this case, it is preferable that the ratio described above is satisfied with respect to the area of the concavo-convex structure G. It is also preferable that the concavo-convex structure G satisfies the size already described. The interface shape between the uneven structure (G) region 501 and the non-G region 502 may be straight or curved as shown in Fig. 21E. As the shape of the uneven structure (G) region 501, a linear shape, a lattice shape, a mesh shape, or the like can be given. 21F, the uneven structure G region 501 is sandwiched by the non-G region 502 and the outer periphery of the uneven structure G region 501 is sandwiched by the uneven structure G region 501, And the outer periphery thereof may be interposed between the non-G regions 502. On the other hand, in Fig. 21, the outline formed by the concavo-convex structure (G) area 501 is described as linear or substantially linear, but the shape described with reference to Fig. 19 can be adopted.

The concavo-convex structure G may be formed even if the concavo-convex structure G region 501 has a plurality of concavoconvex structure G regions 501, And may be different for each region 501.

Regarding the arrangement relationship between the concavo-convex structure (G) area 501 and the non-G area 502 described above, the concavo-convex structure (G) area 501 is surrounded by the non- The case where the structure (G) region 501 is sandwiched in the non-G region 502 can be mixed.

As shown in Figs. 20F and 21F, a non-G region 502 is formed outside the first uneven structure (G) region G1 and a second uneven structure G The second uneven structure G region 501 (G2) may be discontinuous when a non-G region 502 is formed on the outer side of the region 501 (G2).

The non-G region may be constituted by the concavo-convex structure B or by the flat portion, or by the concave-convex structure B and the flat portion.

In the above description, the outer shapes of the pattern wafers 1 and 500 are all rectangular, but the outer shape of the pattern wafers 1 and 500 for the LED is not limited to this, A shape including an arc and a straight line, an n-type (n? 3), a non-n-type (n? 3), a lattice type, a line type or the like can be adopted. The n-type may be an n-type or a non-n-type. For example, a quadrangular shape may be a quadrilateral (square), a rectangle, a parallelogram, a trapezoid, or a shape in which at least one pair of opposed sides of the quadrilateral are non-planar. Incidentally, when n is 4 or more in the n-type (n? 3), it includes a shape as shown in Figs. 19A to 19D. 19A is a quadrangle, Fig. 19B is a hexagon, Fig. 19C is an octagon, and Fig. 19D is a hexagon. The non-n-angular shape may be an angle-free structure, such as a circle, an ellipse, the above-mentioned n-angular, rounded shape (n-angular shape having a radius of curvature of more than 0), or a rounded (N &gt; = 3) including the above-described angular portion having a radius of more than 0). For this reason, for example, the shape illustrated in Figs. 19F to 19H is included. Among them, it is preferable to adopt a shape of line symmetry.

<< LED epitaxial wafer >>

Next, an LED epitaxial wafer using the patterned wafer 1 for LEDs according to the present embodiment will be described.

22 is a schematic cross-sectional view showing an example of an epitaxial wafer for LED according to the present embodiment. As shown in Fig. 22, in the epitaxial wafer 100 for LED, the pattern wafers 1 and 10 for LEDs are provided with a concave-convex structure 20 on the surface thereof. The concave-convex structure 20 is the concavo-convex structure (A) described above. In other words, the arrangement axis A of the concave-convex structure 20 and the crystal axes of the pattern wafers 1 and 10 of the LED satisfy the above-described relation of the rotational shift angle (?) And the convex portion of the concave- And is constituted by the corner portions whose radius of curvature explained is greater than zero. The first semiconductor layer 30, the light emitting semiconductor layer 40, and the second semiconductor layer 50, which are semiconductor layers, are successively laminated on the surface including the concave-convex structure 20 of the LED pattern wafers 1, . Here, in the LED chip made of the epitaxial wafer 100 for LED, the light emitted from the light emitting semiconductor layer 40 is emitted from the side of the second semiconductor layer 50 or the pattern wafers 1 and 10 for the LED And extracted. The first semiconductor layer 30 and the second semiconductor layer 50 are made of different semiconductor crystals. Here, it is preferable that the first semiconductor layer 30 is planarized to have the concave-convex structure 20. At this time, since the concave-convex structure 20 is the concavo-convex structure A, the potential of the first semiconductor layer 30 is reduced and cracks are suppressed. The first semiconductor layer 30 is formed so as to planarize the concave and convex structure 20 so that the performance of the first semiconductor layer 30 as a semiconductor can be reflected in the light emitting semiconductor layer 40 and the second semiconductor layer 50 Therefore, the internal quantum efficiency (IQE) is improved and the crack is suppressed. That is, according to the principle described in the << patterned wafer for LED (1) >>, the first semiconductor layer 30 which can reduce the electric potential of the first semiconductor layer 30 and can suppress cracking and has good crystallinity Can be sequentially reflected on the light emitting semiconductor layer 40 and the second semiconductor layer 50 and the cracks of the semiconductor layer can be reduced even after the second semiconductor layer 50 is formed.

The first semiconductor layer 30 may be composed of the undoped first semiconductor layer 31 and the first doped semiconductor layer 32 as shown in FIG. 23 is a schematic cross-sectional view showing another example of the epitaxial wafer for LED according to the present embodiment. 23, in the LED epitaxial wafer 200, the LED pattern wafers 1, 10, the undoped first semiconductor layer 31, and the doped first semiconductor layer 32 ), The manufacturing time of the LED epitaxial wafer 200 can be shortened in addition to the improvement of the internal quantum efficiency IQE and the crack reduction effect. The non-doped first semiconductor layer 31 is formed so as to planarize the concavoconvex structure 20 so that the performance of the undoped first semiconductor layer 31 as a semiconductor can be improved by the doped first semiconductor layer 32, (40) and the second semiconductor layer (50), the internal quantum efficiency (IQE) is improved and the crack is reduced. That is, the crystallinity of the undoped first semiconductor layer 31 can be improved by the principle described in the << patterned wafer for LED 1 >> (1), and the non-doped first semiconductor layer 31 ) Is successively reflected on the doped first semiconductor layer 32, the light emitting semiconductor layer 40 and the second semiconductor layer 50 and the cracking of the semiconductor layer is suppressed even after the second semiconductor layer 50 is formed Can be reduced.

Furthermore, it is preferable that the first semiconductor layer 30 include the buffer layer 33 as shown in Fig. 24 is a schematic cross-sectional view showing another example of the epitaxial wafer for LED according to the present embodiment. 24, in the epitaxial wafer 300 for an LED, a buffer layer 33 is formed on the concavo-convex structure 20, and then the undoped first semiconductor layer 31 and the first doped semiconductor layer (32) are successively laminated, nucleation and nucleation, which are initial conditions for crystal growth of the first semiconductor layer (30), are improved, and the performance of the first semiconductor layer (30) as a semiconductor is improved, The improvement of the efficiency (IQE) is improved. The buffer layer 33 may be arranged to planarize the concavo-convex structure 20. However, since the growth rate of the buffer layer 33 is slow, from the viewpoint of shortening the manufacturing time of the LED epitaxial wafer 300, It is preferable to planarize the concave-convex structure 20 with the undoped first semiconductor layer 31 formed on the semiconductor substrate. The non-doped first semiconductor layer 31 is formed so as to planarize the concavoconvex structure 20 so that the performance of the undoped first semiconductor layer 31 as a semiconductor is improved by the doped first semiconductor layer 32, And the second semiconductor layer 50, the internal quantum efficiency IQE is improved and the cracks are reduced. 24, the buffer layer 33 is disposed so as to cover the surface of the concavo-convex structure 20, but it may be partially formed on the surface of the concavo-convex structure 20. [ In particular, the buffer layer 33 can be preferentially formed on the bottom of the concave portion of the concave-convex structure 20. [ In this case, since nuclei can be attached preferentially to the bottom of the concave portion of the concave-convex structure 20, the succeeding nucleus growth property becomes good, and the coalescence of the growing semiconductor layers can be satisfactorily maintained. On the other hand, in the case of using the pattern wafers 1 and 10 for LED according to the present embodiment, since the internal quantum efficiency IQE can be preferably improved, the buffer layer 33 need not be formed.

The epitaxial wafers 100, 200 and 300 for LEDs shown in Figs. 22 to 24 are examples in which a double heterostructure semiconductor layer is applied. However, the epitaxial wafers 100, 200 and 300 for LEDs shown in Figs. 22 to 24 are examples in which the first semiconductor layer 30, The lamination structure of the semiconductor layer 50 is not limited to this.

25 is a schematic cross-sectional view showing an example of an LED chip made of the epitaxial wafer for LED shown in Figs. 22 to 24. Fig. 25, in the LED chip 400, a transparent conductive layer 60 is formed on the second semiconductor layer 50, an anode electrode 70 is formed on the surface of the transparent conductive layer 60, And a cathode electrode 80 may be provided on the surface of the first semiconductor layer 30, respectively. The arrangement of the transparent conductive layer 60, the anode electrode 70, and the cathode electrode 80 is not limited as it can be appropriately optimized by the LED chip, but is generally formed as illustrated in Fig.

In the LED chip 400 shown in Fig. 25, the concave-convex structure 20 is formed between the patterned wafer 1 (10) for LED 10 and the first semiconductor layer 30, Likewise, a separate uneven structure can be formed. 26 is a schematic cross-sectional view showing another example of the LED chip according to the present embodiment. As shown in Fig. 26, the following can be given as the concavo-convex structure separately formed.

A concave-convex structure 601 formed on the surface of the patterned wafer for LED 1 (10) opposite to the light-emitting semiconductor layer 40,

An uneven structure 602 formed between the second semiconductor layer 50 and the transparent conductive layer 60;

Convex structure 603 formed on the surface of the transparent conductive layer 60;

An uneven structure 604 formed between the transparent conductive layer 60 and the anode electrode 70;

A concave-convex structure 605 formed between the first semiconductor layer 30 and the cathode electrode 80;

A concave-convex structure 606 formed on the surface of the anode electrode 70;

A concavo-convex structure 607 formed on the surface of the cathode electrode 80;

The concavo-convex structure 608 formed on the side surfaces of the first semiconductor layer 30, the light-emitting semiconductor layer 40, the second semiconductor layer 50, and the pattern wafers 1 and 10 for LED,

By further forming at least one concavo-convex structure of the concavo-convex structures 601 to 608 in addition to the concavo-convex structure 20, the effect according to the concavo-convex structures 601 to 608 described below can be produced.

By forming the concave-convex structure 601, the light extraction efficiency (LEE) is improved. In the LED chip according to the present embodiment, the internal quantum efficiency IQE is improved. That is, it is possible to effectively produce a photon inside the LED chip. Therefore, in the LED chip according to the present embodiment, it is preferable to form the uneven structure 601. On the other hand, the light extraction efficiency (LEE) is likewise greatly improved by removing the LED pattern wafer 1 by, for example, a laser lift-off method instead of forming the concave-convex structure 601.

By forming the concave-convex structure 602, the light extraction efficiency (LEE) can be improved, so that the external quantum efficiency (EQE) is greatly improved. Further, since the diffusion property of electrons in the transparent conductive layer 60 is improved, the size of the LED chip can be increased.

By forming the concave-convex structure 603, the light extraction efficiency (LEE) can be improved. In the epitaxial wafer for LED according to the present embodiment, the internal quantum efficiency IQE is improved. That is, the photon can be effectively generated inside the LED chip. Therefore, in the LED chip according to the present embodiment, it is preferable to form the uneven structure 603.

By forming the uneven structure 604, it is possible to increase the contact area between the transparent conductive layer 60 and the anode electrode 70, so that peeling of the anode electrode 70 can be suppressed. Further, since the ohmic resistance can be reduced and the ohmic contact can be improved, the electron injection efficiency (EIE) can be improved and the external quantum efficiency (EQE) can be improved. In the epitaxial wafer for LED according to the present embodiment, the internal quantum efficiency IQE is improved. That is, the photon can be effectively generated inside the LED chip. Therefore, in the LED chip according to the present embodiment, it is preferable to form the concave-convex structure 604.

By forming the uneven structure 605, the contact area between the first semiconductor layer 30 and the cathode electrode 80 becomes large, so that peeling of the cathode electrode 80 can be suppressed.

By forming the concave-convex structure 606, the fixing strength of the wiring connected to the anode electrode 70 is improved, so that peeling can be suppressed.

By forming the concave-convex structure 607, the fixing strength of the wiring provided on the surface of the cathode electrode 80 is improved, so that peeling can be suppressed.

The amount of emitted light emitted from the side surfaces of the first semiconductor layer 30, the light emitting semiconductor layer 40, the second semiconductor layer 50, and the pattern wafers 1 and 10 for LED is It is possible to reduce the proportion of the emitted light that attenuates and disappears in the waveguide mode. Therefore, the light extraction efficiency (LEE) can be improved and the external quantum efficiency (EQE) can be increased.

As described above, by using the pattern wafers 1 and 10 for LEDs according to the embodiments, the internal quantum efficiency IQE of the epitaxial wafer for LEDs can be improved and the warpage of the epitaxial wafer for LEDs can be reduced . Therefore, even when a large wafer for LEDs such as a 4-inch? Or a 6-inch? Is used, an LED epitaxial wafer with less warpage can be manufactured and the LED chip can be manufactured with a low defect rate. In particular, by using the patterned wafer 1 for LEDs having a diameter of 6 inches or more, the thickness of the patterned wafer 1 for LEDs can be reduced. This improves the environmental suitability and improves the thermal control property at the time of forming the semiconductor layer, so that the crystallinity of the semiconductor layer of the epitaxial wafer for LED is further improved. Further, as described above, since the thickness of the semiconductor layer can be reduced, warping of the LED epitaxial wafer can be effectively suppressed. Further, by forming at least one concave-convex structure of the concave-convex structures 601 to 608 described above, the effect of the concave-convex structures 601 to 608 can be exhibited. In particular, it is preferable to form at least one of the concave-convex structure 601 and the concave-convex structure 603 from the viewpoint of improving the light extraction efficiency (LEE) and achieving high external quantum efficiency. In addition, from the viewpoint of improving the electron injection efficiency (EIE), it is preferable to form the uneven structure 604.

An electrode is formed on the exposed surface of the second semiconductor layer 50 of the epitaxial wafer 100 for LEDs illustrated in FIGS. 22 to 24, The pattern wafers (1) and (10) for LED may be removed from the laminate on which the base material is disposed. Removal of the pattern wafers 1 and 10 for LEDs can be achieved by lift-off using laser light or by total dissolution or partial dissolution of the pattern wafers 1 and 10 for LED. Particularly, when a silicon wafer is used as the pattern wafers 1 and 10 for LED, the removal by dissolution is preferable from the viewpoint of the accuracy of the surface on which the uneven structure is formed (hereinafter referred to as the uneven structure surface). By removing the pattern wafers 1 and 10 for LEDs as described above, it is possible to further improve the light extraction efficiency LEE while maintaining the improvement of the internal quantum efficiency IQE. This is because the difference in refractive index between the pattern wafers 1 and 10 for LEDs and the first semiconductor layer 30, the light emitting semiconductor layer 40, and the second semiconductor layer 50 is large. By removing the pattern wafers 1 and 10 for LED, the LED epitaxial wafer having the first semiconductor layer 30 as a light emitting surface can be pulled up.

Next, a description will be given of the phrases used for the explanation of the elements constituting the epitaxial wafers 100, 200 and 300 for LED. On the other hand, the following description is also applied to the LED chips 400 and 500.

&Lt; Average height of concavo-convex structure (Have) >

The height of the concave-convex structure 20 is given as an average value of the distance between the convex portion of the concave-convex structure and the bottom of the concave portion. First, a region of 50 占 퐉 占 50 占 퐉 in parallel with the main surface of the pattern wafers 1 (10) for LED 10 is held on the concavo-convex structure 20 surface of the LED pattern wafers (1) On the other hand, in the case of an epitaxial wafer for LED in which a semiconductor layer is formed on the pattern wafers 1 and 10 for LED, the semiconductor layer is removed and the surface of the pattern wafers 1 and 10 for LED is observed do. Subsequently, the area of the 50 占 퐉 占 50 占 퐉 area is divided into 25 areas of 10 占 퐉 占 10 占 퐉 which do not overlap with each other. Then, arbitrarily five regions are selected in an area of 25 existing 10 mu m x 10 mu m. Here, the area of the selected 10 탆 x 10 탆 square is defined as area A, area B, area C, area D and area E. Thereafter, the region A is observed at a higher magnification and enlarged until at least 100 convex portions are observed clearly. Subsequently, ten convex portions are arbitrarily selected from the observed convex portions, and the height h of each convex portion is obtained. Here, the height (h) of the convex portion can be determined by observing with a tilt (Tilt) observation or atomic force microscope observation with a scanning electron microscope. And the average height of the elevations of ten convex portions measured from the region A is ha. Regarding the region B, the region C, the region D, and the region E, the same operation as the region A is performed to obtain hb, hc, hd, and he. The average height Have of the concave-convex structure 20 is given as (ha + hb + hc + hd + he) / 5. However, in the case where the concave-convex structure 20 is constituted by a plurality of independent concave portions, by reading the convex portions described above into the concave portions, The height h of the structure 20 is defined. In the case of the epitaxial wafer for LED, the term according to the thickness of the semiconductor layer described below is calculated first, and thereafter, the semiconductor layer is removed and the average height (Have) of the concavoconvex structure 20 is obtained do. That is, the information according to the thickness of the semiconductor layer described below and the average height (Have) of the concavo-convex structure 20 described above are measured at approximately the same portion of the same sample. The average spacing Pave of the concavo-convex structures 20 and the average width (average diameter)? Ave of the bottoms of the convex portions of the concavo-convex structure 20 described above can be obtained by calculating the average And is obtained at the same measurement site.

<Street Hbun>

The distance between the surface of the LED pattern wafers 1 and 10 on the side of the light emitting semiconductor layer 40 and the surface of the first semiconductor layer 30 on the side of the light emitting semiconductor layer 40 is defined as a distance Hbun. Here, the surface of the LED pattern wafers (1) and (10) on the side of the light emitting semiconductor layer 40 is defined as the position of the bottom of the average concave portion of the concavo-convex structure 20. The surface of the first semiconductor layer 30 on the light emitting semiconductor layer 40 side is defined as an average surface. The average is the street average, and the average score is 10 points. That is, the distance Hbun is an average thickness of the first semiconductor layer 30 with reference to the position of the bottom of the concave portion of the concave-convex structure 20. [ On the other hand, the above-mentioned average value is calculated by observing the cross section of the LED epitaxial wafer. As the observation method, transmission electron microscopic observation or scanning electron microscopic observation can be employed. Also, the observation range is set to a range in which 5 to 20 convex portions (or concave portions) can be clearly observed in these observations.

<Street Hbu>

The distance between the surface of the LED pattern wafers 1 and 10 on the light emitting semiconductor layer 40 side and the surface of the undoped first semiconductor layer 31 on the light emitting semiconductor layer 40 side is defined as a distance Hbu . Here, the surface of the LED pattern wafers (1) and (10) on the side of the light emitting semiconductor layer 40 is defined as the position of the bottom of the average concave portion of the concavo-convex structure 20. The surface of the undoped first semiconductor layer 31 on the side of the light emitting semiconductor layer 40 is defined as an average surface. The average is the street average, and the average score is 10 points. That is, the distance Hbu is an average thickness of the undoped first semiconductor layer 31 with reference to the position of the bottom of the concave portion of the concave-convex structure 20. [ On the other hand, the above-mentioned average value is calculated by observing the cross section of the LED epitaxial wafer. As the observation method, transmission electron microscopic observation or scanning electron microscopic observation can be employed. Also, the observation range is set to a range in which 5 to 20 convex portions (or concave portions) can be clearly observed in these observations.

Next, each element constituting the epitaxial wafer 100 for LEDs (including the LED chips 400 and 600 and the LED chips 400 and 600) will be described in detail.

<Ratio of distance (Hbun) to average height (Have) (Hbun / Have)>

The ratio (Hbun / Have) between the distance (Hbun) and the average height (Have) satisfies 2? Hbun / Have? 300.

The ratio Hbun / Have means the ratio between the average height Have of the concave-convex structure 20 and the average thickness Hbun of the first semiconductor layer 30. The larger the ratio Hbun / Have, The average thickness Hbun of one semiconductor layer 30 becomes large. The ratio (Hbun / Have) is 2 or more, which is preferable because the effect of improving the internal quantum efficiency (IQE) by the concavoconvex structure 20 can be expressed. The degree of planarization of the concave-convex structure A by the cracked first semiconductor layer 30 is improved by the ratio Hbun / Have of 2 or more. Thus, the deposition precision of the light emitting semiconductor layer 40 and the second semiconductor layer 50 formed on the first semiconductor layer 30 can be effectively improved. This makes it possible to reflect the performance of the first semiconductor layer 30 having a small potential as a semiconductor to the light emitting semiconductor layer 40 and the second semiconductor layer 50 in a state in which cracks are suppressed, And an epitaxial wafer for LEDs having high internal quantum efficiency (IQE) can be obtained. In addition, when the ratio (Hbun / Have) is 3.5 or more, the flatness of the surface of the first semiconductor layer 30 is improved, and thus the film thickness uniformity of the light emitting semiconductor layer 40 is improved, The uniformity is improved. From the viewpoint of further exhibiting these effects, it is more preferably 5.5 or more, and most preferably 8.0 or more. Particularly, if the ratio Hbun / Have is 10 or more, the influence of the convex portion top of the concavoconvex structure 20 on the surface of the first semiconductor layer 30 can be further reduced, The flatness of the surface on the side of the light emitting semiconductor layer 40 can be improved. That is, the effect of improving the internal quantum efficiency (IQE) is increased. From the same viewpoint, the ratio (Hbun / Have) is preferably 12 or more, more preferably 14 or more, and most preferably 16 or more. It is also possible to increase the collision probability of the potential between the average convex portion of the concave and convex structure 20 of the first semiconductor layer 30 and the light emitting semiconductor layer 40 and to increase the internal quantum efficiency IQE (Hbun / Have) is more preferably 20 or more, and most preferably 25 or more. On the other hand, when the ratio (Hbun / Have) is 300 or less, warpage of the epitaxial wafer 100 for LED can be suppressed, and chip efficiency can be improved.

The index of warping after forming the semiconductor layer is generally known as BOW. BOW is inversely proportional to the thickness of the pattern wafers 1 and 10 for LEDs and is proportional to the square of the size (diameter) of the pattern wafers 1 and 10 for LEDs and the thickness of the semiconductor layer. The larger the BOW is, the more difficult it becomes to manufacture the LED chip. Thus, considering the photolithography process in manufacturing the LED chip, BOW is preferably 1.5 or less. Here, considering that the BOW is made small, the thickness of the pattern wafers (1) and (10) for LEDs may be increased, the thickness of the semiconductor layer may be reduced, and the sizes of the pattern wafers (1) and . However, in the case of increasing the thickness of the patterned wafers 1 and 10 for LEDs, the manufacturing cost of the LED chip is greatly increased, and the thermal behavior of the patterned wafers 1 and 10 for forming the semiconductor layer The film forming property of the semiconductor layer is lowered, and the internal quantum efficiency IQE may be lowered. In addition, reducing the size of the pattern wafers 1 and 10 for LEDs is a factor that greatly reduces the yield of LED chips. That is, if the thickness of the semiconductor layer is made thinner and BOW can be suppressed, the effect is large. Here, it has been described that the film forming property of the semiconductor layer is improved by using the concavo-convex structure (A). That is, by using the pattern wafers 1 and 10 for LEDs having the concavo-convex structure (A), even when the thickness of the semiconductor layer is reduced, the potential can be effectively reduced and cracks can be suppressed, Can be reduced. From this viewpoint, the ratio (Hbun / Have) is preferably 200 or less, more preferably 150 or less. The ratio (Hbun / Have) is more preferably 100 or less, and most preferably 50 or less, from the viewpoint of shortening the film formation time of the semiconductor layer, reducing the amount of the semiconductor layer used, and ensuring environmental compatibility. From the above, it is possible to form a semiconductor layer having a high internal quantum efficiency (IQE) whose cracks are suppressed by satisfying the predetermined ratio Hbun / Have, and at the same time, the patterned wafer 1 for LED 10) can be suppressed, so that a highly efficient LED chip can be produced with high production efficiency.

<Ratio of distance (Hbu) to average height (Have) (Hbu / Have)>

The ratio (Hbu / Have) of the distance (Hbu) to the average height (Have) satisfies 1.5? Hbu / Have? 200.

The ratio Hbu / Have means the ratio between the average height Have of the concave-convex structure 20 and the average thickness Hbu of the undoped first semiconductor layer 31, and the ratio Hbu / The larger the average thickness Hbu of the undoped first semiconductor layer 31 becomes. The ratio Hbu / Have is 1.5 or more so that the degree of planarization of the concave-convex structure A by the undoped first semiconductor layer 31 is improved in a state in which cracks are suppressed. Thus, the deposition precision of the first doped first semiconductor layer 32, the light emitting semiconductor layer 40, and the second semiconductor layer 50 formed on the undoped first semiconductor layer 31 can be effectively improved . Therefore, the crystallinity of the undoped first semiconductor layer 31 having a small potential can be improved by controlling the crystallinity of the doped first semiconductor layer 32, the light emitting semiconductor layer 40, and the second semiconductor layer 50 So that epitaxial wafers for LEDs having high internal quantum efficiency (IQE) can be obtained while suppressing cracks while reducing the production time. In addition, the ratio Hbu / Have of 2.5 or more makes planarization of the concave-convex structure 20 by the undoped first semiconductor layer 31 better, and thus the film thickness uniformity of the light- So that the in-plane uniformity of the emission wavelength is improved. From the viewpoint of exerting these effects, it is most preferable to be 3.5 or more. In particular, if the ratio Hbu / Have is 4 or more, the influence on the surface of the undoped first semiconductor layer 31 at the convex portion of the concave-convex structure 20 can be further reduced, The flatness of the surface on the side of the light emitting semiconductor layer 40 can be improved. That is, the internal quantum efficiency (IQE) improvement and the crack suppressing effect are increased. From the same viewpoint, the ratio (Hbu / Have) is preferably 5 or more, more preferably 8 or more, and most preferably 10 or more. In addition, the ratio (Hbu / Have) is more preferably 12 or more from the viewpoint of increasing the collision probability of dislocations and further increasing the internal quantum efficiency IQE in the undoped first semiconductor layer 31, 15 or more is most preferable. On the other hand, when the ratio (Hbu / Have) is 200 or less, warping of the LED epitaxial wafer 100 can be suppressed. This can be determined from the perspective of the BOW already described. From the same viewpoint, the ratio (Hbu / Have) is preferably 100 or less, more preferably 50 or less. Further, the ratio (Hbu / Have) is most preferably 30 or less from the viewpoints of reducing the amount of the semiconductor layer used, greatly shortening the film formation time, and ensuring environmental compatibility. From the above, it is possible to form a semiconductor layer having a high internal quantum efficiency (IQE) whose cracks are suppressed by satisfying the predetermined range of Hbu / Have, and at the same time, the patterned wafer 1 for LED 10) can be suppressed, so that a highly efficient LED chip can be produced with high production efficiency.

<Convex Structure (20)>

The concavo-convex structure 20, that is, the concavo-convex structure A of the epitaxial wafer 100 for LED according to the present embodiment is substantially the same as that of the pattern wafer 1 for LED It is not particularly limited as long as it is a concavo-convex structure having regularity and a convex portion is composed of a corner portion having a radius of curvature of more than 0. Among them, by satisfying the relationship between the duty and the rotational shift angle? Described with reference to Fig. 8 and the relationship between the average interval Pave and duty explained with reference to Fig. 9, the crack suppressing effect and the internal quantum efficiency IQE, The improvement effect is increased. Further, by satisfying the relationship between the average interval (Pave) and the duty ratio described with reference to Fig. 16, the light extraction efficiency (LEE) can also be improved at the same time. Hereinafter, further preferred embodiments of the concavo-convex structure 20 will be described.

The concavoconvex structure 20 is a structure having a dot-like structure composed of a plurality of independent convex portions and a continuous concave portion, a hole-like structure composed of a plurality of independent concave portions and continuous convex portions, or a hybrid structure including independent convex portions and independent concave portions Structure. Among them, a dot-type structure is most preferable. This is because, as described above, the nucleation and growth of the nuclei of the semiconductor layer become better and the crack suppression effect and the internal quantum efficiency (IQE) improvement effect become larger as described above. In a dot-like structure, a hole-like structure, or a hybrid structure, the outline shape of the bottom portion of one convex portion or the opening shape of the concave portion may be circular, oval, shallow, man-shaped, n- (N &amp;ge; 3) having a corner portion having a radius of curvature of more than 0 can be adopted. Among them, the stress applied from the concavo-convex structure 20 to the semiconductor layer to be grown can be reduced if the round, elliptical, elliptical, or triangular shape having corner portions with curvature radii of more than 0 in each corner is reduced. It grows. In particular, a circle is most preferable. On the other hand, the circle is a substantial circle, and some distortion is considered.

As described above, the average spacing Pave of the concavoconvex structures 20 satisfies 50 nm &amp;le; Pave &amp;le; 1500 nm, whereby a semiconductor layer with a high internal quantum efficiency IQE can be formed while suppressing cracks. In the case of the LED epitaxial wafer in this case, the above-described ratio (Hbun / Have) or the ratio (Hbu / Have) effects can be suitably expressed by the average spacing Pave of 1500 nm or less. This is because the effect of the ratio (Hbun / Have) or the ratio (Hbu / Have) based on the principle already described is not disturbed by the concave-convex structure 20 because the semiconductor layer seen from the concave- convex structure 20 becomes large to be. Therefore, it is possible to simultaneously improve the internal quantum efficiency (IQE) and the crack. In the same principle, the thickness is preferably 1200 nm or less, more preferably 1000 nm or less, and most preferably 950 nm or less. On the other hand, the lower limit value has already been described.

<Shape of convex part>

As described above, the shape of the convex portion constituting the concavoconvex structure 20 is such that the diameter of the convex bottom portion is larger than the diameter of the convex top portion from the viewpoint of the attachment, growth and nucleation of the semiconductor layer, It is more preferable that the convex portion side surface portion connecting the convex portion top portion and the concave portion bottom portion has an inclination angle of two or more steps and the radius of curvature of the point where the inclination changes is more than 0, desirable. In particular, when considered as an epitaxial wafer for an LED, it is preferable that the aspect ratio (Have / φave), which is a parameter indicating the shape of the convex portion, is 0.1 or more and 5.0 or less. At first, the light extraction efficiency LEE can be improved because the volume of the convex portion seen from the photons generated from the light emitting semiconductor layer is increased by 0.1 or more. In particular, if the aspect ratio is 0.3 or more, it is preferable because the number of modes of light diffraction for the emitted light can be increased and the scattering property can be strengthened. From the same viewpoint, the aspect ratio is more preferably 0.5 or more, and most preferably 0.6 or more. On the other hand, when the aspect ratio is 5.0 or less, the inclination angle of the side surface of the convex portion can be made gentle. Thus, it is considered that particles generated when the LED chip is obtained can be suppressed. The aspect ratio is preferably 3.0 or less, more preferably 2.0 or less, and most preferably 1.1 or less from the viewpoints of the same effect and the film forming property of the semiconductor layer, particularly, from the viewpoint of suppressing cracks.

<Bottom of recess>

As described above, it is preferable that the bottom of the concave portion has a flat surface in view of adhesion, growth of the nuclei of the semiconductor layer, and integration of the growing semiconductor layers. Particularly, in the case of the LED epitaxial wafer in this case, the flat surface (hereinafter referred to as &quot; flat surface B &quot;) of the bottom portion of the concave portion of the concave- convex structure 20 and the stable growth surface of the first semiconductor layer 30 Parallel planes (hereinafter referred to as &quot; parallel stable growth planes &quot;) are preferably parallel. In this case, the growth of the first semiconductor layer 30 in the vicinity of the concave portion of the concavoconvex structure 20 becomes good, and the reduction of the potential based on the coalescence of the growing semiconductor layers becomes large, The internal quantum efficiency IQE can be improved because the electric potential in the concavo-convex structure 20 can be effectively dispersed along the concavo-convex structure 20. [ The stable growth surface refers to the surface with the slowest growth rate in the material to be grown. It is generally known that the steady growth surface appears as a facet surface during growth. For example, in the case of a gallium nitride compound semiconductor, a plane parallel to the A axis represented by the M plane is a stable growth plane. The stable growth surface of the GaN-based semiconductor layer is an M plane (1-100), (01-10), (-1010) of hexagonal crystal, and is one of planes parallel to the A axis. On the other hand, depending on the growth conditions, another plane including the A axis which is a plane other than the M plane of the GaN-based semiconductor may be a stable growth plane.

&Lt; Buffer layer &

As the material of the buffer layer 33, an AlGaN structure, an AlN structure, an AlInN structure, an InGaN / GaN superlattice structure, an InGaN / GaN laminate structure, or an AlInGaN / InGaN / GaN laminate structure can be adopted. As for the formation of the buffer layer, the film forming temperature can be set in the range of 350 ° C to 600 ° C. As a result, evenness can be improved with respect to film formation from the narrow concave bottom portion. By using these buffer layers 33, the difference in lattice constant between the LED wafer and the first semiconductor layer 30 can be effectively reduced, and the film forming property and the crystallinity of the first semiconductor layer 30 can be improved have. The thickness of the buffer layer 33 is preferably 1/5 or less of the average height (Have) of the concave-convex structure 20. This is for suppressing the adhesion of nuclei to the side portions of the convex portions with respect to the re-diffusion and recrystallization behavior of the buffer layer 33 in the RAMP process. From this point of view, the film thickness of the buffer layer 33 is more preferably 1/10 or less and most preferably 1/20 or less of the average height (Have) of the concavo-convex structure 20. The buffer layer 33 is preferably formed by MOCVD (Metal Organic Chemical Vapor Deposition) or sputtering. In particular, it is more preferable to employ the sputtering method in that the uniformity of the buffer layer 33 is improved.

<First Semiconductor Layer>

The material of the first semiconductor layer 30 can be selected from among the undoped first semiconductor layer 31 and the first doped semiconductor layer 32 described below. The film thickness Hbun of the first semiconductor layer 30 is set such that the concave and convex structure 20 is flattened by suppressing cracks and the potential inside the first semiconductor layer 30 is reduced, And 800 nm or more from the viewpoint of improving the internal quantum efficiency IQE by reflecting the performance as a semiconductor in the second semiconductor layer 50 and the second semiconductor layer 50. In particular, from the viewpoint of further exhibiting the potential reduction effect by the concave-convex structure 20, it is preferably 1500 nm or more, more preferably 2000 nm or more. From the viewpoint that the light emitting semiconductor layer 40 and the second semiconductor layer 50 reflect the performance as a semiconductor and effectively increase the internal quantum efficiency IQE, it is preferably 2500 nm or more, more preferably 3000 nm or more And most preferably at least 4000 nm. On the other hand, the upper limit value is preferably 100000 nm or less, more preferably 7500 nm or less, and most preferably 6500 nm or less from the viewpoints of warpage and environmental compatibility.

The doped first semiconductor layer 32 is not particularly limited as long as it can be used as an n-type semiconductor layer suitable for the use of an LED. For example, an element semiconductor such as silicon or germanium, or a compound semiconductor such as group III-V, group II-VI, or group VI-VI may be appropriately doped with various elements. In particular, an n-type GaN layer is preferable. As the n-type GaN layer, for example, NH _{3 in the range} of 3 × 10 ^-2 to 4.2 × 10 ^-2 mol / min, trimethyl gallium (TMGa) in the range of 0.8 × 10 ^-4 to 1.8 × 10 ^-4 mol / and a silane gas containing an n-type dopant is supplied at 5.8 x 10 ^-9 to 6.9 x 10 ^-9 mol / min. The film thickness of the doped first semiconductor layer 32 is preferably 800 nm or more, more preferably 1500 nm or more, and most preferably 2000 nm or more, from the viewpoint of electron injection property into the light emitting semiconductor layer 40. On the other hand, the upper limit value is preferably 5000 nm or less from the viewpoint of reducing warpage. From the viewpoint of reducing the amount of the doped first semiconductor layer 32 used and shortening the manufacturing time of the LED epitaxial wafers 200 and 300, it is preferably not more than 4300 nm, more preferably not more than 4000 nm, more preferably not more than 3500 nm or less.

The undoped first semiconductor layer 31 can be appropriately selected within a range that does not hinder the performance of the doped first semiconductor layer 32 as the n-type semiconductor layer. For example, element semiconductors such as silicon and germanium, or compound semiconductors such as group III-V, group II-VI, and group VI-VI can be used. In particular, an undoped nitride layer is preferable. The non-doped nitride layer can be formed by supplying NH ₃ and TMGa on a buffer layer or an LED wafer at a growth temperature of, for example, 900 ° C to 1500 ° C. The film thickness Hbu of the undoped first semiconductor layer 31 is preferably 1000 nm or more from the viewpoint of flattening the concave-convex structure 20. Particularly, from the viewpoint of effectively reducing the potential in the undoped first semiconductor layer 31, it is preferably at least 1500 nm, more preferably at least 2000 nm, and most preferably at least 2500 nm. On the other hand, the upper limit value is preferably 6000 nm or less from the viewpoint of reducing warping of the LED epitaxial wafer 100. In particular, from the viewpoint of shortening the manufacturing time of the LED epitaxial wafers 200 and 300, it is preferably 5000 nm or less, more preferably 4000 nm or less, and most preferably 3500 nm or less.

On the other hand, when at least the non-doped first semiconductor layer 31 and the doped first semiconductor layer 32 are sequentially laminated on the concave-convex structure 20 of the pattern wafers 1 and 10 for LED, Doped semiconductor layer 2 may be formed on the light emitting semiconductor layer 32, and the light emitting semiconductor layer 40 may be formed thereon. In this case, as the other undoped semiconductor layer 2, the materials described for the undoped first semiconductor layer 31 can be used. The thickness of the other undoped semiconductor layer 2 is preferably 10 nm or more, more preferably 100 nm or more, and most preferably 200 nm or more, from the viewpoint of the luminescence of the LED epitaxial wafers 200 and 300 Do. On the other hand, the upper limit value is preferably 500 nm or less, more preferably 400 nm or less, and most preferably 350 nm or less, from the viewpoint of recombination of holes and electrons in the light emitting semiconductor layer 40.

<Light-emitting semiconductor layer>

The light emitting semiconductor layer 40 is not particularly limited as long as it has a light emitting property as a semiconductor light emitting element (for example, LED). For example, as the light emitting semiconductor layer 40, semiconductor layers such as AsP, GaP, AlGaAs, InGaN, GaN, AlGaN, ZnSe, AlHaInP and ZnO can be applied. The light emitting semiconductor layer may be doped with various elements suitably depending on the characteristics. The light emitting semiconductor layer 40 is an active layer of a single or multiple quantum well structure. For example, NH ₃ , TMGa and trimethyl indium (TMIn) are supplied using nitrogen as a carrier gas at a growth temperature of 600 ° C. to 850 ° C. to grow an active layer made of INGaN / GaN to a thickness of 100 Å to 1,250 Å . In the case of a multiple quantum well structure, the In element concentration may be changed with respect to InGaN constituting one layer. Further, an electron blocking layer may be provided between the light emitting semiconductor layer 40 and the second semiconductor layer 50. [ The electronic block layer is composed of, for example, p-AlGaN.

&Lt; Material of Second Semiconductor Layer >

The second semiconductor layer 50 is not particularly limited as long as it can be used as a p-type semiconductor layer suitable for LED applications. For example, an element semiconductor such as silicon or germanium, or a compound semiconductor such as group III-V, group II-VI, or group VI-VI may be appropriately doped with various elements. For example, in the case of the p-type GaN layer, the growth temperature may be raised to 900 ° C or higher, and TMGa and CP ₂ Mg may be supplied to form a film having a thickness of several hundreds to several thousands of angstroms.

&Lt; Material of Pattern Wafer 1 for LED >

The material for the LED pattern wafers (1) (10) is not particularly limited as long as it can be used as the pattern wafers (1) for LED. Sapphire, silicon carbide (SiC), silicon nitride (Si ₃ N _4), gallium nitride (GaN), copper tungsten (W-Cu), silicon, zinc oxide, magnesium oxide, manganese oxide, zirconium oxide, manganese oxide ahyeoncheol oxide, A substrate made of magnesium aluminum, boron zirconium, gallium oxide, indium oxide, lithium aluminum oxide, neodymium oxide gallium oxide, lanthanum strontium aluminum tantalum oxide, strontium titanium oxide, hafnium tungsten, molybdenum, GaP or GaAs Can be used. Among them, sapphire, GaN, GaP, GaAs, silicon carbide, silicon, spinel (for example, an insulating substrate typified by MgAl ₂ O ₄ ) or the like is preferably applied from the viewpoint of lattice matching with the first semiconductor layer 30 Do. In addition, they may be used singly or as a heterostructure wafer in which a separate wafer is provided on a wafer for LED using them. For example, a sapphire wafer having C plane (0001) as the principal plane can be used for the LED wafer. In this case, the M plane which is the stable growth plane of the GaN-based semiconductor layer is a plane parallel to the sapphire wafer A planes 11-20, (1-210), (-2110).

The size of the pattern wafers 1 and 10 for the LEDs is not particularly limited, and examples thereof include 2 inches?, 4 inches?, 6 inches? And 8 inches ?. These may be disk-shaped or may have an orientation flat. Here, the effect of the concavo-convex structure (A) is averaged from the film formation phenomenon of the semiconductor layer, and from the viewpoint of producing a high-quality epitaxial wafer for LEDs, and among the effects described above, the effect of reducing the warp of the epitaxial wafer for LED From the viewpoint of satisfactory exertion, it is preferable to be 4 inches or 6 inches.

The LED pattern wafers 1 and 10 may be removed at least after the first semiconductor layer 30 is laminated. By removing the pattern wafers 1 and 10 for LEDs, the disturbing effect of the waveguide mode becomes large, so that the light extraction efficiency LEE is greatly improved. In this case, it is preferable that the emitting surface of the emitted light of the LED be on the side of the first semiconductor layer 30 as viewed from the light emitting semiconductor layer 40.

&Lt; Transparent conductive layer &

A transparent conductive layer 60 is formed on the second semiconductor layer 50. As the transparent conductive layer 60, for example, a transparent oxide film, ITO (In ₂ O ₃ -SnO _2), ZnO, RuOx, TiOx, IrOx, SnOx, AZnO (ZnO-Al ₂ O _3), IZnO (In ₂ O _3- ZnO), GZO (ZnO-Ga ₂ O ₃ ), or InxOy. The transparent conductive layer 60 can be formed by a vacuum evaporation method, a sputtering method, or a CVD (Chemical Vapor Deposition) method.

<Anode electrode>

The anode electrode 70 is provided on the transparent conductive layer 60. As the anode electrode 70, a transparent oxide film or a transparent metal described in the above-mentioned transparent conductive layer 60 can be used. When the transparent oxide film is employed, the interface between the anode electrode 70 and the transparent conductive layer 60 may be lost. As the transparent metal, an alloy including at least one selected from the group consisting of Ni, Co, Fe, Ti, Cu, Rh, Au, Ru, W, Zr, Mo, Ta, Pt, Or a multilayer film. Particularly, a multi-layered film in which Au is laminated on Ni is preferable in view of adhesive strength. Further, for example, a multilayer film in which Au is deposited on Ni and RhO is deposited on Au may be employed.

<Cathode Electrode>

The cathode electrode 80 is formed on the exposed surface of the first semiconductor layer 30 by etching the first semiconductor layer 30 from the second semiconductor layer 50 side. For example, a metal or metal oxide such as gold, silver, titanium or chromium can be used. In particular, a metal multilayer film is preferable.

<Reflective film>

A reflective film can be formed on the surface opposite to the concave-convex structure 20 of the patterned wafer 1 (10) for LED. By forming the reflective film, the light extraction efficiency (LEE) by the concavoconvex structure 20 can be increased. The reflectance of the reflective film is preferably 80% or more, more preferably 90% or more, and most preferably 91% or more, in terms of the emission wavelength of the light emitting semiconductor layer 40. For example, a dielectric multilayer film can be used. The dielectric multilayer film is a multilayer film in which two or more dielectric bodies having different refractive indexes are alternately laminated. For example, ZrO ₂ , AlN, Nb ₂ O _3, or Ta ₂ O ₃ and SiO ₂ can be laminated with 3 to 8 pairs.

&Lt; Manufacturing method of concave and convex structure 20 >

The LED epitaxial wafer 100 and the LED pattern wafers 1 and 10 according to the present embodiment have been described above. Next, a method for manufacturing the concave-convex structure 20 will be described.

For example, a transfer method, a photolithography method, a thermal lithography method, an electron characterization method, an interference exposure method, a lithography method using a nanoparticle as a mask, a lithography method using a self-organized structure as a mask, or the like. Particularly, from the viewpoints of processing precision and processing speed of the concavo-convex structure 20 of the pattern wafers 1 and 10 for LEDs, it is preferable to adopt the transfer method.

The transfer method in this specification refers to a step of transferring a fine pattern of a mold having a fine pattern on its surface onto a wafer for LED (pattern wafers (1) (10) for LED before fabricating concave and convex structures (20)) . That is, the method includes at least a step of bonding the fine pattern of the mold and the wafer for LED via the transfer material, and a step of peeling the mold. By employing this method, the above-described rotation shift angle? Can be easily satisfied. More specifically, transfer law can be divided into two categories. First, a case where a transfer material transferred to a wafer for LED is used as a permanent agent. In this case, the materials constituting the wafer for LED and the concavo-convex structure 20 are different. In addition, the concave-convex structure 20 remains as a permanent agent and is used as an epitaxial wafer 100 for LED. In this case, in order to secure growth of the first semiconductor layer 30, it is preferable to employ a method in which the surface of the LED wafer is partially exposed. That is, the transfer material is partially disposed on the surface of the LED wafer, and the partially transferred transfer material functions as a mask for inhibiting the growth of the first semiconductor layer 30. Since the LED is used over a long period of several tens of thousands of hours, when the transfer material is used as a permanent agent, the material constituting the transfer material preferably contains a metal element. Particularly, when a metal alkoxide or a condensate of a metal alkoxide which causes a hydrolysis / polycondensation reaction is included in the raw material, the performance as a permanent agent is improved, which is preferable. More preferably, it is a method of transferring a mask material represented by SiO ₂ deposited by a vacuum process such as vapor deposition or sputtering. Further, a mask is partially formed on the wafer for LED by a transfer method, and then an inorganic material represented by SiO ₂ is formed by vapor deposition or sputtering. Thereafter, the inorganic material may be patterned on the LED wafer by removing the mask produced by the transfer method. Alternatively, a layer of an inorganic material may be formed in advance on the main surface of the wafer for LED, and the layer of the inorganic material may be processed by a transfer method. If the material of the LED wafer and the concave-convex structure (20) as described above the other, the concave and convex structure (20) as the metal aluminum, amorphous aluminum oxide, polycrystalline aluminum oxide, polycrystalline sapphire, silicon oxide (SiO _2), silicon nitride ( Si ₃ N _4), silver (Ag), chromium (Cr), it is most preferable that of nickel (Ni), gold (Au) or platinum (Pt), employing any one or a mixture of two or more. As a result, the effect of the rotation shift angle? Described above can be exerted completely.

Second, nanoimprint lithography can be used. The nanoimprint lithography method is a method including a step of transferring a fine pattern of a mold onto a wafer for LED, a step of forming a mask for processing the wafer for LED by etching, and a step of etching the wafer for LED . For example, when one type of transfer material is used, the LED wafer and the mold are first bonded through a transfer material. Then, the transfer material is cured by heat or light (UV), and the mold is peeled off. The concave and convex structure composed of the transfer material is subjected to etching represented by oxygen ashing to partially expose the LED wafer. Thereafter, the LED wafer is processed by etching using the transfer material as a mask. As a processing method at this time, dry etching and wet etching can be employed. When it is desired to increase the height h of the concavo-convex structure 20 of the pattern wafers 1 and 10 for LED, dry etching is useful. In addition, for example, when two kinds of transfer materials are used, the first transfer material layer is first formed on the LED wafer. Then, the first transfer material layer and the mold are bonded through the second transfer material. Thereafter, the transfer material is cured by heat or light (UV), and the mold is peeled off. The concave and convex structure composed of the second transfer material is subjected to etching represented by oxygen ashing to partially expose the first transfer material. Then, using the second transfer material layer as a mask, the first transfer material layer is etched by dry etching. Thereafter, the LED wafer is processed by etching using the transfer material as a mask. As a processing method at this time, dry etching and wet etching can be employed. When it is desired to increase the height h of the concavoconvex structure 20, dry etching is useful.

As the nanoimprint lithography method, a nano-processed sheet method which does not require the residual film processing described below may be employed. The diluted mask layer (2) material is coated on the uneven structure surface of the mold to remove the solvent. By this operation, the mask layer 2 can be arranged inside the concave portion of the mold. The material of the mask layer 1 diluted on the concavo-convex structure of the mold containing the mask layer 2 in the concave portion of the mold is coated and the solvent is removed. By this operation, the mask layer 2 can be filled in the concave portion of the mold to form the concave-convex structure and the mask layer 2, and the mask layer 1 can be formed so as to be planarized. Thus, a nano-processed sheet is produced. Then, the mask layer 1 of the nano-processed sheet is laminated on the LED wafer. Then, an energy line represented by UV light is irradiated to peel off the mold. Dry etching is performed on the resultant mask layer 2 / mask layer 1 / LED wafer on the mask layer 2 side to partially expose the LED wafer. Then, the patterned wafers (1) and (10) for LEDs can be manufactured by etching the wafer for LEDs by performing etching over the mask layer. Particularly, by employing the nano-processed sheet method, the arrangement direction of the concavoconvex structures can be controlled in the direction in which the sheets are joined. For example, a nano-processed sheet is fed out and set on a winding device. Then, the LED wafer is loaded. At this time, the position of the orientation flat of the LED wafer is detected and controlled. Then, the nano-processed sheet is bonded to the loaded LED wafer. That is, the nano-processed sheet is mechanically joined in a predetermined direction. By controlling the direction of the LED wafer to be bonded, the rotation shift angle? Can be easily controlled. At this time, the resolution of the rotation shift angle? Was ± 1 °.

As described above, by adopting the transfer method, it is possible to reflect the fine pattern of the mold on the LED wafer, so that the pattern wafers 1 and 10 for LEDs can be obtained.

A mask layer for processing and forming the concave-convex structure 20 can be transferred and formed on the main surface of the LED wafer by applying the transfer method represented by the nanoimprint lithography method or the nano-processed sheet method. Here, the dry etching method for manufacturing the concave-convex structure 20 using the mask layer will be described. Particularly, it becomes effective when the mask layer formed on the LED wafer is a two or more-layer mask layer. For example, in the case of using a mask layer which is laminated from the main surface side of the LED wafer to the organic resist / inorganic resist in this order and has a concavo-convex structure composed of the organic resist and the inorganic resist on the surface, The effect of the present invention is maximized.

In the following description, the laminate on which the mask layer used to form the concave-convex structure 20 is disposed on the main surface of the LED wafer by dry-etching the LED wafer is referred to as an etching-processed material. The etch process material is an etch process material having a mask layer having a pattern width of 5 占 퐉 or less and an aspect ratio of 0.1 to 5.0 on an LED wafer and etching material to be etched It is preferable that the total thermal resistance value when placed is 6.79 x 10 &lt; ^-3 &gt; (m &lt; 2 &gt; K / W) The thermal resistance value is a value obtained by dividing the thickness of the member by the thermal conductivity (?) Of the material constituting the member.

With this structure, the etching damage to the mask layer due to heat generated at the time of etching is reduced, and the patterned wafer 1 for LED having the desired concavo-convex structure 20 can be manufactured by etching. In addition, throughput can be improved in the dry etching process by using the arrangement member, which is a component of this etching-processed material, as the carrying member.

The etch process material is disposed on the arrangement region of the arrangement members. Furthermore, even if the etching-material to be processed is disposed directly on the arrangement region of the arrangement member, the etching-processed material may be disposed through another member such as a heat-transfer sheet. Regardless, it is important that the total thermal resistance value is 6.79 x 10 ^-3 (m 2 · K / W) or less. Here, the total thermal resistance value refers to a case where the etching-processed member is disposed on the arrangement region of the arrangement member through the heat-transfer sheet as an example, the thermal resistance value of the arrangement member in the arrangement region, the thermal resistance value of the etching- Is the sum of the thermal resistance values of the heat-transfer sheet in the region. On the other hand, the heat-transfer sheet can be replaced by another member. In the case of not using another member represented by the heat-transfer sheet, the heat resistance value of the heat-transfer sheet may be set to zero.

The thermal resistance value is a value obtained by dividing the thickness of the member by the thermal conductivity (?) Of the material constituting the member. That is, the heat resistance value R (m 2 · K / W) is a value calculated by the thickness d (m) of the member / the thermal conductivity λ (W / m · K) of the member. The material and thickness of the member or layer constituting the etching-processed material, and the material and thickness of the arrangement member are adjusted so that the total thermal resistance value becomes R? 6.79 × 10 ^-3 (m 2 · K / W). In other words, the patterned wafer 1 for LED can be manufactured with high precision by performing dry etching by applying the conditions satisfying the entire range of the thermal resistance value R. Thermal resistance of the whole, it is more preferable not more than ^{R≤3.04 × 10 -3 (㎡ · K} / W) is preferable ^{and, R≤1.21 × 10 -3 (㎡ ·} K / W) or less than. It is preferable that the lower limit of the total thermal resistance value R is 0? R. On the other hand, the thermal resistance value can be easily measured by a laser flash method.

Regarding the thickness d of the arrangement member, there is no lower limit from the viewpoint of the thermal resistance value. However, if the thickness d of the arrangement member is too small, there is a possibility that the arrangement member is damaged during transportation of the arrangement member. , For example, 0.001 m or more. In addition, there is an upper limit for the thickness d, which is considered from the viewpoint of the thermal resistance value. At the same time, the thickness d of the arrangement member is preferably 0.05 m or less from the viewpoints of workability and cost in transportation.

The arrangement member is a member for arranging the etch material to be processed and can be used as a conveyance tray for fixing or conveying the etch material to be etched. By using the arrangement member, it is possible to reduce the positional deviation of the etch material to be processed when the etch material to be processed is conveyed to the vacuum reaction tank of the dry etching apparatus. Further, since the plurality of etch materials to be processed can be simultaneously conveyed, the throughput is increased. As the material of the positioning element, such as silicon (Si), aluminum (Al), a metal material such as stainless steel, quartz (SiO _2), silicon carbide (SiC), silicon nitride (SiN), alumina (Al ₂ O ₃₎ , Ceramics such as aluminum nitride (AlN), zirconia oxide (ZrO ₂ ) and yttria oxide (Y ₂ O ₃ ), silicon or aluminum coated with an alumite, silicon or aluminum coated with ceramics on the surface thereof, And metal materials such as silicon and aluminum. These materials are not particularly limited as long as the condition of the total heat resistance value R is satisfied, but it is preferable to select a material from which a reactant with high deposition property is not generated in the dry etching gas. More preferably, silicon (Si), quartz (SiO ₂ ), and aluminum (Al) have a high availability and workability of the arrangement member, silicon carbide (SiC), alumina (Al ₂ O ₃ ) AlN), zirconia oxide (ZrO ₂ ), yttria oxide (Y ₂ O ₃ ), or an inorganic member coated with at least one of them is preferable in view of difficulty in producing reactants with high deposition properties. On the other hand, the inorganic material used here is concretely a metal material having high workability such as silicon (Si) or aluminum. By covering the inorganic member with a material such as silicon carbide (SiC) that does not generate highly accumulative reactants, both ease of processing and responsiveness to dry etching can be achieved. In this case, aluminum nitride (AlN) or the like may not be made of aluminum nitride (AlN) at 100% at the time of covering, partly be made of alumina (Al ₂ O ₃ ) or the like, and the coating layer may be a mixture . Thus, the term &quot; coated with any one or more of them &quot; means that a case where different materials are mixed together when a material is to be coated is meant to be included.

The shape of the arrangement member is not particularly limited as long as the condition of the total heat resistance value R is satisfied, and examples thereof include a thin plate circle shape and a thin plate shape. The surface of the disposing member need not be flat, but may have recesses (hole breaking, pockets) for accommodating the etching-processed material. The arrangement member is not necessarily composed of a single material, but may be composed of two or more kinds of materials. The arrangement member does not need to be formed as a single structure but may be formed by combining two or more kinds of structures such as a base portion and a lid for fixing an etching-processed material by covering a part of the etch-processed material.

The etching damage can be reduced by the dry etching process that satisfies the range of the thermal resistance value R described above. As a result, the patterned wafer 1 for LEDs having a highly concave and convex structure A can be manufactured. Here, the mask layer is preferably a mask layer of two or more layers as described above, and this can be easily manufactured by a nano-imprinting method or a nano-imprint method for two or more layers of resists. In particular, by using a nano-processed sheet, it is possible to form a mask layer having two or more layers with high precision.

For example, a transfer method is applied to obtain a two-layer resist on the main surface of the LED wafer. For example, it is assumed that the organic resist / inorganic resist film is formed in order from the side near the LED wafer, and at least the inorganic resist forms a concave-convex structure. In this case, first, in the case of the nanoimprint method, it is necessary to partially remove the residual film existing in the inorganic resist and the organic resist, and in the case of the nano-processed sheet method, only the organic resist may be partially removed. This process is referred to as a residual film removal process. In the residual film removing step, reactive etching is preferably used, for example, by a gas containing at least one of O ₂ gas, H ₂ gas, Xe gas and Ar gas. For example, when the etching pressure is 0.1 Pa to 5 Pa, the processing accuracy is improved. In particular, by using only the O ₂ gas or a gas containing 50 vol% or less of Ar gas in the O ₂ gas, the processing accuracy is improved. As a result, a fine pattern mask having a high aspect ratio can be formed on the wafer for LED.

In this step of forming a fine pattern mask, it is not always necessary to use a disposing member, and it is not necessary to select the material and shape of each member so as to be within the range of the total heat resistance value R.

The etching method for improving the processing accuracy of the concavo-convex structure 20 of the patterned wafer for LED 1 is an etching method in which a mask layer having a pattern with a pattern width of 5 mu m or less and an aspect ratio of 0.1 to 5.0 is formed on an LED wafer The LED wafer is etched using the mask layer as a mask under the condition that the total heat resistance value R is 6.79 x ^10-3 (m &lt; 2 &gt; K / W) or less by arranging the etch- do. As a result, etching damage to the fine pattern mask is suppressed, etching uniformity of the fine pattern mask in the etching process is maintained, and the accuracy of the concavo-convex structure 20 of the pattern wafer 1 for LED is improved.

From the viewpoint of etching the wafer for LED, etching using chlorine-based gas or fluorine-based gas can be performed. A mixed gas containing at least one of fluorine-based gases (CxHzFy: x = 1 to 4, y = 1 to 8, and z = 0 to 3) easy to reactively etch the LED wafer is used . Examples of the fluorine-based gas include CF ₄ , CHF ₃ , C ₂ F ₆ , C ₃ F ₈ , C ₄ F ₆ , C ₄ F ₈ , CH ₂ F ₂ and CH ₃ F. In order to improve the etching rate of the wafer for LED, a gas obtained by mixing Ar gas, O ₂ gas and Xe gas in the flon gas with 50% or less of the total gas flow rate is used. As the fluorine-based gas, it is difficult to etch an LED wafer (a difficult-etching substrate) that is difficult to be reactive etched or an LED wafer that generates a highly-deposited reactant. In the case of etching an LED wafer, at least one kind of reactive gas- Is used. Examples of the chlorinated gas include Cl ₂ , BCl ₃ , CCl ₄ , PCl ₃ , SiCl ₄ , HCl, CCl ₂ F ₂ , CCl ₃ F and the like. Further, a mixed gas of an O ₂ gas, an Ar gas, or an O ₂ gas and an Ar gas may be added to the chlorine gas in order to improve the etching rate of the etching base material.

The pressure at the time of etching is preferably 0.1 Pa to 20 Pa and more preferably 0.1 Pa to 10 Pa since the ion incident energy contributing to reactive etching is increased and the etching rate of the LED wafer is improved.

Further, two fluorine-based gases having different ratios (y / x) of C and F in the fluorine gas (CxHzFy: x = 1 to 4, y = 1 to 8 and z = 0 to 3) , It is possible to distinguish the angle of the tapered shape of the fine pattern made of the LED wafer by increasing or decreasing the deposition amount of the fluorocarbon film protecting the etching side wall of the LED wafer. When the shape of the mask for the LED wafer is more precisely controlled by dry etching, the ratio of the flow rate of F / C? 3 furon gas to the flow rate of F / C < 3 is 95 sccm: 5 sccm To 60 sccm: 40 sccm, and more preferably 70 sccm: 30 sccm to 60 sccm: 40 sccm. Even when the total flow rate of the gas is changed, the ratio of the flow rate does not change.

From the viewpoint that the etching rate of the wafer for LED is improved when the mixed gas of the front system gas and the Ar gas and the mixed gas of the O ₂ gas and the Xe gas are in a proper amount of the reactive etching component and the ion incident component, The flow rate of the gas flow rate is preferably 99 sccm: 1 sccm to 50 sccm: 50 sccm, more preferably 95 sccm: 5 sccm to 60 sccm: 40 sccm, more preferably 90 sccm: 10 sccm to 70 sccm: 30 sccm to be. From the viewpoint that the etching rate of the wafer for LED is improved when the mixed gas of the chlorine gas and the Ar gas and the mixed gas of the O ₂ gas and the Xe gas are in a proper amount of the reactive etching component and the ion incident component, The flow rate of the gas flow rate is preferably 99 sccm: 1 sccm to 50 sccm: 50 sccm, more preferably 95 sccm: 5 sccm to 80 sccm: 20 sccm, more preferably 90 sccm: 10 sccm to 70 sccm: 30 sccm to be. Even when the total flow rate of the gas is changed, the ratio of the flow rate does not change.

It is preferable to use only BCl ₃ gas or a mixed gas of BCl ₃ gas and Cl ₂ gas and a mixed gas of Ar gas or Xe gas for etching the LED wafer using chlorine-based gas. From the viewpoint that the etching rate of the wafer for LED is improved when the reactive etching component and the ion incident component are in a proper amount, these gas mixtures preferably have a gas flow rate ratio of 99 sccm: 1 sccm to 50 sccm: 50 sccm, More preferably 99 sccm: 1 sccm to 70 sccm: 30 sccm, and more preferably 99 sccm: 1 sccm to 90 sccm: 10 sccm. Even when the total flow rate of the gas is changed, the ratio of the flow rate does not change.

As the plasma etching, a capacitive coupled RIE, an inductively coupled type RIE, an inductively coupled type RIE, or an RIE using an ion attracting voltage can be used. For example, a gas obtained by mixing only CHF ₃ gas or CF ₄ and C ₄ F ₈ at a gas flow rate ratio of 90 sccm: 10 sccm to 60 sccm: 40 sccm is used, and the processing pressure is set in the range of 0.1 to 5 Pa While RIE using capacitive coupled RIE or ion pull-in voltage is used. Further, for example, in the case of using the chlorine-based gas is BCl ₃ gas only, or BCl ₃ gas and Cl ₂ gas or Ar gas, the gas flow rate 95 sccm: 5 sccm ~ 85 sccm : using the mixed gas between 15 sccm and RIE in which a process pressure is set in a range of 0.1 to 10 Pa and a dose-coupled RIE, an inductively coupled RIE or an ion attracting voltage is used.

Further, for example, in the case of using the chlorine-based gas is BCl ₃ gas only, or BCl ₃ gas and Cl ₂ gas or an Ar gas Gas flow rate 95 sccm: 5 sccm ~ 70 sccm : using the mixed gas between 30 sccm and RIE using capacitive coupling type RIE, inductively coupled type RIE, or ion attracting voltage is used while setting the processing pressure in the range of 0.1 Pa to 10 Pa. Further, even when the total gas flow rate of the mixed gas used for etching is changed, the above-mentioned flow rate ratio does not change.

In the dry etching process of the LED wafer, the LED wafer is etched in the state of the etch processed material which is in the range of the total thermal resistance value (R). Thus, even when a fine pattern mask having a pattern width of 5 mu m or less and an aspect ratio of 0.1 to 5.0 is used as a mask, the dry etching damage can be reduced by dry etching the LED wafer in this way, As a result, a concave-convex structure can be formed on the wafer for LED.

The process of forming the fine pattern mask and the dry etching process of the wafer for LED may be continuously performed by the same apparatus. In this case, the material and the shape may be selected so as to satisfy the range of the total thermal resistance value R using the arrangement member in the process of forming the fine pattern mask.

<< Manufacturing Method of Epitaxial Wafer for LED >>

Next, a manufacturing method of the epitaxial wafer 100 for LED will be described. The epitaxial wafer 100 for an LED according to the present embodiment can be fabricated by forming the ratio Hbun / Have and / or the ratio Hbu / Have (described above) on the concavo-convex structure 20 of the pattern wafers 1 and 10 for LED The light emitting semiconductor layer 40, and the second semiconductor layer 50 are sequentially formed so as to satisfy the following expression (1). Particularly, a process of preparing the LED pattern wafers 1 and 10, a process of performing optical measurement on the LED pattern wafers 1 and 10, and a process of using the LED pattern wafers 1 and 10 It is preferable to include the step of manufacturing the epitaxial wafer 100 for LED in this order. In this case, since the accuracy of the pattern wafers 1 and 10 for LEDs can be evaluated in advance, the degree of improvement of the internal quantum efficiency IQE and the light extraction efficiency LEE can be predicted in advance. As the optical measurement, it is possible to employ both of the detection of reflected light and the detection of transmitted light. Particularly, since a highly versatile apparatus can be used, it is preferable to measure haze when transmitting light is detected. On the other hand, from the viewpoint of more accurately determining the accuracy of the concavoconvex structure 20, a method of detecting reflected light is preferable. In this case, depending on the arrangement and size of the concavo-convex structure A, it is possible to appropriately set which of the regular reflection component or the diffuse reflection component is to be detected. The accuracy of the contour of the concavoconvex structure 20 can be evaluated by using the regular reflection component and the volume accuracy of the concavoconvex structure 20 can be evaluated by using the diffuse reflection component. Which is adopted can be appropriately selected in accordance with the concavoconvex structure 20 and the purpose of use. (Diffuse reflection component-specular reflection component), (diffuse reflection component-specular reflection component) / specular reflection component, (diffuse reflection component-specular reflection component) / diffuse reflection component or the like have. In the optical measurement, the defects of the concave-convex structure 20 can be effectively evaluated by making the wavelength of the light source larger than the average interval (Pave) of the concave-convex structures 20.

As described above, by using the patterned wafer 1 for LEDs, the effect of the rotational shift angle? And the shape of the convex top portion is developed, and cracks to the semiconductor layer can be satisfactorily suppressed. In addition, the internal quantum efficiency (IQE) can be effectively improved. Here, by using the pattern wafers 2 for LEDs described below, it is possible to further improve the light extraction efficiency (LEE) while maintaining the above-described effects. The LED pattern wafers (2) are characterized by forming another uneven structure (L) in addition to the pattern wafers (1) for LED. By this concavoconvex structure L, strong light scattering property can be imparted and the light extraction efficiency (LEE) can be further improved.

Regarding the pattern wafers 2 for LED, the concavo-convex structure A corresponds to the concavo-convex structure A described in the pattern wafer 1 for LED. In other words, the LED pattern wafers 1 are provided with a concavo-convex structure L as the concave-convex structure. Therefore, in addition to the effect on the patterned wafer 1 for LED, the effect of the newly added concavo-convex structure L is exhibited. Therefore, it is possible to effectively improve the light extraction efficiency (LEE) in addition to effectively suppressing the crack, greatly improving the crystal quality of the semiconductor layer, and improving the internal quantum efficiency (IQE).

Hereinafter, the patterned wafer for LED 2 will be described in detail. On the other hand, as already described, the pattern wafers 2 for LEDs are further provided with a concavo-convex structure L for the pattern wafers 1 for LEDs. Therefore, in the following description, the description of the added concavo-convex structure L is mainly described. For this reason, other constituent features of the patterned wafer 2 for LEDs, epitaxial wafers for LEDs using the patterned wafers 2 for LED, LED chips using the patterned wafers 2 for LEDs, and patterned wafers 2 for LEDs, A detailed description of the manufacturing method of the LED pattern wafers 1 will be omitted.

The definitions described in the description of the pattern wafer 1 for LED are also applied to the pattern wafer 2 for LED.

The patterned wafer 2 for an LED according to the present embodiment has a concavo-convex structure A having a substantially symmetrical arrangement n times and a substantially symmetrical arrangement At least a part of the concavo-convex structure (A) has a concave-convex structure (L) having a concave-convex structure (L) And the angle (?) Satisfies 0 DEG <? (180 / n) DEG. In other words, the LED pattern wafers 2 according to the present embodiment are arranged on the surface having the concavo-convex structure A of the pattern wafer 1 for LED, (L) having a convexo-concave structure (L).

According to this configuration, the internal quantum efficiency (IQE) of the epitaxial wafer for LEDs using the patterned wafer 2 for LEDs is improved, and the surface having the concavo-convex structure of the patterned wafer 2 (hereinafter, Can be suppressed from being cracked in the semiconductor layer. In addition, light efficiently emitted from the LED can be extracted to the outside of the LED. In other words, it is possible to realize the effect described in the patterned wafer 1 for LED and to improve the light extraction efficiency (LEE) by the concavo-convex structure L.

First, since the concavo-convex structure A of the patterned wafer for LED is the concavo-convex structure A of the patterned wafer 1 for LED described above, it is possible to form a semiconductor layer with a reduced crack by the same principle, Thus, a high-quality semiconductor crystal can be obtained. Further, the internal quantum efficiency (IQE) of the epitaxial wafer for LED can be improved. Hereinafter, the effect of the concavo-convex structure (A) is described, but this can be read with the same effect as the effect of the concavo-convex structure (A) of the pattern wafer for LED (1).

In the patterned wafer 2 for an LED according to the present embodiment, the concave-convex structure L is constituted by a plurality of convex portions and concave portions each having a first average interval PL, And a plurality of convex portions and concave portions formed on at least one surface of the convex portion and the concave portion constituting the concave and convex structure L and having a second average interval PA, (PL / PA) of the second average spacing (PL) to the second average spacing (PA) is preferably more than 1 and less than 2000. Here, the second average spacing PA refers to the average spacing Pave described for the patterned wafer 1 for LED.

According to this configuration, it is possible to increase the difference seen from the luminescent light of the concavo-convex structure A and the concave-convex structure L while suppressing the effect of the concavo-convex structure A by the concavo-convex structure L. [ That is, the function of the patterned wafer 1 for LED can be effectively exhibited, and at the same time, the light extraction efficiency (LEE) can be further improved. This light extraction efficiency (LEE) is attributed to the provision of large optical scattering property by the uneven structure (L).

In the patterned wafer 2 for LED according to the present embodiment, the plurality of convex portions constituting the convexo-concave structure L are spaced apart from each other, and at least the bottom (s) of the concave portions constituting the concave- And the convex portion or the concave portion constituting the convexo-concave structure (A) is preferably formed in the concave portion.

According to this constitution, particularly the effect of the concavo-convex structure (A) is improved. The semiconductor layer can be preferentially grown from the bottom of the concave portion of the concave-convex structure L by forming the concave-convex structure A in the concave portion of the concave-convex structure L. [ Here, since the concave-convex structure A is formed at the bottom of the concave portion, the crack can be suppressed and the internal quantum efficiency (IQE) can be effectively improved by the principle already described.

In the patterned wafer 2 for LED according to the present embodiment, a plurality of the recesses constituting the convexo-concave structure L are spaced apart from each other, and at least the tops of the convex portions constituting the concave- It is preferable that the convex portion or the concave portion constituting the concavoconvex structure A is formed.

According to this configuration, especially the light extraction efficiency (LEE) can be improved. The cracking suppression effect and the internal quantum efficiency IQE (IQE) are improved for the semiconductor layer grown at the convex portion of the concave-convex structure L by forming the concave-convex structure A at the top of the convex portion of the concave- ) Improvement effect can be exhibited. In this case, a space in which the semiconductor layer is not formed can be formed in the concave portion of the concavo-convex structure L. This space has a very small refractive index when viewed from the semiconductor layer. That is, since the difference in refractive index can be increased, the optical scattering property is increased and the light extraction efficiency (LEE) is further improved. In addition, since it is easy to remove the pattern wafers 2 for LED, the laser lift off can be suitably operated depending on the type of the LED.

In the patterned wafer 2 for LED according to the present embodiment, it is preferable that the coating rate of the concavo-convex structure (A) with respect to the concave-convex structure (L) is more than 0% and less than 100%.

With this configuration, when the coating rate exceeds 0%, the effect of the concavo-convex structure (A) described above, that is, the crack can be suppressed and the internal quantum efficiency (IQE) can be improved. On the other hand, when the coating rate is less than 100%, the nucleation and growth of the semiconductor layer can be well maintained. As a result, the growth of the semiconductor layer becomes good, the crack can be suppressed, and the semiconductor layer having a high internal quantum efficiency (IQE) can be formed.

In the patterned wafer 2 for an LED according to the present embodiment, the concave-convex structure A is composed of a plurality of convex portions and concave portions having a first average interval PA, (A) is partially exposed on the surface of the concavoconvex structure (A), and is formed of a plurality of convex portions having a second average interval (PL), and the first average interval PA (PL / PA) of the first average interval PL and the second average interval PL is more than 1 and not more than 2000. Here, the first average spacing PA refers to the average spacing Pave described in the patterned wafer 1 for LED.

According to this configuration, the effect of the concavo-convex structure (A) can be exhibited and the light extraction efficiency (LEE) can be improved. First, the LED pattern wafers 2 have a concavo-convex structure A on its surface, and the concavo-convex structure A includes an exposed portion. Therefore, cracks are suppressed and the internal quantum efficiency IQE ) Can be formed. Then, a concave-convex structure L is formed on the surface of the concave-convex structure A. This concavoconvex structure L has a larger average spacing than the concavoconvex structure A. Therefore, the optical scattering property becomes strong. That is, it is possible to form a semiconductor layer in which cracks are suppressed, and the potential of the semiconductor layer is reduced, so that the internal quantum efficiency IQE is increased. In addition, light emitted effectively by the high internal quantum efficiency (IQE) can be extracted to the outside of the LED by optical scattering.

In the patterned wafer 2 for LED according to the present embodiment, it is preferable that the average spacing PA of the concavo-convex structure A is 50 nm or more and 1500 nm or less. Here, the average distance PA refers to the average distance Pave described in the patterned wafer 1 for LED.

According to this configuration, the effect of the concavo-convex structure (A) is further improved in the principle described for the pattern wafer for LED (1).

In the patterned wafer 2 for LED according to the present embodiment, the duty (? Ave / PA), which is the ratio of the average width (? Ave) of the convex bottom portions of the concave- , The rotation shift angle? Preferably satisfies the range of atan (duty / 2)??? (180 / n) °.

According to this configuration, the effect of the concavo-convex structure (A) becomes more conspicuous on the same principle as the patterned wafer (1) for LED. Therefore, the internal quantum efficiency IQE is further improved, and the cracks in the semiconductor layer are effectively suppressed.

In the following description, when concave and convex structures A and L are described at the same time, the expression concave and convex structure (AL) is used. The patterned wafer 2 for LED according to the present embodiment has a concave-convex structure AL on its surface. The concavo-convex structure AL may be formed by machining a single-sided surface of the wafer for LED, or may be formed separately on one surface of the wafer for LED. That is, the materials constituting the LED wafer and the materials constituting the concavo-convex structure (A) and / or the concavo-convex structure (L) may be the same or different. The convex-and-concave structure (A) has a substantially symmetrical arrangement of n times, and the previously described rotational shift angle (?) Shows a predetermined range, and the shape of the convex top portion is a corner portion having a radius of curvature of more than 0 . On the other hand, the shape of the convex portion may include a table top having a size of 100 nm or less, as already described in the patterned wafer 1 for LED.

Next, the relationship between the arrangement of the concavo-convex structure (A) and the arrangement of the concavo-convex structure (L) will be described. As described above, the concavoconvex structure A is formed on the wafer for LED so that the rotational shift angle? Is within a predetermined range. Here, the rotational shift angle of the arrangement axis L of the concavoconvex structure L with respect to the LED pattern wafer is not particularly limited, but the internal quantum efficiency IQE and the crack suppressing effect can be further improved by satisfying the following range . In the following description, the rotational shift angle? With respect to the arrangement axis A of the concavoconvex structure A is denoted by? A and the rotational shift angle? With respect to the arrangement axis L of the concavoconvex structure L is denoted by? L . The rotation shift angle? L can be defined by reading the concavo-convex structure A in the concavo-convex structure L and reading the array axis A in the array axis L in the definition of the rotation shift angle? have.

? (= |? L -? A |) which is the difference between the rotation shift angle? L and the rotation shift angle? A satisfies the range of 0 占??? (180 / n). Particularly, satisfying the condition of 0 deg. DELTA &amp;thetas; &amp;le; attan (duty / 2 DEG) further increases the internal quantum efficiency IQE and the crack suppression effect. On the other hand, the duty is the duty of the concavoconvex structure A. This is because, in the adhesion of the nucleus of the semiconductor layer improved by the concavo-convex structure (A), the growth, and the merging of the growing semiconductor layers, the surface of the semiconductor layer and the convexity This is because the positional relationship becomes appropriate.

More specifically, since the angle formed by the arrangement axis L of the concave-convex structure L and the surface which is likely to be formed by the growth of the semiconductor layer becomes small, the stress applied from the concavoconvex structure L to the growing semiconductor layer is Can be reduced. As a result, the growth of the semiconductor layer can be maintained favorably, so that the semiconductor layers to be grown are well integrated, the potential is reversed and reduced, and cracks can be suppressed. Among them, it is preferable to satisfy 0 占 Θ L? Atan (duty / 2) 占 because the above effects can be further exerted. Particularly, since the density of convex portions of the concave-convex structure L through which the semiconductor layer to be grown passes is equalized by satisfying 0 占 Θ L? [Atan (duty / 2) 占] / 2, confusion of semiconductor layer growth is suppressed It is preferable. From the same effect, it is most preferable that 0??? L? [Atan (duty / 2)?] / 4 is satisfied. On the other hand, it is considered that the amount of particles generated when the LED is chipped can be reduced by satisfying atan (duty / 2)????? (180 / n) This is because the number of convex portions of the concavo-convex structure L decreases when viewed in the cutting direction when the LED is chipped when the range is satisfied. Of these, it is preferable that the above effect is further exerted by satisfying atan (duty / 2) DEG &amp;le; L (180 / n) DEG.

The concavoconvex structure A has a substantially symmetrical arrangement n times, and satisfies the previously described rotation shift angle? A. On the other hand, the concavo-convex structure L has an arrangement substantially symmetrical m times. The relationship between the rotation shift angle? L and the rotation shift angle? A and the rotation shift angle? L with respect to the concavoconvex structure L is the same as that already described. The rotational symmetry degree n of the concave-convex structure A and the rotational symmetry degree m of the concave-convex structure L may be the same or different. (6, 6), (6, 4), (6), and (6), the combination of the rotational symmetry order n of the concave- convex structure A and the rotational symmetry order of the concave- , 2), (4,6), (4,4), (4,2), (2,6), (2,4) or (2,2). (6,6), (4,6), (2,6), (6,2), and (6,2) are preferable from the viewpoint of more satisfactorily developing the function of the uneven structure (A) , (4,2) or (2,2), and most preferably (6,6), (4,6) or (2,6).

(Concavo-convex structure (L))

Next, the concave-convex structure L will be described. The main function of the concavo-convex structure L is to improve the light extraction efficiency (LEE). Therefore, it is preferable that the light emitting structure of the LED effectively causes optical scattering (light scattering or light diffraction) phenomenon or reflection phenomenon, and the concavo-convex structure L described below can be employed.

The average spacing PL of the concavo-convex structures L is preferably in a range larger than the average spacing PA of the concave-convex structures A from the viewpoint of effectively expressing optical scattering properties (light diffraction or light scattering) It is preferable that the interval PL> the average interval PA be satisfied, and at the same time, it is preferably 1000 nm or more and 100 m or less. In particular, the average interval PL is preferably 1200 nm or more, more preferably 1,500 nm or more, and more preferably 1,500 nm or more, from the viewpoint of manifesting the optical diffraction property more effectively and effectively disturbing the waveguide mode and improving the light extraction efficiency (LEE) And most preferably at least 2000 nm. On the other hand, the upper limit value is preferably 50 m or less, more preferably 20 m or less, and most preferably 10 m or less in view of the production time of the concavo-convex structure L and the amount of the semiconductor layer used.

The width of the convex portion of the convexo-concave structure L is set such that the convex portion 703 of the convexo-concave structure L is convexo-concave, as shown in Figs. 27A and 27B, Is not particularly limited as long as the structure (A) is formed. This is because the first semiconductor layer grows on the exposed surface of the LED wafer 702 when the material of the concavoconvex structure L and the LED wafer 702 are different. On the other hand, when the material of the concave-convex structure L and the material for the LED wafer 702 are the same, it is possible to reduce the potential generated at the top of the convex portion 703 of the convexo-concave structure L by the concave-convex structure A . The internal quantum efficiency IQE and the light extraction efficiency LEE can be obtained regardless of the arrangement of the concavoconvex structure L with respect to the concavo-convex structure L when the concavoconvex structure L and the LED wafer 702 are made of the same material The ratio of the width of the convex portion top of the concavo-convex structure L to the width of the concave portion opening of the concavo-convex structure L (width of the convex top portion / width of the concave portion opening) is preferably as small as possible, Most preferably, substantially zero. In other words, the convex portion of the concavo-convex structure L is most preferably a corner portion having a radius of curvature of more than 0, like the convex portion of the concavo-convex structure A. On the other hand, from the examination results of the pattern wafer 1 for LED, it can be considered that each corner having a radius of curvature of more than 0 includes a case where the size of the table top is 100 nm or less. On the other hand, if the ratio is 0, it means that the width of the convex portion is 0 nm. However, even when the width of the convex portion is measured by a scanning electron microscope, for example, 0 nm can not be accurately measured. Therefore, it is assumed that the width of the convex top portion herein includes all cases where the width is equal to or less than the measurement resolution. When the ratio (the width of the convex top portion / the width of the concave portion opening) is 3 or less, the film forming property of the semiconductor layer can be kept good. This is because the amount of semiconductor that grows at the top of the convex portion 703 of the concave-convex structure L can be reduced. Further, when the ratio is 1 or less, the light extraction efficiency (LEE) can be improved. This is because the refractive index distribution of the patterned wafer (2) 710 for LED and the concavo-convex structure L made of the semiconductor layer becomes appropriate when viewed from the emitted light. From the viewpoint of greatly improving the above-described internal quantum efficiency (IQE) and light extraction efficiency (LEE), the ratio is preferably 0.4 or less, more preferably 0.2 or less, and further preferably 0.15 or less.

When the concavoconvex structure L and the LED wafer 702 are made of the same material and the concave portion 704 of the concavo-convex structure L has a flat surface, the internal quantum efficiency IQE can be improved, The difference between the semiconductor film forming apparatuses can be reduced. In order to improve the internal quantum efficiency (IQE), it is necessary to disperse the electric potential inside the semiconductor layer to reduce the local and macroscopic dislocation density. Here, the initial conditions of these physical phenomena are nucleation and nucleation when a semiconductor layer is formed by CVD (Chemical Vapor Deposition), VPE (vapor phase epitaxy), or sputtering. The nucleation of the bottom of the concave portion of the concavoconvex structure L can be suitably performed by providing the flat surface at the bottom of the concave portion 704 of the concavoconvex structure L. Therefore, And stabilized. As a result, the internal quantum efficiency (IQE) can be increased.

On the other hand, when the uneven structure L is different from the material for the LED wafer 702, the uneven structure L is partially formed on the LED wafer 702, that is, The growth of the first semiconductor layer is realized. Therefore, the concavo-convex structure L in the case where the concavo-convex structure L and the LED wafer 702 are made of different materials is different from the concavo-convex structure L in that the convex portion formed on the LED- And a wafer 702. For example, sapphire, SiC, a nitride semiconductor, when a Si or a LED wafer 702 for the spinels, metal aluminum, amorphous aluminum oxide, polycrystalline aluminum oxide, polycrystalline sapphire, silicon oxide (SiO _2), silicon nitride (Si ₃ N _4), silver (Ag), chromium (Cr), nickel (Ni), of gold (Au) or platinum (Pt), it is possible to form the convex portion 703 is composed of any one or a mixture of two or more.

The duty of the concave and convex structure L expressed by the ratio of the average width of the convex portion bottom portion of the concavo-convex structure L to the average interval PL (average width PL of the convex portion / PL) It is preferably 0.03 or more and 0.83 or less. 0.03 or more, the volume of the convex portion of the concave-convex structure L becomes large, and the optical scattering property is improved. In the same effect, the ratio is more preferably 0.17 or more, and most preferably 0.33 or more. On the other hand, when it is 0.83 or less, the area of the bottom of the concave portion of the concavo-convex structure L can be increased, so that the nucleus attachment and growth of the semiconductor layer and the coalescence of the growing semiconductor layers can be improved. Thus, the internal quantum efficiency IQE can be increased. In the same effect, the ratio is more preferably 0.73 or less, and most preferably 0.6 or less.

The light extraction efficiency due to the optical scattering property by the concavo-convex structure L can be improved by setting the aspect ratio of the concave-convex structure L, that is, the average height of the concave-convex structure L / the average width of the convex portion bottom of the concave- (LEE) can be improved. In particular, from the viewpoint of increasing the number of modes of the optical diffraction, it is preferably 0.3 or more, more preferably 0.5 or more, and most preferably 0.8 or more. On the other hand, from the viewpoint of suppressing cracks and voids to the semiconductor layer, the aspect ratio is preferably 5 or less. In addition, since the time for fabricating the concave-convex structure L can be shortened and the amount of semiconductor used can be reduced, it is more preferably 2 or less, and most preferably 1.5 or less.

The height H of the convex portion 703 of the concavoconvex structure L is preferably 2 times or more of the mean spacing PL in view of the time required for manufacturing the concavoconvex structure L and the amount of semiconductor crystal used . Particularly, when the average spacing PL is equal to or less than the average spacing PL, the refractive index distribution of the concavo-convex structure L becomes appropriate when viewed from the emitted light, so that the light extraction efficiency LEE can be further improved. From this viewpoint, the height H of the concavo-convex structure L is preferably 0.8 times or less, and most preferably 0.7 times or less, the average spacing PL.

Next, the relationship between the uneven structure (A) and the uneven structure (L) will be described. The pattern wafers 2 for an LED of the present invention have the concavo-convex structure A having the average spacing PA satisfying the previously described rotation shift angle? A and the concavo-convex structure L having the average spacing PL And the average interval PL and the average interval PA are different within a predetermined ratio range.

Here, the concavo-convex structure A on one side mainly has a function of improving the light extraction efficiency (LEE) mainly and the convex structure L on the other side mainly has an internal quantum efficiency IQE) and crack suppression. In order to enhance the functions of the respective concavo-convex structures L or A to complement each other, in other words, to improve the internal extraction efficiency (IQE) by suppressing the cracks, LEE does not deteriorate and the internal quantum efficiency IQE is lowered by the other convexo-concave structure L that improves the light extraction efficiency LEE and cracks do not occur. Therefore, (A or L) is formed on at least a part of the surface of the substrate (L or A). On the other hand, the rotation shift angles [Theta] L and [Delta] [theta] are the same as those already described.

27 is a schematic cross-sectional view showing an example of the patterned wafer 2 for LED according to the present embodiment. The LED pattern wafers 2 and 710 shown in Figs. 27A and 27B have a concave-convex structure 720 formed on the main surface of the LED wafer 702, and the concave- (Hereinafter referred to as a concavo-convex structure L) and a second concavo-convex structure (hereinafter referred to as concavo-convex structure A). The concavoconvex structure L has a concave portion 704 (or concave portion 704) that connects the convex portion 703 (or the concave portion 704) and the adjacent convex portion 703 (or the concave portion 704) Or convex portion 703). The plurality of convex portions 703 (or concave portions 704) have an average interval PL.

On the other hand, the concave-convex structure A includes a plurality of convex portions 705 (or concave portions 706) formed on the convex portions 703 and the concave portions 704 constituting the concave-convex structure L, And a concave portion 706 (or a convex portion 705) that connects the convex portion 705 (or the concave portion 706) The plurality of convex portions 705 (or the concave portions 706) have an average interval PA. In Fig. 27A, concavoconvex structures A are formed on the top surface of a plurality of convex portions 703 and the bottom portion of concave portion 704. 27B, concavoconvex structures A are formed on the tops of convex portions 703 connecting a plurality of independent concave portions 704. On the other hand, the concavoconvex structure A is not limited to the example shown in Figs. 27A and 27B, but may be formed on the surface of at least one of the convex portion 703 and the concave portion 704.

On the other hand, the concavoconvex structure A satisfies the previously described rotation shift angle?. It is also preferable that the shape described above is satisfied. It is also preferable that the arrangement of the concavoconvex structures L satisfy the previously described rotation shift angle? L or??.

On the other hand, the concavoconvex structure A may be formed on the side surface of the convex portion 703 connecting the convex portion 703 and the bottom of the concave portion 704. When the concavoconvex structure A is formed on the side surface of the convex portion 703, it is considered that the effect of disturbing the waveguide mode is further strengthened and the traveling direction of the scattered light can be further changed in the thickness direction of the LED. Therefore, it becomes easy to select the sealing material when the LED is packaged.

(Case 1)

In particular, it is preferable that the concavo-convex structure L comprises a plurality of convex portions 703 spaced from each other and at least the concavo-convex structure A is formed at the bottom of the concave portion 704 of the concave- Do.

In this case, the growth of the semiconductor layer can be started with the bottom of the concave portion 704 of the concavoconvex structure L as a starting point. Particularly, since the uneven structure A is formed at the bottom of the concave portion 704, the adhesion and growth of the nuclei of the semiconductor layer described above and the coalescence of the growing semiconductor layers become better, The potential of the semiconductor layer can be suppressed in the vicinity thereof, and at the same time, the crack can be reduced. In addition, since the concavoconvex structure L is composed of the plurality of convex portions 703, it is possible to suppress the cracks in the vicinity of the convex portions 703 of the semiconductor layer growing at the bottom of the concave portions 704. That is, it is possible to improve the internal quantum efficiency (IQE) and improve the reliability of the LED. In addition, as described below, the concavo-convex structure L and the concavo-convex structure A satisfy the relation of the predetermined average interval, so that the optical scattering property becomes large. In particular, since the concavo-convex structure A is formed at least on the bottom of the concave portion 704, the waveguide mode can be disturbed by light scattering or optical reflection, Therefore, the light extraction efficiency (LEE) is simultaneously improved.

(Case 2)

The concavo-convex structure L is constituted by a plurality of mutually spaced concave portions 704 and convex portions 703 constituting the concavo-convex structure A at least at the top of the convex portions 703 of the concave- 705 or recesses 706 are preferably formed.

In this case, it is possible to start the growth of the semiconductor layer from the top of the convex portion 703 of the concave-convex structure L as a starting point. In particular, by forming the concavo-convex structure A at the top of the convex portion 703, cracks can be suppressed to the semiconductor layer and the internal quantum efficiency IQE can be improved, as described above. At this time, the semiconductor layer that grows from the top of the convex portion 703 has better growth performance than the semiconductor crystal that grows from the bottom portion of the concave portion 704. Therefore, the semiconductor layer grown from the bottom of the concave portion 704 can be blocked by the semiconductor layer grown from the top of the convex portion 703. Therefore, cracks are suppressed and the internal quantum efficiency (IQE) is effectively improved. In addition, depending on the growth conditions of the semiconductor layer, it is also easy to generate voids in the recesses 704. [ In this case, the removal accuracy is improved when the pattern wafers (2) 710 for LEDs are removed by, for example, laser lift-off. In addition, as described below, the concavo-convex structure L and the concavo-convex structure A satisfy the relation of the predetermined average interval, so that the optical scattering property becomes large. In particular, since the concavo-convex structure L is constituted by the plurality of concave portions 704, the effect of disturbing the waveguide mode becomes larger because the volume change becomes larger, and the light extraction efficiency LEE is improved.

In the pattern wafers 2 and 710 for LED according to the embodiments of the present invention described as cases 1 and 2, the coverage ratio of the concavo-convex structure A to the concavo-convex structure L is more than 0% and less than 100% .

In this case, the convex portion 703 or the concave portion 704 of the concavo-convex structure L is necessarily provided with the concave-convex structure A. Therefore, the internal quantum efficiency IQE is effectively improved by the above- Cracks inside the layer can be suppressed. On the other hand, the convex portion 703 and the concave portion 704 of the concave-convex structure L are not completely buried by the concave-convex structure A. Thus, the effect of improving the light extraction efficiency (LEE) by the concavo-convex structure (L) can be suppressed from being lowered by the concave-convex structure (A). That is, the effect of simultaneously improving the internal quantum efficiency (IQE) and the light extraction efficiency (LEE) is further enhanced.

(Case 3)

27C is a schematic cross-sectional view showing another example of the patterned wafer 2 for LED. The LED pattern wafers 2 and 710 are each provided with a concave and convex structure 720 on the main surface of the LED wafer 702 and the concave and convex structure 720 has a first concave and convex structure ) And a second concavo-convex structure (hereinafter referred to as concave-convex structure L). The concavoconvex structure A is composed of a convex portion 705 formed so as to be spaced apart from each other and a concave portion 706 connecting between adjacent convex portions 705. The plurality of convex portions 705 have an average spacing PA.

On the other hand, the concave-convex structure L is formed so as to be spaced apart from the concave-convex structure A such that the concave-convex structure A is partially exposed on the surface of the concave-convex structure A. The convex portion 705 and the concave portion And a plurality of convex portions 703 formed on the surface of the substrate 706. The plurality of convex portions 703 have an average interval PL.

The ratio of the average distance PL of the concavo-convex structures L of the pattern wafers 2 and 710 for LEDs described above with reference to Figs. 27A, 27B and 27C to the average distance PA of the concavo- 1 &lt; / RTI &gt; 1 or more and 2,000 or less, it is possible to form a semiconductor layer in which cracking is suppressed and internal quantum efficiency (IQE) is improved, and the light extraction efficiency (LEE) can be improved. Particularly, the difference between the average spacing PL and the average spacing PA is increased to prevent the light extraction efficiency LEE from being affected by the concavo-convex structure A and the internal quantum efficiency IQE by the concavo- (PL / PA) is preferably 1.1 or more, more preferably 1.5 or more, and even more preferably 2.5 or more. The ratio (PL / PA) is preferably 5.5 or more, more preferably 7.0 or more, from the viewpoint of improving the processing resolution of the concave-convex structure (A) and further improving the internal quantum efficiency (IQE) Most preferably 10 or more. On the other hand, it is possible to improve the optical scattering property (light diffraction or light scattering) by the concavo-convex structure A, improve the internal quantum efficiency IQE by the concavo-convex structure A, (PL / PA) is preferably 700 or less, more preferably 300 or less, and even more preferably 100 or less, from the viewpoint of realizing the improvement of the light extraction efficiency (LEE) Further, the stress on the semiconductor layer applied from the concave-convex structure L is reduced to further suppress cracks, the volume of the concave-convex structure L is increased, the density of the concave-convex structure A is increased, The ratio (PL / PA) is preferably 50 or less, more preferably 40 or less, and most preferably 30 or less, from the viewpoint of improving the processing accuracy of the structure L and the concavo-convex structure A.

With respect to the epitaxial wafer for LED and the LED chip using the patterned wafer 2 for LED, the same state as that in the case of using the patterned wafer 1 for LED can be adopted. In this case, the concavo-convex structure 720 composed of the concavo-convex structure L of the pattern wafer 2 for LED and the concavo-convex structure A can be alternatively read as the convexo-concave structure 20 of the pattern wafer 1 for LED have.

The ratio (Hbun) between the surface of the light emitting semiconductor layer on the side of the light emitting semiconductor layer and the surface of the light emitting semiconductor layer on the first semiconductor layer side and the average height Have of the concavoconvex structure A Hbun / Have) corresponds to the ratio (Hbun / Have) described in the pattern wafer 1 for LED.

The distance Hbu between the surface of the LED pattern wafer 2 on the side of the light emitting semiconductor layer and the surface of the undoped first semiconductor layer on the side of the first doped semiconductor layer, (Hbu / Have) with the average height (Have) of the patterned wafer (A) corresponds to the ratio (Hbu / Have) described in the patterned wafer 1 for LED.

The shape of the concavoconvex structure AL may be, for example, a line & space structure in which a plurality of cumulus shaped bodies are arranged, a lattice structure in which a plurality of cumulus shaped bodies are crossed, a dot structure in which a plurality of dots (convex portions, A hole structure in which a plurality of holes (concave) structures are arranged, or the like can be adopted. The dot structure or the hole structure may be, for example, a cone, a cylinder, a quadrangular pyramid, a square column, a hexagonal column, a hexagonal column, n square pyramid (n? 3), a square column of n? 3, a caldera type, . Here, the caldera type refers to a shape in which the tip of a large cone is brought into contact with the tip of a small cone, which is a cavity, and then a small cone is pushed into a large cone, which is also called a volcano type. On the other hand, these shapes have a shape in which the outer diameter of the bottom surface is deformed, a rounded shape with each side of the n-type bottom surface having a radius of curvature of more than 0, a side curved shape, And includes a rounded shape.

On the other hand, the dot structure is a structure in which a plurality of convex portions are arranged independently of each other. That is, each convex portion is separated by a continuous concave portion. On the other hand, each convex portion may be smoothly connected by a continuous concave portion. On the other hand, the hole structure is a structure in which a plurality of concave portions are arranged independently of each other. That is, each concave portion is separated by a continuous convex portion. On the other hand, each concave portion may be smoothly connected by a continuous convex portion.

Whether the dot structure or the hole structure is to be selected can be appropriately selected depending on the apparatus used for manufacturing the LED epitaxial wafer and the LED. Particularly, in an environment in which suppression of cracks and improvement of internal quantum efficiency (IQE) are prioritized, the concavo-convex structure (L) is preferably a dot-like structure. This is because, even with the concavo-convex structure L having a large average spacing PL, the epitaxial lateral overgrowth of the semiconductor layer is caused and at the same time the cracks at the top of the convex portion are suppressed and the internal quantum efficiency IQE This can be improved. On the other hand, in an environment in which the light extraction efficiency (LEE) is particularly desired to be increased, the concavo-convex structure (AL) is preferably a hole structure. This is because, in the case of the hole structure, a change in the refractive index as viewed from the semiconductor layer becomes suitable for the optical scattering property. On the other hand, the combination of the concavo-convex structure A and the concavo-convex structure L (the concavo-convex structure L and the concavo-convex structure A) Hole structure) or (hole structure, dot structure).

Next, the concavo-convex structure A and the concavo-convex structure L constituting the concave-convex structure 720 will be described.

28 is a schematic cross-sectional view showing another example of the patterned wafer 2 for LED according to the present embodiment, including cases (Case 1) and (Case 2) described with reference to Figs. 27A and 27B. As shown in Figs. 28A to 28C, a concave-convex structure L having a large volume change is formed on the surface of the pattern wafers 2 and 710 for LED, convex portions 703 constituting the concave- Concavo-convex structure A having a large structural density is formed on at least one surface of the concave portion 704. By adopting such a configuration, the internal quantum efficiency IQE can be improved and the crack can be reduced by the concavo-convex structure A, and the optical scattering property (light diffraction or light scattering) The extraction efficiency (LEE) can be improved. 28A to 28C show examples of arrangement of the concavo-convex structure A with respect to the concavo-convex structure L. Fig.

28A, the first concavo-convex structure L is constituted by a plurality of convex portions 703 spaced apart from each other, and at least the concave portion 704 of the first concave- It is preferable that the convex portion 705 or the concave portion 706 constituting the second concavoconvex structure A is formed in the concave portion 706.

In this case, as already described in (Case 1) and (Case 2), since the growth of the semiconductor layer can be started from the bottom of the concave portion 704 of the concavo-convex structure L as a starting point, (IQE) can be improved and cracks can be suppressed. Further, the reliability of the LED can be improved. Further, as described above, the concavo-convex structure L and the concavo-convex structure A satisfy the relation of the predetermined average interval, so that the optical scattering property becomes large. In particular, since the concavo-convex structure A is formed at least on the bottom of the concave portion 704, the waveguide mode can be disturbed by light scattering or optical reflection, Therefore, the light extraction efficiency (LEE) is simultaneously improved.

28B, the concavo-convex structure L is constituted by a plurality of concave portions 704 spaced from each other, and at least a convex portion 703 of the convex portion 703 of the concave- It is preferable that the convex portion 705 or the concave portion 706 constituting the light guide plate A is formed.

 In this case, the growth of the semiconductor layer can be started with the top of the convex portion 703 of the concavoconvex structure L as a starting point, as already described in (Case 1) and (Case 2). Therefore, the potential of the semiconductor layer that grows at the top of the convex portion 703 can be effectively reduced and the crack can be reduced. Also, since it is easy to generate a gap in the concave portion 704, the removal accuracy is improved when the pattern wafers 2 and 710 for LED are removed by, for example, laser lift-off. In addition, the concavo-convex structure L and the concavo-convex structure A satisfy the relation of the predetermined average interval, so that the optical scattering property becomes large. In particular, since the concavo-convex structure L is constituted by the plurality of concave portions 704, the effect of disturbing the waveguide mode becomes larger because the volume change becomes larger, and the light extraction efficiency LEE is improved.

On the other hand, in the case where the concavoconvex structure A is formed at any of the convex portion 703 and the concave portion 704 of the concavo-convex structure L shown in Fig. 28C, . &Lt; / RTI &gt;

In the above-described LED pattern wafers (2) 710, it is preferable that the coverage ratio of the concavo-convex structure (A) to the concavo-convex structure (L) is more than 0% and less than 100%.

In this case, since the concavo-convex structure A is necessarily formed in the convex portion 703 or the concave portion 704 of the concavo-convex structure L, the internal quantum efficiency IQE is effectively improved by the above- . On the other hand, the convex portion 703 and the concave portion 704 of the concave-convex structure L are not completely buried by the concave-convex structure A. Thus, the effect of improving the light extraction efficiency (LEE) by the concave-convex structure L can be suppressed from being lowered by the concave-convex structure A. That is, the internal quantum efficiency (IQE) and the light extraction efficiency (LEE) can be improved at the same time, and cracks can be suppressed.

Particularly, from the viewpoint of improving the effect of suppressing the increase in the roughness of the surface of the concavoconvex structure L and disturbing the traveling direction of the emitted light forming the waveguide mode within the semiconductor layer due to the concavo-convex structure L, Or less, more preferably 80% or less, and most preferably 50% or less. In addition, from the viewpoint of improving the internal quantum efficiency (IQE) by the uneven structure (A), reducing the amount of the semiconductor layer used and improving the productivity of the LED, the coating rate is preferably 0.01% or more , More preferably 0.1% or more, and most preferably 0.15% or more. On the other hand, when it is desired to further improve the internal quantum efficiency (IQE), the covering ratio is preferably 50% or more and 90% or less, more preferably 60% or more and 86% or less, Or more and 84% or less. When these ranges are satisfied, the effect of the uneven structure (A) can be most effectively expressed. On the other hand, when it is desired to particularly improve the light extraction efficiency (LEE), it is preferably in the range of 0.1% or more and 30% or less, more preferably 0.1% or more and 10% or less, And most preferably 0.1% or more and 5% or less. By satisfying these ranges, it is possible to suppress the formation of the waveguide mode again by the emission light deviated from the waveguide mode, so that the light extraction efficiency is further improved.

Here, the coverage rate is a planar occupancy rate of the convex portion 705 or the concave portion 706 of the concavo-convex structure A with respect to the convex portion 703 of the concavo-convex structure L and the surface of the concave portion 704. That is, when the projection 703 and the concave portion 704 surrounding the periphery of the convex portion 703 in the case of observing the convex portion 703 from the upper surface side are S, The total coverage of the convex portion 705 or the concave portion 706 of the concave and convex structure A in the concave and convex structure A is Si, the covering ratio is (Si / S) x 100.

29 is a schematic diagram showing the concavo-convex structure of the patterned wafer 2 for LED according to the present embodiment. 29A shows a case in which the concavo-convex structure L is formed by a plurality of independent convex portions 703, and particularly, the concavo-convex structure A is formed on the bottom face of the concave portion 704. Fig. Alternatively, there is shown a case in which the concave-convex structure L is formed on the surface of the concave-convex structure A such that the concave-convex structure A is partially exposed. In this example, the outline shape of the bottom of the convex portion 703 and the outline shape of the bottom portion of the convex portion 705 are circular. Let S be the area of the convex portion 703 on the plane viewed from the top side of the convex portion 703 and the concave portion 704 surrounding the contour of the convex portion 703. Here, the area S is the area of the polygon 841 formed by connecting the top center portions of the other convex portions 703 adjacent to the certain convex portion 703. Assuming that the total area of the area formed by the contour of the convex portion 705 of the concave-convex structure A included in the area S or the total area of the opening of the concave portion 706 is Si, Si / S x 100. On the other hand, Fig. 29A illustrates a case where the concavoconvex structure A is disposed only on the bottom of the concave portion of the concavo-convex structure L. However, as described above, the arrangement of the concavo-convex structure A is not limited thereto. Likewise, FIG. 29B shows a case in which the concavoconvex structure L is formed by a plurality of independent concave portions 704, and particularly, the concavo-convex structure A is formed on the top surface of the convex portion 703. FIG. In this example, the opening shape of the concave portion 704 and the contour shape of the bottom portion of the convex portion 703 are circular. Let S be the area of the concave portion 704 on the plane viewed from the top side of the convex portion 703 and the convex portion 703 surrounding the outline of the concave portion 704. Here, the area S is the area of the polygon 841 formed by connecting the center portions of the openings of the other concave portions 704 adjacent to any of the concave portions 704. Assuming that Si is the total area of the area formed by the outline of the bottom of the convex portion 705 of the concavo-convex structure A included in the area S or the total area of the openings of the concave portion 706 as Si, Si / S x 100. 29B, the concavoconvex structure A is disposed only at the top of the convex portion 703 of the concavo-convex structure L. However, as described above, the arrangement of the concave-convex structure A is not limited to this .

On the other hand, when the concavoconvex structure A is formed only on the top surface of the convex portion 703 of the concavo-convex structure L as shown in Fig. 29B, (SiT / ST x 100 (SiT / ST)) where Si is the sum of the planar areas of the concave-convex structures A included in the upper surface of the top portion of the convex portion 703 having the area ST, ) Can be obtained. On the other hand, this covering ratio is called the covering ratio T to the top surface of the convex portion 703.

Likewise, when the concavoconvex structure A is formed only on the bottom surface of the concave portion 704 of the concavo-convex structure L as shown in Fig. 29A, (SiB / SB 占 100 (SiB / Si)) where Si is the sum of the planar areas of the concavo-convex structures A included in the bottom surface of the concave portion 704 having the area SB and the area SB0, ) Can be obtained. On the other hand, this coating rate is called the coating rate B with respect to the bottom surface of the concave portion 704.

It is preferable that the covering ratio T to the top surface of the convex portion 703 and the covering ratio B to the bottom surface of the concave portion 704 are 1% or more and 90% or less. Particularly, from the viewpoint of improving the internal quantum efficiency (IQE) well and improving the light emission output of the LED, the covering ratio T to the top surface of the convex portion 703 and the coating rate T on the bottom surface of the concave portion 704 The ratio B is preferably 3% or more and 60% or less, more preferably 5% or more and 55% or less, and most preferably 10% or more and 40% or less. Even when the concavoconvex structure L is formed on the top of the convex portion 703, the side surface of the convex portion 703 and the bottom portion of the concave portion 704, The covering ratio of the concavo-convex structure A with respect to the top surface of the convex portion 703 or the covering ratio of the concavo-convex structure A with respect to the bottom surface of the concave portion 704 of the concave- Of the top surface of the concave portion 704 or the covering ratio B of the bottom surface of the concave portion 704.

On the other hand, when a plurality of convex portions 703 are separately formed on the LED wafer 702 in the concavo-convex structure L, the concave-convex structure L is formed in such a manner that the concave- (703). In this case, the plurality of convex portions 703 correspond to the convex portions of the concavo-convex structure L, and the portions between the convex portions 703 where the main surface of the LED wafer 702 is exposed are concave (704).

On the other hand, when the uneven structure L is formed by directly processing the LED wafer 702, the material of the uneven structure L and the LED wafer 702 becomes the same.

28A shows a case in which the concavo-convex structure L is composed of a plurality of independent convex portions 703, and the concavo-convex structure A is formed on the surface of the concave portion 704 of the concave- 28B shows a case in which the concavo-convex structure L is constituted by a plurality of independent convex portions 703 and concavoconvex structures A are formed on the convex portions 703 of the concave-convex structures L. Fig. 28C shows a state in which the concavo-convex structure L is constituted by a plurality of independent convex portions 703 and concave and convex structures A are formed on the convex portions 703 and the concave portions 704 of the concave- . 28A to 28C illustrate the shape of the top of the convex portion 703 of the concavo-convex structure L in a rounded shape, but the shape of the top portion of the convex portion 703 of the concavo- As described above, it may be a shape of a table top shape or the like.

The internal quantum efficiency IQE can be improved by forming the concavo-convex structure A in the concave portion 704 of the concavo-convex structure L, as shown in Fig. 28A. In addition, since the convex-and-concave structure L is constituted by a plurality of independent convex portions 703, the effect of suppressing cracks in the semiconductor layers is increased. This is because the growth of the semiconductor layer starts from the concave portion 704 of the concavo-convex structure L. [ In other words, the adhesion of the nuclei of the semiconductor layer, the growth thereof, and the uniformity of the growing semiconductor layers are improved by the concavo-convex structure (A), and the semiconductor layer having a good growth property becomes the concave portion 704 of the concave- The potential can be reduced in the concave portion 704 of the concave and convex structure L. [ 28A, the concavo-convex structure A is not formed on the side surface portion of the convex portion 703, but the concavo-convex structure A may be formed on the side surface of the convex portion 703. FIG. In this case, it is considered that the effect of disturbing the waveguide mode is further strengthened, and the traveling direction of the scattered light can be further changed in the thickness direction of the LED. Therefore, it becomes easy to select the sealing material when the LED is packaged.

In order to suppress the potential generated at the top of the convex portion 703 of the convexo-concave structure L when the convexo-concave structure L is made of the same material as the LED wafer 702, It is preferable that the diameter of the opening 703 is reduced toward the vertex at the bottom. In particular, the top of the convex portion 703 of the concavo-convex structure L is continuous with the side portion of the convex portion 703 of the concavo-convex structure L, in other words, the top portion of the convex portion L is constituted by each portion having a radius of curvature of more than 0 . The concavoconvex structure L may have the same shape as a disc shape, a cone shape, an n-prism shape (n? 3) shape, and an n-arcuate shape. Among them, the uniformity of growth of the first semiconductor layer is improved, A conical shape, a disc shape, a triangular prism shape, a triangular truncated shape, a hexagonal prism shape, and a hexagonal prism shape is preferable from the viewpoint of further reducing the cracks and dislocations generated in the inside. On the other hand, the tops of the squares may be rounded portions having a radius of curvature of more than 0, even if the rounded portion has a radius of curvature of zero. Particularly, in the case of the pyramid shape, since the corner portions having a radius of curvature of more than 0 are provided, cracks generated during the growth of the semiconductor layer can be suppressed, thereby improving the long-term reliability of the LED. Particularly, in these shapes, it is preferable that the inclination angle of the side surface portion of the convex portion 703 has a turning point of 1 or more and 5 or less. On the other hand, it is more preferably 1 or more and 3 or less. The side surface portion of the convex portion 703 may be a shape having an expanding portion instead of a straight line.

On the other hand, when the concavoconvex structure L and the LED wafer 702 are made of different materials, the convex portion 703 of the convexoconcave structure L may have a conical shape or an n-angular shape (n? 3) The inclined angle of the side surface portion of the convex portion 703 with respect to the surface forming the bottom portion of the convex portion 703, such as a disk or n-prism (n? 3) type, may be a substantially right angle. Particularly, from the viewpoint of improving the growth uniformity of the first semiconductor layer and reducing the cracks and dislocations generated in the first semiconductor layer, it is possible to use a cone, a disk, a triangle, a triangle, a hexagonal, Is preferable. From the viewpoint of suppressing the cracks generated in the first semiconductor layer, it is preferable that the diameter of the convex portion 703 of the concavo-convex structure L becomes smaller toward the vertex at the bottom portion. Particularly, in these shapes, it is preferable that the inclination angle of the side surface portion of the convex portion 703 has a turning point of 1 or more and 5 or less. On the other hand, it is more preferably 1 or more and 3 or less. The side surface portion of the convex portion 703 may be a shape having an expanding portion instead of a straight line. On the other hand, when the concave-convex structure L and the LED-use wafer 702 are made of different materials, the absolute value of the difference between the refractive index nL of the concavo-convex structure L and the refractive index ns of the LED- nL-ns &lt; / RTI &gt; By satisfying this range, it is possible to increase the optical presence of the concavo-convex structure L viewed from the semiconductor layer. That is, since the optical scattering property is increased, the effect of disturbing the waveguide mode is increased. Further, it is easy to design the light extraction from the side direction of the LED or the light extraction from the top face direction.

28B, even when the convex portion 703 of the convexo-concave structure L is formed with the convexo-concave structure A, a flat surface exists at the top of the convex portion 703 of the convexo-concave structure L , And the internal quantum efficiency (IQE) can be favorably improved. This is because the growth of the semiconductor layer starts from the flat surface of the concave-convex structure L. That is, the adhesion and growth of the nuclei of the semiconductor layer on the flat surface of the convex portion 703 of the convexo-concave structure L are improved, and the coalescence of the growing semiconductor layers is improved, The collision of dislocations increases, and the internal quantum efficiency IQE is improved. With respect to the semiconductor layer growing from the bottom of the concave portion 704 of the concavo-convex structure L, it is possible to reduce the potential by lateral growth of the semiconductor layer. The growth of the semiconductor layer growing from the concave portion 704 of the concavo-convex structure L can be inhibited by the semiconductor layer growing from the top of the convex portion 703 of the concave- Therefore, the dislocation density of the semiconductor layer is lowered, and the internal quantum efficiency (IQE) can be improved. In this case, in order to promote the growth of the semiconductor layer, the bottom of the concave portion 704 of the concavo-convex structure L preferably has a flat surface. It is also preferable that the top of the convex portion 703 of the concavoconvex structure L has a structure smaller than the bottom portion. In order to maintain the internal quantum efficiency IQE satisfactorily by the concavo-convex structure A, the concavo-convex structure A has a dot structure composed of the plurality of convex portions 705, The bottom of the portion 706 preferably has a flat surface. Furthermore, a structure in which the diameter of the convex portion 703 of the concavo-convex structure A is reduced toward the apex at the bottom portion is preferable because dislocation dispersion is further promoted. The concavoconvex structure L may have a shape such as a disc shape, a cone shape, an n-prism shape (n? 3) shape, and an n-shape apex shape. Among them, A triangular prism, a triangular prism, a hexagonal prism, or a hexagonal prism is preferable from the viewpoint of reducing the cracks and dislocations generated in the prism. On the other hand, the tops of the squares may be rounded portions having a radius of curvature of more than 0, even if the rounded portion has a radius of curvature of zero. Particularly, in the case of the pyramid shape, since the corner portions having a radius of curvature of more than 0 are provided, the cracks generated during the growth of the semiconductor layer can be suppressed, so that the long-term reliability of the LED is improved. Particularly, in these shapes, it is preferable that the inclination angle of the side surface portion of the convex portion 703 has a turning point of 1 or more and 5 or less. On the other hand, it is more preferably 1 or more and 3 or less. The side surface portion of the convex portion 703 may be a shape having an expanding portion instead of a straight line. In addition, when the concavoconvex structure A is formed at the top of the convex portion 703 of the concave-convex structure L, it is easy to remove the pattern wafers 2 and 710 for LED by, for example, laser lift- It is possible to increase the light emission intensity per input electric power.

By the structure shown in Fig. 28C, the effects expressed by the structures of Figs. 28A and 28B described above can be combined.

28 shows a case in which the concavo-convex structure L is constituted by a plurality of independent convex portions 703, the concavo-convex structure L may be constituted by a plurality of independent concave portions 704. [

30 is a schematic cross-sectional view showing another example of the patterned wafer 2 for LED according to the present embodiment. 30A shows a case in which the concavo-convex structure L is composed of a plurality of independent recesses 704, and the concave-convex structure A is formed on the surface of the convex portion 703 of the concave- 30B shows a case in which the concavo-convex structure L is composed of a plurality of independent recesses 704 and the concavo-convex structure A is formed on the surface of the concave portion 704 of the concavo-convex structure L. Fig. 30C shows a structure in which the concavo-convex structure L is formed by a plurality of independent concave portions 704 and concavoconvex structures A are formed on the convex portions 703 and the concave portions 704 of the concave- .

The internal quantum efficiency IQE can be improved by forming the concavo-convex structure A in the convex portion 703 of the concavo-convex structure L, as shown in Fig. 30A. Further, since the concavo-convex structure L is constituted by a plurality of independent recesses 704, it is easy to form cavities in the recesses 704 of the concavo-convex structure L. [ In this case, the removal precision of the patterned wafer 2 for LED due to the laser lift-off is improved. Furthermore, in the case of forming the cavity, the difference in the refractive index between the semiconductor layer and the cavity becomes very large, so that the degree of increase of the light extraction efficiency (LEE) increases sharply. This also applies to the concavo-convex structure shown in Fig. 30B or 30C.

As described above, the main function of the concavo-convex structure (A) is improvement of internal quantum efficiency (IQE) and suppression of cracks. Therefore, it is preferable that the material of the concavo-convex structure (A) is the same as the material constituting the LED wafer 702. On the other hand, the main function of the concavo-convex structure L is improvement of the light extraction efficiency (LEE). Therefore, the material of the concave-convex structure L may be the same as or different from that of the LED-use wafer 702. For example, in the case where the concavo-convex structure (A) and the concavo-convex structure (L) are both composed of sapphire, SiC (silicon carbide), nitride semiconductor, Si is composed of Si or spinel, concave and convex structure (L) is a metal of aluminum, amorphous aluminum oxide, polycrystalline aluminum oxide, polycrystalline sapphire, silicon oxide (SiO _2), silicon nitride (Si ₃ N _4), silver (Ag), chromium ( (Cr), nickel (Ni), gold (Au), or platinum (Pt).

Fig. 27C is a schematic cross-sectional view showing another example of the patterned wafer 2 for LED according to the present embodiment. As shown in Fig. 27C, a concavo-convex structure A having a high structural density is formed on the surface of the pattern wafers 2 and 710 for LED, and a large volume change is formed on at least a part of the surface of the concave- So that the concavoconvex structure L is formed. More specifically, a concave-convex structure A composed of a plurality of convex portions 705 and a concave portion 706 is formed on the main surface of the LED wafer 702, and the surface of the concave-convex structure A is partially exposed A plurality of convex portions 703 are formed so as to be spaced apart from each other to constitute the concavo-convex structure L.

With this configuration, it is possible to improve the internal quantum efficiency IQE by improving the cracks by the concavo-convex structure A exposed between the convex portions 703 constituting the concavo-convex structure L, The light extraction efficiency (LEE) can be improved by optical scattering property (light diffraction or light scattering).

As shown in Fig. 27C, by forming the concavo-convex structure L in a part of the surface of the concavo-convex structure A, the internal quantum efficiency IQE can be improved and the light extraction efficiency LEE can be improved. This is because the adhesion of the nucleus of the semiconductor layer, growth and coalescence of the growing semiconductor layers can be improved by the concavo-convex structure (A), so that collision of dislocations occurs well and the internal quantum efficiency IQE is improved At the same time, since the merged portion can be dispersed, cracks can be suppressed. Moreover, the optical scattering property by the concavo-convex structure L can disturb the waveguide mode.

When the material of the concavoconvex structure L and the material of the LED wafer 702 are different from each other, the concave-convex structure L has a width of the convex portion such as a disk or n-prism Or may have substantially the same width. It is particularly preferable that the width of the convex portion of the concave-convex structure L is smaller than the width of the convex portion of the concave-convex structure L from the viewpoint of better suppressing the cracks generated in the first semiconductor layer.

On the other hand, when the material of the concave-convex structure L and the material for the LED wafer 702 are the same, in order to suppress the potential generated at the top of the convex portion 703 of the convexo-concave structure L, It is preferable that the top portion of the bottom plate 703 is smaller than the bottom portion thereof. In particular, it is preferable that the top of the convex portion 703 of the concavoconvex structure L is continuous with the side portion thereof, in other words, the width of the convex top portion gradually approaches zero. On the other hand, from the examination on the pattern wafer for LED 1, it can be considered that the expression that the width of the convex top gradually comes close to zero can be interpreted as including the case where the size of the table top is 100 nm or less .

Furthermore, from the viewpoint of further improving the internal quantum efficiency IQE by the concavo-convex structure L, the concavo-convex structure L preferably has a dot structure composed of a plurality of convex portions 703. [ This is because the potential inside the semiconductor layer that grows from the concave portion 704 formed between the convex portions 703 can be reduced by the lateral growth. In view of the same effect, it is preferable that the width of the convex portion of the concave-convex structure L is smaller than the width of the convex portion bottom.

On the other hand, from the viewpoint of further improving the internal quantum efficiency (IQE), the concavo-convex structure A has a dot structure composed of the plurality of convex portions 705 and the bottom portion of the concave portion 706 of the concave- It is preferable to have a flat surface. Furthermore, if the width of the convex portion of the concavoconvex structure A is smaller than the width of the convex portion bottom, it is preferable because dislocation dispersion is further promoted.

As described above, the main function of the concavo-convex structure (A) is improvement of the internal quantum efficiency (IQE). Therefore, it is preferable that the material of the concavo-convex structure (A) is a material constituting the LED wafer 702. On the other hand, the main function of the concavo-convex structure L is improvement of the light extraction efficiency (LEE). Therefore, the material of the concave-convex structure L may be the same as or different from that of the LED-use wafer 702. [

By using the pattern wafers 2 and 710 for LED according to the present embodiment, a semiconductor layer with a high internal quantum efficiency (IQE) can be obtained while suppressing cracks by the principle described above. In addition, the LED chip exhibits high light extraction efficiency (LEE). That is, it is possible to efficiently emit light, efficiently extract the emitted light to the outside of the LED chip, and improve the reliability of the LED chip. Therefore, the LED element manufactured by using the pattern wafers 2 and 710 for LED according to the present embodiment has a small heat generation amount. The fact that the amount of heat generation is small means that not only the long-term stability of the LED element is improved but also the load due to the heat radiation measures (for example, the heat radiation member is excessively installed) can be reduced.

The material for the LED wafer 702 and the concavo-convex structure are different from each other. For example, the material for the LED wafer 702 described above and the material of the aluminum wafer, amorphous aluminum oxide, polycrystalline aluminum oxide, , silicon oxide (SiO _2), silicon nitride (Si ₃ N _4), silver (Ag), chromium (Cr), nickel (Ni), gold (Au) or platinum (Pt) of, any one or a mixture of two or more Can be used.

<< Manufacturing Method of Pattern Wafer (2) for LED >>

Next, a method of manufacturing the patterned wafer 2 (710) for LED according to the embodiment of the present invention will be described.

If the LED pattern wafers (2) 710 according to the present embodiment are provided with the concavo-convex structure satisfying the above-described conditions, the manufacturing method thereof is not limited. By the same manufacturing method as the pattern wafers 1 for LED Can be manufactured.

In the case of the LED pattern wafers 2 and 710, the concavo-convex structure 720 can be manufactured by manufacturing the concavo-convex structure L and then forming the concavo-convex structure A. The manufacturing method of the concavo-convex structure (L) can be classified into two types.

(1) When the wafer for LED is directly processed to form the concavoconvex structure L

As a method of forming the concave-convex structure L by directly processing the wafer for LED 702, a transfer method, a photolithography method, a thermal lithography method, an electron characterization method, an interference exposure method, a lithography method using a nanoparticle as a mask, A lithography method using an organized structure as a mask, or the like. In particular, from the viewpoints of processing accuracy and processing speed of the concavo-convex structure of the LED-use wafer 702, it is preferable to employ a photolithography method or a transfer method. On the other hand, the etching method may be wet etching or dry etching. Particularly, in the case of precisely controlling the plane orientation of the convex portion side surface of the concavo-convex structure L, wet etching is preferable. On the other hand, from the viewpoint of precise control of the shape of the concave-convex structure L, the dry etching method is preferable, and the dry etching method described for the patterned wafer 1 for LED can be employed. The transfer method is the same as that described for the patterned wafer 1 for LED.

(2) When the concavo-convex structure L is separately formed on the LED wafer

As a method of separately forming the concavoconvex structure L on the wafer 702 for LED, a transfer method, a method of forming a thin film containing particles on the wafer 702 for LED, and thereafter removing a binder filling between the particles A part of the resist film formed on the LED wafer 702 is removed and the removed portion is filled with the material constituting the concavo-convex structure L (for example, vapor deposition, sputtering, electroforming, etc.) A method of removing the resist, a method of directly forming the material of the formed concave-convex structure L by forming the material of the concave-convex structure L on the LED wafer 702, and the like.

The concavo-convex structure 720 can be manufactured by manufacturing the concavo-convex structure L by the above-described method, and then by producing the concavo-convex structure A.

As a method of forming the concave-convex structure A on the concavo-convex structure L, a transfer method, a photolithography method, a thermal lithography method, an electron beam lithography method, an interference exposure method, a lithography method using a nanoparticle as a mask, A lithography method using a mask, and the like. In particular, from the viewpoints of processing accuracy and processing speed of the concavo-convex structure of the patterned wafer for LED, it is preferable to employ a lithography method or a transfer method using nanoparticles as a mask. I will explain the law of jurisdiction later.

The concave-convex structure 720 can also be manufactured by manufacturing the concave-convex structure A and then fabricating the concave-convex structure L.

Examples of the method of forming the concavoconvex structure A include a transfer method, a photolithography method, a thermal lithography method, an electron beam lithography method, an interference exposure method, a lithography method using a nanoparticle as a mask, a lithography method using a self- . Particularly, from the viewpoints of processing accuracy and processing speed of the concavo-convex structure, it is preferable to adopt a lithography method or a transfer method using nanoparticles as a mask. The transfer method is the same as that described for the patterned wafer 1 for LED.

The concave-convex structure 720 can be manufactured by manufacturing the concave-convex structure L on the wafer for LED having the concave-convex structure A.

By further processing the concave-convex structure (A), the concave-convex structure 720 can be manufactured. Examples of the method for further processing the concavoconvex structure (A) include a transfer method, a photolithography method, a thermal lithography method, an electron beam lithography method, an interference exposure method, a lithography method using a nanoparticle as a mask, a lithography method using a self- . &Lt; / RTI &gt; In particular, from the viewpoints of processing accuracy and processing speed of the concavo-convex structure of the LED pattern wafers (2) 710, it is preferable to employ a photolithography method or a transfer method. The transfer method is the same as that described for the patterned wafer 1 for LED.

When the concave-convex structure layer having the concave-convex structure 720 is separately formed on the LED wafer 702, the concave-convex structure 720 is manufactured by manufacturing the concave-convex structure A and then forming the concave- .

Examples of the method of forming the concavoconvex structure A include a transfer method, a photolithography method, a thermal lithography method, an electron beam lithography method, an interference exposure method, a lithography method using a nanoparticle as a mask, a lithography method using a self- . Particularly, from the viewpoints of processing accuracy and processing speed of the concavo-convex structure, it is preferable to adopt a lithography method or a transfer method using nanoparticles as a mask. The transfer method is the same as that described for the patterned wafer 1 for LED.

It is possible to manufacture the pattern wafers 2 and 710 for LED by separately forming the concave-convex structure L on the wafer for LED having the concavoconvex structure A.

As a method of separately forming the concave-convex structure L, for example, a transfer method, a method of forming a thin film containing particles on the wafer 702 for LED, and then removing the binder filling the spaces between the particles. A part of the resist film formed on the wafer for LED 702 is removed and the material constituting the uneven structure L is filled in the removed part (for example, vapor deposition, sputtering method, electroforming method, etc.) And the like. Further, a method of forming a film of the material of the concave-convex structure L and directly processing the film of the concavo-convex structure L thus formed can be mentioned.

Example

Hereinafter, examples for the purpose of confirming the effects of the present invention will be described.

The symbols used in the following description have the following meanings.

· DACHP ... Fluorine-containing urethane (meth) acrylate (OPTOOL (registered trademark) DAC HP (manufactured by Daikin Industries)

· M350 ... Trimethylolpropane (EO-modified) triacrylate (M350, manufactured by Toagosei Co., Ltd.)

· I.184 ... 1-hydroxycyclohexyl phenyl ketone (Irgacure (registered trademark; hereinafter the same) 184 manufactured by BASF)

· I.369 ... 2-dimethylamino-1- (4-morpholinophenyl) -butanone-1 (Irgacure 369, manufactured by BASF)

· TTB ... Titanium (IV) tetrabutoxide monomer (manufactured by Wako Pure Chemical Industries, Ltd.)

· SH710 ... Phenyl-modified silicone (manufactured by Dow Corning)

· 3APTMS ... 3-acryloxypropyltrimethoxysilane (KBM5103 (Shin-Etsu Silicone Co., Ltd.))

· MEK ... Methyl ethyl ketone

· MIBK ... Methyl isobutyl ketone

· DR833 ... Tricyclodecane dimethanol diacrylate (SR833 (manufactured by SARTOMER))

· SR368 ... Tris (2-hydroxyethyl) isocyanurate triacrylate (SR833 (manufactured by SARTOMER))

An LED pattern wafer 1 was fabricated and an LED epitaxial wafer was fabricated using the pattern wafer 1 for LED to evaluate internal quantum efficiency (IQE) and cracks. Subsequently, chips were fabricated to compare the efficiency of the LED.

In the following discussion, in order to manufacture the patterned wafer 1 for LED, first, (1) a cylindrical master mold was produced, and (2) a photo-transfer method was applied to a cylindrical master mold to produce a reel-type resin mold. (3) Thereafter, the reel-type resin mold was processed into a nano-processing film. Then, (4) a patterned wafer 1 for LED was produced by using a film for nano processing. Finally, (5) an epitaxial wafer for LED was manufactured using the pattern wafer 1 for LED, and the performance was evaluated. On the other hand, the concavo-convex structure (A) was controlled by the concavo-convex structure of the cylindrical master mold manufactured in (1), the photoelectric transfer method performed in (3), and the nano processing film produced in (4).

(1) Fabrication of cylindrical master mold

A concave-convex structure was formed on the surface of the cylindrical quartz glass by a direct-write lithography method using a semiconductor laser. First, a resist layer was formed on the cylindrical quartz glass surface by a sputtering method. In the sputtering method, a resist layer of 20 nm thickness was formed by using CuO (containing 8 atm% Si) of 3 inches in diameter as a target (resist layer) at a power of RF 100 W. Subsequently, while rotating the cylindrical quartz glass, the front surface was exposed using a 405 nm semiconductor laser with a wavelength of 40 nm. Thereafter, the exposed resist layer was subjected to pulse exposure using a semiconductor laser having a wavelength of 405 nm. On the other hand, the pulse pattern was set so as to be a meat-laying array. Subsequently, the exposed resist layer was developed. The development of the resist layer was carried out for 240 seconds using 0.03 wt% aqueous glycine solution. Subsequently, the etching layer (quartz glass) was etched by dry etching using the developed resist layer as a mask. The dry etching was carried out under conditions of SF ₆ as the etching gas, a processing gas pressure of 1 Pa, and a processing power of 300 W. Finally, only the resist layer residue was peeled from the cylindrical quartz glass having a concavo-convex structure on its surface by using hydrochloric acid of pH 1. The peeling time was 6 minutes.

HD-1101Z (manufactured by Harves Co., Ltd.), which is a fluorine-based mold release agent, was applied to the concave-convex structure of the obtained cylindrical quartz glass, heated at 60 占 폚 for 1 hour, did. Thereafter, the resultant was washed three times with Duracaf HD-ZV (manufactured by Harves) to obtain a cylindrical master mold.

(2) Production of reel-type resin mold

The reel-type resin mold G1 was continuously produced by using the manufactured cylindrical master mold as a mold and applying a photo-nanoimprint method. Subsequently, using a reel-type resin mold G1 as a template, a reel-type resin mold G2 was continuously obtained by a photo-nanoimprint method.

The following material 1 was applied to the adhesive surface of the PET film A-4100 (manufactured by Toyo Boseki Co., Ltd., width 300 mm, thickness 100 탆) by microgravure coating (Yasushi Kasei Co., Ltd.) did. Subsequently, the cylindrical master mold was pressed with a nip roll of the PET film coated with the material 1, and the Fusion UV System Japan was placed under the atmosphere at a temperature of 25 占 폚, a humidity of 60%, and an integrated exposure amount under the lamp center of 1500 mJ / UV light was irradiated using a UV exposure device (H bulb) manufactured by Shikisha Co., Ltd., and photo-curing was continuously performed to obtain a reel-shaped resin mold G1 (length 200 m, width 300 mm) Here, the film thickness of the cured product of the material 1 formed on the PET film was adjusted to 1500 nm by pressing the nip roll.

Subsequently, the reel-type resin mold G1 was selected as a template, and a reel-type resin mold G2 was produced continuously by applying the photo-nanoimprint method.

The material 1 was coated on this adhesive surface of PET film A-4100 (manufactured by Toyo Boseki Co., Ltd., width 300 mm, thickness 100 탆) by microgravure coating (Yasushi Kasei Co., Ltd.) so as to have a coating film thickness of 3 탆. Subsequently, the PET film coated with the material 1 was pressed with a nip roll (0.1 MPa) against the concavo-convex structure surface of the reel-shaped resin mold G1, and the total exposure dose under the lamp center at a temperature of 25 DEG C and a humidity of 60% / Cm &lt; 2 &gt; was irradiated with ultraviolet rays using a UV exposure apparatus (H bulb) manufactured by Fusion UV System Japan K.K., and continuous photocuring was carried out to obtain a reel-type resin mold G2 m, width 300 mm).

Material 1 ... DACHP: M350: I.184: I.369 = 17.5 g: 100 g: 5.5 g: 2.0 g

(3) Fabrication of nano processing film

A dilute solution of the following material 2 was applied to the uneven surface of the reel-type resin mold G2. Subsequently, a dilute liquid of the following material 3 was coated on the uneven structure surface of the reel-type resin mold G2 containing the material 2 inside the concavo-convex structure to obtain a nano processing film.

Material 2 ... TTB: 3 APTMS: SH710: I.184: I.369 = 65.2 g: 34.8 g: 5.0 g: 1.9 g: 0.7 g

Material 3 ... Binding polymer: SR833: SR368: I.184: I.369 = 38 g: 11.5 g: 11.5 g: 1.47 g: 0.53 g

Binding polymers ... A methyl ethyl ketone solution (solid content: 50%, weight average molecular weight: 29000) of a binary copolymer of benzyl methacrylate of 80% by mass and methacrylic acid of 20% by mass,

(2) A material 2 diluted with a mixed solvent of PGME, acetone and isopropanol was applied directly onto the concavo-convex structure side of the reel-type resin mold G2 by using the same apparatus as the production of the reel-type resin mold. Here, the dilution concentration is set so that the amount of solid content contained in the coating material per unit area (material 2 diluted with the mixed solvent) is 20% or less smaller than the volume of the concavo-convex structure per unit area. After coating, the inside of the furnace was passed through a drying furnace at 105 DEG C for 5 minutes, and a reel-type resin mold G2 containing the material 2 inside the concavo-convex structure was wound and recovered.

Subsequently, the reel-type resin mold G2 containing the material 2 inside the concavo-convex structure was released, and (2) the material 3 diluted with the mixed solvent of PGME, MEK, MIBK and acetone Was directly coated on the uneven structure surface. Here, the dilution concentration was set such that the distance between the interface between the material 2 disposed inside the concavo-convex structure and the coated material 3 and the surface of the material 3 was 400 nm to 800 nm. After coating, the film was passed through an air blow drying oven at 105 DEG C for 5 minutes, and a cover film composed of a PET film subjected to releasing treatment on the surface of the material 3 was wound up and recovered.

(4) Fabrication of pattern wafers (1) (10) for LED

As the pattern wafers (1) (10) for LED, a sapphire wafer having a 4-inch phi of C plane (0001) with an orientation flat on the A face (11-20) was used.

The sapphire wafer was subjected to UV-O ₃ treatment for 5 minutes to remove particles on the surface and to make the sapphire wafer hydrophilic. Subsequently, the surface of the material 3 of the nano processing film was bonded to the sapphire wafer. Here, the concavo-convex structure of the reel-shaped resin mold G2 is a concavo-convex structure in which a plurality of concave portions are arranged in a row. Namely, the nano-working film includes a reel-type resin mold G2 having a six-fold symmetrical concave arrangement. Here, the crystal axis of the sapphire wafer and the arrangement axis A of the concavo-convex structure of the nano processing film were adjusted within a predetermined rotation shift angle (?) Range and bonded. The bonding was performed while adjusting the rotation shift angle (?) And the sapphire wafer was heated to 110 占 폚. Subsequently, a high-pressure mercury lamp light source was used, and a UV-LED light source having a center wavelength of 365 nm was used to irradiate light over the reel-type resin mold G2 so that the accumulated light quantity became 1200 mJ / cm2. Thereafter, the reel-type resin mold G2 was peeled off.

Etching (oxygen ashing) using oxygen gas was performed on the two sides of the material of the obtained laminate (material 2 / material 3 / laminate composed of sapphire wafer), material 3 was subjected to nano processing by selecting material 2 as a mask, The wafer surface was partially exposed. The oxygen ashing was performed under the conditions of the treatment gas pressure of 1 Pa and the treatment power of 300 W. Then, reactive ion etching using a mixed gas of BCl ₃ gas and Cl ₂ gas was performed on the two surface sides of the material, and the sapphire wafer was subjected to nano processing. The etching was carried out with an ICP of 150 W, a bias of 50 W, and a pressure of 0.2 Pa, and a reactive ion etching apparatus (RIE-101iPH, manufactured by Sankyo Co., Ltd.) was used.

Finally, a plurality of sapphire wafers were obtained in which a mixture of sulfuric acid and hydrogen peroxide water was mixed at a weight ratio of 2: 1 to prepare a concavo-convex structure 20, that is, a concavo-convex structure A on the surface.

The shape of the convex portion of the concavo-convex structure (A) formed on the sapphire wafer was adjusted by the processing time of the reactive ion etching. That is, the reactive ion etching is stopped before the material 3 completely disappears, so that the shape having the table top is formed at the top of the convex portion, and the reactive ion etching is performed until the material 3 completely disappears, And a rounded top. Further, the diameter (?) Of the bottom of the convex portion was adjusted by excessively performing reactive ion etching, that is, by applying overetching.

(5) Fabrication of epitaxial wafer for LED

On the obtained patterned wafer 1 for LED, a low temperature growth buffer layer of Al _x Ga _{1 - x} N (0 _{? X} ? 1) was formed as a buffer layer in a thickness of 100 Å. Subsequently, undoped GaN was formed as the undoped first semiconductor layer, and Si-doped GaN was formed as a first doped semiconductor layer. Subsequently, a distortion absorbing layer was provided, and then an active layer (well layer, barrier layer = non-doped InGaN, Si-doped GaN) of a multiple quantum well was formed as a light emitting semiconductor layer with a thickness of 60 Å and 250 Å, The six layers and the barrier layers were alternately stacked so as to have seven layers. On the light emitting semiconductor layer, Mg-doped AlGaN, undoped GaN, and Mg-doped GaN were stacked so as to include the electro-blocking layer as the second semiconductor layer. Subsequently, ITO was deposited, etched, and then an electrode pad was attached. In this state, a current of 20 mA was passed between the p-electrode pad and the n-electrode pad using a prober to measure the luminous output.

The internal quantum efficiency (IQE) was determined by PL intensity. The internal quantum efficiency IQE is defined by (the number of photons generated in the light emitting semiconductor layer per unit time / the number of electrons injected into the semiconductor light emitting element per unit time). In this embodiment, PL intensity measured at 300 K / PL intensity measured at 10 K was used as an index for evaluating the internal quantum efficiency (IQE).

The light extraction efficiency (LEE) was calculated from the light emission output and the internal quantum efficiency (IQE).

Cracks were determined by observing the epitaxial wafer for LEDs in which the film formation of the semiconductor layer was stopped during the process of forming the facets, using an optical microscope, an atomic force microscope, and a scanning electron microscope on the semiconductor layer side. Further, the epitaxial wafer for LEDs was taken out together, and a cross section of the semiconductor layer was observed by a scanning electron microscope to evaluate cracks.

(Example 1, Comparative Example 1)

In Example 1 and Comparative Example 1, the influence of the convex top shape was investigated. The shape of the convex portion was observed using a scanning electron microscope. The concavo-convex structure (A) was a meat-laying array. That is, it was a six-fold symmetrical arrangement. In addition, as the average interval (Pave), 300 nm and 900 nm were produced. The rotation shift angle? Was set to 30 °. Under these conditions, the convex portion was compared with the case where the convex portion had a rounded shape (Example 1) and the case where the table top was present (Comparative Example 1). The prepared samples are shown in Table 1. On the other hand, the convex portion of Example 1 had a conical shape in cross section.

As can be seen from Table 1, it can be seen that the internal quantum efficiency (IQE) is improved and the crack is reduced in the case where the shape of the convex portion is rounded (Example 1). First, with respect to the internal quantum efficiency (IQE), it was confirmed from the transmission electron microscope observation that the potentials collide with each other in the vicinity of the concave portion of the concavo-convex structure A in the case where the shape of the convex top portion is rounded (Example 1) And it was confirmed that the dislocation density was reduced because it was confirmed that it was lost. On the other hand, in the case where the table top was present at the top of the convex portion (Comparative Example 1), dislocation was generated on the table top, and it was observed that the potential was growing in the thickness direction of the semiconductor layer. That is, since the frequency of collision between the potentials is small and the dislocation density is high, it is considered that the degree of improvement of the internal quantum efficiency IQE is low. Then, the growth of the semiconductor layer was stopped in the middle of the growth of the crack, and the surface was observed in detail using a scanning electron microscope. As a result, in the case of rounding at the top of the convex portion (Example 1) A semiconductor layer grows preferentially over the concave portion of the semiconductor layer, and the grown semiconductor layers are well coalesced. More specifically, a crack is a density of cracks running in a direction perpendicular to mutually opposite sides of an opening and an opening adjacent to the opening, when attention is paid to a hexagonal opening formed by the formed facet. When the average spacing (Pave) was 300 nm and 900 nm, the crack densities were 39 × 10 ⁹ / cm 2 and 41 × 10 ⁹ / cm 2, respectively. On the other hand, in the case where the table top is present at the top of the convex portion (Comparative Example 1), in the vicinity of the outer periphery of the top portion of the convex portion constituted by the convex top portion and the side surface portion of the convex portion, Formation of voids was observed. It is presumed that a crack occurred due to this void. More specifically, when the average spacing Pave was 300 nm and 900 nm, the crack densities were 93 × 10 ⁹ / cm 2 and 99 × 10 ⁹ / cm 2, respectively.

(Example 2, Comparative Example 2)

In Example 2 and Comparative Example 2, the influence of the rotation shift angle? Was examined. The arrangement of the concavoconvex structures (A) is an array of meat-laying disposition, that is, six-fold symmetry. The average interval Pave was 300 nm in all, and the shape of the top of the convex portion was the same as the shape of Example 1, with all the rounded portions. The rotation shift angle (?) Was used as a parameter to change from 0 ° to 10 ° pitch to 30 °. The evaluated samples are summarized in Table 2. In the sample shown in Table 2, the internal quantum efficiency (IQE) was approximately the same for any sample, and was about 90%.

The cracks in the evaluation items in Table 2 were normalized to 1 when the rotation shift angle? Was 0 ° (Comparative Example 2). More specifically, as the rotation shift angle? Is changed to 0 °, 10 °, 20 °, and 30 °, the crack density is 81 × 10 ⁹ / cm 2, 72 × 10 ⁹ / ⁹ / it was ㎠ and 53 × 10 ⁹ / ㎠. From Table 2, it can be seen that as the rotational shift angle? Increases, the cracks decrease. This is because, as the rotational shift angle? Increases, the adhesion of the nucleus to the bottom of the concave portion of the concave-convex structure A of the semiconductor layer becomes good and the density of the convex portion through which the semiconductor layer to be grown is reduced . In addition, it is presumed that the crack becomes better as the rotation shift angle becomes larger as a result of the diameter of the bottom of the convex portion. In other words, when considering the density of protrusions through which the growing semiconductor layer including the diameter of the bottom of the convex portion passes, it is considered that the density decreases remarkably from the vicinity of the rotational shift angle? .

From Examples 1 and 2, it can be seen that the convex portion of the concavo-convex structure (A) is rounded and has a rotational shift angle? Of more than 0 degrees. 13 and 14, the FWHM and the CL darkness of the semiconductor layer are effectively improved in the region where the crack density is 70 x 10 &lt; ⁹ &gt; / cm &lt; Is set to be larger than 0 DEG and at the same time, the shape of the top of the convex portion is made a corner portion having a radius of curvature of more than 0, the crystal quality of the semiconductor layer is considerably improved by the effect of crack suppression. On the other hand, in this embodiment, the controllability of the rotation shift angle? Is ± 1 °. The crack suppression was more effective when the rotation shift angle (Θ) was 10 ° or more. In particular, it can be seen that as the rotation shift angle? Increases to 10, 20 and 30 degrees, the crack reduction effect increases. On the other hand, most preferably, Θ is 30 °, that is, (180 / n) ° = (180/6) °. On the other hand, although the above results show a difference in absolute value, the same tendency was observed also for the patterned wafer 1 for LED having the shape shown in Fig. From this, it is possible to extract the effect of the rotational shift angle? By using the patterned wafer 1 for LEDs including the convex-and-concave structure A constituted by convex portion tops having corner portions whose radius of curvature is greater than 0, Cracks can be effectively suppressed.

(Example 3)

In the third embodiment, a more preferable range of the average interval (Pave) was examined. The concavo-convex structure A of the patterned wafer for LED 1 has a hexagonal arrangement (six-fold symmetrical arrangement), a convex portion has rounded corners, a convex portion has a domed cross- Lt; RTI ID = 0.0 &gt; 30. The parameters are average spacing (Pave), adjusted in the range of 200 nm to 1800 nm. The prepared samples are summarized in Table 3.

From Table 3, it can be seen that the internal quantum efficiency IQE is improved as the average interval Pave is smaller. This is presumably because the density of the concavo-convex structure A is improved as the average spacing Pave is smaller, and therefore the potential of the semiconductor layer can be dispersed. More specifically, it is considered that the frequency of incorporation of the growing semiconductor layers can be increased, and the coalescence sites can be dispersed. Particularly, it has been confirmed that this phenomenon is manifested by the rounded shape of the top of the convex portion. That is, when a convex portion having a table top not shown in Table 3 was produced, the potential was confirmed in the semiconductor layer located on the convex portion. Therefore, the internal quantum efficiency IQE tends to decrease.

On the other hand, when the emission output of the LED was evaluated, the average interval (Pave) was 300 nm more than in the case where the average interval (Pave) was 200 nm. In addition, the light emission output was larger in the case where the average interval Pave was 900 nm than in the case where the average interval Pave was 1200 nm and 1500 nm. Furthermore, the light emission output was larger in the case where the average interval Pave was 300 nm than in the case where the average interval Pave was 900 nm. As described above, it is understood that the performance of the LED chip is not determined only by the magnitude of the internal quantum efficiency (IQE). This is the effect of light extraction efficiency (LEE). The average interval (Pave) was 300 nm, 900 nm, 700 nm, 450 nm, 1200 nm, 200 nm and 1800 nm, respectively, This is because, when the average interval (Pave) is 300 nm, the optical diffraction is very strong and the number of diffraction modes is limited, but the diffraction intensity in a predetermined direction is considered to be large. Then, if the average spacing Pave is 900 nm and 700 nm, the diffraction mode intensity is small, but it is considered that the diffraction mode number is greatly increased. When the average distance exceeds 1000 nm, the light scattering property becomes excessively strong, so that the light which has been guided in the LED chip is disturbed once in its traveling direction and there is a probability of being guided again, I think. From the above, it can be seen that the smaller the average interval Pave, the larger the internal quantum efficiency IQE. It has been found that the epitaxial wafers for LEDs preferably have an average interval (Pave) of 200 nm to 1200 nm, and more preferably 300 nm to 900 nm.

(Example 4)

In Example 4, a more preferable range of the duty of the concavo-convex structure (A) was investigated. The concavo-convex structure A of the patterned wafer for LED 1 has a hexagonal arrangement (six-fold symmetry arrangement), a convex portion has rounded corners, a convex portion has a dome- ) Was 30 °, and the average interval (Pave) was 700 nm. The parameter was duty and adjusted in the range of 0.29 to 0.93. The prepared samples are summarized in Table 4.

From Table 4, it can be seen that the internal quantum efficiency (IQE) is greatly changed between duty 0.86 and 0.93. This is considered to be because, when the duty is 0.93, the size of the concave bottom portion becomes smaller than the stable core size of the semiconductor layer. That is, since the adhesion and growth of the nuclei are somewhat impaired, the potential reduction effect is lowered and the internal quantum efficiency (IQE) is estimated to be lowered. On the other hand, the larger the duty ratio, the better the light extraction efficiency (LEE) is. This is considered to be because the volume of the convex portion seen from the photon becomes large, and the mode number of the optical diffraction increases. On the other hand, regarding the cracks, it was approximately the same in all samples. From the above, it can be understood that the duty of the concavo-convex structure (A) in the case of the epitaxial wafer for LED is preferably less than 0.93. Further, from the viewpoint of increasing the external quantum efficiency (EQE), it is preferable that the value is 0.57 or more, and more preferably 0.71 or more. On the other hand, the crack density was between 40 × 10 ⁹ / cm 2 and 50 × 10 ⁹ / cm 2.

(Example 5)

In Example 5, a more preferable range of the relationship between the thickness of the first semiconductor layer of the epitaxial wafer for LED and the concavo-convex structure (A) was examined. (Hbu) of the undoped first semiconductor layer, the film thickness (Hbun) of the doped first semiconductor layer and the average spacing (Pave) and the average height (Have) of the concave- convex structure (A) Efficiency (IQE), cracks, and warpage of epitaxial wafers for LEDs were evaluated.

The results of the review are summarized in Table 5. The meanings of the terms shown in Table 5 are as follows.

· No .: Control number of sample

N: the degree of arrangement of the concavo-convex structure (A) (n in the symmetrical arrangement of n times)

Pave: average interval (Pave) of the concavo-convex structure (A), and the dimension is "nm"

Have: Average height (Have) of the concavo-convex structure (A), and the dimension is "nm"

Θ: rotation angle of rotation (Θ), and the dimension is "°"

Hbun: film thickness of the first semiconductor layer, and the dimension is &quot; nm &quot;

Hbu is the film thickness of the undoped first semiconductor layer, and the dimension is &quot; nm &quot;

Hbun / Have is the ratio of the film thickness of the first semiconductor layer to the average height (Have) of the concavo-convex structure (A)

Hbu / Have: ratio between the film thickness of the undoped first semiconductor layer and the average height (Have) of the concavo-convex structure (A)

· IQE: Internal quantum efficiency, dimension is "%"

Crack: A crack generated in the semiconductor layer, the case where it is equivalent to that of Embodiment 1 is represented by o, and the case where it is equivalent to that of Comparative Example 1 is indicated by x.

&Amp;bull; &amp;le; &amp;le; &amp;le; &amp;le; &quot;

· Overall: Overall evaluation considering IQE and warpage

On the other hand, Comparative Example 5 shown in Table 5 is a case in which epitaxial wafers for LEDs were produced in the same manner as in Example 1, using a flat sapphire wafer having no concavo-convex structure.

In addition, the sample shown in Table 5 is provided with the corner portion of which all the convex portions are rounded. Also, the duty was 0.7.

 The following can be seen from Table 5. The internal quantum efficiency IQE is 1.17 times to 1.7 times larger than that in the case where the Hbun / Have is not in the range of 6.0 to 346.2 and the internal quantum efficiency IQE is not included in the concavo-convex structure (Comparative Example 5), and the warpage of the epitaxial wafer for LED . At this time, Hbu / Have is 3.3 or more and 203.8 or less. In addition, it is understood that if Hbun / Have is 17.6 or more and 72.5 or less, the improvement of the internal quantum efficiency (IQE) and the reduction of the warp become more remarkable. At this time, Hbu / Have is not less than 9.6 and not more than 42.5. This is because, since Hbun / Have satisfies a range of a predetermined value or more, the electric potential in the first semiconductor layer can be dispersed and reduced by the concavo-convex structure (A), and Hbun / Have satisfies a range of a predetermined value or less , The film thickness of the first semiconductor layer can be reduced, and warpage can be reduced. No. 12, Hbun / Have has a small value of 6.0 and Hbu / Have has a small value of 3.3. Therefore, the improvement rate of the internal quantum efficiency (IQE) is slightly lower than that in the case where there is no concavo-convex structure (Comparative Example 5). This is considered to be because the improvement in the performance of the light emitting semiconductor layer and the second semiconductor layer as a semiconductor is limited because the potential reduction effect inside the first semiconductor layer is slightly weak. In No. 1, Hbun / Have is 346.2 and Hbu / Have is 203.8, which is a large value, and it can be seen that warping of the LED epitaxial wafer affects chip formation. From the above, it can be seen that the improvement of the internal quantum efficiency (IQE) and the reduction of warping can be improved at the same time by having Hbun / Have within a predetermined range.

(Pattern wafer 2 for LED)

As above, in the first to fifth embodiments, the patterned wafer 1 for LED has been described. In the following embodiments, the LED pattern wafers 2 to which another concavo-convex structure L is added to the pattern wafers 1 for LEDs will be described.

In the following examination, the concavo-convex structure (A) was formed on the surface of the wafer for LED by using the nano-working film used for manufacturing the patterned wafer 1 for LEDs in the first to fifth embodiments. Subsequently, a concave-convex structure L was further formed to obtain a patterned wafer 2 for LED having the concavo-convex structure A and the concavo-convex structure L. [ Finally, an epitaxial wafer for LEDs was fabricated using the patterned wafer 2 for LED having the obtained concavo-convex structure, and thereafter chips were formed and the performance was evaluated. On the other hand, the concave-convex structure L was controlled by the mask shape and the dry etching condition in the photolithography method. A mold was produced in the same manner as in Example 1 and subjected to mold release treatment in the same manner as in Example 1. [

The nano-working film was processed in the same manner as the pattern wafers (1) for LEDs of Examples 1 to 5 described above to process wafers for LED. As the wafer for the LED, a C-plane (0001) sapphire wafer having an orientation flat on the A-plane (11-20) was used. The size of the LED wafer was 4 inches in diameter.

The shape of the convex portion of the concavo-convex structure (A) formed on the sapphire wafer was controlled in the same manner as the pattern wafers (1) for LEDs of Examples 1 to 5.

The patterned wafer 1 for an LED having the concavoconvex structure A formed thereon, that is, the pattern wafer 1 for LEDs, was further processed to produce a concave-convex structure L. A novolak resin for photoresist was formed on the concavo-convex structure (A) of the pattern wafer for LED (1) by spin coating and prebaked on a hot plate at 120 占 폚. Subsequently, lithography was carried out to produce a concavo-convex structure L. Here, the concavo-convex structure L is formed into a dot shape by using the negative development of the photoresist, and the concavo-convex structure L is formed into a hole structure by positively developing the photoresist. In any case, as the concavoconvex structure L, the convex portion or the concave portion was arranged in a dish arrangement and the average interval PL was 3.2 m.

The obtained pattern wafers 2 for LEDs were observed with a scanning electron microscope. The dot-like concavo-convex structure L was the following dot-shaped body.

The mean spacing (PL) was 3.2 ㎛, and the cells were arranged in a row.

The diameter of the bottom of the dot was 2.4 탆, and the shape of the bottom was approximately circular.

The concave bottom between the dots was flat.

· The top of the dot has a flat surface, and the dot is a conical shape. The flat surface of the dots top was approximately circular and had a diameter of 1.6 mu m.

The top of the dots is a circular table top, and the concave and convex structures A are arranged only on top of the dots.

On the other hand, the hole-like concavo-convex structure L was the following hole-shaped body.

The mean spacing (PL) was 3.2 탆, and the cells were arranged in a row.

The diameter of the opening of the hole was 1.5 占 퐉, and the opening shape was approximately circular.

The depth of the hole was 1.4 탆.

The convex portion between the holes is flat, and the concavoconvex structure A is disposed on only this flat face.

The shape of the hole was a cone with a roughly circular bottom surface, and the top of the cone was a corner with a radius of curvature of more than 0.

Another concavo-convex structure L was also produced. First, spin-on glass was formed on the concavo-convex structure (A) of the pattern wafer for LED (1) by the spin coating method and then sintered to obtain SiO ₂ . At this time, it was confirmed that the concavo-convex structure (A) was planarized by SiO ₂ . Subsequently, a novolak resin for photoresist was formed on SiO ₂ by spin coating, and prebaked on a hot plate at 120 ° C. Subsequently, lithography was carried out and only SiO _{2 was} processed to produce a concavo-convex structure L. Here, the photoresist was positively developed to partially form a substantially disc-shaped SiO ₂ on the surface of the concavo-convex structure (A). The mean spacing (PL) was 3.2 占 퐉, and the array was arranged in a closed-cell arrangement.

The obtained SiO ₂ pattern (concave-convex structure L) observed by the scanning electron microscope of the patterned wafer 2 for LED was the following dot-shaped body.

The mean spacing (PL) was 3.2 탆, and the cells were arranged in a row.

The diameter of the bottom of the dot was 1.5 탆, and the shape of the bottom was approximately circular.

The concavo-convex structure A was formed at the bottom of the concave portion between the dots.

On the patterned wafer for LED 2, a low temperature growth buffer layer of Al _x Ga _{1 - x} N (0 _{? X} ? 1) was formed as a buffer layer in a thickness of 100 Å. Subsequently, undoped GaN was deposited as the undoped first semiconductor layer, and Si-doped GaN was deposited as the doped first semiconductor layer. Subsequently, a distortion absorbing layer was provided, and then an active layer (well layer, barrier layer = non-doped InGaN, Si-doped GaN) of a multiple quantum well was formed as a light emitting semiconductor layer with a thickness of 60 Å and 250 Å, The six layers and the barrier layers were alternately stacked so as to have seven layers. On the light emitting semiconductor layer, Mg-doped AlGaN, undoped GaN, and Mg-doped GaN were stacked so as to include the electro-blocking layer as the second semiconductor layer. Then, ITO was deposited, etched, and then an electrode pad was attached. In this state, a current of 20 mA was passed between the p-electrode pad and the n-electrode pad using a prober to measure the luminous output.

The internal quantum efficiency (IQE) was determined by PL intensity. The internal quantum efficiency IQE is defined by (the number of photons emitted from the light emitting semiconductor layer per unit time / the number of electrons injected into the LED per unit time). In this embodiment, PL intensity measured at 300 K / PL intensity measured at 10 K was used as an index for evaluating the internal quantum efficiency (IQE).

The light extraction efficiency (LEE) was calculated from the luminescence output and internal quantum efficiency (IQE).

The cracks were judged by observation using an optical microscope, an atomic force microscope, and a scanning electron microscope at the semiconductor layer side of the epitaxial wafer for LED after forming the semiconductor layer. Further, the epitaxial wafer for LEDs was taken out together, and the cross section of the semiconductor layer was observed with a scanning electron microscope to evaluate cracks. On the other hand, regarding the evaluation of the crack, the film formation of the semiconductor layer was stopped during the formation of the facets.

(Example 6, Comparative Example 6)

In Example 6, the following were investigated.

1. A conventional patterned sapphire substrate (PSS: patterned sapphire substrate), that is, a pattern wafer for LEDs only with a concavo-convex structure L and a pattern wafer 2 for LEDs having both the concavo-convex structure A and the concavo- )

2. Influence of the shape of convex portion of convex-concave structure (A)

3. The difference between the dot-like concavo-convex structure L and the hole-

4. The case where the concavoconvex structure A is formed on the top of the convex portion of the concavoconvex structure L and the case where the concavo-convex structure A is formed on the bottom of the concave portion of the concave-

The shape of the convex portion of the concave-convex structure (A) was observed using a scanning electron microscope. The concavo-convex structure (A) was a meat arrangement. That is, it was a six-fold symmetrical arrangement. The average interval PA was 300 nm, and the diameter of the bottom of the convex portion was 220 nm. The rotation shift angle? Was set to 30 °. Under these conditions, the case where the convex portion top has a rounded corner portion and the case where the table top is provided were produced by changing the processing time of the reactive ion etching. On the other hand, the shape of the rounded corner portion is a shape in which curved lines bulging upward slightly in the contour of the cross section of the cross section at the top of the convex portion when the cross sectional shape of the convex portion is assumed. In other words, the side portion of the convex portion has a slightly bulged shape. In addition, in the PSS as the sample of Comparative Example 6, only the uneven structure L was produced by the above-described photolithography method. The prepared samples are shown in Table 6.

The meanings of the terms in Table 6 are as follows.

· N ... Rotational symmetry order of the concave and convex structure (A).

· PA ... Is the average spacing of the concavo-convex structure (A), and the dimension is &quot; nm &quot;.

· Θ ... Is the rotation shift angle (?) Of the concave and convex structure (A), and the dimension is "°".

· Top shape of convex part ... The shape of the top of the convex portion of the concave-convex structure (A). The table top (100 nm) means that the flat surface of the convex portion of the concavo-convex structure (A) has a diameter of 100 nm.

· M ... Rotational symmetry order of the concave and convex structure (L).

· PL ... Is the average spacing of the concavo-convex structure (L), and the dimension is &quot; nm &quot;.

·rescue… In the case where the concave-convex structure L is formed by directly processing the concave-convex structure A by the above-described method, the case where the concave-convex structure L is a dot type is referred to as a dot, . The case of forming convex portions of the concavo-convex structure L made of SiO ₂ separately on the surface of the concave-convex structure A is referred to as SiO ₂ . These terms are also used in the seventh to ninth embodiments and have the same meaning.

· AonL ... In a case where the concavoconvex structure A is disposed on the top surface of the top portion of the convex portion of the concavoconvex structure L

· AinL ... When the concavoconvex structure A is disposed at the bottom of the concave portion of the concavoconvex structure L

· PL / PA ... The ratio of the average interval (PL) to the average interval (PA).

· IQE ... Internal quantum efficiency, calculated by the method already described. The dimension is "%".

· Lighting output ... (Comparative Example 6) in which only the concavo-convex structure L is 1,

·crack… Crack observed by optical microscope. The case where the LED chip which caused the abnormality in the light emission output was 10% or more was rated as?, The case where the LED chip was 5% or more and less than 10% was rated as?, And the case where the LED chip was less than 5%

As can be seen from Table 6, when both the concave-convex structure A and the concavo-convex structure L are formed as compared with the case of only the concave-convex structure L (Comparative Example 6), cracks, internal quantum efficiency IQE, , And light emission and emission are both improved. This is because, in the case of Comparative Example 6, the light extraction efficiency (LEE) can be improved by the microscopic concavo-convex structure (L), but the density of the concave- It can not be done. By the provision of the concave-convex structure (A), it was confirmed from the transmission electron microscopic observation that the dislocation disappears and is reduced. That is, when the concavoconvex structure A is formed, it is possible to start the growth of the semiconductor layer from the concave portion of the concave-convex structure A. As a result, the potential is reduced. In addition, the reduction of the dislocation can be achieved by dispersing the merged portion by the uneven structure (A) because the merging of the growing semiconductor layers is a principle. As a result, the residual stress on the semiconductor layer is reduced and it is presumed that cracks are suppressed.

It can be seen that when the concave and convex structure A and the concave and convex structure L are both formed, the top portion of the convex portion of the concave and convex structure A has stronger influence than the concave and convex structure L type. It can be seen that the inner quantum efficiency IQE is further improved and the cracks are reduced when the shape of the top of the convex portion of the concavoconvex structure A is rounded. First, with respect to the internal quantum efficiency (IQE), it was confirmed from transmission electron microscope observation that the probability of collision between dislocations in the vicinity of the concave portion of the concavo-convex structure is high when the convex portion has rounded corners . The crack density estimated from the observation image of the scanning electron microscope was 51 to 57 x 10 &lt; ⁹ &gt; / cm &lt; 2 &gt; when the convex portion of the concavoconvex structure A was rounded. On the other hand, in the case where the table top is present at the convex portion of the convexo-concave structure (A), a potential is generated from above the table top, and this potential is observed to grow in the thickness direction of the semiconductor layer. Further, the growth of the semiconductor layer was stopped in the middle, and the surface was observed in detail using a scanning electron microscope. As a result, when there was a round at the top of the convex portion, the semiconductor layer was preferentially grown from the concave portion of the concave- , And it was observed that the grown semiconductor layers were well coalesced. From the observation of the scanning electron microscope, the estimated crack density was 82 to 89 × 10 ⁹ / cm 2. On the other hand, in the case where the table top is present at the top of the convex portion, the frequency at which voids are partially formed in the vicinity of the periphery of the convex top portion composed of the convex top portion and the side surface portion of the convex portion due to the influence of the semiconductor layer growing from above the convex top portion Was slightly higher. That is, from the viewpoint of increasing the collision frequency between the potentials and effectively reducing the dislocation density, it was found that the convex portion of the concave-convex structure A is preferably a corner portion having a radius of curvature of more than 0. On the other hand, with respect to these tendencies, similar tendencies can be observed with respect to the convex shape shown in Fig.

The comparison of the arrangement of the concavo-convex structure A with respect to the concavo-convex structure L shows the case where the concavo-convex structure A is formed at the bottom of the concave portion of the concavo-convex structure L in order to improve the internal quantum efficiency IQE Which is the largest. In this examination, a plurality of convex portions of the concavo-convex structure L made of SiO ₂ were formed on the surface of the concavo-convex structure (A). That is, the condition for not starting the growth of the semiconductor layer from the convex top of the concave-convex structure L is set. Therefore, the semiconductor layer can be preferentially grown from the concave portion of the concavo-convex structure L. [ Here, it is considered that the recessed structure bottom A of the concave-convex structure L is provided with the concave-convex structure A, so that the potential of the semiconductor layer is reduced and cracks are suppressed based on the phenomenon already described.

(Example 7, Comparative Example 7)

In Example 7, the influence of the rotation shift angle? Was examined. The arrangement of the concavoconvex structures (A) is an array of meat-laying disposition, that is, six-fold symmetry. In addition, the average distance PA was 300 nm in all, and the shape of the top of the convex portion was rounded, and the diameter of the bottom of the convex portion was 220 nm. The rotation shift angle (?) Was used as a parameter to change from 0 ° to 10 ° pitch to 30 °. In addition, the concavo-convex structure L was produced by evaluating two types of hole type (holl) and SiO ₂ . In the case of the hole type, AonL, and in the case of SiO ₂ , AinL. The evaluated samples are summarized in Table 7.

In the samples described in Table 7, the internal quantum efficiency (IQE) was approximately the same in all samples when the concavo-convex structure L was a hole type, and was about 75%. In the case where the concavo-convex structure L was SiO ₂ , it was approximately the same in all samples, and was about 85%.

Cracks in the evaluation items in Table 7 are expressed by normalizing to 1 when the rotation shift angle? Is 0 °. As a concrete numerical value, when the concavoconvex structure L is a hole type, the crack density is 99 × 10 ⁹ / cm 2 and 87 × 10 ⁹ / cm 2 as the rotation shift angle θ changes to 0 °, 10 °, 10 ⁹ / cm 2, 69 × 10 ⁹ / cm 2 and 66 × 10 ⁹ / cm 2, respectively. On the other hand, in the case where the concavo-convex structure L was SiO ₂ , it was changed to 81 × 10 ⁹ / cm 2, 69 × 10 ⁹ / cm 2, 56 × 10 ⁹ / cm 2 and 54 × 10 ⁹ / cm 2. From Table 7, it can be seen that when the rotation shift angle? Increases, the cracks decrease. This is because the effect of the concavo-convex structure A of the patterned wafer 1 for LED is exhibited even when the concavo-convex structure L is formed. On the other hand, with respect to these tendencies, similar tendencies can be observed with respect to the convex shape shown in Fig.

From Examples 6 and 7, it can be seen that the internal quantum efficiency (IQE), the light extraction efficiency (LEE), and the crack can be improved by providing both the concavo-convex structure (A) I could. Further, it was found that the inner quantum efficiency (IQE) and the crack suppressing effect are further enhanced by the convex portion of the convexo-concave structure (A) being rounded portions. It was also found that a semiconductor layer having a high internal quantum efficiency (IQE) with cracks suppressed at a rotational shift angle? Of 10 ° or more was formed. In particular, it can be seen that the effect of reducing the warp becomes larger as the rotational shift angle? Increases by 10 °, 20 °, and 30 °. On the other hand, most preferably, Θ is 30 °, that is, (180 / n) ° = (180/6) °.

(Example 8)

In the eighth embodiment, a more preferable range of the ratio of the average interval PA to the average interval PL was investigated. The concave and convex structures A of the pattern wafers 2 for LEDs are arranged in a row in a square fashion (six-fold symmetry arrangement), the convex portion has rounded corners, and the rotation shift angle? The parameters are average spacing (PL) / average spacing (PA), fixed by moving the average spacing (PL) and moving the average spacing (PA). The average interval (PA) was adjusted in the range of 200 nm to 1800 nm. The concavo-convex structure L employed a hole type (holl) AonL having an average spacing PL of 3000 nm. The prepared samples are summarized in Table 8.

From Table 8, it can be seen that the larger the ratio PL / PA is, the higher the internal quantum efficiency IQE is. This is considered to be because the larger the ratio PL / PA is, the better the effect of the concavoconvex structure A can be expressed even when the concave-convex structure L is formed. In particular, a large ratio PL / PA means that the presence of the concavo-convex structure A seen from the concavo-convex structure L decreases. In other words, when viewed from a semiconductor layer which is made to run by CVD, the concave-convex structure L is confirmed first. Subsequently, when the surface of the concave-convex structure L is close to the surface of the concave-convex structure L, the presence of the concave-convex structure A can be recognized. Inversely, this means that the concave-convex structure L is well grown on the surface of the concave-convex structure A without being influenced by the large structure. Actually, as a result of stopping the growth of the semiconductor layer in the middle and confirming the growth state by a scanning electron microscope, the frequency of incorporation of the growing semiconductor layers becomes higher as the ratio (PL / PA) becomes larger, . Particularly, it has been confirmed that this phenomenon is expressed more satisfactorily by the rounded shape of the top of the convex portion. That is, when a convex portion with a table top is produced, the frequency of finding the potential in the semiconductor layer positioned on the convex top portion increases. For this reason, the internal quantum efficiency IQE tends to decrease. From the above, it was found that the ratio (PL / PA) is preferably more than 2.7, more preferably 3.6 or more, and most preferably 4.6 or more.

On the other hand, when the emission output of the LED was evaluated, the ratio (PL / PA) of 10.7 was larger than that of the case where the ratio (PL / PA) was 16.0. In addition, the emission output was larger in the case where the ratio (PL / PA) was 3.6 and the ratio (PL / PA) was 3.6, as compared with the case where the ratio (PL / PA) was 2.7 and 1.8. Furthermore, the light emission output was larger in the case where the ratio (PL / PA) was 10.7, as compared with the case where the ratio (PL / PA) was 3.6. Thus, it can be seen that the performance of the LED is not determined only by the magnitude of the internal quantum efficiency (IQE). This is the effect of light extraction efficiency (LEE). The PL / PA ratios were 10.7, 3.6, 4.6, 7.1, 2.7, 16.0 and 1.8, respectively. This is because, when the ratio (PL / PA) is 10.7, the optical diffraction is very strong and the number of diffraction modes is limited, but it is considered that the diffraction intensity in a predetermined direction is large. Then, if the ratio (PL / PA) is 3.6 and 4.6, the diffraction mode intensity is small, but the number of diffraction modes is considerably increased. When the ratio (PL / PA) is less than 3.6, the light scattering property becomes too strong, so that the light which has been guided in the LED once disturbs its traveling direction, . From the above, it can be seen that the larger the ratio PL / PA, the larger the internal quantum efficiency IQE. Further, it was found that the ratio (PL / PA) of the LED is preferably 2.7 to 16.0, more preferably 3.6 to 10.7. On the other hand, when the concavoconvex structure L was made of SiO ₂ , the same examination was made, and the same tendency as in Example 8 was observed.

(Example 9)

In Example 9, a more preferable range of the duty of the concavo-convex structure (A) was investigated. The convexo-concave structure A of the patterned wafer 2 for LED has a square arrangement (six-fold symmetry arrangement), a convex shape has rounded corners, a rotation angle θ of 30 °, ) Was set to 300 nm. The parameter is duty and adjusted in the range of 0.17 to 0.96. As the concavo-convex structure L, a hole type (holl) was produced. The prepared samples are summarized in Table 9.

From Table 9, it can be seen that the internal quantum efficiency (IQE) greatly varies between 0.73 and 0.96. This is considered to be because, when the duty is 0.96, the size of the bottom of the concave portion of the concave-convex structure A is smaller than the size of the stable nucleus of the semiconductor layer. That is, since the adhesion and growth of the nuclei are somewhat impaired, the potential reduction effect is lowered and the internal quantum efficiency (IQE) is estimated to be lowered. On the other hand, the larger the duty ratio, the better the light extraction efficiency (LEE) is. That is, it can be understood that the function of improving the light extraction efficiency (LEE) can be added by adjusting the duty in addition to the suppression of the crack and the improvement of the internal quantum efficiency (IQE), which are basic functions of the concave- convex structure (A). This is considered to be because the volume of the convex portion seen from the photon becomes large, and the mode number of the optical diffraction increases. On the other hand, as for the cracks, it was approximately the same in all samples and ranged from 49 to 52 x 10 ⁹ / cm 2. From the above, it can be seen that the duty of the concavo-convex structure (A) when viewed as an LED is preferably less than 0.96. Further, from the viewpoint of increasing the external quantum efficiency (EQE), it is preferable that the value is 0.53 or more, and more preferably 0.63 or more. On the other hand, when the concavoconvex structure L was made of SiO ₂ , the same examination was made, and the same tendency as in Example 9 was observed.

INDUSTRIAL APPLICABILITY The present invention can be applied to an LED, and particularly applicable to a GaN-based semiconductor light emitting device applied to a blue LED, an ultraviolet LED, and a white LED.

This application is based on patents 2013-116025 of May 31, 2013 and 2013-116024 of May 31, 2013. These are all included here.

Claims (15)

(A) having a substantially symmetrical arrangement n times at least on a part of its main surface,
At least a part of the convexo-concave structure (A) is formed such that the rotational shift angle (?) Of the array axis A of the concave-convex structure (A) with respect to the crystalline axis direction of the patterned wafer for LED in the main surface is 0 < / n) °,
The convex portion of the convexo-concave structure (A) is a corner portion having a radius of curvature of more than 0
And pattern wafers for LEDs. The patterned wafer for LED according to claim 1, further comprising an uneven structure (L) having an arrangement substantially symmetrical with m times, which is different from the uneven structure (A). The structure according to claim 2, wherein the concave-convex structure (L) comprises a plurality of convex portions and concave portions having a first average interval (PL) And a plurality of convex portions and concave portions formed on at least one surface of the convex portion and the concave portion and having a second average pitch PA and the first average pitch PL and the second average pitch And the ratio (PL / PA) of the total area (PA) is more than 1 and not more than 2000. The concavo-convex structure (L) according to claim 3, wherein a plurality of the convex portions constituting the convexo-concave structure (L) are spaced apart from each other, and at least the concave- And the plurality of convex portions or the concave portions constituting the concave portion are formed. The structure according to claim 3, wherein a plurality of the concave portions constituting the concavo-convex structure (L) are spaced apart from each other, and at least the convexo-concave structure (A) is formed at the top of a plurality of convex portions constituting at least the concave- And the plurality of convex portions or the concave portions constituting the convex portions are formed. 6. The patterned wafer for LED according to any one of claims 3 to 5, wherein the coverage ratio of the uneven structure (A) to the uneven structure (L) is more than 0% and less than 100%. The structure according to claim 2, wherein the concave-convex structure (A) comprises a plurality of convex portions and concave portions having a first average interval (PA) And a plurality of convex portions having a second average spacing PL formed between the first and second average spacings PA and PL so that the concave and convex structures A are partially exposed, ) Is in a range of more than 1 and not more than 2,000. The patterned wafer for LED according to claim 1 or 2, wherein an average spacing (Pave) of the concave-convex structures (A) satisfies 50 nm? Pave? 1500 nm. The method according to claim 1 or 2, wherein a duty (? Ave / Pave), which is a ratio of an average width (? Ave) of the convex bottom portion of the convexo-concave structure (A) , The rotation shift angle (?) Satisfies a range of atan (duty / 2)??? (180 / n). 10. The patterned wafer for LED according to any one of claims 1 to 9, wherein the patterned wafer for LED is a sapphire wafer, a silicon wafer, a silicon carbide wafer, or a gallium nitride wafer. A patterned wafer for LED according to any one of claims 1 to 10, wherein at least a first semiconductor layer, a light-emitting semiconductor layer and a second semiconductor layer are stacked in this order on the main surface on which the concavo- Wherein the epitaxial wafer is an epitaxial wafer. 12. The semiconductor light emitting device according to claim 11, wherein the distance (Hbun) between the surface of the LED pattern wafer on the side of the light emitting semiconductor layer and the surface of the light emitting semiconductor layer on the side of the first semiconductor layer, (Hbun / Have) to Have (Have) satisfy 2? Hbun / Have? 300. The LED according to claim 11, wherein the first semiconductor layer includes a first undoped semiconductor layer and a first doped semiconductor layer which are sequentially stacked from the patterned wafer side of the LED, The ratio (Hbu / Have) of the distance (Hbu) between the surface of the undoped first semiconductor layer and the surface of the undoped first semiconductor layer on the doped first semiconductor layer side to the average height Have of the concave- convex structure (A) Hbu / Have &amp;le; 200. &lt; / RTI &gt; A method for manufacturing a patterned wafer for LED according to any one of claims 1 to 10,
A step of optically inspecting the prepared pattern wafers for LED;
A process for producing the epitaxial wafer for LED described in any one of claims 11 to 13 using the optically-inspected patterned wafer for LED
Wherein the epitaxial layer is formed on the epitaxial wafer. The method according to claim 14, wherein the step of preparing the pattern wafers for LED is performed so as to satisfy the rotation shift angle (?) By a transfer method using a mold having a fine pattern on its surface A method of manufacturing a wafer.

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