KR20150144715A - Error detection in stored data values - Google Patents

Abstract

An apparatus has a plurality of storage units. A parity generator is configured to generate a parity value in accordance with the respective values stored in the storage units. The parity generator is configured such that determination of the parity value is independent of read access to data stored in the storage units. A detector is configured to detect a change in the parity value.

Description

Error detection of stored data values {ERROR DETECTION IN STORED DATA VALUES}

The present invention relates to a data processing system. More particularly, the present invention relates to a data storage device having circuitry configured to store data values and provided to detect changes in stored data values.

The data value stored in the data storage device may be susceptible to change, for example, by particle strike which causes a bit flip of the stored data value. For this reason, a conventional data storage device has been provided with a mechanism for determining whether the data value read from the data storage device has been altered in any way after it was originally stored. One such mechanism is to provide a parity checking circuit. Such parity checking circuitry may be used to determine whether a parity value is generated (e.g., by passing a data value to an XOR tree to produce a single last parity bit) And is stored in association with the data value of the next data storage device. When the stored data values are later read, the individual bits of these data values are passed back to the same XOR tree so that a compare parity can be generated, which is then stored in association with the data value when the data value was originally stored It can be compared with a parity bit. If the two parity bit values are different, it is known that a bit flip has occurred in the stored data value, and then an appropriate response such as discarding such stored data value or attempting to correct such stored data value may be performed.

An example of a data storage device 10 configured to operate in this manner is schematically illustrated in FIG. It should be noted that although a multi-bit data value is initially received and the bits of such a data value may be provided for each bit cell 11-14 (although only four bit cells are shown for clarity, This multi-bit data value is also passed to the XOR tree 15 which generates a single bit parity value P that is stored in the location 16 in association with the stored data value. When read access is performed, individual bits of this data value are also passed to the XOR tree 17 (which is configured identically to the XOR tree 15) and the last parity bit value is passed to the parity bit read from the parity bit storage 16 P and the comparator circuit 18. If these two values are different, the error flag is asserted.

In a first aspect, the invention provides a data processing apparatus comprising: a plurality of storage units configured to receive data and output the data in response to a read access; And a parity generator associated with the plurality of storage units, wherein the parity generator receives each value from each of the plurality of storage units at a plurality of inputs; Determine a parity value from the plurality of input units; The parity value being independent of read access to data stored in the plurality of storage units and the apparatus being further configured to detect a change in the parity value Device.

The present technique recognizes that whenever there is a read access to the stored data value, the energy consumed in generating parity bits for comparison with the initially generated parity bits is not beneficial. In particular, the read access can be performed on data values at a much greater frequency than the write approach, and thus a significant difference between the energy consumption associated with the generation of the original parity bits and the energy consumption associated with the generation of parity bits for each read access It has been recognized that asymmetry can occur. Accordingly, the present invention proposes a configuration in which a parity generator is provided that is designed to generate a parity value from a plurality of inputs received from a plurality of storage units, wherein the generation of the parity value is performed by Independent of read access. Thus, a device with lower energy consumption is provided, since the parity value is not recalculated each time a read access is performed.

The parity generator is configured to be independent of read access so that no transition occurs in the stored data value parity generation circuit unless the value of the data bit stored in one of the data storage units is unchanged. Accordingly, parity determination can occur simultaneously. That is, it is executed as soon as an error occurs in one of the stored data bits. This is beneficial because it not only can be flagged as soon as an error occurs, but also helps to prevent accumulation of errors. This is significant in a data storage device that tries to avoid data errors by using parity values generated based on stored data values because if two bits change in the stored data value (or indeed any additional even number of bits , This change can not be detected by this parity method, and this parity value is again equal to the first parity value. Thus, the generation of parity bits that change as soon as one of the data bits changes in the stored data value helps to prevent potential data corruption that is overlooked by an even number of bit flips.

The detector configured to detect a change in the parity value may take various forms and may be one of a transition detector and an active comparator. That is, such a detector may take the form of a device configured to detect a change in the parity value itself, or it may take the form of a device configured to compare a parity value with another value to determine whether the parity value has undergone a change .

In some embodiments, the apparatus further comprises a second parity generator configured to generate a second parity value associated with the data when the data is received by the plurality of storage units.

The second parity value may be used in various ways in the apparatus, but in some embodiments the second parity value may be stored in the additional storage unit associated with the plurality of storage units when the data is stored by the plurality of storage units Lt; / RTI > And the second parity value is read from the additional storage unit by the detector for comparison with the parity value to detect a change in the parity value. Thus, the second parity value may indicate a "snapshot" of the value that the parity value associated with the data stored in the storage unit when the data was first received, so that the detector has no read access to the stored data From this initial snapshot, you can continue to monitor for any deviations.

The relative timing of the generation of the parity value of the apparatus may vary according to a particular implementation requirement, but in some embodiments, the parity generator may generate the parity value after the second parity generator generates the second parity value . The second parity generator generates the second parity value and then constructs the parity generator to generate the parity value so that the first snapshot of the "true" parity of the stored data (i.e., Corresponding to what it had) is first picked up as the second parity value, after which any comparison can be made to this first "true" value.

In some embodiments, the data storage device further comprises a write enable signal line configured to transmit a write enable signal asserted when the data word is being written to the plurality of data storage units, wherein the write enable A signal line is coupled to the detector and the detector is disabled when the write enable signal is asserted. The period in which such a data word is written in the plurality of data storage units is recognized as a period in which the parity generation circuit is temporarily in an undetermined state because the dependence of the parity bit on the value of the individual data bit of the data word being written Because. Thus, when these data bits are recorded, the value of the parity bit can be shortened by the relative timing of writing of each individual data bit. This short pending period can be correctly ignored by disabling the detector for a period during which the write enable signal is asserted. Thus, detection of a change in the value of the parity bit is active only for the remainder of the time when the real error occurring in the stored data value is to be detected.

In some embodiments, the data storage device is a multiport register file including a plurality of read ports from which the plurality of storage units can be read. The present technique is particularly advantageous in that the provision of a plurality of read ports may result in the generation of a parity value associated with each read access, potentially at a significant frequency, and to avoid such parity generation associated with each read access, as provided by the present technique , It is recognized that the multiport register file represents a device in which some of the advantages of the present technology are exhibited. The multiport register file may also be a particularly advantageous situation for the implementation of the technique because of the large number of interconnections that must be provided in connection with the layout of the multiport register file. Thus, if the present technique has more gates (usually XOR gates) to provide than conventional parity generation schemes, such as adding one XOR gate in association with each flip flop storing each bit of data value, for example Although this may be necessary, this larger number of gates does not necessarily mean more area for the provision of register files. This is due to the fact that the layout area of these multiport register files is usually dependent on that interconnect. For example, a modern multiport register file may have nine write ports and fourteen read ports, meaning that 23 parallel (horizontal) word lines are needed for each flip flop. It has been found in the implementation of such multi-port register files that these can often be "wired controlled" with considerable "white space" Since the provision of such parity generation circuitry can be added as little as one additional horizontal signal, it is possible to reduce the additional gate cost to a layout implementing the technique without significantly affecting the area required for the multiport register file It is possible.

The parity generator may be provided in various ways. In some embodiments, the parity generator includes linearly coupled logic circuitry provided in association with the plurality of storage units, each logic circuit having as its input one respective data bit of each storage unit. A data bit stored in each storage unit is coupled to a linearly coupled logic circuit that provides one input for the XOR gate and another input provided by the output of the previous XOR gate (e.g., one XOR gate for each storage The chain set of XOR gates provided in association with the unit) has the advantage of only being added to the storage unit itself. In practice, it may be possible for additional logic circuitry (e.g., XOR gates) to be superimposed in a storage unit (e.g., a flip-flop), especially when a double-height cell is used in the layout.

In another embodiment, however, the parity generator comprises a hierarchical tree of logic circuits, the logic circuit of the lowest level of the hierarchical tree having as its input each data bit of each pair of storage units, The logic circuit at the top level of the hierarchical tree generates parity bits as its input. The hierarchical tree of these logic circuits has the advantage that there is a potential cost of some additional horizontal wiring in the layout, but the parity calculation latency is reduced. However, as described above, this additional horizontal wiring actually has little effect on the layout area in an implementation such as a multi-port register file in which the existing white space of the layout can absorb such wiring. The number of gates (e.g., XOR gates) of such parity generation logic circuits is usually the same.

In some embodiments having a hierarchical structure of logic circuits, the data storage device receives the parity value output at the highest level of the hierarchical tree and outputs the parity value at the scan output of the scan unit in response to the scan-out signal And the scan unit configured as described above. Thus, by this scan unit, the contents of a plurality of data storage units can be observed through a single point of the scan chain. For example, rather than a series of data bits corresponding to the entire contents of the data storage unit, an inspection pattern can be written to the data storage unit via a conventional (parallel) data path, and the last parity bit is scanned Out.

Although the parity generator may simply generate one parity value that depends on all of the data bits of the data word, in some embodiments the parity generator may generate a parity value that is less than all of the data stored in the plurality of storage units And generates a sub parity bit according to a small amount of data. This also reduces the wait time for parity calculation due to the fact that fewer data bits are used to generate these sub parity bits.

A particular implementation of the generation of sub-parities for a data word may take many forms. For example, in one embodiment, the parity generator is configured to generate a plurality of sub-parity bits for data stored in the plurality of storage units. Thus, rather than generating one parity bit for the entire data word, the data can be divided into two parts, for example, and sub-parity bits can be generated for each of these parts. This allows a more precise determination of the location of the error that occurs when a change in one of these sub-parity bits is detected by the detector, particularly in embodiments where the parity generator is provided in linear concatenation, Is generally faster than the determination of bits.

However, there may be cases where a portion of the data word can be ignored, for example, a sub parity bit is generated because another portion of the data word needs to be monitored for the occurrence of an error. Thus, in some embodiments, the parity generator is configured such that at least one data bit stored in the plurality of storage units does not affect the value of the sub-parity bit.

In some embodiments, the data storage device is configured to store a plurality of data words, wherein the parity generator is configured to generate a respective parity bit for each of the data words, And to generate an error flag if the value of any of the bits changes. With the error flag thus generated, it can be recognized that an error has occurred in one of the plurality of data words stored in the data storage device, and an appropriate corrective action can be taken. Further, the present technology recognizes that an error has occurred in a plurality of data words rather than a specific position where a data error occurs (that is, a specific data word including an error in a plurality of data words in this case) It is recognized that there are more important situations. For example, in a register file, for a particular data word (or a particular data bit), a target correction may be made for a particular data word (e.g., because such an error is relatively rare in one of the data words stored in the plurality of data words stored by the register file) It is desirable to simply replace or update the entire contents of the register file instead of taking action.

In some embodiments, the apparatus is configured to store a plurality of data words, the parity generator being configured to generate a respective parity bit for each of the data words, the apparatus comprising: a non-error value or error Wherein the error register is configured to switch to maintaining the error value if at least one of the parity bits is changed. This configuration provides a " sticky register "that maintains a non-error value in a normal environment, but it is configured such that if one of the parity bits changes its value, the error value is maintained, We will keep this error value constant. Thus, such an error register can be monitored (e.g., via a polling mechanism) to determine if an error has occurred in one of a plurality of data words stored in the data storage device, and as in the example described above, Such as replacing or updating all of a plurality of data words without further attempting to determine if the error has occurred.

In a second aspect, the present invention provides a method comprising: storing data in a plurality of data storage units; Outputting the data from the plurality of storage units in response to a read access; Receiving a value from each of the plurality of storage units at each of a plurality of inputs of a parity generator associated with the plurality of storage units; Determining a parity value from the plurality of input units; Outputting the first parity value; And detecting a change in the output parity by an active comparator, wherein the determination of the parity value is independent of the read access to the data stored in the plurality of storage units.

In a third aspect, the present invention provides a system comprising: means for storing data in a plurality of data storage units; Means for outputting the data from the plurality of storage units in response to a read access; Means for receiving a value from each of the plurality of storage units at each of a plurality of inputs of a means for generating a parity value associated with the plurality of storage units, The means being configured to generate a parity value that is independent of the read access to the data stored in the plurality of storage units; Means for outputting the first parity value; And means for detecting a change in the output parity.

In a fourth aspect, the invention provides a data processing apparatus comprising: a plurality of data storage units each configured to store a respective data bit of a data word; A stored data value parity generation circuit configured to generate a parity bit for the data word according to a data bit of a data word stored in the plurality of data storage units; And a transition detection circuit configured to detect a change in the value of the parity bit, and wherein the stored data value parity generation circuit generates, when the data word is read from the plurality of data storage units, To the data storage device.

The stored data value parity generation circuit is configured such that the stored data value parity generation circuit does not cause a transition if the value of the data bit stored in one of the data storage units does not change.

Wherein the data storage device further comprises a write parity bit circuit configured to generate a write parity and store the write parity when a new data word is written to the plurality of data storage units, And to detect the change by comparing the stored parity bit with the stored parity bit.

The transition detection circuit is configured such that the transition detection circuit does not cause a transition if the parity bit for the data word does not change.

Wherein the data storage device further comprises a write enable signal line configured to transmit a write enable signal asserted when the data word is being written to the plurality of data storage units, And the transition detection circuit is disabled when the write enable signal is asserted.

The data storage device may be a multiport register file including a plurality of read ports through which the plurality of data storage units can be read.

The stored data value parity generation circuit comprises linearly coupled logic circuits provided in association with the plurality of data storage units, each logic circuit having as its input one respective data bit of each data storage unit .

Wherein the stored data value parity generating circuit comprises a hierarchical tree of logic circuits, the logic circuit of the lowest level of the hierarchical tree having as its input each data bit of each pair of data storage units, The logic circuit of the highest level of the logic circuit generates a parity bit for the data word as its input.

The data storage device may further comprise the scan unit configured to receive a parity for a data word output at the highest level of the hierarchical tree and output the parity bit at a scan output of the scan unit in response to a scanout signal have.

The stored data value parity generation circuit may be configured to generate a sub parity bit for the data word according to a data bit number less than all the data bits of the data word stored in the plurality of data storage units.

The stored data value parity generation circuit may be configured to generate a plurality of sub parity bits for the data word.

The stored data value parity generation circuit may be configured such that at least one of the data bits of the data word stored in the plurality of data storage units does not affect the value of the sub parity bit.

The data storage device may be configured to store a plurality of data words and the stored data value parity generation circuit may be configured to generate a respective parity bit for each of the data words, And a combinational logic circuit configured to generate an error flag if any one of the respective parity bits changes in value.

The data storage device may be configured to store a plurality of data words and the stored data value parity generation circuit may be configured to generate a respective parity bit for each of the data words, And - an error register configured to maintain an error value or an error value, wherein the error register can be configured to switch to maintaining the error value if at least one of the values of the respective parity bits changes.

In a fifth aspect, the invention provides a method comprising: storing each data bit of a data word in a plurality of data storage units; Generating a parity bit for the data word through a plurality of intermediate steps according to a data bit of the data word stored in the plurality of data storage units, wherein when the data word is read from the plurality of data storage units, Wherein no conversion takes place at an intermediate stage of the process; And detecting a change in the value of the parity bit.

In a sixth aspect, the present invention provides an apparatus comprising: means for storing a respective data bit of a data word in a plurality of data storage units; Means for generating a parity bit for the data word through a plurality of intermediate steps in accordance with the data bits of the data word stored in the plurality of data storage units, Means for not switching in a plurality of intermediate steps; And means for detecting a change in the value of the parity bit.

The invention will now be described, by way of example only, with reference to the embodiments thereof, as illustrated in the accompanying drawings.
1 schematically illustrates the use of parity bit generation to determine if an error has occurred in such stored data values between when a stored data value according to the prior art was recorded and when it was read.
Figure 2 is a schematic diagram of a data storage device configured to detect errors in stored data values in one embodiment.
Figure 3 is a schematic diagram of a data storage device configured to detect errors in stored data values in another embodiment.
Figures 4A and 4B are schematic diagrams illustrating two embodiments of a parity generation circuit provided in association with a data storage unit.
5A is a diagram schematically illustrating the provision of a parity generation circuit as a linearly connected XOR gate in one embodiment.
5B schematically illustrates providing a parity generation circuit as an XOR tree in one embodiment.
Figure 6 schematically illustrates that in one embodiment the scan flops provide a parity generator circuit as an XOR tree coupled to the output of the XOR tree.
7 is a diagram schematically illustrating the generation of one or more sub-parity bits in one embodiment.
Figure 8 is a schematic diagram of a multiport register file in one embodiment.
Figure 9 is a schematic illustration of a series of steps taken in the method of one embodiment.

Figure 2 schematically illustrates a data storage device 20 of one embodiment. This data storage device 20 is a register file provided in close association with a processor unit for storage of a specific data value used by the processor unit. These data values are stored as data words in the data storage device, and in the write operation, the data words are written to the storage capacity of the data storage device, which in this embodiment is each configured to store one bit of the data word And is provided by a plurality of data storage units 21-24 provided by a set of flip flops. The number of bits of the data word to be stored (in particular by the fact that the data storage units 23 and 24 are separated by a series of dots) may exceed four and only four data storage units Will be understood to be merely illustrative. Further, although the data storage device 20 is configured to store a plurality of data words, for the sake of understanding, only the storage capacity associated with one data word is shown.

As part of the write process, the data word is also sent to the XOR tree 25, which is also configured to generate a single parity bit P depending on each value of the data bits of the data word. This parity bit P is stored in the parity bit storage location 26 provided in association with the data storage unit 21-24 which stores the data word itself. Simultaneous parity generation circuit 27 is also provided in association with data storage unit 21-24 which holds the stored data word. In particular, this simultaneous parity generation circuit 27 includes a parity logic unit 28-30 provided in association with a substantially first data storage unit 21 of a data storage unit holding a data word. Each parity logic unit 28-30 is configured to take an input derived from a previous stage of the set of data storage units and to logically combine the input with the value held by the associated data storage unit. 2, the parity logic unit 28-30 is each XOR gate so that the XOR gate 28 takes as its input the value stored in the data storage unit 21,22 and the XOR gate 29, Takes as its input the output of the XOR 28 as one input and the value stored in the data storage unit 23 and the XOR gate 30 receives as its input the output from the previous XOR gate (not shown) And takes a value stored in the data storage unit 24. [ In this way, parity bits are generated which depend on each content of the data storage unit 21-24. In particular, it should be noted that, in this way, it is arranged to calculate the parity bits in real time regardless of any read accesses to the data storage units 21-24. The parity bit generated by the XOR gate 28-30 is somewhat pending while the data word is being written to the data storage unit 21-24, but once the data word is written, Will not be switched until there is a bit flip in one of the units (or until a new data word is written to the data storage unit). The output of the last XOR gate 30 provides one input to the active comparator circuit 31 which takes the value P stored in the parity bit store 26 as its other input. The active comparator circuit 31 has "active" in that it switches only when, for example, one of its inputs provided by the various XOR gates changes.

3 schematically shows a data storage device 40 of another embodiment. 2, the data storage device 40 is a register file provided in close association with a processor unit for storage of specific data used by the processor unit. Also, as in the embodiment shown in FIG. 2, the data storage device 40 is configured to store a plurality of data words, but for clarity, only the storage capacity associated with one data word is shown.

Here, as in the case of the embodiment shown in FIG. 2, during a write access, a multi-bit data word is written to the set of data storage units 41-44, each holding a single bit of the data word. However, here, unlike the embodiment in Fig. 2, no parity bit is calculated and stored as part of the write operation. However, the concurrent parity generation chain indicated by the parity logic units 45-47 of FIG. 3 corresponds directly to the concurrent parity chain 27 indicated by the parity logic units 28-30 of FIG.

3, the output of the last component 47 of the concurrent parity chain is detected by a transition detector 48 configured to detect any change in this value and output an error detection signal when such a change is detected . The set of data storage units 41-44 of FIG. 3 corresponds to a particular row (row 0) of the data storage device, and this data storage device includes additional rows of such data storage units ). Writing to a particular row of such a data storage device is possible when the corresponding "write enable" signal for this row is asserted (and those skilled in the art are familiar with the use of this write enable signal, ). 3, transition detector 48 is also coupled to the write enable signal line, which is coupled in reverse to the enable input of transition detector 48. [ This configuration ensures that transition detection is not possible during the recording process. However, when these rows are not being recorded, the transition detector is activated. Thus, any change in state of this row due to an error can then be captured by the transition detector 48. This embodiment of FIG. 3 has advantages in the required layout area, as compared to the embodiment shown in FIG. 2, because the additional XOR tree and parity storage units (member numbers 25 and 26, respectively, . However, a feature of the embodiment shown in FIG. 3 is that these rows are more vulnerable than during the write cycle. This is because the reference parity bit (such as that stored in the parity bit storage unit 26 of FIG. 2) is not part of the embodiment of FIG. 3 and there is a possibility that a change that occurs during the recording process is not present. However, considering that in many cases the write process is relatively infrequent and the subsequent read process is relatively much more frequent, such risk can be determined to be at an acceptable low level. Similar to the active comparator circuit 31 shown in FIG. 2, the transition detector 48 is configured to be switched only when the value of its input (from the parity logic unit 47) is changed.

4A and 4B are diagrams illustrating the operation of the associated data storage unit 23 and associated parity generation logic 29 or data storage unit 43 and its associated parity generation logic 46 of FIG. And schematically illustrates two embodiments of separate data storage units with parity generation logic. 4A schematically shows a data storage unit implemented as a flip-flop. When such a flip-flop is provided as a data storage unit in a register file implemented in RTL (register-transfer level), such register file can be synthesized by a synthesis tool using, for example, a flip- Logic can also be implemented in RTL. Alternatively, the parity detection logic (XOR gate in this example) may be provided in the flip-flop itself and the register file may be implemented by placement and routing techniques. Providing the XOR logic in the flip-flop is especially possible when a double-height flip-flop cell is used. Figure 4b schematically shows an example where the data storage unit is provided in an on-demand bit cell based register file design.

Figures 5A and 5B schematically illustrate two alternative embodiments for providing concurrent parity detection logic. In Fig. 5A, a separate parity detection unit (XOR gate 60) is provided as a linear concatenation or chain. In contrast, FIG. 5B shows that a pair of individual data storage units 61 are compared at the lowest level of the hierarchical tree and combined together in an iterative process to generate a final parity bit for the data word stored in the data storage unit 61 Schematically illustrates the concurrent parity generation logic arranged as a hierarchical tree in which XOR gates 62 are arranged. The advantage of the tree structure shown in FIG. 5B is the reduced parity calculation latency for the linear concatenation shown in FIG. 5A despite the cost of the horizontal wiring.

Figure 6 schematically illustrates an embodiment in which the concurrent parity generation logic is arranged as a hierarchical tree, as shown in Figure 5B, in which the output of the XOR tree (gate) - flop (63). The scan flip 63 is configured to provide the output of the XOR tree (i.e., the parity bit) at its output in response to a scan-out signal (i.e., its scan clock input). This allows automatic test pattern generation (ATPG) data words to be written (in parallel) to a separate data storage unit 61 (in the example shown, such data storage unit 61 is able to write 8- Storage location), the XOR tree 62 may observe each of the flip flops 61 of the register file. There is no need to scan the register file flipflops 61 throughout the scan chain by adding observation check points (scan flops 63) at the end of the XOR tree 62. [ A standard ATPG can be used, for example, to test a register flip flop 61 by applying a first pattern in parallel to a register file and then applying a second pattern to a register file in parallel. An exact response to the flip bits between subsequent patterns can be observed in the scan output of the scan flip-flop 63 to inspect the register file. Thus, a slightly increased area can improve the checking capability of the register file, and a significant number of scan flip-flops (as compared to the normal scheme in which a chain of scan flip-flops is associated with each individual data storage unit 61 one by one) Can be reduced.

Figure 7 schematically shows a data word 64 in which parity computation can be performed on all lesser data words. This is illustrated in FIG. 7 by the sub-parity bit A generated based on the four most significant bits of the data word 64 and the sub-parity bit B generated based on the four least significant bits of the data word 64. In some embodiments, both subparity bits A and B are generated to provide a full coverage for monitoring the data word 64 for errors and to provide a reduced coverage for a single parity bit generated for the entire data word 64 Parity calculation wait time because a smaller number of bits are combined to produce each sub parity bit. This, of course, is made up of the cost of the additional logic required to compute the two subparity bits, as opposed to a single parity bit. Instead, only one of the two sub-parity bits shown in FIG. 7, for example, only sub-parity bit A may be generated. This may be beneficial for situations in which only a portion of the data word 64 requires monitoring of the occurrence of an error, the remainder being less important and errors occurring in this portion being negligible.

Figure 8 schematically shows a register file 70 that is configured to store a plurality of data words 71. For example, in the embodiment shown in Figure 8, this is a 128 word register file, The data word 71 is an 8-bit word. This register file 70 is a multiport register file having nine write ports and fourteen read ports. Parity logic 72 associated with a storage unit provided for storage of each data word 71 so that a parity bit for a given stored data word is not generated each time a stored data word is read, It may be particularly advantageous to configure it according to the present technique. The concurrent parity generation circuit 72 of FIG. 8 is shown only schematically and may be provided in more detail in accordance with the embodiment shown in FIG. 2 or FIG.

("Error flag") such that the error flag is asserted if an error is detected by one of the parity logic units 72 for one of the stored data words 71 73 are provided with the output of each concurrent parity logic unit 72. This, in turn, notifies the generation of the error almost instantly and the appropriate corrective action can be taken quickly. Combining logic 73 may be provided by, for example, a tree of OR gates to combine these outputs into a single output. It should be noted that a single output to the combinational logic 73 is also provided in the "sticky" This sticky error register is configured to maintain a value indicating a "no error" state until at least one of the outputs of each parity logic unit 72 changes, thereby causing the "sticky" To maintain a value indicating an "error" state that will be maintained despite an additional change in the received input value until reset. It should be noted that alternatively, the output of each parity logic unit 72 may be provided directly to a "sticky" Because the change in the parity bit generated by any parity logic unit 72 can be used to cause the " sticky "error register 74 to maintain its" error " Thus, this sticky error register 74 can be monitored by, for example, a polling process to identify when an error has occurred. In the embodiment shown in FIG. 8, the system is configured to respond to an error flag (or an error state maintained by register 74) by causing the entire contents of register file 70 to be refreshed when such an error occurs. Thus, in this embodiment it is more efficient to simply identify where to rewrite the contents of each stored data word 71 than to identify where the specific error occurred and take a corrective action for that particular storage location .

Figure 9 schematically shows a series of steps taken in the method of one embodiment. In a first step 100, a write (e.g., by identifying a particular row in a register file in which such a data word is to be written and asserting an enable signal for that row) to write the data word to the selected storage location Process is performed. As part of the write process, in step 101 parity bits are generated via the XOR tree and stored in association with the data word. Then, as indicated in step 102, a state is set in which the XOR connection (simultaneous parity generation circuit) coupled to this storage location and the active comparison circuit are switched only when a bit flip occurs in the stored data word. While this bit flip does not occur in the data word ("No" path from step 103), it is determined in step 104 whether this data word is to be read. If it is a data word to be read, the flow proceeds through step 105 (and in particular it should be noted that this has no effect on the XOR connection or the active comparator circuit) where the data word is read from its storage location. The flow then proceeds to step 102 again. Alternatively, if no reading is performed ("No" path from step 104), the flow directly returns to step 102. However, when the bit flip occurs in the data word ("Yes" path from step 103), this bit flip causes the parity change to spread through the XOR connection (step 106) and, in step 107, The detected parity change is displayed.

While specific embodiments of the invention have been described herein, it will be appreciated that the invention is not so limited and many modifications and additions may be possible within the scope of the invention. For example, various combinations with the features of the independent claims of the following dependent claims may be possible without departing from the scope of the present invention.

Claims (17)

As an apparatus,
A plurality of storage units configured to receive data and output the data in response to a read access; And
And a parity generator associated with the plurality of storage units,
Receive each value from each of said plurality of storage units at a plurality of inputs;
Determine a parity value from the plurality of input units;
Wherein the determination of the parity value is independent of a read access to data stored in the plurality of storage units,
Wherein the apparatus further comprises a detector configured to detect a change in the parity value. 2. The apparatus of claim 1, wherein the detector is one of a transition detector and an active comparator. 2. The apparatus of claim 1, further comprising a second parity generator configured to generate a second parity value associated with the data when the data is received by the plurality of storage units. 4. The apparatus of claim 3, wherein the second parity value is stored in an additional storage unit associated with the plurality of storage units when the data is stored by the plurality of storage units;
And the second parity value is read from the additional storage unit by the detector for comparison with the parity value to detect a change in the parity value. The apparatus of claim 3, wherein the parity generator is configured to generate the parity value after the second parity generator generates the second parity value. 2. The memory device of claim 1, further comprising a write enable signal line configured to transmit a write enable signal asserted when the data word is being written to the plurality of data storage units, And wherein the detector is disabled when the write enable signal is asserted. 2. The apparatus of claim 1, wherein the apparatus is a multiport register file including a plurality of read ports from which the plurality of storage units can be read. 2. The apparatus of claim 1, wherein the parity generator comprises a linear concatenated logic circuit provided in association with the plurality of storage units, each logic circuit having a respective data bit of each storage unit as one of its inputs Lt; / RTI > 2. The apparatus of claim 1, wherein the parity generator comprises a hierarchical tree of logic circuits,
The logic circuit of the lowest level of the hierarchical tree having as its input each data bit of each pair of storage units,
Wherein the logic circuit at the highest level of the hierarchical tree generates a parity bit as its input. The apparatus of claim 9, further comprising a scan unit configured to receive a parity value output from a highest level of the hierarchical tree and output the parity value in a scan output unit of a scan unit in response to a scan- . 2. The apparatus of claim 1, wherein the parity generator is configured to generate sub-parity bits according to less than all of the data stored in the plurality of storage units. 12. The apparatus of claim 11, wherein the parity generator is configured to generate a plurality of sub parity bits for data stored in the plurality of storage units. 12. The apparatus of claim 11, wherein the parity generator is configured such that at least one data bit stored in the plurality of storage units does not affect the value of the sub parity bit. 2. The apparatus of claim 1, wherein the apparatus is configured to store a plurality of data words, the parity generator being configured to generate respective parity bits for each of the data words,
Further comprising: a combinational logic circuit configured to generate an error flag when any one of the respective parity bits changes in value. 2. The apparatus of claim 1, wherein the apparatus is configured to store a plurality of data words, the parity generator being configured to generate respective parity bits for each of the data words,
And an error register configured to maintain a non-error value or an error value, wherein the error register is configured to switch to maintaining the error value if at least one value of the respective parity bits is changed. Storing data in a plurality of data storage units;
Outputting the data from the plurality of storage units in response to a read access;
Receiving a value from each of the plurality of storage units at each of a plurality of inputs of a parity generator associated with the plurality of storage units;
Determining a parity value from the plurality of input units;
Outputting the first parity value; And
Detecting a change in the output parity by an active comparator,
Wherein the determination of the parity value is independent of the read access to the data stored in the plurality of storage units. Means for storing data in a plurality of data storage units;
Means for outputting the data from the plurality of storage units in response to a read access;
Means for receiving a value from each of the plurality of storage units at each of a plurality of inputs of a means for generating a parity value associated with the plurality of storage units, The means being configured to generate a parity value that is independent of the read access to the data stored in the plurality of storage units;
Means for outputting the first parity value; And
And means for detecting a change in the output parity.

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