KR20150144035A - Apparatus and method for manufacturing a power semiconductor device - Google Patents
Apparatus and method for manufacturing a power semiconductor device Download PDFInfo
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- KR20150144035A KR20150144035A KR1020140072631A KR20140072631A KR20150144035A KR 20150144035 A KR20150144035 A KR 20150144035A KR 1020140072631 A KR1020140072631 A KR 1020140072631A KR 20140072631 A KR20140072631 A KR 20140072631A KR 20150144035 A KR20150144035 A KR 20150144035A
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- oxide film
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- igbt
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- 238000000034 method Methods 0.000 title claims abstract description 54
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title description 19
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 229910052751 metal Inorganic materials 0.000 claims abstract description 26
- 239000002184 metal Substances 0.000 claims abstract description 26
- 238000000227 grinding Methods 0.000 claims abstract description 5
- 239000010410 layer Substances 0.000 claims description 59
- 229920002120 photoresistant polymer Polymers 0.000 claims description 33
- 238000005468 ion implantation Methods 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 15
- 229920005591 polysilicon Polymers 0.000 claims description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 239000011229 interlayer Substances 0.000 claims description 7
- 238000009792 diffusion process Methods 0.000 claims description 6
- 238000010030 laminating Methods 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 238000007517 polishing process Methods 0.000 claims 1
- 238000010438 heat treatment Methods 0.000 description 7
- 239000000047 product Substances 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 230000007261 regionalization Effects 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 239000007888 film coating Substances 0.000 description 1
- 238000009501 film coating Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/326—Application of electric currents or fields, e.g. for electroforming
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
The present invention uses a p + substrate as a collector of an IGBT as a power semiconductor device for replacing a part of an IGBT with a power MOSFET in order to improve operating characteristics, which is a disadvantage of an IGBT, to form an IGBT and a power MOSFET as parallel heaters on the same semiconductor substrate The n + buried layer is formed as the drain of the power MOSFET and connected together with the rear metal electrode. The collector region of the IGBT and the drain region of the power MOSFET are formed in advance on the substrate, and the substrate thinned by grinding proceeds only in the rear portion metal process, minimizing the problem of breakage of the substrate and having excellent thermal characteristics as a thinned substrate. In addition, since all processes can be processed using general semiconductor equipment, they have cost competitiveness by minimizing additional investment. Further, since the IGBT and the power MOSFET are formed in one guard ring, the size of the chip can be reduced.
Description
The present invention relates to a power semiconductor device and a manufacturing method thereof, and more particularly, to a power semiconductor device and a manufacturing method thereof. More particularly, the present invention relates to a power semiconductor device and a manufacturing method thereof. IGBTs and power MOSFETs are packaged together in a single product for fast operation speed, which is the advantage of power MOSFETs in IGBTs. In order to reduce costs, the IGBT collector And a power MOSFET and a manufacturing method of a power semiconductor device for manufacturing a thin-thickness device for excellent heat-generating characteristics.
In the power semiconductor device and the manufacturing method thereof, the power MOSFET has a high operating speed, but the current driving capability is relatively low. Use the CollMOS or Super-Junction MOSFET to complement the drive capability. However, it is relatively difficult to manufacture and the cost is much higher. In addition, the IGBT has superior driving capability, but the operating speed is relatively slow.
1 is a cross-sectional view of an IGBT according to an embodiment of the present invention. This is commonly referred to as RCIGBT (Reverse Conducting Insulated Gate Bipolar Transistor).
RCIGBT is the same as creating two devices inside a guard ring simultaneously with IGBT and power MOSFET. The RCIGBT is made by forming the source and gate of the power MOSFET on the substrate of the low concentration epitaxial layer, completing the metal on the front part, grinding the rear part to thin the substrate, and forming the drain area of the power MOSFET and the collector area of the IGBT (LASER) by a heat treatment method for a sufficient drive while preventing photoresist film coating, pattern formation process, ion implantation, removal of a photoresist film, and melting of a front surface metal. Special protective equipment shall be used for the processing of thin substrates in the backside machining. In addition, in the heat treatment process after forming the drain and collector regions having a high concentration, the front surface portion is made of aluminum, and the heat treatment process should proceed at a temperature of 600 ° C or less or a limited heat treatment process such as laser heat treatment so as to prevent melting of the front surface metal. As a result, it costs a lot of money by using devices that require expensive operating costs. On the other hand, since the thickness of the device is much thinner than that of arranging two devices in parallel, the heat-releasing characteristic is superior to the case of arranging two devices of IGBT and a freewheeling diode. Also, since the reflow diode does not operate when turned on, but the power MOSFET also operates when turned on, thereby exhibiting excellent turn-on operation characteristics. In addition, the method of arranging the IGBT and the freewheeling diode in parallel requires the guard ring region separately at the outermost part in order to obtain the withstand voltage of each device. Therefore, RCIGBT, in which the IGBT and the power MOSFET are built in one guard ring (Reverse Conducting Insulated Gate Bipolar Transistor) has a relatively small total device size. At this time, the area of the guard ring becomes wider as the internal pressure increases, and a few hundred microns to several millimeters may be used.
As a result, although RCIGBT is excellent in thermal characteristics and operating characteristics, it is expensive to manufacture, and a method of arranging IGBTs and freewheeling diodes in parallel is not difficult in manufacturing, but has poor thermal characteristics and operating characteristics.
The present invention has been made in view of the above problems, and it is an object of the present invention to provide a method of manufacturing a semiconductor device, in which a substrate is thinned in a RCIGBT in which a power MOSFET is embedded in an IGBT and a thin substrate is formed, and a drain region of the power MOSFET and a collector region of the IGBT are coated, (LASER) heat treatment process and a back metal process for a sufficient drive while preventing injection, removal of the photoresist film and melting of the front side metal. As a result of such a process, the substrate easily breaks down and causes a rise in cost. In addition, production is almost impossible in a typical semiconductor manufacturing plant.
On the other hand, in order to arrange the two devices in parallel in the IGBT and the freewheeling diode, since the guard ring region is separately required at the outermost region to obtain the breakdown voltage of each device, the size of the whole device is increased, It is relatively high in heat characteristic and requires additional internal wiring at the time of packaging. This can lead to reliability problems.
In order to compensate for the above disadvantages, the IGBT and the power MOSFET are mounted in parallel on a single chip, the process progress in a thin substrate state is minimized to reduce the breakdown, thereby improving the heating characteristic, the operating speed, And a method of manufacturing the same.
According to an aspect of the present invention, there is provided a power semiconductor device for forming an IGBT and a power MOSFET in parallel on the same semiconductor substrate, comprising: growing an initial oxide film on a P + silicon substrate; Applying a first photoresist; Etching the initial oxide film; Removing the first photoresist film; Forming an N + buried layer; Driving the N + buried layer; Removing the initial oxide film; Growing an N buffer epitaxial layer; Growing an N-epitaxial layer: forming a field oxide film; Applying a second photoresist; Forming a trench pattern; Etching the field oxide film; Trenching the silicon; Removing the second photoresist film; Growing a sacrificial oxide film; Removing the sacrificial oxide film; Growing a gate oxide film; Depositing doped polysilicon; Forming a polysilicon gate doped with polysilicon; Applying a third photoresist; Forming an active pattern; etching the field oxide film; Removing the third photoresist layer; Forming a pad oxide film; Performing P-body ion implantation; Driving the P-body; Applying a fourth photosensitive film; Forming an N + source pattern; performing N + source ion implantation; Removing the fourth photosensitive film; Applying a fifth photosensitive film; Forming a P + source pattern; performing P + source ion implantation; Removing the fifth photosensitive film; Laminating an interlayer insulating film; Applying a sixth photosensitive film; Forming a contact pattern; etching the interlayer insulating film by contact etching; Removing the sixth photosensitive film; Stacking a metal layer; Applying a seventh photosensitive film; Forming a front side metal pattern; etching the front side metal by metal etching; Removing the seventh photosensitive film; Grinding the back surface of the substrate; And laminating the rear surface metal on the surface of the substrate.
Preferably, the diffusion formed concentration of the N + buried layer is higher than that of the P + silicon substrate.
Preferably, the P + buried layer (collector of the IGBT) region and the N + buried layer (drain of the power MOSFET) region can be formed by replacing the P + heavily doped substrate with a substrate of low concentration.
Preferably, the P + collector region and the N + drain region can be formed by adjusting the area ratio to match the electrical characteristics.
Preferably, the P + collector region and the N + drain region can be formed by an ion implantation method instead of an impurity doping method
Preferably, it is not possible to use an N buffer epitaxial layer.
Preferably, the P + collector region and the N + drain region are formed by the above methods and other methods including the source region (emitter of IGBT) and N-drain (base of IGBT) and gate of the power MOSFET It can be formed by changing the structure.
According to the power semiconductor device and the manufacturing method of the present invention, since the IGBT and the power MOSFET are mounted on a single chip in parallel, when the ratio of the two devices and the chip size are appropriately selected, the power driving capability, the operating speed, By utilizing the advantages of the two devices, such as the characteristics, it is possible to manufacture cost-competitive products. On the other hand, RCIGBT, which has excellent heat dissipation characteristics, can be manufactured at a semiconductor factory that produces general power device products without the need to invest expensive special equipment. As a result, it will be possible to expand the market by mass-producing and supplying high-performance products such as RCIGBT at relatively low prices.
1 is a cross-sectional view of an RCIGBT according to an embodiment of the present invention.
2 is an embodiment of a power semiconductor device according to the present invention.
3A to 3L are cross-sectional process diagrams for explaining a method of manufacturing a power semiconductor device in which an IGBT and a power MOSFET according to an embodiment of the present invention are mounted on a single chip in parallel.
Hereinafter, a method of manufacturing a power semiconductor device in which an IGBT and a power MOSFET according to an embodiment of the present invention are mounted on one chip in parallel is described in detail with reference to the drawings.
2 is an embodiment of a power semiconductor device according to the present invention.
2, an N + source 316, a P + source 318, a P-body 314, a
Hereinafter, an embodiment of a power semiconductor device according to an embodiment of the present invention will be described in detail with reference to FIGS. 3A to 3L. The same reference numerals are given to the components having the same configurations and functions as those in Fig.
Referring to FIG. 3A, an initial oxide film 302 is grown on a P + collector silicon substrate 301, and then a first photoresist layer (not shown) is formed and photolithography is performed to form an N + buried layer pattern. Next, the initial oxide film 302 is etched using the first photoresist film as a mask. Then, the first photosensitive film is removed. Subsequently, the N + buried layer is deposited. Next, the doped high concentration N + drain region 303 is diffused into the drive-in process. The high concentration N + drain region 303 here becomes the N + drain region of the power MOSFET, and the P + silicon substrate 301 becomes the P + collector region of the IGBT. The ratio of the N + drain region of the power MOSFET to the P + collector region of the IGBT is determined by the desired characteristics of the final product. The initial oxide film preferably has a thickness of 200 ANGSTROM or more in order to sufficiently prevent the N + drain region from diffusing into the P + collector region. It is also preferable that the drive phosphor has a temperature range of 1000 캜 or higher. It is also possible to conduct the N + drain region by the ion implantation method instead of the doping (POCL3) method.
Referring to FIG. 3B, the N-buffer epitaxial layer 304 and the N-epitaxial layer 305 are successively grown on the upper oxide film 302 after the initial oxide film 302 is completely removed. Next, a field oxide film 306 is formed on the upper part and a trench pattern is formed after the second photoresist film 307 is applied. The open field oxide layer is then etched and the trenches 308 etched with silicon. Here, the N buffer epitaxial layer and the N-epitaxial layer determine the concentration (resistivity) and thickness depending on the characteristics of the power MOSFET and the IGBT. Preferably, the N buffer epitaxial layer has a resistivity of 1? -Cm or less and a thickness of 1 占 퐉 or more, and the N-epitaxial layer has a resistivity of 1 ㏀ -cm or less and a thickness of 5 占 퐉 or more. The thickness of the field oxide film varies depending on the subsequent process and has a thickness of about 500 ANGSTROM or more. Also, the trench structure has a width of about 0.2 탆 to 5 탆 and a depth of 0.5 탆 to 10 탆, depending on the characteristics of the product. The N buffer epitaxial layer may optionally not be used.
Next, as shown in FIG. 3C, the second photoresist layer 307 is removed and the sacrificial oxide layer 309 is grown. Here, the sacrificial oxide film 307 preferably has a thickness of 100 Å to 3000 Å.
Subsequently, the sacrificial oxide film 309 is removed and a
After the
After the doped
Next, as shown in FIG. 3E, a third photoresist layer 312 is applied to define active and guard ring regions and an active pattern is formed.
Next, as shown in FIG. 3F, the remaining third photoresist layer 312 is etched using a wet etching method or a dry etching method using the masking medium as the field oxide layer 306. Next, the third photoresist layer 312 is removed and a pad oxide layer 313 is formed. The pad oxide film 313 preferably has a thickness of 100 ANGSTROM to 1000 ANGSTROM.
After the pad oxide film 313 is formed, ion implantation of the P-region 314 proceeds. When the ion implantation of the P-region 314 proceeds, the boron is preferably in the range of 1.0e13 to 1.0e14 atoms / cm2 at 30 KeV to 2 MeV.
After the ion implantation of the P-region 314 proceeds, the diffusion process proceeds. The diffusion process preferably ranges from 1050 ° C to 1200 ° C for 30 minutes to 6 hours.
Next, in FIG. 3G, a fourth photoresist layer 315 is applied and a pattern is formed to form a high concentration N.sup. + Source (emitter) region 316. Next, as shown in FIG. After the application of the fourth photoresist film 315, ion implantation proceeds to the N + source (emitter) region 316 through the opened region. The N + source (emitter) ion implantation region 316 is typically phosphorus of (Ph +) and acetic Nick (As +) for use in the ion source and the ion implantation is 3.0e15 ~ 1.0e16atoms / cm 2 with 60KeV ~ 180KeV . ≪ / RTI >
Referring to FIG. 3H, the fourth photoresist layer 315 is removed, and the fifth photoresist layer 317 is coated to form a pattern. After the fifth photoresist film 317 is applied, ion implantation proceeds to the P + source (emitter) region 318 through the opened region. Where a P + source (emitter) ion implantation is generally used a boron source (B + or Bf2 +) to the ion source and ion implantation region 318 is 30KeV ~ 1MeV to have a range of 5.0e14 ~ 1.0e16atoms / cm 2 desirable.
3I, the fifth photoresist layer 317 is removed and a first oxide layer 319, which is an interlayer insulating layer, is formed. The first oxide layer preferably has a thickness of 1000 Å to 3000 Å. The first oxide film 319 is an oxide film which is not doped with impurities.
After forming the first oxide film 319, boron phosphorous silica glass (BPSG) 320 is sequentially stacked. Preferably, the BPSG has a thickness of 5000 ANGSTROM to 15000 ANGSTROM.
Next, the BPSG flow process is performed for planarization. The BPSG flow process preferably has a condition of 850 to 1100 DEG C for about 30 minutes to 2 hours. Borophosphosilicate glass (BPSG) 320 may also be used as the phosphorus silica glass (PSG).
Next, referring to FIG. 3J, a fifth photoresist layer 317 is removed and then a sixth photoresist layer (not shown) is formed to form a contact region 322 for connection between a source (emitter) 321) is applied, pattern formation and etching process are performed.
Referring to FIG. 3K, after the sixth photoresist layer 321 is removed, a front photoresist layer (not shown) is formed on the front photoresist layer 323 to form a front surface metal layer. It is also possible to use Ti or TiN as an interlayer metal in order to improve the contact resistance at the time of connection with the silicon permanent magnet. The thickness of the front part metal has a thickness of 1 탆 to 6 탆 according to the wiring material or method in the subsequent package.
Next, in FIG. 3L, the seventh photosensitive film (not shown) is removed, and then the rear surface metal 324 is laminated to form a rear electrode, thereby completing the process. The rear-side electrode is in common contact with the collector region 301 of the IGBT and the drain region 303 of the power MOSFET.
While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the scope of the present invention.
301: P + substrate, collector of IGBT 303: N + buried layer, drain of power MOSFET
304: N buffer layer, N buried layer, drain of power MOSFET, N base of IGBT
305: N-epitaxial layer buffer layer, N-drain of power MOSFET, N-base of IGBT
306: field oxide film 310: gate oxide film
311: gate 314: P-body, guard ring
316: N + source, N + emitter 318: P + source, P + emitter
319, 320: interlayer insulating film 323: front part metal
324: rear portion metal
Claims (17)
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| Application Number | Priority Date | Filing Date | Title |
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| KR1020140072631A KR20150144035A (en) | 2014-06-16 | 2014-06-16 | Apparatus and method for manufacturing a power semiconductor device |
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| KR1020140072631A KR20150144035A (en) | 2014-06-16 | 2014-06-16 | Apparatus and method for manufacturing a power semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111785777A (en) * | 2020-06-28 | 2020-10-16 | 上海华虹宏力半导体制造有限公司 | High voltage CMOS device and method of manufacturing the same |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111785777A (en) * | 2020-06-28 | 2020-10-16 | 上海华虹宏力半导体制造有限公司 | High voltage CMOS device and method of manufacturing the same |
| CN111785777B (en) * | 2020-06-28 | 2023-10-20 | 上海华虹宏力半导体制造有限公司 | High voltage CMOS device and method of manufacturing the same |
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