KR20150094655A - 고성능 패키지 온 패키지 - Google Patents

고성능 패키지 온 패키지 Download PDF

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Publication number
KR20150094655A
KR20150094655A KR1020157016960A KR20157016960A KR20150094655A KR 20150094655 A KR20150094655 A KR 20150094655A KR 1020157016960 A KR1020157016960 A KR 1020157016960A KR 20157016960 A KR20157016960 A KR 20157016960A KR 20150094655 A KR20150094655 A KR 20150094655A
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KR
South Korea
Prior art keywords
package
microelectronic
microelectronic elements
terminals
contacts
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Ceased
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KR1020157016960A
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English (en)
Korean (ko)
Inventor
일리야스 모하메드
벨가셈 하바
Original Assignee
인벤사스 코포레이션
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Publication of KR20150094655A publication Critical patent/KR20150094655A/ko
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H01L25/0652—
    • H01L23/13—
    • H01L23/3128—
    • H01L23/5389—
    • H01L25/0655—
    • H01L25/105—
    • H01L25/18—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/865—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/24—Configurations of stacked chips at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
KR1020157016960A 2012-12-10 2013-12-10 고성능 패키지 온 패키지 Ceased KR20150094655A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/709,723 2012-12-10
US13/709,723 US9165906B2 (en) 2012-12-10 2012-12-10 High performance package on package
PCT/US2013/074079 WO2014093317A1 (en) 2012-12-10 2013-12-10 High performance package on package

Publications (1)

Publication Number Publication Date
KR20150094655A true KR20150094655A (ko) 2015-08-19

Family

ID=49885423

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020157016960A Ceased KR20150094655A (ko) 2012-12-10 2013-12-10 고성능 패키지 온 패키지

Country Status (7)

Country Link
US (1) US9165906B2 (https=)
EP (1) EP2929561B1 (https=)
JP (1) JP6276781B2 (https=)
KR (1) KR20150094655A (https=)
CN (1) CN104937716B (https=)
TW (1) TWI523178B (https=)
WO (1) WO2014093317A1 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018125411A1 (en) * 2016-12-28 2018-07-05 Intel Corporation Methods of forming package structures for enhanced memory capacity and structures formed thereby

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US9123555B2 (en) * 2013-10-25 2015-09-01 Invensas Corporation Co-support for XFD packaging
US9443780B2 (en) * 2014-09-05 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having recessed edges and method of manufacture
US10847469B2 (en) * 2016-04-26 2020-11-24 Cubic Corporation CTE compensation for wafer-level and chip-scale packages and assemblies
WO2017039628A1 (en) * 2015-08-31 2017-03-09 Daniel Sobieski Inorganic interposer for multi-chip packaging
US9871007B2 (en) * 2015-09-25 2018-01-16 Intel Corporation Packaged integrated circuit device with cantilever structure
US10438877B1 (en) * 2018-03-13 2019-10-08 Semiconductor Components Industries, Llc Multi-chip packages with stabilized die pads

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US5679977A (en) 1990-09-24 1997-10-21 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
US5148266A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies having interposer and flexible lead
US5148265A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies with fan-in leads
US6177636B1 (en) 1994-12-29 2001-01-23 Tessera, Inc. Connection components with posts
US6665194B1 (en) * 2000-11-09 2003-12-16 International Business Machines Corporation Chip package having connectors on at least two sides
KR101166575B1 (ko) 2002-09-17 2012-07-18 스태츠 칩팩, 엘티디. 적층형 패키지들 간 도선연결에 의한 상호연결을 이용한반도체 멀티-패키지 모듈 및 그 제작 방법
JP2007324354A (ja) * 2006-05-31 2007-12-13 Sony Corp 半導体装置
US9941245B2 (en) 2007-09-25 2018-04-10 Intel Corporation Integrated circuit packages including high density bump-less build up layers and a lesser density core or coreless substrate
JP5081578B2 (ja) * 2007-10-25 2012-11-28 ローム株式会社 樹脂封止型半導体装置
TW200945545A (en) 2007-12-12 2009-11-01 United Test & Assembly Ct Lt Package-on-package semiconductor structure
US8354742B2 (en) * 2008-03-31 2013-01-15 Stats Chippac, Ltd. Method and apparatus for a package having multiple stacked die
FR2938976A1 (fr) 2008-11-24 2010-05-28 St Microelectronics Grenoble Dispositif semi-conducteur a composants empiles
US20100133682A1 (en) * 2008-12-02 2010-06-03 Infineon Technologies Ag Semiconductor device
US8455300B2 (en) 2010-05-25 2013-06-04 Stats Chippac Ltd. Integrated circuit package system with embedded die superstructure and method of manufacture thereof
KR101061531B1 (ko) * 2010-12-17 2011-09-01 테세라 리써치 엘엘씨 중앙 콘택을 구비하며 접지 또는 배전을 개선한 적층형 마이크로전자 조립체
US9171792B2 (en) * 2011-02-28 2015-10-27 Advanced Semiconductor Engineering, Inc. Semiconductor device packages having a side-by-side device arrangement and stacking functionality
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US9117811B2 (en) 2011-06-13 2015-08-25 Tessera, Inc. Flip chip assembly and process with sintering material on metal bumps
KR20130005465A (ko) * 2011-07-06 2013-01-16 삼성전자주식회사 반도체 스택 패키지 장치
US8436457B2 (en) * 2011-10-03 2013-05-07 Invensas Corporation Stub minimization for multi-die wirebond assemblies with parallel windows

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018125411A1 (en) * 2016-12-28 2018-07-05 Intel Corporation Methods of forming package structures for enhanced memory capacity and structures formed thereby
US10177161B2 (en) 2016-12-28 2019-01-08 Intel Corporation Methods of forming package structures for enhanced memory capacity and structures formed thereby
US10734393B2 (en) 2016-12-28 2020-08-04 Intel Corporation Methods of forming package structures for enhanced memory capacity and structures formed thereby

Also Published As

Publication number Publication date
US20140159248A1 (en) 2014-06-12
EP2929561B1 (en) 2019-09-04
US9165906B2 (en) 2015-10-20
EP2929561A1 (en) 2015-10-14
WO2014093317A1 (en) 2014-06-19
CN104937716B (zh) 2018-06-19
CN104937716A (zh) 2015-09-23
JP6276781B2 (ja) 2018-02-07
TW201426940A (zh) 2014-07-01
TWI523178B (zh) 2016-02-21
JP2015537393A (ja) 2015-12-24

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