KR20150068723A - Liquid Crystal Display Apparatus and Method for Manufacturing The Same - Google Patents

Abstract

According to one aspect of the present invention, a liquid crystal display apparatus which can reduce a number of masks required for manufacturing a lower substrate comprises: a gate electrode formed on a thin film transistor area on a substrate, and a first common electrode formed on a pixel area; a gate insulation film formed on the entire substrate including the gate electrode and the first common electrode; a source electrode and a drain electrode formed on the gate insulation film; a pixel electrode formed on the gate insulation film in the pixel area; a protective film formed on the entire substrate including the pixel electrode; and a second common electrode formed on the protective film.

Description

TECHNICAL FIELD [0001] The present invention relates to a liquid crystal display device and a manufacturing method of a liquid crystal display device,

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a method of manufacturing a liquid crystal display device in which the number of masks necessary for a manufacturing process of a liquid crystal display device is reduced.

Of the flat panel display apparatuses, liquid crystal display apparatuses are expanding in application fields due to the development of mass production technology, ease of driving means, low power consumption, high image quality, and large screen realization.

1A to 1G are process cross-sectional views illustrating a manufacturing process of a lower substrate constituting a general liquid crystal display device.

1A, a gate electrode 20 and a common electrode line 21 are formed on a substrate 10 using a first mask, and then a gate electrode 20 and a common electrode line 21 are formed as shown in FIG. A gate insulating film 25 is formed on the entire surface of the substrate including the common electrode wiring 21.

Next, a material layer (not shown) and a source / drain electrode layer (not shown) for forming an active layer are sequentially stacked on the entire surface of the substrate including the gate electrode 20 and the connecting electrode 21, The active layer 30, the source electrode 62, and the drain electrode 64 are formed by patterning the material layer and the source / drain electrode layer for the active layer formation using a second mask (halftone mask) as shown in FIG.

In this way, the gate electrode 20, the active layer 30, the source electrode 62, and the drain electrode 64 constitute a thin film transistor (TFT).

1D, the first passivation layer 70 and the planarization layer 80 are formed on the substrate including the source electrode 62 and the drain electrode 64. Then, the first passivation layer 70 and the planarization layer 80 are planarized The hole H1 and the hole H2 are formed by patterning the layer 80 and the hole H3 is formed by patterning the gate insulating film 25 and the first protective film 70 using the fourth mask. At this time, the holes H1 and H3 constitute the first contact hole CH1, and a part of the common electrode line 21 is exposed to the outside through the first contact hole CH1. In one embodiment, the planarization layer 80 may be formed using Photo Acryl.

Next, as shown in Fig. 1E, a common electrode 90 is pattern-formed on the planarization layer 80 by using a fifth mask. At this time, the common electrode 90 is electrically connected to the common electrode line 21 through the first contact hole CH1.

Next, as shown in FIG. 1F, a second protective film 92 is formed on the entire surface of the substrate including the common electrode 90, and then a first protective film 70 and a second protective film 92 Is patterned to form a hole H4. At this time, the hole H2 and the hole H4 constitute the second contact hole CH2, and a part of the drain electrode 64 is exposed to the outside through the second contact hole CH2.

Next, as shown in FIG. 1G, the pixel electrode 94 is pattern-formed on the second protective film 92 by using the seventh mask. In one embodiment, the pixel electrode 94 is patterned in the form of a finger. The pixel electrode 94 and the drain electrode 64 are contacted through the second contact hole, and a data voltage input through a data line (not shown) is supplied to the pixel region.

In the case of the above-described liquid crystal display device, a lower substrate was manufactured through a 7-mask process as shown in the table of FIG. The reason why the lower substrate is manufactured through the 7 mask process in the general liquid crystal display device is to sufficiently secure the storage capacitance Cst which maintains the charged state of the pixel in the high resolution model (for example, QHD class).

More specifically, since the pixel size becomes smaller (for example, 200 ppi or higher) in a high-resolution model, the absolute area for securing the storage capacitance Cst for maintaining the charged state of the pixel becomes smaller, so that the storage capacitance can be secured It is necessary to reduce the distance between the pixel electrode and the common electrode. However, if the distance between the pixel electrode and the common electrode is reduced to secure the storage capacitance, it becomes impossible to secure the charging characteristic due to an increase in load. Therefore, in the case of a general liquid crystal display device, The mask process is used.

As described above, in the general liquid crystal display device, since the 7-mask process is used for manufacturing the lower substrate, the productivity is lowered and the manufacturing cost is increased.

In addition, since a gate line and a common electrode line are formed on the same layer in a general liquid crystal display device, the gap between the gate line and the common electrode line must be ensured, and the aperture ratio is lowered.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a liquid crystal display device and a method of manufacturing a liquid crystal display device which can reduce the number of masks required for manufacturing a lower substrate.

It is another object of the present invention to provide a liquid crystal display device and a method of manufacturing a liquid crystal display device capable of improving the aperture ratio.

According to an aspect of the present invention, there is provided a liquid crystal display device including: a first common electrode formed on a gate electrode and a pixel region formed in a thin film transistor region on a substrate; A gate insulating film formed on the entire surface of the substrate including the gate electrode and the first common electrode; A source electrode and a drain electrode formed on the gate insulating film; A pixel electrode formed on the gate insulating film in the pixel region; A protective layer formed on the entire surface of the substrate including the pixel electrode; And a second common electrode formed on the protective film.

According to another aspect of the present invention, there is provided a method of manufacturing a liquid crystal display device including patterning a gate electrode, a first common electrode, and a common electrode line on a substrate including a thin film transistor region and a pixel region step; Forming a gate insulating film on the entire surface of the substrate including the gate electrode, the first common electrode, and the common electrode line; Sequentially forming a material layer for forming an active layer and a source / drain electrode layer for forming a source / drain electrode on the entire surface of the substrate; Patterning the material layer and the source and drain electrode layer simultaneously using a halftone mask to form an active layer, a source electrode, and a drain electrode in the thin film transistor region; Forming a pixel electrode in the pixel region; Forming a protective layer on the entire surface of the substrate including the pixel electrode; And patterning the second common electrode on the protective film.

As described above, according to the present invention, since the lower substrate of the liquid crystal display device can be manufactured through the 5-mask process, the productivity can be improved, and the manufacturing cost of the liquid crystal display device can be reduced.

In addition, according to the present invention, a separate planarization layer for securing the storage capacitance is not required, so that the transmittance of the liquid crystal display device can be improved.

According to the present invention, since the drain electrode and the pixel electrode are directly in contact with each other, a separate contact hole for contact between the drain electrode and the pixel electrode is not required, so that the reduction of the pixel area due to the contact hole is minimized, Can be improved.

In addition, according to the present invention, it is possible to secure a sufficient storage capacitance while manufacturing a lower substrate of a high-resolution model liquid crystal display device through a 5 mask process, thereby preventing occurrence of image quality defects such as cross talk and afterimage .

In addition, according to the present invention, since the common electrode line is formed by stacking the first conductive film for forming the first common electrode and the second conductive film for forming the gate electrode, the aperture ratio can be improved, The image quality of the display device can be improved.

1A to 1G are process cross-sectional views illustrating a process of manufacturing a lower substrate of a general liquid crystal display device.
2 is a table showing the number of masks required for manufacturing the lower substrate shown in Fig.
3 is a cross-sectional view showing the structure of a lower substrate of a liquid crystal display device according to an embodiment of the present invention;
4 is a view showing a configuration of an overall storage capacitance in a lower substrate of a liquid crystal display device according to the present invention.
5A to 5G are cross-sectional views illustrating a process of manufacturing a lower substrate of a liquid crystal display device according to an embodiment of the present invention.
6 is a table showing the number of masks required for manufacturing the lower substrate shown in Fig.

Hereinafter, a liquid crystal display device and a method of manufacturing the same according to embodiments of the present invention will be described with reference to the accompanying drawings.

In describing embodiments of the present invention, when it is described that a structure (electrode, line, layer, contact) is formed over or on another structure, and below or below the substrate, It should be interpreted to include the case where a third structure is interposed between these structures as well as when they are in contact with each other.

The terms " above or above " and " below or below " are intended to illustrate the liquid crystal display device of the present invention and a method of manufacturing the same, based on the drawings. Accordingly, the terms 'above' or 'above' and 'below or below' may be different from each other in the structure of the liquid crystal display device after the manufacturing process and manufacture are completed.

Before describing the contents of the present invention in detail, a method of adjusting the liquid crystal layer arrangement of the liquid crystal display device and a general configuration of the liquid crystal display device will be briefly described.

The twisted nematic (TN) mode, the VA (Vertical Alignment) mode, the IPS (In Plane Switching) mode and the FFS (Fringe Field Switching) mode are examples of a method of controlling the arrangement of the liquid crystal layer in the liquid crystal display device.

In the IPS mode and the FFS mode, a pixel electrode and a common electrode are disposed on a lower substrate to adjust the alignment of the liquid crystal layer by an electric field between the pixel electrode and the common electrode.

In the IPS mode, a pixel electrode and a common electrode are alternately arranged in parallel so that a horizontal electric field is generated between both electrodes to adjust the alignment of the liquid crystal layer. In the IPS mode, the alignment of the liquid crystal layer is not adjusted in the upper portion of the pixel electrode and the common electrode, so that the transmittance of light is reduced in the corresponding region.

The FFS mode is designed to solve the shortcomings of the IPS mode. In the FFS mode, a pixel electrode and a common electrode are formed so as to be spaced apart with an insulating layer therebetween. At this time, one electrode is formed in a plate shape or a pattern, and the other electrode is formed in a finger shape, and the alignment of the liquid crystal layer is controlled through a fringe field generated between the electrodes Method.

It is assumed that the liquid crystal display device according to the embodiments of the present invention described below has a structure of the FFS mode.

A liquid crystal display device having various liquid crystal layer alignment methods as described above generally includes a liquid crystal panel, a back light unit for supplying light to the liquid crystal panel, and a driving circuit.

The liquid crystal panel includes a lower substrate (TFT array substrate) on which a plurality of pixels are formed, an upper substrate (color filter array substrate) on which color filters are formed to correspond to a plurality of pixels, and a liquid crystal layer interposed between the lower substrate and the upper substrate .

The backlight unit supplies light generated in the light source to the liquid crystal panel, and may include a plurality of light sources (LED or CCFL) for generating light to be illuminated on the liquid crystal panel, and a plurality of optical members for improving light efficiency.

The driving circuit section includes a timing controller (T-con), a data driver (D-IC), a gate driver (G-IC), a backlight driving section and a power supply section for supplying driving power to the driving circuit.

All or part of the driving circuit portion may be formed on the liquid crystal panel by COG (Chip On Glass) or COF (Chip On Flexible Printed Circuit) method.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

<Liquid Crystal Display Device>

3 is a cross-sectional view illustrating the structure of a lower substrate of a liquid crystal display device according to an embodiment of the present invention. In FIG. 3, for convenience of explanation, the illustration of the gate link, the gate pad, and the data pad area is omitted.

On the lower substrate, a plurality of data lines (not shown) and a plurality of gate lines (not shown) are formed so as to intersect each other, and a plurality of pixel regions are defined by a plurality of data lines and a plurality of gate lines formed so as to cross each other . Each pixel region is defined as one pixel. At this time, a thin film transistor (TFT) is formed in a region where a plurality of data lines and a plurality of gate lines cross each other (thin film transistor region). 3, the structure of the lower substrate will be described with reference to one pixel among the plurality of pixels for convenience of explanation.

3, a gate electrode 312, a first common electrode 314, and a common electrode line 316 are formed on a substrate 300 in a lower substrate of a liquid crystal display device according to an embodiment of the present invention. Is formed. The substrate 300 may be made of glass or transparent plastic.

The gate electrode 312 may be formed of a double conductive film. Specifically, the first conductive film 318 formed on the substrate 300 is formed using a transparent metal material, and the second conductive film 319 formed on the first conductive film 318 is formed using a low resistance metal Or may be formed using a material. In one embodiment, the transparent metal material forming the first conductive film 318 may be indium-tin-oxide (ITO). In addition, the low resistance metal material forming the second conductive film 319 may be copper (Cu). Here, the low-resistance material means a metallic material whose resistance value is lower than a predetermined reference value.

The first common electrode 314 is formed in the form of a plate on the substrate 300 and is formed in a plate shape on the substrate 300 except for the TFT region, that is, on the substrate 300 . The first common electrode 314 and the pixel electrode 346 constitute the first storage capacitance Cst1 with the gate insulating layer 320 interposed therebetween.

Here, the storage capacitance Cst serves to keep the voltage applied to the liquid crystal constant until the next signal is received.

In one embodiment, the first common electrode 314 may be formed in a single process using a halftone mask (HTM) and a gate electrode 312 formed of a double conductive film as described above. According to this embodiment, the first common electrode 314 is formed using the same material as the first conductive film 318 constituting the gate electrode 312.

A predetermined region of the first common electrode 314 is exposed to the outside through the contact hole CH.

The common electrode line 316 is for applying a common voltage to the first and second common electrodes 314 and 360 and may be formed on the substrate 300 in parallel with the gate line. In one embodiment, the common electrode line 316 may be formed through a single process with the gate electrode 312 and the first common electrode 314 using a halftone mask.

According to this embodiment, the common electrode line 316 may be formed in the same shape as the gate electrode 312 formed in the double conductive film structure. That is, the common electrode line 316 may be formed by stacking a second conductive film 319 of a low-resistance metal material on the first conductive film 318 constituting the first common electrode 314. Accordingly, the first common electrode 314 is directly connected to the common electrode line 316 including the low-resistance metal material without a separate contact hole, thereby reducing the resistance of the first common electrode 314 do.

A gate insulating layer 320 is formed on the entire surface of the substrate including the gate electrode 312, the first common electrode 314, and the common electrode line 316. The gate insulating film 320 is formed on the entire surface of the substrate except for the contact hole CH region and the pad region (not shown). The gate insulating layer 320 may be formed of a silicon nitride (SiNx) or a silicon oxide (SiOx) material.

An active layer 330 is patterned on the gate insulating layer 320. The active layer 330 is formed in the TFT region and may be formed of a silicon-based semiconductor material or an oxide semiconductor material.

On the active layer 330, a source electrode 342, a drain electrode 344, and a pixel electrode 346 are patterned. The source electrode 342 and the drain electrode 344 are formed in the TFT region. The source electrode 342 is connected to the data line and the drain electrode 344 is spaced from the source electrode 342 while facing the source electrode 342.

The gate electrode 312, the active layer 330, the source electrode 342, and the drain electrode 344 constitute a thin film transistor TFT.

The pixel electrode 346 is formed in the pixel region. In one embodiment, the pixel electrode 346 is formed on the pixel region to be in direct contact with the drain electrode 344. The pixel electrode 346 may be formed using a transparent metal material such as indium-tin-oxide (ITO). Accordingly, in the liquid crystal display device according to the present invention, since the contact hole, which is essentially required for electrically connecting the drain electrode and the pixel electrode in a general liquid crystal display device, is not required, the area of the pixel region can be increased, The aperture ratio and transmittance of the region can be increased.

A protective film 350 is formed on the source electrode 342, the drain electrode 344, and the pixel electrode 346. The protective film 350 is formed on the entire surface of the substrate except for the contact hole CH region and the pad region (not shown). The protective film 350 may be made of an inorganic insulating material such as silicon nitride or silicon oxide.

At this time, the contact hole CH may be formed by etching a predetermined region of the gate insulating film 320 and the protective film 350.

A second common electrode 360 is formed on the passivation layer 350. The second common electrode 360 may be formed of the same material as the first common electrode 314. That is, the second common electrode 360 may be formed of a transparent metal material such as indium-tin-oxide. In one embodiment, the second common electrode 360 includes slits or is formed to have a finger shape. Accordingly, a fringe field is formed between the pixel electrode 346 and the second common electrode 360.

The second common electrode 360 is electrically connected to the first common electrode 314 through the contact hole CH so that the common electrode line 316 directly connected to the first common electrode 314 Voltage is applied.

Since the first common electrode 314 is formed under the pixel electrode 346 in addition to the second common electrode 360 formed on the pixel electrode 346 in the present invention, (346) and the first storage capacitance (Cst1).

4, the first storage capacitance Cst1 formed between the first common electrode 314 and the pixel electrode 346, the first storage capacitance Cst1 formed between the pixel electrode 346 and the second common electrode 360 The second storage capacitance Cst2 is connected in parallel, so that the total storage capacitance Cst is increased as compared with the prior art.

As described above, in the case of the lower substrate of the liquid crystal display device according to the present invention, sufficient storage capacitance is secured to prevent occurrence of image quality defects such as cross talk and afterimage, It is possible to reduce the stability and the flicker. In addition, in the case of the lower substrate of the liquid crystal display device according to the present invention, since a separate planarization layer (PAC) is not required for securing the storage capacitance, the decrease in transmittance caused by the thick planarization layer can be eliminated.

<Manufacturing Method of Liquid Crystal Display Device>

Hereinafter, a method of manufacturing the liquid crystal display device according to the present invention will be described with reference to FIGS. 5 to 6. FIG.

5A to 5G are schematic cross-sectional views of a lower substrate of a liquid crystal display device according to an embodiment of the present invention. 5A to 5G, the illustration of the gate link, the gate pad, and the data pad area is omitted for convenience of explanation.

5A, a first conductive layer 318 and a second conductive layer 319 are sequentially formed on a substrate 300. Then, as shown in FIG. 5B, the first conductive layer 318 and the second conductive layer 319 are sequentially patterned using a halftone mask, The film 318 and the second conductive film 319 are patterned to form the gate electrode 312, the first common electrode 314, and the common electrode line 316. [ The gate electrode 312 is formed in the TFT region and the first common electrode 314 is formed in the pixel region.

More specifically, both the first conductive film 318 and the second conductive film 319 remain in the gate electrode 312 and the common electrode line 316, and the first common electrode 314 is electrically connected to the first conductive film The first conductive film 318 and the second conductive film 319 are removed except for the gate electrode 312, the first common electrode 314 and the common electrode line 316 The first conductive film 318 and the second conductive film 319 are patterned using a halftone mask. At this time, the first conductive layer 318 and the second conductive layer 319 are patterned so that the first conductive layer 318 and the second conductive layer 319 are left in the pad region (not shown).

5C, a gate insulating layer 320, an active layer forming material 520, and a source / drain electrode layer 320 are formed on the gate electrode 312, the first common electrode 314, and the common electrode line 316, (522) are sequentially formed.

5D, the active layer forming material 520 and the source / drain electrode layer 522 are patterned using a halftone mask to form the active layer 330, the source electrode 342, and the drain electrode 344 ). That is, the active layer 330, the source electrode 342, and the drain electrode 344 are formed through one process.

At this time, the active layer 330 is patterned to be formed on the gate electrode 312 in the TFT region, and the source electrode 342 and the drain electrode 344 are pattern-formed so as to be spaced apart from each other on the active layer 330.

The gate electrode 312, the active layer 330, the source electrode 342, and the drain electrode 344 constitute a thin film transistor TFT.

Next, as shown in FIG. 5E, the pixel electrode 346 is pattern-formed in the pixel region. In one embodiment, the pixel electrode 346 is patterned to directly contact the drain electrode 344. As described above, since the pixel electrode 346 directly contacts the drain electrode 344 without a separate contact hole, the area of the pixel region can be increased, and the aperture ratio and transmittance of the pixel region can be increased.

As described above, in the present invention, the pixel electrode 346 constitutes the first common electrode 314 and the first storage capacitance Cst1 with the gate insulating film 320 interposed therebetween.

5F, the protective layer 350 of the pixel electrode 346 is formed and a predetermined region of the gate insulating layer 320 and the protective layer 350 is patterned to expose the first common electrode 314 to the outside And is etched to form a contact hole CH.

5G, the second common electrode 360 is patterned by using a transparent conductive material such as indium-tin-oxide (ITO) on the passivation layer 350. Next, as shown in FIG. In one embodiment, the second common electrode 360 may include a slit or be patterned to have a finger shape. Accordingly, a fringe field is formed between the pixel electrode 346 and the second common electrode 360.

Since the second common electrode 360 is formed on the pixel electrode 346 in addition to the first common electrode 314 formed under the pixel electrode 346 in the present invention, (346) and the second storage capacitance (Cst2).

Therefore, in the present invention, the first storage capacitance Cst1 formed between the first common electrode 314 and the pixel electrode 346, the second storage capacitance Cst2 formed between the pixel electrode 346 and the second common electrode 360, Since the storage capacitance Cst2 is connected in parallel, the total storage capacitance Cst increases as described in Equation (1) above. Accordingly, it is possible to prevent the occurrence of image quality defects such as crosstalk and afterimage due to the sufficient storage capacitance, and to stabilize gray scale display and reduce flicker.

6, a gate electrode 312, a first common electrode 314, and a common electrode line 316 are formed through a first mask process (HTM) using a halftone mask, as shown in FIG. A source electrode 342 and a drain electrode 344 are formed through a second mask process using a halftone mask HTM and the pixel electrode 346 is formed through a third mask process And the second common electrode 360 is formed through the fifth mask process to form the lower substrate of the liquid crystal display device through the fifth mask process, The number of masks can be reduced as compared with a process of manufacturing a lower substrate of a liquid crystal display device, thereby improving productivity and manufacturing cost.

In addition, since the present invention does not require a separate planarization layer (PAC) in order to secure storage capacitance, it is possible to prevent a decrease in transmittance caused by a thick planarization layer.

It will be understood by those skilled in the art that the present invention can be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

300: substrate 312: gate electrode
314: first common electrode 316: common electrode line
320: gate insulating film 330: active layer
342: source electrode 344: drain electrode
346: pixel electrode 350: protective film
360: second common electrode

Claims (10)

A first common electrode formed in a pixel region and a gate electrode formed in a thin film transistor region on a substrate;
A gate insulating film formed on the entire surface of the substrate including the gate electrode and the first common electrode;
A source electrode and a drain electrode formed on the gate insulating film;
A pixel electrode formed on the gate insulating film in the pixel region;
A protective layer formed on the entire surface of the substrate including the pixel electrode; And
And a second common electrode formed on the protective film. The method according to claim 1,
The gate electrode and the first common electrode are formed on the same layer,
Wherein the gate electrode comprises: a first conductive layer formed on the substrate and made of a transparent conductive material; And a second conductive film formed on the first conductive film and made of a low-resistance metal material having a resistance value equal to or lower than a predetermined reference value,
Wherein the first common electrode comprises the first conductive film. The method according to claim 1,
And the pixel electrode is formed to be directly connected to the drain electrode. The method according to claim 1,
Further comprising a common electrode line formed on the same layer as the gate electrode and the first common electrode,
The common electrode line may include: a first conductive layer formed on the substrate and made of a transparent conductive material; And a second conductive film formed on the first conductive film and made of a low-resistance metal material having a resistance value equal to or less than a predetermined reference value,
Wherein the first conductive film is directly connected to the first common electrode. The method according to claim 1,
Wherein the second common electrode is electrically connected to the first common electrode through a contact hole for exposing a predetermined region of the first common electrode to the outside. The method according to claim 1,
Wherein the second common electrode includes a plurality of slits or is formed in a finger shape. Patterning a gate electrode, a first common electrode, and a common electrode line on a substrate including a thin film transistor region and a pixel region;
Forming a gate insulating film on the entire surface of the substrate including the gate electrode, the first common electrode, and the common electrode line;
Sequentially forming a material layer for forming an active layer and a source / drain electrode layer for forming a source / drain electrode on the entire surface of the substrate;
Patterning the material layer and the source and drain electrode layer simultaneously using a halftone mask to form an active layer, a source electrode, and a drain electrode in the thin film transistor region;
Forming a pixel electrode in the pixel region;
Forming a protective layer on the entire surface of the substrate including the pixel electrode; And
And patterning the second common electrode on the protective film. 8. The method of claim 7,
The step of patterning the gate electrode, the first common electrode, and the common electrode line,
Forming a first conductive layer made of a transparent conductive material on the substrate;
Forming a second conductive film on the first conductive film, the second conductive film being made of a low-resistance metal material having a resistance value equal to or lower than a predetermined reference value; And
Patterning the first conductive film and the second conductive film simultaneously using a halftone mask to form the gate electrode composed of the first and second conductive films, the first common electrode composed of the first conductive film, And forming the common electrode line composed of the first and second conductive films. 8. The method of claim 7,
In the step of patterning the pixel electrodes,
Wherein the pixel electrode is pattern-formed so that the pixel electrode is directly connected to the drain electrode. The method according to claim 1,
After the step of forming the protective film,
Etching the predetermined region of the gate insulating film and the protective film to form a contact hole exposing a part of the first common electrode,
In the step of patterning the second common electrode,
Wherein the second common electrode is pattern-formed such that the second common electrode is electrically connected to the first common electrode through the contact hole.

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