KR20150067803A - Semiconductor package structure for improving efficiency of thermal emission and method for fabricating the same - Google Patents

Semiconductor package structure for improving efficiency of thermal emission and method for fabricating the same Download PDF

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KR20150067803A
KR20150067803A KR1020130152511A KR20130152511A KR20150067803A KR 20150067803 A KR20150067803 A KR 20150067803A KR 1020130152511 A KR1020130152511 A KR 1020130152511A KR 20130152511 A KR20130152511 A KR 20130152511A KR 20150067803 A KR20150067803 A KR 20150067803A
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semiconductor chip
semiconductor
chip die
semiconductor substrate
die
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강동희
정규익
마상윤
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앰코 테크놀로지 코리아 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/073—Apertured devices mounted on one or more rods passed through the apertures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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Abstract

In a method for manufacturing a semiconductor package structure according to the present invention, a penetration part for mounting semiconductor chip dies is formed in a semiconductor substrate. One among the semiconductor chip dies is bonded to another chip die by a flip chip method. After that, one among the bonded semiconductor chip dies is mounted through the penetration part. The others are connected to the semiconductor substrate by a wiring method. Therefore, a stacked semiconductor package is manufactured with a simplified method. Also, a semiconductor chip die located on a lower surface among the semiconductor chip dies bonded by a flip chip method is mounted on the penetration part of the semiconductor substrate to manufacture a package. Therefore, heat generated from the semiconductor chip die is easily discharged through the penetration part so heat dissipation efficiency can be improved.

Description

열방출 개선을 위한 반도체 패키지 구조 및 제조 방법{SEMICONDUCTOR PACKAGE STRUCTURE FOR IMPROVING EFFICIENCY OF THERMAL EMISSION AND METHOD FOR FABRICATING THE SAME} Technical Field [0001] The present invention relates to a semiconductor package structure for improving heat emission and a manufacturing method thereof. [0002]

본 발명은 반도체 패키지 구조에 관한 것으로, 특히 반도체 패키지 제조에 있어서, 반도체 기판에 반도체 칩 다이가 관통하여 장착되기 위한 관통부를 형성하고, 다수개 반도체 칩 다이 중 하나의 칩 다이를 다른 칩 다이에 플립 칩 방식으로 접합한 후, 접합된 다수개의 반도체 칩 다이 중 하나를 관통부를 통해 안착되도록 하고, 나머지 칩을 반도체 기판상에 배선 연결하는 방식으로 반도체 패키지를 제조함으로써 적층형 반도체 패키지의 공정을 보다 간략화하고 열방출 효과를 개선시킬 수 있도록 하는 열방출 개선을 위한 반도체 패키지 구조 및 제조 방법에 관한 것이다.
The present invention relates to a semiconductor package structure, and more particularly, to a semiconductor package structure in which a semiconductor chip is formed in a semiconductor substrate with a penetration portion through which the semiconductor chip die is to be inserted and a chip die of a plurality of semiconductor chip dies is flip- The semiconductor package is manufactured in such a manner that one of the plurality of semiconductor chip dies bonded together is seated through the through portion and the remaining chips are connected to the semiconductor substrate by wiring so as to simplify the process of the stacked semiconductor package And more particularly, to a semiconductor package structure and a manufacturing method for improving heat emission, which can improve the heat emission effect.

최근 들어, 전자기기의 소형화에 대응하여 전자기기에 탑재되는 반도체 부품의 고밀도화, 고집적화가 요구되고 있다. 이에 따라 반도체 칩의 칩 크기의 소형화가 요구되고 있으며, 작은 크기의 칩을 이용한 고집적도의 패키지에 대한 요구 또한 증가하고 있다.2. Description of the Related Art In recent years, in response to downsizing of electronic devices, there has been a demand for higher density and higher integration of semiconductor components mounted on electronic devices. Accordingly, there is a demand for downsizing the chip size of the semiconductor chip, and a demand for a highly integrated package using a small-sized chip is also increasing.

이와 같은 요구에 따른 패키징 방식의 하나로 다수의 반도체 칩 다이를 적층하여 형성시키는 패키지가 제안되고 있다.A package for stacking and forming a plurality of semiconductor chip dies as one of packaging methods according to such a demand has been proposed.

도 1은 종래 적층형 반도체 패키지의 단면을 도시한 것이다.1 shows a cross section of a conventional stacked semiconductor package.

도 1을 참조하면, 적층형 반도체 패키지에서는 마더 다이(mother die)인 제1 반도체 칩 다이(102)와 도터 다이(daughter die)인 제2 반도체 칩 다이(104)를 플립칩(flip chip) 방식으로 접합시킨 후, 제1 반도체 칩 다이(102)를 반도체 기판(substrate)(100)에 배선 연결하는 방식으로 접착시킴으로써 적층형 반도체 패키지를 제조하게 된다.Referring to FIG. 1, a first semiconductor chip die 102, which is a mother die, and a second semiconductor chip die 104, which is a daughter die, are formed by a flip chip method After the bonding, the first semiconductor chip die 102 is adhered to the semiconductor substrate 100 by wiring so as to manufacture a stacked semiconductor package.

그러나, 위와 같은 종래 적층형 반도체 패키지에서는 단순히 2개의 반도체 칩 다이(102, 104)를 먼저 접합시킨 후, 반도체 기판(100)상에 적층하는 구조로 형성하고 있어서, 반도체 패키지의 두께가 두꺼워지는 문제점이 있었다.However, in the conventional stacked semiconductor package as described above, the two semiconductor die dies 102 and 104 are first bonded together and then laminated on the semiconductor substrate 100, so that the thickness of the semiconductor package becomes thick there was.

또한, 반도체 기판(100) 상에 2개의 반도체 칩 다이(102, 104)를 적층시키고자 제2 반도체 칩 다이(104)에 대해서는 백그라인딩(back grinding)을 수행하는 추가의 공정이 필요하게 되어 공정이 복잡하고, 적층된 반도체 칩 다이의 구조에 따라 반도체 칩 다이에서 발생하는 열에 대한 열방출 효율도 저하되는 문제점이 있었다.
Further, an additional process of performing back grinding on the second semiconductor chip die 104 to stack the two semiconductor chip dies 102 and 104 on the semiconductor substrate 100 is required, There is a problem that the heat dissipation efficiency of heat generated in the semiconductor chip die is also lowered due to the structure of the complicated and stacked semiconductor chip die.

(특허문헌)(Patent Literature)

대한민국 공개특허번호 10-2008-0017372호(공개일 2008년 2월 26일)에는 칩간 접속부에 관한 기술이 개시되어 있다.
Korean Patent Publication No. 10-2008-0017372 (published on February 26, 2008) discloses a technique relating to a chip-to-chip connection.

따라서, 본 발명에서는 반도체 패키지 제조에 있어서, 반도체 기판에 반도체 칩 다이가 관통하여 장착되기 위한 관통부를 형성하고, 2개 반도체 칩 다이 중 하나의 칩 다이를 다른 칩 다이에 플립 칩 방식으로 접합한 후, 접합된 2개의 반도체 칩 다이 중 하나를 관통부를 통해 안착되도록 하고 나머지 칩을 반도체 기판상에 배선 연결하는 방식으로 반도체 패키지를 제조함으로써 적층형 반도체 패키지의 공정을 보다 간략화하고 열방출 효과를 개선시킬 수 있도록 하는 열방출 개선을 위한 반도체 패키지 구조 및 제조 방법을 제공하고자 한다.
Therefore, according to the present invention, in manufacturing a semiconductor package, a penetration portion for mounting the semiconductor chip die through the semiconductor substrate is formed, and one of the two semiconductor die dies is bonded to another chip die in a flip chip manner , It is possible to simplify the process of the stacked semiconductor package and improve the heat release effect by manufacturing the semiconductor package by placing one of the two bonded semiconductor chip dies through the through portion and wiring the remaining chips on the semiconductor substrate And to provide a semiconductor package structure and a manufacturing method for improving heat emission.

상술한 본 발명은 반도체 패키지 제조 방법으로서, 반도체 기판에 반도체 칩 다이가 관통하여 장착되기 위한 관통부를 형성시키는 단계와, 상기 관통부를 덮도록 제1 반도체 칩 다이를 상기 관통부의 상부에 위치시켜 상기 관통부 주변영역의 반도체 기판상에 접착시키는 단계와, 제2 반도체 칩 다이를 상기 반도체 기판상 상기 관통부를 통해 상기 제1 반도체 칩 다이에 접합시키는 단계를 포함한다.According to the present invention, there is provided a method of manufacturing a semiconductor package, comprising the steps of: forming a penetration portion through which a semiconductor chip die is inserted into a semiconductor substrate; placing the first semiconductor chip die on the penetration portion so as to cover the penetration portion; Bonding the second semiconductor chip die to the first semiconductor chip die through the penetration portion on the semiconductor substrate.

또한, 상기 제2 반도체 칩 다이의 하부면에는 메탈 스퍼터링을 수행하는 단계를 더 포함하는 것을 특징으로 한다.Further, the method may further include performing metal sputtering on a lower surface of the second semiconductor chip die.

또한, 상기 메탈 스퍼터링은, 상기 제2 반도체 칩 다이의 하부면에 대한 솔더링 공정을 위해 수행되는 것을 특징으로 한다.The metal sputtering is performed for the soldering process on the lower surface of the second semiconductor chip die.

또한, 상기 제2 반도체 칩 다이는, 상기 반도체 기판 외부로 기설정된 두께 범위내에서 돌출 형성되는 것을 특징으로 한다.Further, the second semiconductor chip die is protruded outside the semiconductor substrate within a predetermined thickness range.

또한, 본 발명은 반도체 패키지 구조로서, 반도체 칩 다이가 관통하여 장착되기 위한 관통부가 형성된 반도체 기판과, 상기 관통부의 한쪽 개구부를 덮으면서 상기 관통부 주변영역의 반도체 기판상에 접착되는 제1 반도체 칩 다이와, 상기 관통부의 다른쪽 개구부를 통해 상기 제1 반도체 칩 다이에 접합되어 상기 반도체 기판에 장착되는 제2 반도체 칩 다이를 포함한다.According to another aspect of the present invention, there is provided a semiconductor package structure, including: a semiconductor substrate having a through-hole formed therein for mounting the semiconductor chip die through the semiconductor substrate; and a first semiconductor chip bonded to the semiconductor substrate in the peripheral region of the through- And a second semiconductor chip die bonded to the first semiconductor chip die through the other opening of the penetration portion and mounted on the semiconductor substrate.

또한, 상기 제2 반도체 칩 다이의 하부면에는 메탈 스터터링을 수행되는 것을 특징으로 한다.In addition, metal stuttering is performed on the lower surface of the second semiconductor chip die.

또한, 상기 메탈 스퍼터링은, 상기 제2 반도체 칩 다이의 하부면에 대한 솔더링 공정을 위해 수행되는 것을 특징으로 한다.The metal sputtering is performed for the soldering process on the lower surface of the second semiconductor chip die.

또한, 상기 제2 반도체 칩 다이는, 상기 반도체 기판 외부로 기설정된 두께 범위내에서 돌출 형성되는 것을 특징으로 한다.
Further, the second semiconductor chip die is protruded outside the semiconductor substrate within a predetermined thickness range.

본 발명에 따르면 반도체 패키지 제조에 있어서, 반도체 기판에 반도체 칩 다이가 관통하여 장착되기 위한 관통부를 형성하고, 다수개 반도체 칩 다이 중 하나의 칩 다이를 다른 칩 다이에 플립 칩 방식으로 접합한 후, 접합된 다수개의 반도체 칩 다이 중 하나를 관통부를 통해 안착되도록 하고 나머지 칩을 반도체 기판상에 배선 연결하는 방식으로 반도체 패키지를 제조함으로써 적층형 반도체 패키지의 공정을 보다 간략화할 수 있는 이점이 있다. According to the present invention, in manufacturing a semiconductor package, a penetration portion for mounting a semiconductor chip die through the semiconductor substrate is formed, and one of the plurality of semiconductor chip dies is flip chip bonded to another chip die, There is an advantage that the process of the stacked semiconductor package can be simplified by manufacturing the semiconductor package by placing one of the plurality of semiconductor chip dies bonded through the through portion and wiring the remaining chips on the semiconductor substrate.

또한, 플립칩 방식으로 접합된 다수개의 반도체 칩 다이 중 하부면에 위치한 반도체 칩 다이를 반도체 기판상 관통부에 안착시켜 패키지를 제조함으로써 반도체 칩 다이로부터 발생되는 열이 관통부를 통해 보다 쉽게 방출될 수 있도록 하여 열방출 효과를 개선시킬 수 있는 이점이 있다.
Also, since the semiconductor chip die placed on the lower surface among the plurality of semiconductor chip dies joined by the flip chip method is placed on the penetration portion on the semiconductor substrate, the heat generated from the semiconductor chip die can be more easily discharged through the through- So that the heat radiation effect can be improved.

도 1은 종래 적층형 반도체 패키지 구조 단면도,
도 2a 내지 도 2c는 본 발명의 실시예에 따른 적층형 반도체 패키지 형성 공정 단면도,
도 3은 종래 일반적인 적층형 반도체 패키지들의 구조 단면도,
도 4는 본 발명의 실시예에 따른 반도체 기판상 관통부에 반도체 칩 다이를 형성한 적층형 반도체 패키지의 구조 단면도,
도 5는 종래 반도체 패키지 구조와 본 발명의 반도체 패키지 구조에서의 열방출 효율을 도시한 그래프 예시도.1 is a sectional view of a conventional stacked semiconductor package structure,
FIGS. 2A to 2C are sectional views of a process of forming a stacked semiconductor package according to an embodiment of the present invention,
3 is a structural cross-sectional view of a conventional stacked semiconductor package,
4 is a structural cross-sectional view of a stacked semiconductor package in which a semiconductor chip die is formed on a penetrating portion on a semiconductor substrate according to an embodiment of the present invention,
5 is a graph showing an example of a heat dissipation efficiency in a conventional semiconductor package structure and a semiconductor package structure of the present invention.

이하, 첨부된 도면을 참조하여 본 발명의 동작 원리를 상세히 설명한다. 하기에서 본 발명을 설명함에 있어서 공지 기능 또는 구성에 대한 구체적인 설명이 본 발명의 요지를 불필요하게 흐릴 수 있다고 판단되는 경우에는 그 상세한 설명을 생략할 것이다. 그리고 후술되는 용어들은 본 발명에서의 기능을 고려하여 정의된 용어들로서 이는 사용자, 운용자의 의도 또는 관례 등에 따라 달라질 수 있다. 그러므로 그 정의는 본 명세서 전반에 걸친 내용을 토대로 내려져야 할 것이다.Hereinafter, the operation principle of the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The following terms are defined in consideration of the functions of the present invention, and these may be changed according to the intention of the user, the operator, or the like. Therefore, the definition should be based on the contents throughout this specification.

도 2a 내지 도 2c는 본 발명의 실시예에 따른 열방출 개선을 위한 적층형 반도체 패키지 형성을 위한 공정 단면도를 도시한 것이다. 이하, 도 2a 내지 도 2c를 참조하여 본 발명의 적층형 반도체 패키지 형성 방법에 대해 상세히 설명하기로 한다.2A to 2C are cross-sectional views illustrating a process for forming a stacked semiconductor package for improving heat emission according to an embodiment of the present invention. Hereinafter, a method for forming a stacked semiconductor package of the present invention will be described in detail with reference to FIGS. 2A to 2C.

먼저, 도 2a에서 보여지는 바와 같이 다수의 반도체 칩 다이가 장착되는 반도체 기판에 예를 들어 플립칩 방식으로 접합된 2개의 반도체 칩 다이(도 2c에 도시됨) 중 하부면에 위치한 반도체 칩 다이가 반도체 기판(200)을 관통하여 장착될 수 있도록 하기 위한 관통부(202)를 형성시킨다. 이때, 본 발명에서는 이러한 관통부(202)에 반도체 칩 다이를 안착하여 적층형 반도체 패키지 구조를 형성함으로써, 반도체 기판(200)은 종래 적층형 반도체 패키지에서보다 상대적으로 얇게 형성될 수 있으며, 예를 들어 0.2 ∼ 0.6mm 두께 범위로 형성될 수 있다. First, as shown in FIG. 2A, a semiconductor chip die placed on the lower surface of two semiconductor chip dies (shown in FIG. 2C), for example, flip chip bonded to a semiconductor substrate on which a plurality of semiconductor die dies are mounted A penetrating portion 202 for allowing the semiconductor substrate 200 to penetrate through the semiconductor substrate 200 is formed. At this time, in the present invention, by forming the stacked semiconductor package structure by seating the semiconductor chip die on the penetration portion 202, the semiconductor substrate 200 can be formed relatively thinner than in the conventional stacked semiconductor package, for example, 0.2 To about 0.6 mm in thickness.

이어, 도 2b에서와 같이 반도체 기판(200)상 형성된 관통부(202)를 덮도록 마더 다이(mother die)인 제1 반도체 칩 다이(204)를 관통부(202)의 상부 중앙에 위치시킨 후, 제1 반도체 칩 다이(204)를 반도체 기판(200)상에 접착시킨다. 이때, 제1 반도체 칩 다이(204)는 솔더링(soldering)(206)을 통해 배선 연결될 수 있다.Next, as shown in FIG. 2B, the first semiconductor chip die 204, which is a mother die, is positioned at the upper center of the penetration portion 202 so as to cover the penetration portion 202 formed on the semiconductor substrate 200 , The first semiconductor chip die 204 is bonded onto the semiconductor substrate 200. At this time, the first semiconductor chip die 204 may be connected by wiring through a soldering 206.

그런 후, 도 2c에서와 같이 반도체 기판(200)상 관통부(202)를 덮도록 장착된 제1 반도체 칩 다이(204)의 하부면에 예를 들어 플립칩(flip chip) 방식으로 도터 다이(daughter die)인 제2 반도체 칩 다이(208)를 접합시킨다. 이때, 제2 반도체 칩 다이(208)는 반도체 기판(200)상 관통부(202)를 통해 제1 반도체 칩 다이(204)에 접합되며, 접합된 제2 반도체 칩 다이(208)는 관통부(202)를 통해 돌출된다.2C, the first semiconductor chip die 204 is mounted on the semiconductor substrate 200 so as to cover the penetration portion 202. The first semiconductor chip die 204 is mounted on the lower surface of the first semiconductor chip die 204 by, for example, a flip- the second semiconductor chip die 208 being a daughter die. At this time, the second semiconductor chip die 208 is bonded to the first semiconductor chip die 204 through the penetration portion 202 on the semiconductor substrate 200, and the bonded second semiconductor chip die 208 is bonded to the penetration portion 202, respectively.

이때, 위와 같은 관통부(202)는 반도체 기판(200)의 평면도를 도시한 참조번호 250에서 보여지는 바와 같이 예를 들어 사각형의 반도체 칩 다이 장착될 수 있도록 사각형의 관통부(202)로 형성될 수 있다. 또한, 마더 다이인 제1 반도체 칩 다이(204)의 크기 보다는 작고, 도터 다이인 제2 반도체 칩 다이(208)의 크기보다는 크게 형성되어 제2 반도체 칩 다이(208)는 관통부(202)를 통과할 수 있으며, 제1 반도체 칩 다이(204)는 관통부 주변의 반도체 기판(202)상에 접착될 수 있도록 한다.At this time, the penetration portion 202 may be formed as a rectangular penetration portion 202 so that the semiconductor chip 200 may be mounted on a semiconductor chip die, for example, as shown at 250 in a plan view of the semiconductor substrate 200 . The size of the second semiconductor chip die 208 is smaller than the size of the first semiconductor chip die 204 as the mother die and larger than the size of the second semiconductor chip die 208 as the daughter die, And the first semiconductor die 204 can be bonded onto the semiconductor substrate 202 around the perforations.

즉, 본 발명에서는 상술한 바와 같이 2개 반도체 칩 다이(204, 208) 중 하나의 칩 다이를 다른 칩 다이에 플립칩 방식으로 접합한 후, 접합된 2개의 반도체 칩 다이(204, 208) 중 하나를 관통부(202)를 통해 안착되도록 하고 나머지 반도체 칩 다이를 반도체 기판(200)상에 배선 연결하는 방식으로 반도체 패키지를 제조한다.That is, in the present invention, as described above, one of the two semiconductor die dies 204 and 208 is flip-chip bonded to another die die, and then the two semiconductor die dies 204 and 208 A semiconductor package is fabricated in such a manner that one is seated through the penetration portion 202 and the remaining semiconductor chip die is connected to the semiconductor substrate 200 by wiring.

이에 따라 적층된 2개의 반도체 칩 다이 중 하나를 관통부를 통해 안착되도록 하는 방식으로 반도체 패키지를 제조함으로써 관통부에 안착되는 반도체 칩 다이에 대한 백그라인딩(back grinding) 공정이 필요없게 되어 적층형 반도체 패키지의 공정을 보다 간략화 할 수 있다. 또한, 플립칩 방식으로 접합된 2개의 반도체 칩 다이 중 하부면에 위치한 반도체 칩 다이를 반도체 기판상 관통부에 안착시켜 패키지를 제조함으로써 적층된 반도체 칩 다이로부터 발생되는 열이 관통부를 통해 보다 쉽게 방출될 수 있도록 하여 열방출 효과를 개선시킬 수 있다.Thus, by manufacturing the semiconductor package in such a manner that one of the two stacked semiconductor chip dies is seated through the penetration portion, there is no need for a back grinding process for the semiconductor chip die that is seated in the penetration portion, The process can be simplified. In addition, a semiconductor chip die placed on a lower surface of two semiconductor chip dies joined by a flip chip method is placed on a penetration portion on a semiconductor substrate to manufacture a package, so that heat generated from the semiconductor chip die stacked through the through- So that the heat emission effect can be improved.

도 3은 종래 일반적인 적층형 반도체 패키지의 단면도를 도시한 것이고, 도 4는 본 발명의 실시예에 따른 반도체 기판상 관통부에 반도체 칩 다이를 형성한 적층형 반도체 패키지의 단면도를 도시한 것이다.FIG. 3 is a cross-sectional view of a conventional multi-layered semiconductor package, and FIG. 4 is a cross-sectional view of a multi-layered semiconductor package in which a semiconductor chip die is formed in a penetrating portion on a semiconductor substrate according to an embodiment of the present invention.

도 5는 위 도 3과 도 4에서 도시된 종래 반도체 패키지 구조에서의 열방출 효율과 본 발명의 관통부에 반도체 칩 다이를 형성한 적층형 반도체 패키지 구조에서의 열방출 효율을 도시한 그래프 예시도이다.5 is a graph illustrating heat dissipation efficiency in the conventional semiconductor package structure shown in FIGS. 3 and 4 and heat dissipation efficiency in a stacked semiconductor package structure in which a semiconductor chip die is formed in the penetration portion of the present invention .

위 도 5를 참조하면, 반도체 패키지별 열발생 그래프에서 보여지는 바와 같이 도 3에서와 같은 종래 일반적인 적층형 반도체 패키지 구조에서는 적층된 반도체 칩 다이로부터 발생되는 열이 높아 열방출 효율이 매우 낮을 것을 알 수 있다. 그러나, 도 4에서와 같은 본 발명의 적층형 반도체 패키지 구조에서는 적층된 반도체 칩 다이로부터 발생되는 열이 낮아 열방출 효율이 매우 높은 것을 알 수 있다.Referring to FIG. 5, as shown in the heat generation graph for each semiconductor package, it is seen that the heat generated from the stacked semiconductor chip dies is very low in the conventional stacked semiconductor package structure as shown in FIG. have. However, in the stacked semiconductor package structure of the present invention as shown in FIG. 4, the heat generated from the stacked semiconductor chip die is low and the heat dissipation efficiency is very high.

즉, 도 4에서와 같은 본 발명의 적층형 반도체 패키지 구조에서는 도터 다이(daughter die)인 반도체 칩 다이(208)가 반도체 기판(200)상 형성된 관통부에 안착된 후, 반도체 기판(200)상 하부로 돌출되도록 형성됨으로써, 적층된 반도체 칩 다이(208)로부터 발생된 열이 반도체 기판(200)상 형성된 관통부를 통해 보다 용이하게 방출될 수 있기 때문이다.4, the semiconductor chip die 208, which is a daughter die, is mounted on a penetrating portion formed on the semiconductor substrate 200, and then the semiconductor chip 200 is mounted on the semiconductor substrate 200 The heat generated from the stacked semiconductor chip die 208 can be more easily discharged through the penetration portion formed on the semiconductor substrate 200. [

상기한 바와 같이, 본 발명에 따르면 반도체 패키지 제조에 있어서, 반도체 기판에 반도체 칩 다이가 관통하여 장착되기 위한 관통부를 형성하고, 다수개 반도체 칩 다이 중 하나의 칩 다이를 다른 칩 다이에 플립 칩 방식으로 접합한 후, 접합된 다수개의 반도체 칩 다이 중 하나를 관통부를 통해 안착되도록 하고 나머지 칩을 반도체 기판상에 배선 연결하는 방식으로 반도체 패키지를 제조함으로써 적층형 반도체 패키지의 공정을 보다 간략화할 수 있다. 또한, 플립칩 방식으로 접합된 다수개의 반도체 칩 다이 중 하부면에 위치한 반도체 칩 다이를 반도체 기판상 관통부에 안착시켜 패키지를 제조함으로써 반도체 칩 다이로부터 발생되는 열이 관통부를 통해 보다 쉽게 방출될 수 있도록 하여 열방출 효과를 개선시킬 수 있다.As described above, according to the present invention, there is provided a method of manufacturing a semiconductor package, comprising: forming a penetration portion through which a semiconductor chip die is inserted into a semiconductor substrate; The process of the stacked semiconductor package can be simplified by manufacturing the semiconductor package by connecting one of the plurality of semiconductor chip dies bonded to each other through the penetration portion and connecting the remaining chips to the semiconductor substrate by wiring. Also, since the semiconductor chip die placed on the lower surface among the plurality of semiconductor chip dies joined by the flip chip method is placed on the penetration portion on the semiconductor substrate, the heat generated from the semiconductor chip die can be more easily discharged through the through- So that the heat emission effect can be improved.

한편 상술한 본 발명의 설명에서는 구체적인 실시예에 관해 설명하였으나, 여러 가지 변형이 본 발명의 범위에서 벗어나지 않고 실시될 수 있다. 따라서 발명의 범위는 설명된 실시 예에 의하여 정할 것이 아니고 특허청구범위에 의해 정하여져야 한다.
While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Accordingly, the scope of the invention should not be limited by the described embodiments but should be defined by the appended claims.

200 : 반도체 기판 202 : 관통부
204 : 제1 반도체 칩 다이 208 : 제2 반도체 칩 다이200: semiconductor substrate 202:
204: first semiconductor chip die 208: second semiconductor chip die

Claims (8)

반도체 기판에 반도체 칩 다이가 관통하여 장착되기 위한 관통부를 형성시키는 단계와,
상기 관통부를 덮도록 제1 반도체 칩 다이를 상기 관통부의 상부에 위치시켜 상기 관통부 주변영역의 반도체 기판상에 접착시키는 단계와,
제2 반도체 칩 다이를 상기 반도체 기판상 상기 관통부를 통해 상기 제1 반도체 칩 다이에 접합시키는 단계
를 포함하는 반도체 패키지 제조 방법.
Forming a penetrating portion for mounting the semiconductor chip die through the semiconductor substrate;
Positioning the first semiconductor chip die on the upper portion of the penetration portion so as to cover the penetration portion and adhering the first semiconductor chip die on the semiconductor substrate in the region around the penetration portion;
Bonding the second semiconductor chip die to the first semiconductor chip die through the penetration portion on the semiconductor substrate
≪ / RTI >
제 1 항에 있어서,
상기 제2 반도체 칩 다이의 하부면에는 메탈 스퍼터링을 수행하는 단계
를 더 포함하는 것을 특징으로 하는 반도체 패키지 제조 방법.
The method according to claim 1,
And performing metal sputtering on the lower surface of the second semiconductor chip die
≪ / RTI >
제 2 항에 있어서,
상기 메탈 스퍼터링은,
상기 제2 반도체 칩 다이의 하부면에 대한 솔더링 공정을 위해 수행되는 것을 특징으로 하는 반도체 패키지 제조 방법.
3. The method of claim 2,
In the metal sputtering,
Wherein the step of performing the soldering process is performed for a soldering process on the lower surface of the second semiconductor chip die.
제 1 항에 있어서,
상기 제2 반도체 칩 다이는,
상기 반도체 기판 외부로 기설정된 두께 범위내에서 돌출 형성되는 것을 특징으로 하는 반도체 패키지 제조 방법.
The method according to claim 1,
Wherein the second semiconductor chip die comprises:
Wherein the semiconductor substrate is protruded outside the semiconductor substrate within a predetermined thickness range.
반도체 칩 다이가 관통하여 장착되기 위한 관통부가 형성된 반도체 기판과,
상기 관통부의 한쪽 개구부를 덮으면서 상기 관통부 주변영역의 반도체 기판상에 접착되는 제1 반도체 칩 다이와,
상기 관통부의 다른쪽 개구부를 통해 상기 제1 반도체 칩 다이에 접합되어 상기 반도체 기판에 장착되는 제2 반도체 칩 다이
를 포함하는 반도체 패키지 구조.
A semiconductor substrate on which a penetration portion for allowing the semiconductor chip die to penetrate is mounted,
A first semiconductor chip die which is bonded onto the semiconductor substrate in the peripheral region of the penetration portion while covering one opening of the penetration portion,
And a second semiconductor chip die attached to the semiconductor substrate via the other opening of the penetration portion and bonded to the first semiconductor chip die,
And a semiconductor package.
제 5 항에 있어서,
상기 제2 반도체 칩 다이의 하부면에는 메탈 스터터링을 수행되는 것을 특징으로 하는 반도체 패키지 구조.
6. The method of claim 5,
Wherein a metal stator is formed on a lower surface of the second semiconductor chip die.
제 6 항에 있어서,
상기 메탈 스퍼터링은,
상기 제2 반도체 칩 다이의 하부면에 대한 솔더링 공정을 위해 수행되는 것을 특징으로 하는 반도체 패키지 구조.
The method according to claim 6,
In the metal sputtering,
Wherein the second semiconductor chip die is performed for a soldering process on a lower surface of the second semiconductor chip die.
제 5 항에 있어서,
상기 제2 반도체 칩 다이는,
상기 반도체 기판 외부로 기설정된 두께 범위내에서 돌출 형성되는 것을 특징으로 하는 반도체 패키지 구조.
6. The method of claim 5,
Wherein the second semiconductor chip die comprises:
Wherein the semiconductor substrate is protruded outside the semiconductor substrate within a predetermined thickness range.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111223853A (en) * 2018-11-23 2020-06-02 三星电子株式会社 Semiconductor package and method of manufacturing the same
KR20210017857A (en) * 2019-08-09 2021-02-17 삼성전기주식회사 Electronic component module and manufacturing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111223853A (en) * 2018-11-23 2020-06-02 三星电子株式会社 Semiconductor package and method of manufacturing the same
KR20210017857A (en) * 2019-08-09 2021-02-17 삼성전기주식회사 Electronic component module and manufacturing method thereof
US11191150B2 (en) 2019-08-09 2021-11-30 Samsung Electro-Mechanics Co., Ltd. Electronic component module and method for manufacturing the same

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