KR20150065489A - High voltage semiconductor device and manufacturing method thereof - Google Patents

High voltage semiconductor device and manufacturing method thereof Download PDF

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Publication number
KR20150065489A
KR20150065489A KR1020130150874A KR20130150874A KR20150065489A KR 20150065489 A KR20150065489 A KR 20150065489A KR 1020130150874 A KR1020130150874 A KR 1020130150874A KR 20130150874 A KR20130150874 A KR 20130150874A KR 20150065489 A KR20150065489 A KR 20150065489A
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South Korea
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column
layer
semiconductor layer
doping layer
concentration
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KR1020130150874A
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Korean (ko)
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김태완
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주식회사 케이이씨
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Priority to KR1020130150874A priority Critical patent/KR20150065489A/en
Publication of KR20150065489A publication Critical patent/KR20150065489A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

An embodiment of the present invention relates to a high voltage semiconductor device and a manufacturing method thereof. For this, an embodiment of the present invention discloses a high voltage semiconductor device which includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type which is formed on the first semiconductor layer; a column of the second conductivity type which is formed with a depth on the second semiconductor layer; a doping layer of the second conductivity type which is formed between a column and the second semiconductor layer; a well region of the second conductivity type which is formed on the upper part of the doping layer and the column; and a source region of the first conductivity type which is formed on the well region.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a high-voltage semiconductor device,

The present invention relates to a high-voltage semiconductor device and a manufacturing method thereof.

Generally, high voltage semiconductor devices such as power MOS field effect transistors (MOSFET) and insulated gate bipolar transistors (IGBT) have a source region and a drain region, respectively, on the upper surface and the lower surface of the semiconductor body. Further, the high-voltage semiconductor element has a gate insulating film on the upper surface of the semiconductor body adjacent to the source region and a gate electrode formed on the gate insulating film.

In the turn-on state of the high-voltage semiconductor device, the semiconductor body not only provides a conductive path to the drift current flowing from the drain region to the source region, but also provides a conductive path in the vertical direction Lt; RTI ID = 0.0 > depletion < / RTI > region. By the nature of the depletion region provided by the semiconductor body, the breakdown voltage of these high voltage semiconductor elements is determined.

In such a high-voltage semiconductor device, research is continued to reduce the resistance of the semiconductor body in the turn-on state, which provides a conductive path, in order to minimize the conduction loss occurring in the turn-on state and ensure a fast switching speed . It is generally known that by increasing the impurity concentration in the semiconductor body, the turn-on resistance of the semiconductor body can be reduced.

However, in the case of increasing the impurity concentration in the semiconductor body, there is a problem that the breakdown voltage is reduced by increasing the space charge in the semiconductor body.

Recently, in order to solve such a problem, a P-type conductive impurity region (hereinafter referred to as a P-type column layer) and an N-type conductivity A super junction structure in which an impurity region (hereinafter referred to as an N-type column layer) is alternately formed in the horizontal direction and the internal pressure is supported by a depletion layer extending from the junction of the P-type column layer and the N- Have been proposed.

In the case of such a high-voltage semiconductor device, it is necessary to always maintain a breakdown voltage generated when a reverse voltage is applied to increase reliability, and to control the concentration of an internal electric field for structural stability.

An embodiment of the present invention is to provide a high-voltage semiconductor device capable of increasing a breakdown voltage and a method of manufacturing the same.

A high-voltage semiconductor device according to an embodiment of the present invention includes: a first semiconductor layer of a first conductivity type; A second semiconductor layer of a first conductivity type formed on the first semiconductor layer; A second conductive type column formed at a predetermined depth in the second semiconductor layer; A second conductive type doping layer formed between the column and the second semiconductor layer; A well region of a second conductivity type formed on top of the column and the doping layer; And a source region of a first conductivity type formed in the well region.

The charge amount of the column may be equal to or greater than the charge amount of the second semiconductor layer.

The concentration of the impurities implanted into the column may be equal to or greater than the concentration of the impurities implanted into the doping layer.

The concentration of the impurity implanted into the doping layer may be 10% to 100% of the concentration of the impurity implanted into the column.

The sum of the charge amount of the doping layer and the charge amount of the column may be formed to be equal to or greater than the charge amount of the second semiconductor layer.

The column may be formed in the trench formed in the second semiconductor direction from the top of the second semiconductor layer.

The column and the second semiconductor layer may be alternately arranged in the horizontal direction on the first semiconductor layer.

The doping layer may be formed on the inner wall of the trench.

The doping layer may be formed on the inner wall of the trench in a tilt implant manner.

The width of the doped layer may be less than 50% of the width of the column.

According to another aspect of the present invention, there is provided a method of manufacturing a high-voltage semiconductor small-sized semiconductor device, including: a first step of forming a substrate and a semiconductor layer of a first conductivity type; A second step of forming a trench having a predetermined depth from the top of the semiconductor layer toward the substrate; A third step of forming a doping layer of a second conductivity type on the inner wall of the trench; A fourth step of forming a column by implanting an impurity of a second conductivity type on the doping layer in the trench; A fifth step of implanting impurities of a second conductivity type from an upper portion of the semiconductor layer to form a well region; And forming a source region by implanting an impurity of a first conductivity type into the well region.

In the third step, the doping layer may be formed on the inner wall of the trench by a tilt implant method.

The charge amount of the column may be equal to or greater than the charge amount of the semiconductor layer.

The concentration of the impurity in the column may be equal to or greater than the concentration of the impurity in the doping layer.

The concentration of the impurity in the doping layer may be 10% to 100% of the concentration of the impurity in the column.

The sum of the charge amount of the doping layer and the charge amount of the column may be formed to be equal to or greater than the charge amount of the second semiconductor layer.

The column and semiconductor layers may be alternately arranged in a horizontal direction on the substrate.

The width of the doped layer may be less than 50% of the width of the column.

According to the high-voltage semiconductor device and the method of manufacturing the same according to the embodiment of the present invention, by setting the charge amount of the column to be equal to the charge amount of the semiconductor layer or to be larger than the charge amount of the semiconductor layer, So that structural stability can be achieved.

According to an embodiment of the present invention, a doping layer is formed in the peripheral region of the column, and the concentration of the impurity implanted into the column is equal to or greater than the concentration of the impurity implanted into the doping layer, .

1 is a cross-sectional view illustrating a high-voltage semiconductor device according to an embodiment of the present invention.
FIG. 2A is a profile of the concentration shown along the line X-X 'in FIG.
FIG. 2B is a profile of the concentration shown along the line Y-Y 'in FIG.
FIG. 3A is a profile of electric field intensity along the line X-X 'in FIG.
FIG. 3B is a profile of electric field intensity along the line Y-Y 'in FIG.
3C is a profile of the electric field intensity obtained by enlarging the area A in FIG. 3B.
4 is a graph showing a breakdown voltage of a high-voltage semiconductor device according to an embodiment of the present invention.
5A to 5E are views illustrating a method of manufacturing a high-voltage semiconductor device according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the present invention.

FIG. 1 is a cross-sectional view showing a high-voltage semiconductor device according to an embodiment of the present invention, FIG. 2 is a profile of concentration along a line Y-Y 'in FIG. 1, FIG. 3B is a profile of the electric field intensity along the line Y-Y 'in FIG. 1, FIG. 3C is a profile of the electric field intensity enlarged in the region A in FIG. 3B, FIG. 3 is a graph showing breakdown voltage of a high-voltage semiconductor device according to an embodiment of the present invention. FIG.

1, a high-voltage semiconductor device 100 according to an exemplary embodiment of the present invention includes a substrate 110, a semiconductor layer 120, a doping layer 130, a column 140, a well region 150, A source region 160, a gate insulating layer 170, a gate electrode 180, and a source electrode 190.

The substrate 110 may correspond to a base layer for growing a semiconductor material and may be formed by implanting high-concentration Group 5 impurities such as phosphorus (P), arsenic (As), or antimony (Sb). The substrate 110 may be, for example, an n + type semiconductor substrate.

The semiconductor layer 120 is formed on the substrate 110. The semiconductor layer 120 may be formed on the substrate 110 by epitaxial growth. Accordingly, the semiconductor layer 120 may be an n-type semiconductor having a lower concentration than the substrate 110. The thickness of the semiconductor layer 120 may be, for example, 5 to 40 Ωm in resistivity and 15 to 50 袖 m in a semiconductor device of 400 to 800 V.

The doped layer 130 is formed on the inner wall of the trench 131 formed to have a certain depth in a direction from the upper portion to the lower portion of the semiconductor layer 120 after the semiconductor layer 120 is grown. Here, the trench 131 is formed along the direction from the inside of the semiconductor layer 120 to the substrate 110. The plurality of trenches 131 may be formed to be spaced apart from each other. Group III impurities such as boron (B), gallium (Ga), or indium (In) are formed on the inner wall of the trench 131 formed as described above, that is, the lower surface and both side surfaces of the doped layer 130 by a tilt implant method . This doping layer 130 is equal to or less than the concentration of impurities being injected into the column 140. That is, the doping layer 130 is heavily doped with impurities as compared with the column 140. Accordingly, the doping layer 130 may be a p-type semiconductor having a concentration equal to or lower than that of the column 140.

In addition, the width of the doping layer 130 is preferably 50% or less of the width of the column 140.

The column 140 may be formed on the doping layer 130 formed in the trench 131 by epitaxial growth under the atmosphere of a Group 3 impurity such as boron (B), gallium (Ga), or indium (In) And thus can be formed of a p-type semiconductor.

Here, the concentration of the impurity implanted into the column 140 is equal to the concentration of the impurity implanted into the doping layer 130 or greater than the concentration of the impurity implanted into the doping layer 130. Accordingly, the column 140 may be a p-type semiconductor or a p + -type semiconductor having a concentration equal to or greater than that of the doping layer 130.

The width of the column 140 is preferably at least twice the width of the doped layer 130.

In the high-voltage semiconductor device having the super junction structure as in the present invention, the charge amount Qp of the column 140 and the charge amount Qn of the semiconductor layer 120 are substantially the same (i.e., Qp? Qn The depletion layer formed along the column 140 and the semiconductor layer 120 expands to the entire column 140 and has a breakdown voltage magnitude proportional to the depletion layer width L D.

The sum of the charge amount Qp of the doping layer 130 and the charge amount Qp of the column 140 may be greater than or equal to the charge amount Qn of the semiconductor layer 120. As the amount of charge Qp of the doping layer 130 increases, the electric field formed between the two columns 140 in the semiconductor layer 120 is dispersed to both sides and the lower part through the doping layer 130. That is, the electric field formed between the sides of the column 140 can be reduced and dispersed by the doping layer 130. More specifically, in the absence of the doping layer 130, a maximum electric field is generated between the columns 140 on the side of the column 140. When the doping layer 130 is applied, The electric field is more biased and dispersed toward the substrate 110 than in the case where the doping layer 130 is not present, and the size of the electric field also decreases. As the electric field intensity decreases, the breakdown voltage necessary for reaching the critical electric field Ec also increases. When the position where the critical electric field is generated is dispersed and moved to the substrate 110 as a whole, (For example, a current and a voltage generated by a high electric field of an insulating film and electrodes). Therefore, the high-voltage semiconductor device 100 according to the embodiment of the present invention can be structurally stable.

Referring to FIGS. 2A and 2B, the doping concentration of the high-voltage semiconductor device 100 according to an embodiment of the present invention is shown by a dotted line. When the doping concentration is lower than the conventional structure (solid line) Lt; RTI ID = 0.0 > concentration. ≪ / RTI >

The concentration of the impurity implanted into the doping layer 130 may be 10% to 100% of the concentration of the impurity implanted into the column 140. If the concentration is 10% or more, it is possible to increase the magnitude of the breakdown voltage required to reach the critical electric field Ec by inducing the intensity of the electric field applied to the side of the column 140 to be weak, ) Can be stabilized. If the concentration of the impurity implanted into the doping layer 130 is limited to 100% or less, the breakdown voltage can not be satisfied because the Qp = Qn condition can not be satisfied and the high concentration diffusion The resistance value of the high-voltage semiconductor element 100 may be reduced during the turn-on operation due to the reduction in the width of the semiconductor layer 120.

Accordingly, the strength of the electric field applied to the side region of the column 140 through the doping layer 130 is weakened, thereby improving the structural stability of the high-voltage semiconductor device 100.

Referring to FIG. 3A, it can be seen that the intensity of the internal electric field is entirely decreased in the XX 'direction due to the presence of the doping layer 130.

Referring to FIGS. 3B and 3C, the threshold voltage (Ec, dotted line) of the high-voltage semiconductor device 100 according to the embodiment of the present invention is smaller than the conventional structure (solid line) in the YY ' In the doping layer 130 formed in the lower region of the column 140, particularly in the lower region of the column 140. It can be seen that the electric field is relatively more shifted to the doping layer 130 formed in the lower region than the doping layer 130 formed in the side region of the column 140. The critical electric field value Ec is a boundary condition of the critical electric field intensity at which a breakdown voltage is generated in the semiconductor substrate.

On the other hand, the calculation formula of the breakdown voltage for the high-voltage semiconductor element 100 is known as follows.

[Equation 1]

BV = E C * L D

Where BV is the breakdown voltage, E C is the magnitude of the electric field at the reverse voltage, and L D is the length of the column 140.

In Equation 1, the high-voltage semiconductor device 100 according to an embodiment of the present invention may have a sum of electric field intensities of the column 140 and the doping layer 130 with respect to E C. Therefore, the high-voltage semiconductor device 100 according to the embodiment of the present invention can increase the breakdown voltage by the sum of the electric field intensities of the increased column 140 and the doped layer 130, and the reliability of the device can be secured .

FIG. 4 is a graph showing a comparison between a breakdown voltage (dotted line) of a high-voltage semiconductor device 100 and a breakdown voltage (solid line) of an existing structure according to an embodiment of the present invention.

Referring to FIG. 4, it can be seen that the breakdown voltage of the high-voltage semiconductor device 100 according to the embodiment of the present invention is increased as in the calculation according to Equation (1).

The well region 140 may be formed by implanting a Group 3 impurity such as boron (B) so as to have a certain depth in the direction from the upper surface of the semiconductor layer 120 and the substrate 110 toward the substrate 110, . The well region 140 may be formed of a P-type semiconductor. The upper surface of the well region 140 is the same as the upper surface of the first conductive semiconductor layer 120.

The source region 160 is formed by implanting Group 5 impurities into a certain region of the well region 140 at a predetermined depth and then diffusing the dopant. The source region 160 may be formed of an n + type semiconductor.

The gate insulating layer 170 is formed between the well regions 150 and may be formed to cover the upper surface of the semiconductor layer 120. The gate insulating layer 170 may be formed of an oxide layer so as to expose at least a portion of the source region 160 so that the source electrode 190 may then form a contact with the source region 160 .

The gate electrode 180 is formed corresponding to the upper portion of the semiconductor layer 120. The gate 180 is formed on top of two adjacent well regions 140 with a gate insulating layer 170 therebetween. The gate electrode 180 may be formed of doped polysilicon.

The source electrode 190 is formed to cover the gate insulating layer 170 and the well region 150. The source electrode 190 forms a contact with the source region 160 so that the source electrode 190 and the source region 160 can be electrically connected.

5A to 5E are views illustrating a method of manufacturing a high-voltage semiconductor device according to an embodiment of the present invention.

5A, a trench 131 formed from the top of the semiconductor layer 120 is formed in a state in which the substrate 110 which is an n + type and the semiconductor layer 120 which is an n type are formed. Although the trenches 131 are illustrated at both edges of the semiconductor layer 120 in FIG. 5A, a plurality of trenches 131 are disposed apart from the semiconductor layer 120 in a wafer state.

Referring to FIG. 5B, a ternary impurity is implanted into the inner surface of the trench 131 through a tilt implant method, thereby forming a doped layer 130 of a p-type semiconductor. The doping layer 130 formed on the inner surface of the trench 131 may have a substantially uniform thickness.

Referring to FIG. 5C, a Group III impurity is ion-implanted on the doping layer 130 formed on the inner surface of the trench 131, and the column 140 is formed by epitaxial method or the like. That is, the column 140 may be formed by epitaxial growth under an atmosphere of a Group III impurity. Thus, a p-type semiconductor column 140 is formed.

Referring to FIG. 5D, a well region 150, which is a p-type semiconductor, is formed by implanting a Group III impurity through an ion implantation method on the top of the column 140. Further, the source region 160 of the n + type semiconductor is formed by implanting the Group 5 impurity into the inside of the well region 150 again.

5E, an oxide layer is formed on the semiconductor layer 120, the well region 150, and the source region 160 to form a gate insulating layer 170, and a gate electrode 180 is formed through the polysilicon. Can be formed. In addition, the source electrode 190 made of metal is formed on the upper portion and is in contact with the source region 160, so that the high-voltage semiconductor element 100 according to the embodiment of the present invention can be formed.

According to the high-voltage semiconductor device and the method for fabricating the same according to the embodiment of the present invention, the charge amount of the column 140 is set to be equal to or larger than the charge amount of the semiconductor layer, The doping layer 130 is formed in the peripheral region of the column 140 so that the concentration of the impurity implanted into the column 140 is lower than that of the doping layer 130. [ The breakdown voltage can be increased by forming the impurity to be equal to or larger than the concentration of the impurity implanted into the impurity region 130.

It is to be understood that the present invention is not limited to the above-described embodiment, but may be embodied in various forms without departing from the spirit and scope of the invention as defined in the appended claims. It will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.

100; Power semiconductor device 110; Board
120; A semiconductor layer 130; Doping layer
140; Column 150; Well region
160; Source region 170; Gate insulating layer
180; A gate electrode 190; Source electrode

Claims (18)

A first semiconductor layer of a first conductivity type;
A second semiconductor layer of a first conductivity type formed on the first semiconductor layer;
A second conductive type column formed at a predetermined depth in the second semiconductor layer;
A second conductive type doping layer formed between the column and the second semiconductor layer;
A well region of a second conductivity type formed on top of the column and the doping layer; And
And a source region of a first conductivity type formed in the well region. The method according to claim 1,
Wherein the charge amount of the column is equal to or greater than the charge amount of the second semiconductor layer. The method according to claim 1,
Wherein a concentration of an impurity implanted into the column is equal to or greater than a concentration of an impurity implanted into the doping layer. The method according to claim 1,
Wherein the concentration of the impurity implanted into the doping layer is 10% to 100% of the concentration of the impurity implanted into the column. The method according to claim 1,
Wherein a sum of the charge amount of the doping layer and the charge amount of the column is formed to be equal to or greater than the charge amount of the second semiconductor layer. The method according to claim 1,
Wherein the column is formed inside the trench formed in the second semiconductor direction from the top of the second semiconductor layer. The method according to claim 1,
Wherein the column and the second semiconductor layer are alternately arranged in the horizontal direction on the first semiconductor layer. The method according to claim 1,
Wherein the doping layer is formed on the inner wall of the trench. The method according to claim 1,
Wherein the doping layer is formed on the inner wall of the trench in a tilt implant manner. The method according to claim 1,
Wherein a width of the doping layer is 50% or less of a width of the column. A first step of forming a substrate and a semiconductor layer of a first conductivity type;
A second step of forming a trench having a predetermined depth from the top of the semiconductor layer toward the substrate;
A third step of forming a doping layer of a second conductivity type on the inner wall of the trench;
A fourth step of forming a column by implanting an impurity of a second conductivity type on the doping layer in the trench;
A fifth step of implanting impurities of a second conductivity type from an upper portion of the semiconductor layer to form a well region; And
And forming a source region by implanting an impurity of a first conductivity type into the well region. ≪ RTI ID = 0.0 > 11. < / RTI > 12. The method of claim 11,
Wherein the doping layer of the third step is formed on the inner wall of the trench by a tilt implant method. 12. The method of claim 11,
Wherein a charge amount of the column is equal to or greater than a charge amount of the semiconductor layer. 12. The method of claim 11,
Wherein a concentration of an impurity in the column is equal to or greater than a concentration of an impurity in the doping layer. 12. The method of claim 11,
Wherein a concentration of an impurity in the doping layer is 10% to 100% with respect to a concentration of an impurity in the column. 12. The method of claim 11,
Wherein a sum of the charge amount of the doping layer and the charge amount of the column is formed to be equal to or greater than the charge amount of the second semiconductor layer. 12. The method of claim 11,
Wherein the column and the semiconductor layer are alternately arranged in a horizontal direction on the substrate. 12. The method of claim 11,
Wherein a width of the doping layer is 50% or less of a width of the column.
KR1020130150874A 2013-12-05 2013-12-05 High voltage semiconductor device and manufacturing method thereof KR20150065489A (en)

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