KR20150052678A - Analog to Digital Converter using Automatic Calibration of Clock - Google Patents

Abstract

Provided is an analog to digital converter comprising: a ramp signal generation unit generating a ramp signal with a preset grade; a first latch end having a plurality of first latches, each of the first latches receiving an analog input voltage corresponding to an analog signal and each reference voltage, and amplifying a difference between two voltages according to a first clock to generate a first differential (+) output and a first differential (-) output; a second latch end having a plurality of second latches and including a second latch receiving the differential output of one first latch via each of (+) and (-) input end and a second latch receiving the first differential (-) output of one first latch and receiving the first differential (+) output of the adjacent first latch, which receives a low reference voltage adjacent to the reference voltage of the first latch, via (+) and (-) end respectively; a clock signal confirming unit dividing a plurality of second differential output signals into plural sections with the same length according to the inputted ramp signal, generating a clock signal with a preset frequency to check whether a gap between temporal points when each of the second differential outputs is changed is regular; and a second clock phase change unit receiving a clock count checking value from the clock signal checking unit and generating the second clock by repeatedly adjusting a time delay value of the second clock relative to the first clock.

Description

[0001] The present invention relates to an analog to digital converter using an automatic calibration of a clock,

The present embodiment relates to a method and apparatus for converting an analog signal into a digital signal using automatic calibration of a clock.

It should be noted that the following description merely provides background information related to the present embodiment and does not constitute the prior art.

An analog to digital converter is an apparatus that converts an analog signal into a digital signal and receives the signals of temperature, pressure, voice, image, voltage and the like continuously measured and digitizes it.

To date, various types of ADCs have been proposed. For example, a flash ADC, a pipeline ADC, and a successive approximation register ADC (SAR ADC) have been proposed, and they are used in applications suited to their respective characteristics. Flash ADCs operate relatively fast, but they have the disadvantage that their area increases rapidly with accuracy. Pipelined ADCs support fast operation characteristics and high precision, but each stage has the disadvantage of power consumption due to the use of amplifiers. A successive approximation ADC has a drawback that it has a low power consumption rate of the circuit and a simple circuit configuration but operates relatively slowly.

Another example of an analog-to-digital converter is an ADC that uses an interpolation technique to reduce the number of exponentially increasing comparators as the number of digital output bits increases. By applying this interpolation technique, the same precision as the flash ADC described above can be realized while reducing the number of comparators. However, since the static current flows in the comparator, the power consumption is still high even if the number of comparators is reduced.

One of the ADCs designed to solve this problem is a comparator using a latch capable of using a dynamic current. Each latch outputs an output value in accordance with a clock signal, which is a problem in inputting a clock signal at an accurate timing.

The main purpose of the present embodiment is to obtain the output value of an accurate A / D converter by adjusting the timing of the clock signal in the analogue digital converter without internally controlling the timing of the clock signal driving the AD converter from the outside have.

According to an aspect of the present embodiment, there is provided a liquid crystal display comprising: a ramp signal generator for generating a ramp signal of a predetermined slope; The first latch includes a plurality of first latches, each of the first latches receives an analog input voltage corresponding to the analog signal and each reference voltage, amplifies two voltage differences according to the first clock to generate a first differential (+ A first latch stage for outputting a first differential (-) output; A second latch having a plurality of second latches and receiving the differential outputs of one first latch at the (+) and (-) input terminals, a first differential (-) output of any one of the first latches, A second latch stage including a second latch receiving a first differential (+) output of a first adjacent latch receiving a low reference voltage adjacent to a reference voltage of the first latch to the (+) and (-) terminals, respectively; A plurality of second differential output signals are divided into a plurality of sections having the same length based on the received ramp signal and a clock signal having a predetermined frequency is generated to check whether the interval between the times when the respective second differential outputs are changed is constant A clock signal verifying unit; And a second clock phase changing unit for receiving the clock count confirmation value from the clock signal checking unit and generating the second clock by repeatedly adjusting the delay time value of the second clock with respect to the first clock, Converter.

As described above, according to the present embodiment, according to the present embodiment, in the analog-to-digital converter, the timing of the clock signal for driving the AD converter from the outside is not adjusted by the user, It is possible to obtain an output value of the output signal.

1 is a diagram illustrating an analog-digital converter 100 using an interpolation technique.
2 is a diagram showing output characteristics of the latch.
3 is a diagram for explaining the calibration analog-to-digital converter 300. As shown in FIG.
4 is a diagram for explaining the operation of the ramp signal generator 310. Referring to FIG.
5 is a diagram for describing a latch added to the second latch stage.
FIG. 6 is a diagram showing outputs of the second latches 531, 532, 533, 534, and 535 when the ramp signal is connected to the input terminal of the analog-to-digital converter 320 in a state in which the calibration is properly completed.
7 is a diagram illustrating a method for generating a clock signal and outputting a second differential output signal using the generated clock signal.
FIG. 8 is a diagram for explaining a method for determining the delay time value of the second clock signal 550. FIG.

Hereinafter, the present embodiment will be described in detail with reference to the accompanying drawings. It should be noted that, in adding reference numerals to the constituent elements of the drawings, the same constituent elements are denoted by the same reference numerals even though they are shown in different drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

In describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are intended to distinguish the constituent elements from other constituent elements, and the terms do not limit the nature, order or order of the constituent elements. When a component is described as being "connected", "coupled", or "connected" to another component, the component may be directly connected to or connected to the other component, It should be understood that an element may be "connected," "coupled," or "connected."

1 is a diagram illustrating an analog-to-digital converter using an interpolation technique.

The analog digital converter 100 using the interpolation technique includes a reference voltage generator 110, a first latching column 120, and a second latching column 130.

1, only the part (a) of the analog-to-digital converter 100 using the interpolation technique will be described since the remaining part except the part (a) of FIG. 1 operates in the same manner as the part (a).

The reference voltage generating unit 110 generates the reference voltages V1 and V2 and inputs the reference voltages V1 and V2 to the negative input terminals of the first latches 121 and 122. At this time, the reference voltage generator 110 may include a plurality of resistors R1 and R2 connected in series between the power supplies for supplying the two voltages Vrefp and Vrefn, respectively. The reference voltages V1 and V2 input to the negative input terminals of the first latches 121 and 122 correspond to voltages obtained by dividing between the two voltages Vrefp and Vrefn using a plurality of resistors R1 and R2. Here, both of the voltages Vrefp and Vrefn may be positive voltages, and of the two voltages Vrefp and Vrefn, Vrefp may be a positive voltage and Vrefn may be a negative voltage. Also, one of the two voltages Vrefp and Vrefn may be a ground voltage.

The first latch array 120 includes a plurality of first latches 121, 122. The plurality of first latches 121 and 122 amplify and output the difference between the reference voltages V1 and V2 and the analog input voltage Vin corresponding to the analog signal. The first latches 121 and 122 receive the reference voltages V1 and V2 and the analog input voltage Vin. The reference voltages V1 and V2 are input to the negative input terminals of the first latches 121 and 122 and the analog input voltage Vin is input to the positive input terminals of the first latches 121 and 122 . (A1 ⁺ , A1 ^- ), (A2 ⁺ , A2 ^- )} by amplifying the difference between the reference voltages V1 and V2 and the analog input voltage Vin according to the first clock 140, Output. Here, the differential signal {(A1 ⁺ , A1 ^- ), (A2 ⁺ , A2 ^- )} may be referred to as a first differential output signal pair.

The second latch array 130 includes a plurality of second latches 131, 132, and 133.

The first differential output signal pairs {(A1 ⁺ , A1 ^- ), (A2 ⁺ , A2 ^- )} of the first latches 121 and 122 of the first latch row 120 (+) And (-) input terminals of the two latches 131, 132 and 133, respectively. (+) Output (A1 ⁺ ) of the first differential output signal pair of the first latch 121 is input to the (+) input terminal of the second latch 131 and the first differential output signal The negative (-) output (A1 ^- ) of the pair is input to the negative input terminal of the second latch 131. (+) Output (A2 ⁺ ) of the first differential output signal pair of the first latch 122 is input to the (+) input terminal of the second latch 133, and the first differential output signal The negative (-) output (A2 ^- ) of the pair is input to the negative input terminal of the second latch 133. (-) output (A1 ^- ) of the first differential output signal pair of the first latch 121 is input to the negative input terminal of the second latch 132 of the second latch column, (+) Output (A2 ⁺ ) of the first differential output signal pair of the second latch 132 is input to the (+) input terminal of the second latch 132 of the second latch column. The plurality of second latches 131, 132, and 133 amplify the difference between the two voltages input from the first latches 121 and 122 according to the second clock 150 to generate a differential signal {L1 ⁺ , L1 ^- ), (L2 ⁺ , L2 ^- ), (L3 ⁺ , L3 ^- )}. Here, the differential signal {(L1 ⁺ , L1 ^- ), (L2 ⁺ , L2 ^- ), (L3 ⁺ , L3 ^- )} is a second differential output signal pair.

2 is a diagram showing output characteristics of the latch.

Referring to FIG. 2 (a), the first latches 121 and 122 of FIG. 1 vary in the time taken for output to occur depending on the voltage difference between the signals input to the two (+) and (-) input terminals. When the magnitude of the analog input voltage Vin is located between V1 and V2 and the difference between the analog input voltage Vin and the reference voltage V1 is smaller than the difference between the analog input voltage Vin and the reference voltage V2, The differential output signal pairs {(A1 ⁺ , A1 ^- ), (A2 ⁺ , A2 ^- )} of the first latches 121 and 122 have the form as shown in FIG. That is, since the difference between the analog input voltage Vin and the reference voltage V1 is smaller than the difference between the analog input voltage Vin and the reference voltage V2, the differential output signal pair A1 ⁺ , A1 ^- The time required for the change becomes longer than the time required for the differential output signal pair (A2 ⁺ , A2 ^- ) to change to the digital level. Since the first latch 121 has a higher reference voltage V1 than the input voltage Vin, the output signal A1 ^{+ of the} latch 121 generates an output having a low level and the output signal of the first latch 121 (A1 ^- ) generates an output having a high level. On the other hand, since the first latch 122 has a lower reference voltage V2 than the input voltage Vin, the output signal A2 ^{+ of} the first latch 122 generates an output having a high level and the output of the first latch 122 The output signal A2 < ^- >

2B, for example, when the magnitude of the analog input voltage Vin is located between V1 and V2 and the difference between the analog input voltage Vin and the reference voltage V1 is larger than the difference between the analog input voltage Vin and the reference voltage V1, (A1 ⁺ , A1 ^- ), (A2 ⁺ , A2 ^- )} of the first latches 121 and 122 are the same as those of FIG. 2 (b) I have. That is, since the difference between the analog input voltage Vin and the reference voltage V1 is larger than the difference between the analog input voltage Vin and the reference voltage V2, the differential output signal pair A1 ⁺ , A1 ^- Becomes shorter than the time required for the differential output signal pair (A2 ⁺ , A2 ^- ) to change to the digital level. The first latch 121 generates a low level output signal A1 ⁺ of the first latch 121 because the reference voltage V1 is higher than the input voltage Vin and the output of the first latch 121 The output signal A1 ^- generates an output having a high level. On the other hand, since the first latch 122 has a lower reference voltage V2 than the input voltage Vin, the output signal A2 ^{+ of} the first latch 122 generates an output having a high level and the output of the first latch 122 The output signal A2 < ^- >

In general, the latch can not apply the interpolation method to the output of the steady state. However, interpolation is possible in a specific time interval (T1) by using a characteristic in which the time required for the latch to generate the output in the normal state is proportional to the voltage difference of the signal input to the (+) and (-) input terminals.

FIG. 3 is a diagram for explaining the analog-to-digital converter calibration 300. FIG.

The analog-to-digital converter calibration 300 according to the present embodiment includes a ramp signal generator 310, an analog-to-digital converter 320, a clock signal verifier 330, and a second clock phase changer 340.

 The ramp signal generating unit 310 generates a ramp signal of a predetermined slope. The ramp signal generator 310 may generate the ramp signal using various methods, but uses a capacitor and a switch to generate the ramp signal.

4 is a diagram for explaining the operation of the ramp signal generator 310. Referring to FIG.

Referring to FIG. 4, when the first switch is closed, the capacitor C1 is charged by the current source I1, and the voltage increases at a predetermined slope. Here, the ramp signal generator 310 provides the analog-to-digital converter 320 with the voltage of the capacitor C1 that increases at a constant slope. The ramp signal generating unit 310 generates a ramp signal to provide a ramp signal to the analog-to-digital converter 320 when the calibrating operation is performed, and does not provide the ramp signal when the calibrating operation is completed.

The analog-to-digital converter 320 amplifies and outputs the difference between the reference voltage and the analog input voltage.

5 is a diagram for describing a latch added to the second latch stage.

Referring to FIG. 5, the analog-to-digital converter 320 includes a reference voltage generator 510, a first latch stage 520, and a second latch stage 530.

The reference voltage generating unit 510 generates the reference voltages V1 and V2 and inputs the reference voltages V1 and V2 to the negative input terminals of the first latches 521 and 522 of the first latch stage 520 do. The reference voltages V1 and V2 correspond to voltages obtained by dividing two voltages Vrefp and Vrefn by using a plurality of resistors connected in series.

The first latch stage 520 includes a plurality of first latches 521, 522. The plurality of first latches 521 and 522 receive the reference voltages V1 and V2 and the analog input voltage Vin corresponding to the analog signals and amplify the difference between the two voltages according to the first clock 540, Outputs a differential (+) output and a first differential (-) output. The reference voltages V1 and V2 are input to the negative input terminals of the first latches 521 and 522 and the analog input voltage Vin is input to the positive input terminals of the first latches 521 and 522 . First latch stage 520 The first latch 521 receives the reference voltage V1 and the analog input voltage Vin and amplifies the difference between the two voltages according to the first clock 540 to generate a differential signal { A1 ⁺ , A1 ^- )}. First latch stage 520 The first latch 522 receives the reference voltage V2 and the analog input voltage Vin and amplifies the difference between the two voltages according to the first clock 540 to generate a differential signal { A2 ⁺ , A2 ^- )}. Here, the differential signal {(A1 ⁺ , A1 ^- ), (A2 ⁺ , A2 ^- )} may be referred to as a first differential output signal pair.

The second latch stage 530 includes a plurality of second latches 531, 532, 533, 534, and 535. A second latch receiving a differential output of one first latch at each of the (+) and (-) input terminals, and a first differential (-) output of one of the first latches and a reference voltage of either one of the first latches And a second latch receiving the first differential (+) output of the adjacent first latch receiving the adjacent low reference voltage to the (+) and (-) terminals, respectively.

A plurality of the respective second latch stage 530, a first latch stage 520, a first latch (521, 522), a first differential output signal pair of ^{{(A1 +, A1 - -} ), (A2 +, A2)} (+) And (-) input terminals of the second latches 531, 532, 533, 534, and 535. The (+) output (A1 ⁺ ) of the first differential output signal pair of the first latch stage 520 of the first latch stage 520 is input to the (+) input terminal of the second latch stage second latch 531, (-) output (A1 ^- ) of the first differential output signal pair is input to the (-) input terminal of the second latch stage second latch 531. (+) Output (A2 ⁺ ) of the first differential output signal pair of the first latch 522 of the first latch stage 520 is input to the (+) input terminal of the second latch stage second latch 535, (-) output (A 2 ^- ) of the first differential output signal pair is input to the negative input terminal of the second latch stage second latch 535. (-) output (A1 ^- ) of the first differential output signal pair of the first latch 521 of the first latch stage 520 is connected to the second latch 532, 533, 534 of the second latch stage 530 (+) Output terminal A2 ⁺ of the first differential output signal pair of the first latch 522 is input to the negative input terminal of the second latch 532, 533, and 534, do. The plurality of second latches 531, 532, 533, 534 and 535 amplify the difference between the two voltages input from the first latches 521 and 522 according to the second clock 550, ^{+, L1 -), (L2} +, L2 -), (L3 +, L3 -), (L4 +, L4 -), (L5 +, L5 - a)} and outputs. Wherein the differential shape of the signal ^{{(L1 +, L1 -)} , (L2 +, L2 -), (L3 +, L3 -), (L4 +, L4 -), (L5 +, L5 -)} is the second differential Output signal pair.

Referring to FIG. 5, the second latch stage 530 may further include a second latch between the second latches of the second latching column 150 of FIG. 1 to distinguish the subdivided voltage levels. The added plurality of second latches 532 and 534 are connected to the positive input terminal connected to the negative output A1 ^- of the differential output signal pair of the first latch 521 of the first latch stage 520, The voltage level can be divided by adjusting the ratio of the cross sectional area of the (-) input terminal transistor connected to the (+) output (A2 ⁺ ) of the differential output signal pair of the first latch 520 of the one latch stage 520. The ratio of the cross-sectional area of the (+) input transistor of the second latch 531 connected to the output of the first latch stage 520 to the cross-sectional area of the transistor connected to the (-) input end of the second latch 531 is 1: 1, ) Of the transistor connected to the (-) input terminal of the second latch 533 and the cross-sectional area of the (+) input terminal transistor of the second latch 533 is 1: The ratio of the cross-sectional area of the (+) input terminal transistor of the second latch 534 to the cross-sectional area of the (-) input terminal transistor of the second latch 534 is 1: 1, And the ratio of the cross-sectional area of the (-) input terminal transistor to 1: 1. Here, a representing the cross-sectional area ratio of the transistor may be a positive integer such as 2, 3, 4 or the like excluding 1. Here, if the number of the second latches is increased in the second latch stage 530, high precision can be realized while reducing power consumption. That is, since the number of the first latches of the first latch stage 520 increases in proportion to ²ⁿ exponential functions as n increases with respect to the precision n bits of the digital level, The number should be large. However, by adding a plurality of second latches that adjust the ratio of the cross-sectional area of the input transistor to the second latching stage 530, high precision can be realized while minimizing the number of first latches added to the first latching stage 520 have.

FIG. 6 is a diagram showing outputs of the second latches 531, 532, 533, 534, and 535 when a ramp signal is connected to the input terminal of the analog-to-digital converter 320 in a state where calibration is properly performed.

6, the second differential output signal of the second latch stage 530 is 5, L5 is the output signal value of the latch 531 of the second latch stage, L4 is the output signal value of the latch 532 of the second latch stage L3 is the output signal value of the latch 533 of the second latch stage, L2 is the output signal value of the latch 534 of the second latch stage, L1 is the output signal value of the latch 535 of the second latch stage to be. The second differential output signal used here uses the (+) output of all the second latches.

The clock signal verifying unit 330 divides the five second differential output signals into a plurality of sections having the same length based on the received ramp signal, generates a clock signal having a predetermined frequency, Check whether this is a schedule. The generated clock signal repeats '1' and '0' at the same interval. The clock signal verifying unit 330 measures the number of clocks from a point at which one output signal level of the second latch stage 530 changes to a point at which the next output signal level changes using the generated clock signal. For example, the clock signal verifier 330 may determine the number of clocks between the point where the outputs L5 and L4 change, the number of clocks between the points where the outputs L4 and L3 change, the number of clocks between the points where the outputs L3 and L2 change, And the number of clocks between the point where the L1 output changes. The operation of the clock signal verifying unit 330 will be described with reference to FIG.

7 is a diagram illustrating a method for generating a clock signal and outputting a second differential output signal using the generated clock signal.

The clock signal verifying unit 330 sets t1, t2, t3, t4, and t5 as the times when the respective differential output signal levels of the second latch stages 530 change with respect to the ramp signal input having a predetermined slope. If time is set at t1, t2, t3, t4, t5, the time interval is divided into sec1 between t1 and t2, sec2 between t2 and t3, sec3 between t3 and t4, and sec4 between t4 and t5. Here, the clock signal verifying unit 330 checks whether the lengths of sec1, sec2, sec3, and sec4 are equal to each other. When the lengths are equal to each other, it can be confirmed that the correct second differential output signal is output.

The clock signal verifying unit 330 measures the interval between the times when the respective second differential outputs are changed by the number of preset frequency clock signals. Using the generated clock signal, the clock signal verifying unit 330 obtains the value of L4 at a point t1 at which the value of L5 is changed by half of the number of clock signals from the point t1 where the value of C1 is changed to the point t3 where the value of L3 is changed The number of clock signals up to the point t2 where the clock signal is changed is measured. If the number of clock signals measured by the clock signal verifying unit 330 is the same, it can be regarded as a proper analog-to-digital converter. The point at which the values of the output values L5, L4, L3, L2 and L1 of the second latch stage 530 are changed may be changed according to the length of the delay time between the first clock 540 and the second clock 550 .

The second clock phase change unit 340 adjusts the phase difference between the generation point of the first clock 540 and the generation point of the second clock 550 to gradually increase or decrease. The second clock phase change unit 340 may be configured to change the input timing of the second clock signal 550 so that the differential output signal of the first latch stage 520 can be input at a proper timing when the differential output signal of the first latch stage 520 is input to the second latch stage 530 . The second clock phase changing unit 340 receives the result of the clock signal checking unit 330 and adjusts the input time point of the second clock 550. The operation of the second clock phase change unit 340 is described with reference to FIG.

FIG. 8 is a diagram for explaining a method for determining the delay time value of the second clock signal 550. FIG.

The second clock phase changing unit 340 receives the result of the clock signal checking unit 330 and operates. The second clock phase changing unit 340 checks whether or not the lengths of sec1, sec2, sec3 and sec4 are equal to each other according to the result of the clock signal verifying unit 330, And adjusts the input time of the second clock signal 550 through the process of FIG.

Referring to FIG. 8, when the first clock 540 is generated, the second clock phase changing unit 340 increases the delay time 810 until the second clock 550 is generated, The output value L4 of the latch 532 of the second latch stage 530 changes faster than the time t2 when the output signal level of the latch 532 of the second latch stage 530 changes. The output value L2 of the second latch stage 530 latch 534 changes later than the time t4 when the output signal level of the latch 534 of the second latch stage 530 changes. Here, the operations of L4 and L2 change symmetrically about L3.

The second clock phase change unit 340 may delay the delay time until the second clock signal 550 is generated at the time when the first clock signal 540 is generated, The output value L4 of the second latch stage 532 changes later than the time t2 when the output signal level of the second latch stage 530 latch 532 changes. The output value L2 of the second latch stage 530 latch 534 changes more quickly than the time t4 when the output signal level of the latch 534 of the second latch stage 530 changes. Here, the operations of L4 and L2 change symmetrically about L3.

The second clock phase change unit 340 may delay the delay time until the second clock signal 550 is generated at the time when the first clock signal 540 is generated and then shorten the delay time so that one second differential output signal So that the distance from the starting point to the point where the next second differential output signal is generated is the same. That is, the second clock phase change unit 340 uses the clock signal generated by the clock signal check unit 330 to change the L5 value, the L4 value, the L3 value, The delay time between the time when the first clock signal 540 is generated and the time when the second clock signal 550 is generated so that the number of clock signals between the points where the L1 value is changed is long, do. The most suitable delay time can be found by repeating the above procedure.

The foregoing description is merely illustrative of the technical idea of the present embodiment, and various modifications and changes may be made to those skilled in the art without departing from the essential characteristics of the embodiments. Therefore, the present embodiments are to be construed as illustrative rather than restrictive, and the scope of the technical idea of the present embodiment is not limited by these embodiments. The scope of protection of the present embodiment should be construed according to the following claims, and all technical ideas within the scope of equivalents thereof should be construed as being included in the scope of the present invention.

110: Reference voltage generator 120:
130: second latch column 140: first clock
150: second clock 310: ramp signal generator
320: analog-to-digital conversion unit 330: clock signal verification unit
340: second clock phase changing unit 510: reference voltage generating unit
520: first latch stage 530: second latch stage
540: first clock signal 550: second clock signal

Claims (3)

An apparatus for converting an analog signal into a digital signal,
A ramp signal generator for generating a ramp signal of a predetermined slope;
The first latch includes a plurality of first latches, each of the first latches receives an analog input voltage corresponding to the analog signal and each reference voltage, amplifies two voltage differences according to the first clock to generate a first differential (+ A first latch stage for outputting a first differential (-) output;
A second latch having a plurality of second latches and receiving the differential outputs of one first latch at the (+) and (-) input terminals, a first differential (-) output of any one of the first latches, A second latch stage including a second latch receiving a first differential (+) output of a first adjacent latch receiving a low reference voltage adjacent to a reference voltage of the first latch to the (+) and (-) terminals, respectively;
A plurality of second differential output signals are divided into a plurality of sections having the same length based on the received ramp signal and a clock signal having a predetermined frequency is generated to check whether the interval between the times when the respective second differential outputs are changed is constant A clock signal verifying unit; And
And a second clock phase change unit for receiving the clock count confirmation value from the clock signal check unit and generating the second clock by repeatedly adjusting the delay time value of the second clock with respect to the first clock,
/ RTI > The method according to claim 1,
Wherein the clock signal verifying unit measures the interval between the time when the second differential output changes and the number of the clock signals generated. The method according to claim 1,
Wherein the second clock phase changing unit adjusts the phase difference between the generation point of the first clock and the generation point of the second clock so as to be gradually increased or decreased.

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