KR20150038630A - 비터비 패킹 명령 - Google Patents

비터비 패킹 명령 Download PDF

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Publication number
KR20150038630A
KR20150038630A KR20157006068A KR20157006068A KR20150038630A KR 20150038630 A KR20150038630 A KR 20150038630A KR 20157006068 A KR20157006068 A KR 20157006068A KR 20157006068 A KR20157006068 A KR 20157006068A KR 20150038630 A KR20150038630 A KR 20150038630A
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KR
South Korea
Prior art keywords
viterbi
bits
register
packing
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
KR20157006068A
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English (en)
Korean (ko)
Inventor
마오 쳉
루시안 코드레스쿠
Original Assignee
퀄컴 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 퀄컴 인코포레이티드 filed Critical 퀄컴 인코포레이티드
Publication of KR20150038630A publication Critical patent/KR20150038630A/ko
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H03M13/4107—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing add, compare, select [ACS] operations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H03M13/4161—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing path management
    • H03M13/4169—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing path management using traceback
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6502—Reduction of hardware complexity or efficient processing
    • H03M13/6505—Memory efficient implementations

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  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)
  • Executing Machine-Instructions (AREA)
KR20157006068A 2006-03-23 2007-03-23 비터비 패킹 명령 Ceased KR20150038630A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/389,443 2006-03-23
US11/389,443 US8290095B2 (en) 2006-03-23 2006-03-23 Viterbi pack instruction
PCT/US2007/064816 WO2007109793A2 (en) 2006-03-23 2007-03-23 Viterbi pack instruction

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
KR1020127022669A Division KR101585492B1 (ko) 2006-03-23 2007-03-23 비터비 패킹 명령

Publications (1)

Publication Number Publication Date
KR20150038630A true KR20150038630A (ko) 2015-04-08

Family

ID=38523331

Family Applications (3)

Application Number Title Priority Date Filing Date
KR20157006068A Ceased KR20150038630A (ko) 2006-03-23 2007-03-23 비터비 패킹 명령
KR1020087025411A Ceased KR20080112311A (ko) 2006-03-23 2007-03-23 비터비 패킹 명령
KR1020127022669A Expired - Fee Related KR101585492B1 (ko) 2006-03-23 2007-03-23 비터비 패킹 명령

Family Applications After (2)

Application Number Title Priority Date Filing Date
KR1020087025411A Ceased KR20080112311A (ko) 2006-03-23 2007-03-23 비터비 패킹 명령
KR1020127022669A Expired - Fee Related KR101585492B1 (ko) 2006-03-23 2007-03-23 비터비 패킹 명령

Country Status (11)

Country Link
US (1) US8290095B2 (https=)
EP (1) EP1997229A2 (https=)
JP (1) JP5180186B2 (https=)
KR (3) KR20150038630A (https=)
CN (1) CN101405945B (https=)
BR (1) BRPI0708809A2 (https=)
CA (1) CA2643940A1 (https=)
IN (1) IN266883B (https=)
MX (1) MX2008011985A (https=)
RU (1) RU2008141908A (https=)
WO (1) WO2007109793A2 (https=)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9354877B2 (en) * 2011-12-23 2016-05-31 Intel Corporation Systems, apparatuses, and methods for performing mask bit compression
US9390058B2 (en) * 2013-09-24 2016-07-12 Apple Inc. Dynamic attribute inference
US9367309B2 (en) 2013-09-24 2016-06-14 Apple Inc. Predicate attribute tracker
US9552205B2 (en) * 2013-09-27 2017-01-24 Intel Corporation Vector indexed memory access plus arithmetic and/or logical operation processors, methods, systems, and instructions
US10198263B2 (en) 2015-09-19 2019-02-05 Microsoft Technology Licensing, Llc Write nullification
US11681531B2 (en) 2015-09-19 2023-06-20 Microsoft Technology Licensing, Llc Generation and use of memory access instruction order encodings
US10180840B2 (en) * 2015-09-19 2019-01-15 Microsoft Technology Licensing, Llc Dynamic generation of null instructions
US10031756B2 (en) 2015-09-19 2018-07-24 Microsoft Technology Licensing, Llc Multi-nullification
US10061584B2 (en) 2015-09-19 2018-08-28 Microsoft Technology Licensing, Llc Store nullification in the target field

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4012722A (en) * 1975-09-20 1977-03-15 Burroughs Corporation High speed modular mask generator
US4128880A (en) * 1976-06-30 1978-12-05 Cray Research, Inc. Computer vector register processing
US5752001A (en) * 1995-06-01 1998-05-12 Intel Corporation Method and apparatus employing Viterbi scoring using SIMD instructions for data recognition
US5621674A (en) 1996-02-15 1997-04-15 Intel Corporation Computer implemented method for compressing 24 bit pixels to 16 bit pixels
DE69840527D1 (de) 1997-04-17 2009-03-19 Ntt Docomo Inc Sendegerät für ein Mobilfunksystem
US6334202B1 (en) 1998-07-22 2001-12-25 Telefonaktiebolaget Lm Ericsson (Publ) Fast metric calculation for Viterbi decoder implementation
US6798736B1 (en) 1998-09-22 2004-09-28 Qualcomm Incorporated Method and apparatus for transmitting and receiving variable rate data
US20020002666A1 (en) * 1998-10-12 2002-01-03 Carole Dulong Conditional operand selection using mask operations
US6115808A (en) * 1998-12-30 2000-09-05 Intel Corporation Method and apparatus for performing predicate hazard detection
US6333954B1 (en) * 1999-10-21 2001-12-25 Qualcomm Incorporated High-speed ACS for Viterbi decoder implementations
US6654878B1 (en) 2000-09-07 2003-11-25 International Business Machines Corporation Register bit scanning
GB2367650B (en) 2000-10-04 2004-10-27 Advanced Risc Mach Ltd Single instruction multiple data processing
US20040054877A1 (en) 2001-10-29 2004-03-18 Macy William W. Method and apparatus for shuffling data
US7313639B2 (en) * 2003-01-13 2007-12-25 Rambus Inc. Memory system and device with serialized data transfer
KR20040085545A (ko) 2003-03-31 2004-10-08 삼성전자주식회사 통신 시스템에서 오류 정정 부호의 복호 장치 및 방법
US20050149701A1 (en) * 2003-12-24 2005-07-07 Inching Chen Method, apparatus and system for pair-wise minimum and minimum mask instructions

Also Published As

Publication number Publication date
US20070223629A1 (en) 2007-09-27
CN101405945A (zh) 2009-04-08
JP2009531987A (ja) 2009-09-03
RU2008141908A (ru) 2010-04-27
CN101405945B (zh) 2013-03-27
KR20080112311A (ko) 2008-12-24
EP1997229A2 (en) 2008-12-03
WO2007109793A2 (en) 2007-09-27
CA2643940A1 (en) 2007-09-27
US8290095B2 (en) 2012-10-16
BRPI0708809A2 (pt) 2011-06-14
WO2007109793A3 (en) 2007-12-27
IN266883B (https=) 2015-06-11
JP5180186B2 (ja) 2013-04-10
MX2008011985A (es) 2008-10-03
KR101585492B1 (ko) 2016-01-22
KR20120116500A (ko) 2012-10-22

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