KR20150033878A - Semiconductor apparatus, manufacturing method of the semiconductor apparatus and electronic apparatus having the semiconductor apparatus - Google Patents

Abstract

The present technique relates to a semiconductor device which can improve the property of a device by forming an oxide layer only in the region where a gate is locally formed in a device isolation layer of defining an active region. The semiconductor device of the present technique includes a first device isolation layer which defines an active region and includes an etched recess in a gate region, a second device isolation layer which is filled in the lower part of the recess, a gate located in the upper part of the second device isolation layer, and a sealing layer located in the upper part of the gate.

Description

TECHNICAL FIELD [0001] The present invention relates to a semiconductor device, a method of manufacturing the same, and an electronic apparatus having the semiconductor device.

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device capable of locally forming an oxide film only in a region where a word line (gate) ≪ / RTI >

As the semiconductor device becomes increasingly highly integrated, the pattern formed on the active area of the semiconductor substrate has been reduced to the area of the device isolation region formed to prevent the electrical conduction between the patterns.

Conventional device isolation regions have been formed through a local oxidation of silicon (LOCOS) process. As the area of the device isolation region is reduced, an STI (shallow trench isolation process has been developed.

In the STI process, an isolation trench having a predetermined depth is formed on a semiconductor substrate, an insulating material is deposited to fill the trench and a subsequent CMP process is performed to remove an unnecessary insulating film, .

However, as the design rule of the semiconductor device is gradually reduced, the size of the transistor becomes smaller, and the width of the trench for device isolation is gradually narrowed. As a result, the thickness of the sidewall oxide film (Wox) formed on the sidewall of the trench for element isolation becomes gradually thinner, resulting in the deterioration of the reliability of the HEIP (Hot Electron Induced Puchthrough) and the transistor.

However, when the entire device isolation film is formed of an oxide film in order to maximize the thickness of the wall oxidation, a shim is further generated in the device isolation film, so that a bridge between the word lines can be generated.

The embodiment of the present invention can improve the characteristics (retention time, channel resistance (Rch), row hammer, etc.) of an element by forming an oxide film in a region where a word line (gate) And a method of manufacturing the same.

A semiconductor device according to an embodiment of the present invention includes a first device isolation film which defines an active region and includes a recess in which a gate region is etched, a second device isolation film buried in a lower portion of the recess, A gate located on top of the gate, and a sealing film located on top of the gate.

A semiconductor device according to another embodiment of the present invention includes a device isolation film defining an active region, a gate recess formed in the active region of the gate region, an etched gate recess and a gate formed under the gate recess, The device isolation film may include an oxide film locally located only below the gate.

An electronic device according to an embodiment of the present invention includes a memory device for storing data and reading stored data in accordance with a data input / output control signal, and a memory controller for generating data input / output control signals to control data input / output operations of the memory device Wherein the memory device defines an active region and includes a first device isolation film including a recess in which a gate region is etched, a second device isolation film buried in a lower portion of the recess, And a sealing film overlying the gate.

In this embodiment, an oxide film is formed in a region where word lines (gates) are formed in the device isolation film region to maximize the thickness of the sidewall oxide film locally, thereby improving the characteristics of the semiconductor device.

1 is a plan view showing a layout of a semiconductor device according to an embodiment of the present invention;
FIG. 2 is a cross-sectional view showing a cross section along AA 'and B-B' in FIG. 1; FIG.
FIGS. 3A through 3E are process sectional views illustrating a process for forming the structure of FIG. 2. FIG.
4 is a cross-sectional view showing a structure of a semiconductor device according to another embodiment of the present invention;
5A and 5B are process cross-sectional views illustrating a process for forming the structure of FIG.
6 is a block diagram briefly showing a configuration of a memory device according to an embodiment of the present invention;
7 is a block diagram briefly showing the configuration of an electronic device having a memory device according to an embodiment of the present invention;
Figures 8A and 8B are diagrams illustrating embodiments of the memory device of Figure 7;
9 is a block diagram briefly showing a configuration of an electronic device according to another embodiment of the present invention.
10 is a block diagram schematically showing the structure of an electronic device according to another embodiment of the present invention.
11 is a block diagram schematically showing a structure of an electronic device according to another embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a plan view showing a layout of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view showing a cross section taken along line A-A 'and B-B' in FIG.

Referring to FIGS. 1 and 2, the semiconductor device of the present embodiment is configured such that the active region 104 defined by the device isolation film 102 does not intersect perpendicularly to the gate (word line) 106, 6F ² < / RTI > structure. At this time, the gate 106 has a buried gate (BG) structure buried in the bottom of the active region 104 and the device isolation film 102, and the active region 104 in the gate region And is formed in a protruded fin structure. That is, the buried gate 106 is formed to have a fin gate structure that is formed to contact the upper surface and both side surfaces of the active region 104, thereby forming a channel on three sides of the active region 103. A gate insulating film 110 is formed between the buried gate 106 and the active region 104.

A side wall oxide film 108 is formed on the sidewall of the active region 104 and the device isolation film 102 includes a first device isolation film 102a and a second device isolation film 102b. At this time, the first device isolation film 102a includes a nitride film, and the second device isolation film 102b includes an oxide film. At this time, the second device isolation film 102b is locally formed only in a specific region of the entire device isolation film 102, for example, under the buried gate 106. [ That is, in this embodiment, the device isolation film 102 is not formed entirely of the nitride film 102a but is locally formed in the region where the gate 106 is formed, using the oxide film 102b. As described above, by forming the oxide film 102b locally only in a specific region of the device isolation film 102, it is possible to prevent a problem (e.g., a bridge between word lines) that may occur when the entire device isolation film is formed into an oxide film Can be improved. For example, by improving the potential barrier height of the bottom region of a transistor having a pin structure and locally improving the hydrogen passivation effect, the retention time of the word line (gate) ) Can be improved. In particular, by forming the element isolation film 102 under the gate 106 as an oxide film, the thickness of the sidewall oxide film is locally increased to improve the retention time, channel resistance (Rch), and row hammer characteristics Can be improved.

The second isolation film 102b includes SiO ₂ and may be formed by a high-density plasma (HDP) chemical vapor deposition (CVD) method. Alternatively, the second isolation film 102b may be formed of a SiO ₂ single film or a multilayer structure in which a SiO ₂ film and another insulating film are deposited in multiple layers.

A sealing insulating film 112 for insulating the buried gate 106 is formed on the top of the buried gate 106. The sealing insulating film 112 includes a nitride film. The sealing insulating film 112 is not shown in FIG. 1 for convenience of explanation.

3A to 3E are process sectional views illustrating a process for forming the structure of FIG.

3A, a pad oxide film (not shown) and a pad nitride film (not shown) are formed on the semiconductor substrate 300, and a photoresist film (not shown) is formed on the pad nitride film. At this time, the pad oxide film is formed to suppress the stress caused by the pad nitride film from being transferred to the semiconductor substrate 300. Then, the photosensitive film is subjected to an exposure and development process to form a photosensitive film pattern (not shown) defining the active region 302.

Next, a mask pattern is formed by etching the pad nitride film and the pad oxide film using the photoresist pattern as a mask, and the semiconductor substrate 300 is etched using the hard mask pattern as a mask to form an element isolation trench 304 ).

Referring to FIG. 3B, a sidewall oxide film 306 is formed on the sidewall of the trench 304 for element isolation. At this time, the sidewall oxide film 306 includes a high temperature oxide (HTO) oxide film having excellent step coverage. After the HTO oxide film is formed, an annealing process may be performed to improve the quality of the oxide film.

Next, an insulating film is formed so that the element separating trenches 304 are buried, and then the insulating film is planarized to form the first element separating film 308a. The first element isolation film 308a includes a nitride film.

After the first isolation film 308a is formed, the pad nitride film and the pad oxide film are removed. For example, the pad nitride film is removed by a wet etching method using a phosphoric acid solution, and the pad oxide film is removed by wet cleaning using a hydrogen fluoride solution.

Referring to FIG. 3C, a mask pattern (not shown) is formed to define a buried gate region on the active region 302 and the first isolation film 308a. At this time, the buried gate region corresponds to a region where reference numeral 106 is formed in FIG.

Subsequently, the active region 302 and the first isolation film 308a are etched using the mask pattern as an etching mask to form a recess 310 for a gate in which a buried gate is to be formed. At this time, the first isolation layer 308a is etched deeper than the active region 302 by the etch selectivity ratio of the active region 302 and the device isolation layer 308a, 302 are protruded from the first element isolation film 308a.

Particularly, in this embodiment, the gate recess 310 is formed deeply so that the height of the protruded fin is higher than the height of the target fin to be finally formed.

Next, referring to FIG. 3D, an oxide film (not shown) is formed so that the gate recess 310 is buried, and then the oxide film is planarized. At this time, the oxide film includes SiO ₂ and may be formed by high-density plasma (HDP) chemical vapor deposition (CVD).

Then, the oxide film buried in the gate recess 310 is etched back to form the second isolation film 308b under the recess 310 for the gate. That is, in the gate recess 310, a second isolation film 308b made only of an oxide film is locally formed on the first isolation film 308a. At this time, the second isolation film 308b is formed to the point where the height of the projected active region 302 becomes the height of the target pin.

The second isolation layer 308b is formed in the gate recess 310 to complete the isolation layer 308 defining the active region 302.

Next, referring to FIG. 3E, a gate insulating film 312 is formed on the surface of the active region 302 by oxidizing the active region 302 exposed in the recess 310 for the gate. The gate insulating layer 312 may be formed by oxidizing the active region 302 through a radical oxidation process. Or the gate insulating layer 312 may be formed by depositing a high dielectric constant material having a high dielectric constant in the active region 302 inside the gate recess 310 by using atomic layer deposition or chemical vapor deposition. On the surface of the substrate.

Next, a conductive film for a gate is formed so as to fill the recess 310 for a gate, and then the conductive film is planarized. At this time, the conductive film for the gate may be a single metal material such as Ti, TiN, W, WN, or a mixed material thereof. Or doped polysilicon may be used as the conductive film for the gate.

Next, the conductive film for the gate is selectively removed to form the buried gate 314 so that the conductive film for the gate remains at a constant height only below the recess 310 for the gate. At this time, the conductive film for the gate can be selectively removed only through the etch-back process. Then, a sealing insulating film 316 is formed on the buried gate 314 so that the gate recess 310 is buried. The sealing insulating film 316 includes a silicon nitride film (Si ₃ N ₄ ). As a method of forming the sealing insulating film 316, chemical vapor deposition (CVD) may be used. In this case, the chemical vapor deposition may be performed by using atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), metalorganic chemical vapor deposition CVD (MOCVD) and thermal chemical vapor deposition (CVD).

Subsequent processes to follow are the same as those of the conventional semiconductor device having a buried gate structure, and therefore, a description thereof will be omitted.

4 is a cross-sectional view illustrating a structure of a semiconductor device according to another embodiment of the present invention. In Fig. 4, the same reference numerals are used for the same structures as in Fig.

In FIG. 2, the case where the second isolation film 102b is formed of a single oxide film (SiO ₂ ) 102b has been described. In FIG. 4, the second isolation film is formed in a multilayer structure. That is, in FIG. 4, the second isolation layers 102c and 102d include a structure in which oxide layers of different materials are stacked or a structure in which an oxide layer and a nitride layer are stacked. At this time, the material film 102c in contact with the active region 104 is formed of an oxide film.

5A to 5C are process sectional views illustrating a process for forming the structure of FIG. In the present embodiment, for convenience of description, the same reference numerals are assigned to the structures as shown in Figs. 3A to 3E.

First, a recess 310 for a gate is formed through the process as shown in FIGS. 3A to 3C.

Next, referring to FIG. 5A, a barrier film 308c is formed on the inner surface of the recess 310 for the gate. At this time, the barrier film 308c includes an oxide film. An oxide film (308c) comprises a SiO _2, a high-density plasma can be formed by;; (Chemical Vapor Deposition CVD) (HDP High-Density Plasma) CVD.

Next, the insulating film 308d is formed so that the gate recess 310 is buried, and then the insulating film 308d is planarized. At this time, the insulating film 308d includes a nitride film or an oxide film.

Referring to FIG. 5B, the barrier film 308c and the insulating film 308d are etched by a predetermined depth to protrude the active region 302 in the gate recess 310 in a pin shape. At this time, the height of the projected pin is set to the height of the target fin to be finally formed.

In this way, the double-layered insulating films 308c and 309d are formed in the gate recess 310 as the second device isolation film, thereby completing the device isolation film 308 defining the active region 302.

Referring next to FIG. 5C, a gate insulating layer 312 is formed on the surface of the active region 302 by oxidizing the active region 302 exposed in the recess 310 for the gate. The gate insulating layer 312 may be formed by oxidizing the active region 302 through a radical oxidation process. Or the gate insulating layer 312 may be formed by depositing a high dielectric constant material having a high dielectric constant in the active region 302 inside the gate recess 310 using an atomic layer deposition method or a chemical vapor deposition method On the surface thereof.

Next, a conductive film for a gate is formed so as to fill the recess 310 for a gate, and then the conductive film is planarized. At this time, the conductive film for the gate may be a single metal material such as Ti, TiN, W, WN, or a mixed material thereof. Or doped polysilicon may be used as the conductive film for the gate.

Next, the conductive film for the gate is selectively removed to form the buried gate 314 so that the conductive film for the gate remains at a constant height only below the recess 310 for the gate. At this time, the conductive film for the gate can be selectively removed only through the etch-back process. Then, a sealing insulating film 316 is formed on the buried gate 314 so that the gate recess 310 is buried. The sealing insulating film 316 includes a silicon nitride film (Si ₃ N ₄ ). As a method of forming the sealing insulating film 316, chemical vapor deposition (CVD) may be used. In this case, the chemical vapor deposition may be performed by using atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), metalorganic chemical vapor deposition CVD (MOCVD) and thermal chemical vapor deposition (CVD).

Subsequent processes to follow are the same as those of the conventional semiconductor device having a buried gate structure, and therefore, a description thereof will be omitted.

6 is a block diagram briefly showing a configuration of a memory device according to an embodiment of the present invention.

The memory device 500 includes a memory cell array 510, a row decoder 520, a control circuit 530, a sense amplifier 540, a column decoder 550 and a data input / 560).

The memory cell array 510 includes a plurality of word lines WL1 to WLn (n is a natural number), a plurality of bit lines BL1 to BLn and a plurality of word lines WL1 to WLn and bit lines BL1 And a plurality of memory cells (not shown) connected between the memory cells BLn and BLn for storing data. Each memory cell includes a transistor that is a switching device that is turned on or off according to the voltage applied to the word lines WL1 to WLn. Each transistor is formed in an active region defined by a device isolation film. At this time, the word lines WL1 to WLn may be formed to be obliquely intersected with the active region as shown in FIG. 1 and FIG. 2 and to be buried in the active region and the isolation region. Furthermore, the device isolation film may not be formed only of a nitride film as shown in FIG. 2 but may include an oxide film locally. For example, only the element isolation films formed under the word lines (the buried gates) WL1 to WLn in the device isolation film are formed as an oxide film locally, thereby improving the characteristics of the semiconductor device while preventing bridging between the word lines.

The row decoder 520 generates a word line selection signal (row address) for selecting a memory cell to which data is to be read or written and applies the word line selection signal (row address) to the word lines WL1 to WLn to select one of the plurality of word lines WL1 to WLn And selects any one of the word lines.

The control circuit 530 controls the operation of the sense amplifier 540 according to a control signal (not shown) input from the outside.

The sense amplifier 540 senses and amplifies the data of the memory cell and also stores the data in the memory cell. At this time, the sense amplifier 540 includes a plurality of sense amplifiers (not shown) for sensing and amplifying data corresponding to each of the plurality of bit lines BL1 to BLn, Amplifies the data of each of the plurality of bit lines BL1 to BLn in response to a control signal output from the control unit 530. [

The column decoder 550 generates column select signals for operating the sense amplifiers connected to the cells selected by the row decoder 520, and outputs the column select signals to the sense amplifier 540.

The data input / output circuit 560 transfers write data input from the outside to the sense amplifier 540 in accordance with a plurality of column select signals output from the column decoder 550, And outputs the sense amplifier amplified sense amplifiers 540 according to the selection signals.

The row decoder 520, the control circuit 530, the sense amplifier 540 and the column decoder 550 among the components of the memory device 500 described above are substantially identical to the corresponding components used in the conventional memory device And can be configured identically.

By applying the above-described device isolation structure to the cell array of the memory device 500, the operating characteristics of the memory device 550 can be improved.

7 is a block diagram briefly illustrating the configuration of an electronic device having a memory device according to an embodiment of the present invention.

The electronic device 600 of FIG. 7 includes a memory controller 610, a memory interface (PHY) 620, and a memory device 630.

The memory controller 610 generates a data input / output control signal (command signal CMD, address signal ADD) for controlling the operation of the memory device 630 and outputs it to the memory device 630 through the memory interface 620 Thereby controlling the data input / output (READ / WRITE) operation of the memory device 630. The memory controller 610 includes a control device for controlling data input / output to / from memory devices in a typical data processing system. The memory controller 610 may be embedded in a processor of an electronic device such as a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), or in the form of a system on chip (SoC) Chip. ≪ / RTI > Although the memory controller 610 is shown as one block in FIG. 7, the memory controller 610 may include both a controller for a volatile memory and a controller for a nonvolatile memory.

The memory controller 610 may be an integrated device electronics (IDE), a serial advanced technology attachment (SATA), a small computer system interface (SCSI), a redundant array of independent disks (SSD), a solid state disk (SSD) ), A PCMCIA (Personal Computer Memory Card International Association), a MultiMediaCard (MMC), an embedded MMC (eMMC), a Compact Flash (CF), a graphic card And a conventional controller for controlling a memory such as a memory.

The memory interface 620 provides a physical layer interface between the memory controller 610 and the memory device 30 and is used to transmit and receive data between the memory controller 610 and the memory device 30 according to the clock signal CLK. And processes the timing of the data.

The memory device 630 includes a plurality of memory cells for storing data and stores the data DATA according to the control signals CMD and ADD from the memory controller 610 applied through the memory interface 620 Or reads the stored data and outputs it to the memory interface 620. At this time, the memory device 630 may include the memory device 500 of FIG. 6 described above. That is, the device isolation film that defines the active region in the cell array of the memory device 630 may be formed of an oxide film locally. For example, only the element isolation films formed under the word lines (the buried gates) WL1 to WLn in the device isolation film are formed as an oxide film locally, thereby improving the characteristics of the semiconductor device while preventing bridging between the word lines.

Such a memory device 630 may include volatile memory and non-volatile memory. The volatile memory may include a dynamic random access memory (DRAM), a moblie DRAM, a static random access memory (SRAM), and the like. The nonvolatile memory may include a Nor Flash memory, a NAND flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a spin transfer random access memory (STTRAM), a magnetic random access memory (MRAM), and the like. In addition, although the memory device 630 is shown only as one block in FIG. 7, it may include a plurality of memory chips. When the memory device 630 is composed of a plurality of memory chips, the plurality of memory chips may be formed in a form of a plane mounted on a board (board) or a stack.

The operation characteristics of the electronic device can be improved by applying the above-described device isolation film structure to the cell array of the memory device 630 in the electronic device 600. [

FIG. 8 is a diagram illustrating an embodiment of the memory device 630 of FIG.

8A is a view showing a state in which a plurality of memory chips 720 are mounted on a module substrate 710 configured to be plugged into a memory slot of a computer.

The semiconductor module 700 includes a plurality of memory chips 720 mounted on a module substrate 710 and a command link 730 through which signals ADD, CMD, and CLK for controlling the operation of the memory chips 720 are transferred. And a data link 740 through which data (DATA) input and output to and from the memory chips 720 are transferred.

At this time, each memory chip 720 may include the memory device 500 of FIG. 6 described above. That is, the device isolation film that defines the active region in the cell array of the memory chip 720 may be formed as an oxide film locally. For example, only the element isolation films formed under the word lines (the buried gates) WL1 to WLn in the device isolation film are formed as an oxide film locally, thereby improving the characteristics of the semiconductor device while preventing bridging between the word lines.

In FIG. 8A, only the memory chips 720 are mounted on the front surface of the module substrate 710, but the memory chips 720 may be mounted on the rear surface of the module substrate 710. At this time, the number of memory chips 720 mounted on the module substrate 710 is not limited to that illustrated in FIG. 8A. The material and structure of the module substrate 710 are also not particularly limited.

8B is a diagram illustrating another embodiment of the memory device of FIG.

The memory device 750 may be formed by stacking a plurality of semiconductor layers (semiconductor chips) 752 in a stack structure, and at least one memory device 750 may be mounted on a board And may operate under the control of the memory controller 610. At this time, the memory device 750 may include a structure in which the same semiconductor layers (chips) are connected through a through silicon via (TSV) or a structure in which different kinds of semiconductor layers (chips) are connected via TSV. 8B illustrates a structure in which signal transmission between the semiconductor layers is performed through TSV. However, the present invention is not limited to this, and can be applied to a structure in which layers are stacked through a tape having wire bonding, interposing, or wiring.

At this time, the semiconductor layer 752 may include the memory device 500 of FIG. 6 described above. That is, the device isolation film defining the active region in the cell array of the semiconductor layer 752 may be formed as an oxide film locally. For example, only the element isolation films formed under the word lines (the buried gates) WL1 to WLn in the device isolation film are formed as an oxide film locally, thereby improving the characteristics of the semiconductor device while preventing bridging between the word lines.

9 is a block diagram briefly showing a configuration of an electronic device according to another embodiment of the present invention.

The electronic device 800 of FIG. 9 includes a data storage 810, a memory controller 820, a buffer (cache) memory 830, and an input / output (I / O) interface 840.

The data storage unit 810 stores data (DATA) applied from the memory controller 820 according to a control signal from the memory controller 820, reads the stored data, and outputs the read data to the memory controller 820. The data storage unit 810 includes a non-volatile memory that can store data without losing data even when the power is turned off. The data storage unit 810 includes a Nor Flash memory, a NAND flash memory, a phase change random access memory (PRAM) A Resistive Random Access Memory (RRAM), a Spin Transfer Torque Random Access Memory (STTRAM), a Magnetic Random Access Memory (MRAM), and the like.

The memory controller 820 decodes commands inputted from an external device (host device) through the input / output interface 840 and controls data input / output to the data storage 810 and the buffer memory 830 according to the decoded result do. Such a memory controller 820 may include the memory controller 610 of FIG. Although the memory controller 820 is shown as one block in FIG. 9, the memory controller 820 includes a controller for controlling the nonvolatile memory 810 and a controller for controlling the buffer memory 830, which is a volatile memory, Lt; / RTI >

The buffer memory 830 temporarily stores data to be processed by the memory controller 820, that is, data to be input to and output from the data storage unit 810. The buffer memory 830 stores data (DATA) applied from the memory controller 820 in accordance with a control signal from the memory controller 820, reads the stored data, and outputs the read data to the memory controller 820. The buffer memory 830 includes a volatile memory such as a Dynamic Random Access Memory (DRAM), a Moblie DRAM, and a Static Random Access Memory (SRAM).

An input / output (I / O) interface 840 provides a physical connection between the memory controller 820 and an external device (host) so that the memory controller 820 receives control signals for data input / output from external devices, Allowing you to exchange data. The input / output (I / O) interface 840 may include one of a variety of interface protocols such as USB, MMC, PCI-E, SAS, SATA, PATA, SCSI, ESDI,

In this electronic device 800, the device isolation film defining the active region in the memory cell array of the data storage unit 810 or the buffer memory 830 may be formed as an oxide film locally. For example, only the element isolation films formed under the word lines (the buried gates) WL1 to WLn in the device isolation film are formed as an oxide film locally, thereby improving the characteristics of the semiconductor device while preventing bridging between the word lines.

The electronic device 800 of FIG. 9 can be used as an auxiliary storage device or an external storage device of the host device. Such an electronic device 800 may be a solid state disk (SSD), a USB memory (Universal Serial Bus Memory), a secure digital (SD) card, a mini Secure Digital card (mSD) A Secure Digital High Capacity (SDHC), a Memory Stick Card, a Smart Media Card (SM), a Multi Media Card (MMC) ), An embedded multimedia card (eMMC), a compact flash (CF) card, and the like.

The operation characteristics of the electronic device can be improved by applying the above-described device isolation film structure to the cell array of the buffer memory 830 in the electronic device 800. [

10 is a block diagram briefly showing the structure of an electronic device according to another embodiment of the present invention.

The electronic device 900 of FIG. 10 may include an application processor 910, a memory device 920, a data communication portion 930, and a user interface 940.

The application processor 910 is an apparatus for controlling the operation of the electronic device 900 as a whole and controls and adjusts a series of processes of processing data according to an instruction input through the user interface 940 and outputting the result. The application processor 910 may be implemented as a multi-core processor to perform multi-tasking. In particular, the application processor 910 may include a memory controller 912, which controls the data input / output operations of the memory device 920, in the form of SoC. At this time, the memory controller 912 may include both a controller for controlling a volatile memory (e.g., a DRAM) and a controller for controlling a nonvolatile memory (e.g., FLASH). This memory controller 912 may include the memory controller 610 of FIG.

The memory device 920 stores data necessary for operation of the electronic device 900 or reads the stored data and provides the data to the memory controller 912 according to a control signal from the memory controller 912. [ Such a memory device 920 may include volatile memory and non-volatile memory. In particular, the device isolation film defining the active region in the memory cell array of the memory device 920 may be formed locally as an oxide film. For example, only the element isolation films formed under the word lines (the buried gates) WL1 to WLn in the device isolation film are formed as an oxide film locally, thereby improving the characteristics of the semiconductor device while preventing bridging between the word lines.

The data communication unit 930 performs data transmission / reception between the application processor 910 and the external device according to a predefined communication protocol. The data communication unit 930 may include a module capable of connecting with a wired network and a module capable of connecting with a wireless network. The wired network module may include a local area network (LAN), a universal serial bus (USB), an Ethernet, a power line communication (PLC), and the like. (CDMA), Time Division Multiple Access (TDMA), Frequency Division Multiple Access (FDMA), Wireless Local Area Network (WLAN) Zigbee, Ubiquitous Sensor Network (USN), Bluetooth, Radio Frequency Identification (RFID), Long Term Evolution (LTE), Near Field Communication (NFC) , A wireless broadband Internet (Wibro), a high speed downlink packet access (HSDPA), a wideband code division multiple access (WCDMA), an ultra wideband UWB), and the like.

The user interface 940 includes user input and output devices that allow a user to input data necessary for the portable electronic device 900 and output the processed result in the portable electronic device 900 to the user in the form of a voice signal or an image signal. For example, the user interface 940 includes a button, a keypad, a display (screen), a speaker, and the like.

The electronic device 900 described above may be a mobile phone, a smart phone, a tablet computer, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, a portable multimedia player (PMP), a personal navigation device or portable navigation device (PDN), a handheld game console, or an e-book. And can be implemented as a handheld device. In addition, the electronic device 900 may be embodied as an embedded system for performing a specific function in an automobile, a ship, or the like.

The operation characteristics of the electronic device can be improved by applying the above-described device isolation film structure to the cell array of the memory device 920 in the electronic device 900. [

11 is a block diagram briefly showing the structure of an electronic device according to another embodiment of the present invention.

The electronic device 1000 of FIG. 11 includes a processor 1010, a system controller 1020, and a memory device 1030. The electronic device 1000 may further include an input device 1042, an output device 1044, a storage device 1046, a processor bus 1052 and an expansion bus 1054.

The processor 1010 is an apparatus that controls the operation of the electronic device 1000 as a whole and processes (computes) the data (or command) input through the input devices 1042 and outputs the result to the output device 1044 Control and adjust the sequence of sending. Such a processor 1010 may comprise a conventional central processing unit (CPU) or microprocessor (MCU). The processor 1010 may be coupled to the system controller 1020 via a processor bus 1052 that includes an address bus, a control bus, and / or a data bus. The system controller 1020 is connected to an expansion bus 1054, such as a peripheral component interconnection (PCI). Accordingly, the processor 1010 can be connected to the system controller 1020 via an input device 1042 such as a keyboard or a mouse, an output device 1044 such as a printer or a display device, a hard disk drive (HDD), a solid state drive ) Or a storage device 1046 such as a CDROM. The processor 1010 may be implemented as a multi-core processor.

The system controller 1020 controls data input / output with the memory device 1030 and the peripheral devices 1042, 1044, and 1046 under the control of the processor 1010. [ The system controller 1020 may include a memory controller 1022 that controls data input / output to / from the memory device 1030. At this time, the memory controller 1022 may include the memory controller 610 of FIG. The system controller 1020 may include both a memory controller hub (MCH) and an input / output controller hub (ICU) of Intel Corporation. The system controller 1020 may include a processor 1010 and a processor 1010. The system controller 1020 may include a processor 1010 and a processor 1010. The system controller 1020 may include a processor 1010, As shown in FIG. Or only the memory controller 1022 in the system controller 1020 may be embedded in the processor 1010 or included in the processor 1010 in the form of SoC.

The memory device 1030 stores data (DATA) applied from the memory controller 1022 in accordance with a control signal from the memory controller 1022, reads the stored data, and outputs the read data to the memory controller 1022. Such a memory device 1030 may include the memory device 500 of FIG. That is, in this embodiment, the device isolation film that defines the active region in the memory cell array of the memory device 1030 may be formed of an oxide film locally. For example, only the element isolation films formed under the word lines (the buried gates) WL1 to WLn in the device isolation film are formed as an oxide film locally, thereby improving the characteristics of the semiconductor device while preventing bridging between the word lines.

Storage device 1046 stores data to be processed in electronic device 1000. Such a storage device includes a data storage device or an external storage device embedded in a computing system, and may include the memory system 800 of FIG.

The electronic device 1000 may be a personal computer, a server, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, A mobile phone, a smart phone, a digital music player, a portable multimedia player (PMP), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, , Global Positioning System (GPS), Voice Recorder, Telematics, Audio Visual System, Smart Television, and other embedded systems. And may include various electronic systems that operate.

The operating characteristics of the electronic device can be improved by applying the above-described device isolation film structure to the cell array of the memory device 1030 in the electronic device 1000. [

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, It should be regarded as belonging to the claims.

102 and 308: Element isolation films 102a and 308a:
102b, 102b-102c, 308b, 308c-308d:
104, 302: active area 106, 314: buried gate
108, 306: sidewall oxide film 110, 312: gate insulating film
112, 316: sealing insulating film 300: semiconductor substrate
304: Device isolation trench 310: Gate recess

Claims (16)

A first device isolation layer defining an active region and including a recess in which a gate region is etched;
A second isolation layer buried in the bottom of the recess;
A gate located above the second isolation film; And
And a sealing film located above the gate. The device according to claim 1, wherein the first isolation film
And a nitride film. The semiconductor device according to claim 2, wherein the second isolation film
Oxide film. The method according to claim 3, wherein the oxide film
High-density plasma (HDP) SiO ₂ . The semiconductor device according to claim 2, wherein the second isolation film
And a multilayer film in which an oxide film and a nitride film are stacked. The semiconductor device according to claim 5,
And is located on an inner side surface and a bottom surface of the recess so as to be in contact with a sidewall of the active region. 7. The method according to claim 6,
High-density plasma (HDP) SiO ₂ . 2. The method of claim 1,
And a fin structure protruding from the second isolation film in the gate region. The semiconductor device according to claim 1, wherein the second isolation film
Wherein the gate electrode is in contact with a sidewall of the active region and is located only at a lower portion of the gate. A device isolation layer defining an active region;
A gate recess in which the active region of the gate region and the isolation film are etched; And
And a gate formed under the gate recess,
The device isolation film
And an oxide film located locally only at a lower portion of the gate. 11. The method according to claim 10,
High-density plasma (HDP) SiO ₂ . 11. The method according to claim 10,
Wherein the gate electrode is in direct contact with a sidewall of the active region at a lower portion of the gate. 11. The method of claim 10,
And a fin structure protruding from the device isolation film in the gate region. A memory device for storing data according to the data input / output control signal and for reading the stored data; And
And a memory controller for generating the data input / output control signal and controlling a data input / output operation of the memory device,
The memory device
A first device isolation layer defining an active region and including a recess in which a gate region is etched;
A second isolation layer buried in the bottom of the recess;
A gate located above the second isolation film; And
And a sealing film overlying the gate. 15. The method of claim 14,
Wherein the first isolation film comprises a nitride film, and the second isolation film comprises an oxide film. 16. The device according to claim 15, wherein the second isolation film
(HDP) < _{RTI ID} = 0.0 > SiO2. ≪ / RTI >

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