KR20150057812A - Semiconductor apparatus and method of the same - Google Patents

Abstract

The present invention relates to a semiconductor device. More particularly, the present invention relates to a technique for reducing contact resistance and parasitic capacitance by changing a cell structure. A semiconductor device according to an embodiment of the present invention includes a device isolation layer which is formed with a lattice type on a semiconductor substrate and defines an active region; a gate structure which crosses the major axis direction of the active region; and a bit line structure which is formed in the upper part of the device isolation layer in the major axis direction of the active region.

Description

Technical Field [0001] The present invention relates to a semiconductor device and a method of forming the same,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a technique for reducing parasitic capacitance and contact resistance by changing a cell structure.

The semiconductor device can operate according to a predetermined purpose through a process of injecting impurities into a certain region of a silicon wafer or depositing a new material, and a typical example is a semiconductor memory device. Inside the semiconductor memory device, there are many elements such as a transistor, a capacitor, and a resistor for performing a predetermined purpose, and each element is connected through a conductive layer to exchange data or signals.

As semiconductor device manufacturing technology has been developed, efforts have been made to improve the degree of integration of semiconductor devices and to form more chips on one wafer. Accordingly, the minimum line width in the design rule is getting smaller to increase the degree of integration. In addition, semiconductor devices are required to operate at higher speeds while simultaneously reducing power consumption.

In order to improve the degree of integration, it is necessary not only to reduce the size of various components in the semiconductor device but also to reduce the length and width of the interconnecting wires. As a wiring used in the semiconductor memory device, a word line for transferring a control signal and a bit line for transferring data are exemplified. When the width of the word line and the bit line or the size of the cross section is reduced, the resistance which hinders the transfer of the control signal or data increases. Such an increase in resistance may slow transmission of signals and data in the semiconductor device, increase power consumption, and may further cause the operation device of the semiconductor memory device to operate.

Conversely, if the widths of the word lines and the bit lines are kept the same as conventional to prevent the increase of the resistance despite the increase in the degree of integration, the physical distance between the adjacent word lines or bit lines must be close to each other. Compared to a word line to which a control signal having a relatively high potential is transmitted, a bit line that transfers data transmitted from a unit cell capacitor may not normally transmit data due to an increase in parasitic capacitance. If the data can not be transferred through the bit line, the sense amplifier may not detect the data, which means that the semiconductor memory device can not output the data stored in the unit cell to the outside it means.

Embodiments of the present invention are intended to maximize the overlap region between a storage node contact and an active region to minimize resistance while reducing parasitic capacitance between a bit line and a storage node contact.

A semiconductor device according to an embodiment of the present invention includes: a device isolation layer formed in a lattice pattern on a semiconductor substrate to define an active region; A gate structure formed in a direction transverse to the major axis direction of the active region; And a bit line structure formed on the device isolation film in the major axis direction with the active region.

A method of forming a semiconductor device according to an embodiment of the present invention includes the steps of forming a lattice type device isolation film on a semiconductor substrate to define an active region; Forming a gate structure in a direction transverse to the major axis direction of the active region; Forming a bit line contact in contact with the active region; And forming a bit line structure to connect to the bit line contact over the isolation layer in a direction transverse to the major axis direction of the gate structure.

In this technique, the bit line is disposed on the device isolation film and the buried gate is disposed perpendicular to the active region, maximizing the overlap region between the storage node contact and the active region, thereby minimizing the resistance.

The technique also has the effect of reducing the capacitance between the bit line and the storage node contact by removing the overlap of the storage node contact and the bit line contact.

1 is a plan view and a sectional view showing a semiconductor device according to an embodiment of the present invention,
FIGS. 2A to 2R are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention,
3 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention,
4 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention,
5 is a block diagram briefly showing a configuration of a memory device according to an embodiment of the present invention;
6 is a block diagram briefly showing the configuration of an electronic device having a memory device according to an embodiment of the present invention;
Figure 7 illustrates an embodiment of the memory device of Figure 6;
8 is a block diagram schematically illustrating a configuration of a memory system according to another embodiment of the present invention.
9 is a block diagram schematically showing the structure of an electronic device according to another embodiment of the present invention;
10 is a block diagram briefly showing the structure of an electronic device according to another embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention.

The present invention relates to a semiconductor device having a 4F ² cell structure, in which a device isolation film is formed in a lattice shape to define an active region, and a bit line structure is formed on the device isolation film so that the active region and the bit line structure are parallel The storage node contact is formed so as to overlap with the active region as much as possible to minimize the resistance and minimize the parasitic capacitance by removing the adjacent portion of the bit line contact and the storage node contact by the separator.

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 1 to 10. FIG.

First, FIG. 1 is a sectional view (II) of a semiconductor device according to an embodiment of the present invention, taken along the line Y-Y 'in a plan view (i) and a plan view (i).

In a semiconductor device, an active region 101 is defined by forming a device isolation film 102, 103 in a lattice form on a semiconductor substrate 100. The gate structure 106 is formed in a line type in the direction crossing the major axis direction of the active region 101 and the bit line structure 120 is formed in the direction of the major axis of the active region 101, As shown in FIG. The bit line structure 120 and the active area 101 are connected by a bit line contact 119 and the bit line contact 119 overlaps the active area 101 and the device isolation layer 103, . A storage node contact 145 is formed so as to overlap with both ends of the active region 101 respectively and a storage node 147 is formed on the storage node contact 145.

", "

" 형태로 형성된다. 이때, 스토리지노드 콘택(145)은 x축으로는 비트라인 구조물(120)에 의해 분리되고, Y축으로는 스토리지노드 콘택 분리막(135, 139)에 의해 분리된다. 스토리지노드 콘택 분리막(135: 제 1 분리막)는 소자분리막(102) 상부에 형성되고, 스토리지노드 콘택 분리막(139: 제 2 분리막)는 비트라인 콘택(119) 상부에 형성된다. The storage node contact 145 is formed between the storage node contact separator 135 and the storage node contact separator 139. The storage node contact 145 also forms a first pattern in the major axis direction of the storage node contact separator 135 on the metal contact 113 and a second pattern in the second cross direction of the storage node contact separator 135, And one end of the first pattern and one end of the second pattern are connected to form a single pattern. At this time, the first pattern surrounds the major axis direction of the insulating film 129 and the second pattern surrounds the minor axis direction of the insulating film 129. One end of the first pattern is connected to one end of the second pattern, the other end of the first pattern is connected to the metal contact 113, and the other end of the second pattern is connected to the storage node contact separator 139 Respectively. Thus, the storage node contact 145 has a "

","

The storage node contacts 145 are separated by the bit line structure 120 along the x axis and separated by the storage node contact separators 135 and 139 along the Y axis. A contact isolation film 135 (first isolation film) is formed on the device isolation film 102 and a storage node contact isolation film 139 (second isolation film) is formed on the bit line contact 119.

The silicide films 111 and 112 and the metal contact 113 are stacked between the active region 101 and the bit line contact 119 or between the active region 101 and the storage node contact 145. The gate structure 106 also has a structure in which a gate conductive material 107 and a capping network 109 are stacked on a gate insulating film 105 formed in a trench (not shown) formed in the active region 101. The bit line structure 120 also includes bit line spacers 125 which are stacked with a bit line conductor 121 and a capping film 123 and which surround the stack structure. In addition, the unit cell according to the present invention has a structure in which one gate structure 106 is 2F and one bit line structure 120 is 2F and 4F ² structure.

", "

" 형태로 형성함으로써 스토리지노드(147)와의 접촉마진을 증가시킨다.In this manner, the device isolation films 102 and 103 are formed in a lattice shape to define the active region 101, and a storage node contact separator 139 is formed between the bit line contact 119 and the storage node contact 145 Thereby minimizing the parasitic capacitance. In addition, by forming the bit line structure 120 above the device isolation layer 103, the overlap region of the storage node contact 145 and the active region 101 is maximized to solve the resistance problem and the storage node contact 145 is referred to as "

","

Quot; shape to increase the contact margin with the storage node 147.

Hereinafter, a method of forming a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 2A to 2R. 2A to 2R, (i) is a plan view, and (ii) and (iii) are sectional views.

2A, an active region line pattern is formed by etching a semiconductor substrate 100 in a line type to form a device isolation film 103, and then a semiconductor substrate 100 is patterned in a direction transverse to the long axis direction of the active region line pattern. (100) is etched to form an isolation film (102), thereby separating the active region line pattern to form an active region (101). Thus, each active region 101 has a structure in which it is surrounded by a lattice type device isolation film 102, 103.

Referring to FIG. 2B, a gate structure 106 is formed in a direction transverse to the major axis direction of the active region 101. 2B is a plan view, FIG. 2B is a sectional view taken along the line X-X ', and FIG. 3I is a sectional view taken along the line Y-Y' in the plan view.

The active region 101 and the device isolation film 103 are etched to form a trench (not shown), and the device isolation film 103 is formed in the active region 101, as shown in the sectional view (X) So that the upper portion of the active region 101 is exposed. A gate insulating film 105 is formed in the active region 101 exposed along the trench of the trench and a gate conductive material 107 for use as a gate electrode is formed on the gate insulating film 105 and the element isolation film 103 And a capping film 109 is formed on the gate conductive material 107. Hereinafter, the gate conductive material 107 and the capping film 109 are referred to as a gate structure 106. At this time, the gate conductive material 107 may include a single material such as tungsten, polysilicon, or a combination material of a laminated structure, and the capping film 109 may be formed of a nitride material.

Referring to FIG. 2C, a portion of the active region 101 exposed in the cross-sectional view (iii) of FIG. 2B is etched to form a trench 110. Referring to FIG. 2D, ) Was subjected to silicidation (heat treatment) And silicide films 111 and 112 are formed. At this time, the silicide film 112 formed between the gate structures 106 is connected to the bit line contact to be formed later, and the two silicide films 111 formed outside the gate structure 106 are connected to the storage node contacts to be formed later Respectively. The silicide films 111 and 112 are provided to improve the contact resistance margin between the bit line contact to be formed later and the active region 101 and can be formed before the bit line contact is formed to maximize the length of the silicide films 111 and 112 have.

Referring to FIG. 2E, a contact material 113 is formed by performing a planarization process (cmp) after gap filling a metal material on the silicide films 111 and 112. The contact 113 is formed between the bit line contact and the silicide film 112 or the storage node contact and the silicide film 111 to be formed later so that damage to the silicide films 111 and 112 is prevented in forming the bit line contact hole or the storage node contact hole. . The metal material forming the contact 113 may include TiN, Ti, W, and the like.

Referring to FIG. 2F, a nitride film 115 and an oxide film 117 are sequentially stacked on the entire upper surface of the structure including the metal contact 113. At this time, it is preferable that the nitride film 115 is deposited thinly to prevent oxidation by the oxide film 117.

Next, a mask (not shown) for forming a bit line contact hole is deposited on the oxide film 117, and then the nitride film 115 and the oxide film 117 are partially etched to form a bit line contact hole (not shown). Next, a bit line contact 119 (not shown) is formed by forming a bit line contact hole (not shown).

Referring to FIG. 2G, (i) is a plan view and (ii) is a cross-sectional view taken along the line X-X 'in a plan view (i). A bit line structure 120 is formed on top of a bit line contact 119 and the bit line structure 120 as shown in plan view (i) is formed in a line shape and extends across the major axis direction of the gate structure 106 As shown in FIG.

In order to form the bit line structure 120, a bit line conductor 121 is formed on the bit line contact 119, a capping film 123 is formed on the bit line conductor 121, The bit line spacers 125 are formed to enclose both the tops and sidewalls of the line conductive material 121 and the capping film 123. At this time, a hole 127 is formed between the bit line structures 120. In addition, the bit line structure 120 may be a separator for separating the storage node contacts formed later in the X axis.

2 (h) is a plan view, (ii) is a cross-sectional view of the planar view (i) taken along the X-line, and (iii) is a cross-sectional view of the planar view (i) taken along the Y-line. An insulating material is applied to the holes 127 between the bit line structures 120 to form an oxide film 129. At this time, the oxide film 129 may be formed by etching with an oxidizing material or the like and performing a planarization process.

Hereinafter, (i) is a plan view and (ii) is a cross-sectional view of the plan view (i) taken along line Y-Y 'in FIGS. 2i to 2r.

Referring to FIG. 2I, a hard mask film 131 spaced apart from the oxide film 129 is formed. The hard mask film 131 may be formed of a polysilicon material and has a line pattern formed in the long axis direction of the gate structure 106 on top of two gate structures 106 crossing one active region.

Referring to FIG. 2J, spacers 133 are formed on both side walls of the hard mask film 131. The spacer 133 may be formed of a nitride material. The hard mask film 131 and the spacer 133 thus formed can be a separation film for separating the storage node contacts in the Y axis.

Referring to FIG. 2K, the lower oxide film 129 is etched using the hard mask film 131 and the spacer 133 as masks to remove a portion of the device isolation film 102, thereby exposing the device isolation film 102. At this time, the device isolation film 102 may be etched to the same height as the silicide films 111 and 112. The oxide film 129 and the device isolation film 102 are etched to form a storage node contact layer 135 by performing a planarization process in a hole (not shown).

Referring to FIG. 2L, the remaining hard mask layer 131 is removed through a strip process, and then the remaining portions of the spacer 133 and the storage node contact separator 135 are removed. And patterning is performed to form a hard mask film 138 for exposing the bit line contacts. 2L, the center portion of the remaining hard mask film 131 is removed by using a mask in FIG. 2K to form holes 137 (FIG. 2 The hard mask film 131 may be separated to form the hard mask film 138. In this case, At this time, it is preferable that the hole 137 is located above the bit line contact 119.

Referring to FIG. 2M, the oxide film 129 is etched using the hard mask film 138 as a mask to form a hole (not shown) and expose the bit line contact 119 under the hole. Thereafter, a nitriding material is applied to a hole (not shown), and a planarization process is performed to form a storage node separating film 139. The upper surface of the storage node contact separator 139 may be formed at the same height as the upper surface of the hard mask film 138.

Then, referring to FIG. 2N, the hard mask film 138 remaining in FIG. 2M is removed through an etching process or a strip process. At this time, a portion of the upper surface of the oxide film 129 is etched together with over etch, thereby forming a recess A. Thereafter, the hard mask film 138 is removed and polysilicon is deposited on the recesses A to form the hard mask film 140 again.

2O, a planarization process is performed to remove the upper portions of the hard mask film 138, the hard mask film 140 and the storage node contact separators 135 and 139 to remove a portion of the oxide film 129 and a hard mask So that the upper portion of the film 140 is exposed.

Referring to FIG. 2P, the oxide film 129 is etched using the remaining hard mask film 140 and the storage node contact separators 135 and 139 as a mask to form holes 143a and 143b. Therefore, the holes 143a and 143b are located on both side walls of the storage node contact separator 135.

", "

" 형태로 형성됨으로써, 추후 형성되는 스토리지노드와의 접촉면적이 증가하게 된다.Referring to FIG. 2Q, the remaining hard mask layer 140 is removed, a hard mask layer 140 is removed, a metal material is coated in the holes 143a and 143b, and a planarization process is performed. Node contact 145 is formed. At this time, the storage node contact 145 is formed between the storage node contact separator 135 and the storage node contact separator 139. The storage node contact 145 also forms a first pattern in the major axis direction of the storage node contact separator 135 on the metal contact 113 and a second pattern in the second cross direction of the storage node contact separator 135, And one end of the first pattern and one end of the second pattern are connected to form a single pattern. At this time, the first pattern surrounds the major axis direction of the insulating film 129 and the second pattern surrounds the minor axis direction of the insulating film 129. One end of the first pattern is connected to one end of the second pattern, the other end of the first pattern is connected to the metal contact 113, and the other end of the second pattern is connected to the storage node contact separator 139 Respectively. As such, the storage node contact 145 has a "

","

The contact area with the storage node to be formed later increases.

Referring to Figure 2r, a storage node 147 is formed on the storage node contact 145.

3 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.

3, the bit line contact 119 and the bit line structure 120 are formed by moving the bit line contact 119 to the left side in the same manner as in FIG. 1, FIG. 2A to FIG. 2R, It is possible to increase the overlapped area between the electrodes. Also, the distance between the adjacent active region 101 and the bit line contact 119 increases, thereby preventing the adjacent active region from being electrically connected to the bit line contact 119.

4 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.

A semiconductor device according to another embodiment of the present invention includes a bit line structure 120 formed by forming a bit line contact 119 at a position as shown in FIG. 1 of the present invention and moving only the bit line structure 120 to the left, And the bit line contact 119 can be increased.

5 is a block diagram briefly showing a configuration of a memory device according to an embodiment of the present invention.

The memory device 500 includes a memory cell array 510, a row decoder 520, a control circuit 530, a sense amplifier 540, a column decoder 550 and a data input / 560).

The memory cell array 510 includes a plurality of word lines WL1 to WLn (n is a natural number), a plurality of bit lines BL1 to BLn and a plurality of word lines WL1 to WLn and bit lines BL1 And a plurality of memory cells (not shown) connected between the memory cells BLn and BLn for storing data. Each memory cell includes a transistor that is a switching device that is turned on or off according to the voltage applied to the word lines WL1 to WLn, and each transistor includes a gate (not shown) and a source / drain region (junction region) ).

The row decoder 520 generates a word line selection signal (row address) for selecting a memory cell to which data is to be read or written and applies the word line selection signal (row address) to the word lines WL1 to WLn to select one of the plurality of word lines WL1 to WLn And selects any one of the word lines.

The control circuit 530 controls the operation of the sense amplifier 540 according to a control signal (not shown) input from the outside.

The sense amplifier 540 senses and amplifies the data of the memory cell and also stores the data in the memory cell. At this time, the sense amplifier 540 includes a plurality of sense amplifiers (not shown) for sensing and amplifying data corresponding to each of the plurality of bit lines BL1 to BLn, Amplifies the data of each of the plurality of bit lines BL1 to BLn in response to a control signal output from the control unit 530. [

The column decoder 550 generates column select signals for operating the sense amplifiers connected to the cells selected by the row decoder 520, and outputs the column select signals to the sense amplifier 540.

The data input / output circuit 560 transfers write data input from the outside to the sense amplifier 540 in accordance with a plurality of column select signals output from the column decoder 550, And outputs the sense amplifier amplified sense amplifiers 540 according to the selection signals.

The row decoder 520, the control circuit 530, the sense amplifier 540 and the column decoder 550 among the components of the memory device 500 described above are substantially identical to the corresponding components used in the conventional memory device And can be configured identically.

The memory device 500 is included in a memory cell array and is formed in a lattice form on a semiconductor substrate, and includes a device isolation film defining an active region, a gate structure formed in a direction transverse to the major axis direction of the active region, And a bit line structure formed on the device isolation layer in the major axis direction. Accordingly, the memory cell array 510 minimizes the parasitic capacitance of the bit line structure and the storage node contact, thereby increasing the data sensing margin and maximizing the overlap region of the storage node contact and the active region, thereby minimizing the resistance problem.

6 is a block diagram briefly illustrating the configuration of an electronic device having a memory device according to an embodiment of the present invention.

6 includes a memory controller 610, a memory interface (PHY) 620, and a memory device 630.

The memory controller 610 generates a data input / output control signal (command signal CMD, address signal ADD) for controlling the operation of the memory device 630 and outputs it to the memory device 630 through the memory interface 620 Thereby controlling the data input / output (READ / WRITE) operation of the memory device 630. The memory controller 610 includes a control device for controlling data input / output to / from memory devices in a typical data processing system. The memory controller 610 may be embedded in a processor of an electronic device such as a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), or in the form of a system on chip (SoC) Chip. ≪ / RTI > Although the memory controller 610 is shown as one block in Fig. 6, the memory controller 610 may include both a volatile memory controller and a non-volatile memory controller.

The memory controller 610 may be an integrated device electronics (IDE), a serial advanced technology attachment (SATA), a small computer system interface (SCSI), a redundant array of independent disks (SSD), a solid state disk (SSD) ), A PCMCIA (Personal Computer Memory Card International Association), a MultiMediaCard (MMC), an embedded MMC (eMMC), a Compact Flash (CF), a graphic card And a conventional controller for controlling a memory such as a memory.

The memory interface 620 provides a physical layer interface between the memory controller 610 and the memory device 630 and transmits and receives data between the memory controller 610 and the memory device 30 according to the clock signal CLK. And processes the timing of the data.

The memory device 630 includes a plurality of memory cells for storing data and stores the data DATA according to the control signals CMD and ADD from the memory controller 610 applied through the memory interface 620 Or reads the stored data and outputs it to the memory interface 620. At this time, the memory device 630 may include the memory device 500 of FIG. 5 described above.

Such a memory device 630 may include volatile memory and non-volatile memory. The volatile memory may include a dynamic random access memory (DRAM), a moblie DRAM, a static random access memory (SRAM), and the like. The nonvolatile memory may include a Nor Flash memory, a NAND flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a spin transfer random access memory (STTRAM), a magnetic random access memory (MRAM), and the like. In addition, although the memory device 630 is shown only as one block in FIG. 6, it may include a plurality of memory chips. When the memory device 630 is composed of a plurality of memory chips, the plurality of memory chips may be formed in a form of a plane mounted on a board (board) or a stack.

The memory device 630 includes a device isolation film formed in a lattice form on a semiconductor substrate and defining an active region, a gate structure formed in a direction transverse to the major axis direction of the active region, And a bit line structure formed on the bit line structure. Thus, the memory device 630 minimizes the parasitic capacitance of the bit line structure and the storage node contact, thereby increasing the data sensing margin and maximizing the overlap region of the storage node contact and the active region, thereby minimizing the resistance problem.

FIG. 7 is a diagram illustrating an embodiment of the memory device 630 of FIG.

7A is a view showing a state in which a plurality of memory chips 720 are mounted on a module substrate 710 configured to be plugged into a memory slot of a computer.

The semiconductor module 700 includes a plurality of memory chips 720 mounted on a module substrate 710 and a command link 730 through which signals ADD, CMD, and CLK for controlling the operation of the memory chips 720 are transferred. And a data link 740 through which data (DATA) input and output to and from the memory chips 720 are transferred.

In this case, each memory chip 720 may include the memory device 500 of FIG. 5 described above, and each memory chip 720 may include a device isolation film formed in a lattice form on a semiconductor substrate to define an active region, A gate structure formed in a direction transverse to the major axis direction of the region, and a bit line structure formed in the active region and above the device isolation film in the major axis direction. Accordingly, the memory device 500 minimizes the parasitic capacitance of the bit line structure and the storage node contact to increase the data sensing margin and maximizes the overlap region of the storage node contact and the active region, thereby minimizing the resistance problem.

In FIG. 7A, only the memory chips 720 are mounted on the front surface of the module substrate 710, but the memory chips 720 may be mounted on the rear surface of the module substrate 710. At this time, the number of memory chips 720 mounted on the module substrate 710 is not limited to that illustrated in FIG. The material and structure of the module substrate 710 are also not particularly limited.

FIG. 7B is a diagram illustrating another embodiment of the memory device of FIG. 6. FIG.

The memory device 750 may be formed by stacking a plurality of semiconductor layers (semiconductor chips) 752 in a stack structure, and at least one memory device 750 may be mounted on a board It may operate under the control of the memory controller 610 of FIG. At this time, the memory device 750 may include a structure in which the same semiconductor layers (chips) are connected through the penetrating electrodes TSV, or a structure in which different kinds of semiconductor layers (chips) are connected through the penetrating electrodes TSV have. 7B illustrates a structure in which signal transmission between the semiconductor layers is performed through the penetrating electrode TSV. However, the present invention is not limited to this, and the present invention can be applied to a structure in which layers are stacked through a tape having wire bonding, interposing, have.

At this time, the semiconductor layer 752 may include the memory device 500 of FIG. 5 described above. The semiconductor layer 752 is formed in a lattice form on a semiconductor substrate and includes a device isolation film defining an active region, a gate structure formed in a direction transverse to the major axis direction of the active region, Lt; RTI ID = 0.0 > a < / RTI > Accordingly, the memory device 500 minimizes the parasitic capacitance of the bit line structure and the storage node contact to increase the data sensing margin and maximizes the overlap region of the storage node contact and the active region, thereby minimizing the resistance problem.

8 is a block diagram briefly showing a configuration of an electronic device according to another embodiment of the present invention.

8 includes a data storage 810, a memory controller 820, a buffer (cache) memory 830, and an input / output (I / O) interface 840.

The data storage unit 810 stores data (DATA) applied from the memory controller 820 according to a control signal from the memory controller 820, reads the stored data, and outputs the read data to the memory controller 820. The data storage unit 810 includes a non-volatile memory that can store data without losing data even when the power is turned off. The data storage unit 810 includes a Nor Flash memory, a NAND flash memory, a phase change random access memory (PRAM) A Resistive Random Access Memory (RRAM), a Spin Transfer Torque Random Access Memory (STTRAM), a Magnetic Random Access Memory (MRAM), and the like.

The memory controller 820 decodes commands inputted from an external device (host device) through the input / output interface 840 and controls data input / output to the data storage 810 and the buffer memory 830 according to the decoded result do. This memory controller 820 includes the memory controller 620 of FIG. 8, the memory controller 820 includes a controller for controlling the nonvolatile memory 810 and a controller for controlling the buffer memory 830, which is a volatile memory, Lt; / RTI >

The buffer memory 830 temporarily stores data to be processed by the memory controller 820, that is, data to be input to and output from the data storage unit 810. The buffer memory 830 stores data (DATA) applied from the memory controller 820 in accordance with a control signal from the memory controller 820, reads the stored data, and outputs the read data to the memory controller 820. The buffer memory 830 includes a volatile memory such as a Dynamic Random Access Memory (DRAM), a Moblie DRAM, and a Static Random Access Memory (SRAM).

An input / output (I / O) interface 840 provides a physical connection between the memory controller 820 and an external device (host) so that the memory controller 820 receives control signals for data input / output from external devices, Allowing you to exchange data. The input / output (I / O) interface 840 may include one of a variety of interface protocols such as USB, MMC, PCI-E, SAS, SATA, PATA, SCSI, ESDI,

The electronic device 800 may be connected to a semiconductor substrate through a semiconductor substrate separately from a data storage unit 810, a memory controller 820, a buffer memory 830, and an input / output (I / O) And an electrode (Through Silicon Via, TSV). The electronic device 800 may include a plurality of through electrodes and may include various types of data such as a data storage unit 810, a memory controller 820, a buffer memory 830, and an input / output (I / O) And may be electrically connected directly or indirectly to the configuration.

The buffer memory 830 is formed in a lattice form on a semiconductor substrate and includes a device isolation film defining an active region, a gate structure formed in a direction transverse to the major axis direction of the active region, Lt; RTI ID = 0.0 > a < / RTI > Accordingly, the memory device 500 minimizes the parasitic capacitance of the bit line structure and the storage node contact to increase the data sensing margin and maximizes the overlap region of the storage node contact and the active region, thereby minimizing the resistance problem.

The electronic device 800 of Fig. 8 can be used as an auxiliary storage device or an external storage device of the host device. Such an electronic device 800 may be a solid state disk (SSD), a USB memory (Universal Serial Bus Memory), a secure digital (SD) card, a mini Secure Digital card (mSD) A Secure Digital High Capacity (SDHC), a Memory Stick Card, a Smart Media Card (SM), a Multi Media Card (MMC) ), An embedded multimedia card (eMMC), a compact flash (CF) card, and the like.

9 is a block diagram briefly showing the structure of an electronic device according to another embodiment of the present invention.

The electronic device 900 of FIG. 9 may include an application processor 910, a memory device 920, a data communication portion 930, and a user interface 940.

The application processor 910 is an apparatus for controlling the operation of the electronic device 900 as a whole and controls and adjusts a series of processes of processing data according to an instruction input through the user interface 940 and outputting the result. The application processor 910 may be implemented as a multi-core processor to perform multi-tasking. In particular, the application processor 910 may include a memory controller 912, which controls the data input / output operations of the memory device 920, in the form of SoC. At this time, the memory controller 912 may include both a controller for controlling a volatile memory (e.g., a DRAM) and a controller for controlling a nonvolatile memory (e.g., FLASH). Such a memory controller 912 may include the memory controller 610 of FIG.

The memory device 920 stores data necessary for operation of the electronic device 900 or reads the stored data and provides the data to the memory controller 912 according to a control signal from the memory controller 912. [ Such a memory device 920 may include volatile memory and non-volatile memory. In particular, the memory device 920 includes a plurality of memory cells for storing data.

The data communication unit 930 performs data transmission / reception between the application processor 910 and the external device according to a predefined communication protocol. The data communication unit 930 may include a module capable of connecting with a wired network and a module capable of connecting with a wireless network. The wired network module may include a local area network (LAN), a universal serial bus (USB), an Ethernet, a power line communication (PLC), and the like. (CDMA), Time Division Multiple Access (TDMA), Frequency Division Multiple Access (FDMA), Wireless Local Area Network (WLAN) Zigbee, Ubiquitous Sensor Network (USN), Bluetooth, Radio Frequency Identification (RFID), Long Term Evolution (LTE), Near Field Communication (NFC) , A wireless broadband Internet (Wibro), a high speed downlink packet access (HSDPA), a wideband code division multiple access (WCDMA), an ultra wideband UWB), and the like.

The user interface 940 includes user input and output devices that allow a user to input data necessary for the portable electronic device 900 and output the processed result in the portable electronic device 900 to the user in the form of a voice signal or an image signal. For example, the user interface 940 includes a button, a keypad, a display (screen), a speaker, and the like.

The electronic device 900 described above may be a mobile phone, a smart phone, a tablet computer, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, a portable multimedia player (PMP), a personal navigation device or portable navigation device (PDN), a handheld game console, or an e-book. And can be implemented as a handheld device. In addition, the electronic device 900 may be embodied as an embedded system for performing a specific function in an automobile, a ship, or the like.

Such an electronic device 900 includes through silicon vias (TSV) in the semiconductor substrate separately from the components such as the application processor 910, the memory device 920, the data communication unit 930, and the user interface 940 can do. The electronic device 900 may include a plurality of penetrating electrodes and may be electrically or indirectly connected to various configurations, such as an application processor 910, a memory device 920, a data communication portion 930, and a user interface 940 have. The memory device 920 includes a device isolation film formed in a lattice form on a semiconductor substrate and defining an active region, a gate structure formed in a direction transverse to the major axis direction of the active region, Lt; RTI ID = 0.0 > a < / RTI > Thus, the memory device 920 minimizes the parasitic capacitance of the bit line structure and the storage node contact, thereby increasing the data sensing margin and maximizing the overlap region of the storage node contact and the active region, thereby minimizing the resistance problem.

10 is a block diagram briefly showing the structure of an electronic device according to another embodiment of the present invention.

The electronic device 1000 of FIG. 10 includes a processor 1010, a system controller 1020, and a memory device 1030. The electronic device 1000 may further include an input device 1042, an output device 1044, a storage device 1046, a processor bus 1052 and an expansion bus 1054.

The processor 1010 is an apparatus that controls the operation of the electronic device 1000 as a whole and processes (computes) the data (or command) input through the input devices 1042 and outputs the result to the output device 1044 Control and adjust the sequence of sending. Such a processor 1010 may comprise a conventional central processing unit (CPU) or microprocessor (MCU). The processor 1010 may be coupled to the system controller 1020 via a processor bus 1052 that includes an address bus, a control bus, and / or a data bus. The system controller 1020 is connected to an expansion bus 1054, such as a peripheral component interconnection (PCI). Accordingly, the processor 1010 can be connected to the system controller 1020 via an input device 1042 such as a keyboard or a mouse, an output device 1044 such as a printer or a display device, a hard disk drive (HDD), a solid state drive ) Or a storage device 1046 such as a CDROM. The processor 1010 may be implemented as a multi-core processor.

The system controller 1020 controls data input / output with the memory device 500 and the peripheral devices 1042, 1044, and 1046 under the control of the processor 1010. The system controller 1020 may include a memory controller 1022 that controls data input / output to the memory device 500. At this time, the memory controller 1022 may include the memory controller 610 of FIG. The system controller 1020 may include both a memory controller hub (MCH) and an input / output controller hub (ICU) of Intel Corporation. The system controller 1020 may include a processor 1010 and a processor 1010. The system controller 1020 may include a processor 1010 and a processor 1010. The system controller 1020 may include a processor 1010, As shown in FIG. Or only the memory controller 1022 in the system controller 1020 may be embedded in the processor 1010 or included in the processor 1010 in the form of SoC.

The memory device 1030 stores data (DATA) applied from the memory controller 1022 in accordance with a control signal from the memory controller 1022, reads the stored data, and outputs the read data to the memory controller 1022. Such a memory device 1030 may include the memory device 610 of FIG. That is, in this embodiment, the memory device 1030 includes a device isolation film formed in a lattice form on a semiconductor substrate to define an active region, a gate structure formed in a direction transverse to the major axis direction of the active region, And a bit line structure formed on the device isolation layer in a direction of the first direction. Thus, the memory device 1030 minimizes the parasitic capacitance of the bit line structure and the storage node contact, thereby increasing the data sensing margin and maximizing the overlap region of the storage node contact and the active region, thereby minimizing the resistance problem.

Storage device 1046 stores data to be processed in electronic device 1000. Such a storage device includes a data storage device or an external storage device embedded in the computing system, and may include the memory system 800 of FIG.

The electronic device 1000 may be a personal computer, a server, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, A mobile phone, a smart phone, a digital music player, a portable multimedia player (PMP), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, , Global Positioning System (GPS), Voice Recorder, Telematics, Audio Visual System, Smart Television, and other embedded systems. And may include various electronic systems that operate.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, It should be regarded as belonging to the claims.

100: semiconductor substrate 101: active region
102, 103: Element isolation film 105: Gate insulating film
107: gate conductive material 109: capping film
111, 112: a silicide film 113: a contact
115: nitride film 117: oxide film
119: bit line contact 121: bit line conductor
123: capping film 125: spacer
120: bit line structure 106: gate structure
129: oxide film 131, 138, 140: hard mask film
133: Spacer 135, 139: Storage node contact separator
147: storage node

Claims (20)

A device isolation layer formed in a lattice form on a semiconductor substrate to define an active region;
A gate structure formed in a direction transverse to the major axis direction of the active region; And
And a bit line structure formed on the active region and above the isolation film in a major axis direction
≪ / RTI > The method according to claim 1,
And a bit line contact formed to overlap the active region and the upper portion of the device isolation film to connect the active region and the bit line structure. The method of claim 2,
Wherein the bit line structure is formed on the bit line contact,
Wherein the active region is formed to overlap the active region and the upper portion of the device isolation film. The method according to claim 1,
And a bit line contact formed over the active region,
Wherein the bit line structure is formed on the bit line contact,
Wherein the active region is formed to overlap the active region and the upper portion of the device isolation film. The method of claim 2,
A storage node contact formed to overlap with both ends of the active region, respectively; And
A storage node formed on the storage node contact,
Further comprising: The method of claim 5,
Wherein the storage node contact has a structure in which one end of a first pattern extending in a first direction is connected to one end of a second pattern extending in a second direction perpendicular to the first direction, A semiconductor device. The method of claim 5,
Further comprising a storage node contact isolation for isolating the storage node contact,
The storage node contact separator comprises:
A first separator formed on the isolation layer; And
And a second isolation layer formed on the bit line contact. The method of claim 7,
Wherein the storage node contacts are separated in the X-axis by the bit line structure and separated in the Y-axis by the storage node contact separator. The method according to claim 1,
Wherein the semiconductor device has a bit line structure of 2F, a gate structure of 2F, and a unit cell of 4F ² structure. The method of claim 5,
A silicide film between the active region and the bit line contact or the storage node contact; And
Between the silicide film and the bit line contact or the storage node contact,
The semiconductor device further comprising: Defining an active region by forming a lattice type element isolation film on a semiconductor substrate;
Forming a gate structure across the major axis direction of the active region;
Forming a bit line contact in contact with the active region; And
Forming a bit line structure to connect to the bit line contact over the device isolation film in a direction transverse to the major axis direction of the gate structure
And forming a gate electrode on the semiconductor substrate. The method of claim 11,
The bit line contact
Wherein the active region is formed to extend over the active region and the device isolation film and connected to the bit line structure. The method of claim 11,
Wherein the bit line contact is formed to overlap the active region and the upper portion of the isolation film to connect the active region and the bit line structure. 14. The method of claim 13,
The step of forming the bit line structure
Wherein the bit line structure is formed to overlap the active region and the device isolation film. The method of claim 12,
The step of forming the bit line contact
Forming a silicide film on the active region;
Forming an insulating film on the silicide film;
Forming a bit line contact hole by etching the insulating film; And
And filling the bit line contact holes with a metal material to form the bit line contacts
Wherein the semiconductor device is a semiconductor device. 16. The method of claim 15,
And forming a contact between the silicide film and the insulating film. 15. The method of claim 14,
Forming storage node contacts that overlap with both ends of the active region, respectively; And
Further comprising forming a storage node on top of the storage node contact. 18. The method of claim 17,
Before forming the storage node contact,
Forming a storage node contact isolation layer for isolating the storage node contact. ≪ Desc / Clms Page number 21 > 18. The method of claim 17,
Wherein forming the storage node contact separator comprises:
Forming an insulating film on the entire upper surface of the structure including the bit line contact;
Forming a first hard mask film for forming a first separation film on the insulating film;
Forming a spacer on a sidewall of the first hard mask film;
Etching the insulating layer to expose the isolation layer using the first hard mask layer and the spacer as a mask to form a first hole;
Filling the first hole with a nitride material to form a first separation layer;
Forming a second hard mask over the insulating film;
Etching the insulating layer to expose the bit line contact using the second hard mask layer as a mask to form a second hole; And
And filling the second hole with a nitride material to form a second separation layer
And forming a gate electrode on the semiconductor substrate. The method of claim 19,
Wherein forming the storage node contact comprises:
Etching the part of the insulating film to remove the second hard mask film and remove the second hard mask film;
Forming a third hard mask layer in a region where the second hard mask film is removed and a region where the insulating film is partially etched;
Performing a planarization process to expose a portion of the insulating film and to remove the top surface of the third hard mask film so that the top surface of the third hard mask film is the same as the top surface of the exposed insulating film;
Etching the sidewall of the insulating layer using the third hard mask layer as a mask to form a third hole;
Removing the third hard mask film; And
A step of embedding a metal material in a region where the third hole and the third hard mask film are removed,
And forming a gate electrode on the semiconductor substrate.

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