KR20150005509A - Nonvolatile resistive memory element with a metal nitride containing switching layer - Google Patents

Abstract

The nonvolatile resistive memory element has a novel variable resistance layer comprising a metal nitride, a metal oxide-nitride, a bimetal oxide-nitride, or a multilayer stack thereof. One method of forming a novel variable resistance layer includes an interlayer deposition process wherein metal nitride layers are disposed between the metal oxide layers and then converted into a substantially homogeneous layer by an anneal process. Another method of forming a novel variable resistive layer includes an in-situ deposition procedure wherein various ALD processes are sequentially interleaved to form a metal oxide-nitride layer. Alternatively, the metal oxide is formed, nitrided, and annealed to form a variable resistance layer, or a metal nitride is formed, oxidized, and annealed to form a variable resistance layer.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a nonvolatile memory device having a metal nitride-

The present invention relates to non-volatile resistive memory elements, and more particularly, to a non-volatile resistive memory element having a metal nitride containing switching layer and a method of forming the same.

Non-volatile memory devices are used in devices that require permanent data storage, such as digital cameras and digital music players, and computer systems. Electrically Erasable Programmable Read Only Memory (EPROM) and NAND Flash are currently non-volatile memory technologies. However, as device dimensions shrink, scaling issues challenge traditional non-volatile memory technology. This led to the study of alternative nonvolatile memory technologies, including resistive switching nonvolatile memory.

A resistive switching nonvolatile memory is formed using bistable, i.e., memory elements having two stable states with different resistances. The bistable memory element may be placed in a high resistance state or a low resistance state by application of a suitable voltage or current. Voltage pulses are typically used to switch a bistable memory element from one resistance state to another. Subsequently, non-destructive read operations may be performed on the memory element to verify the value of the data bits stored therein.

The resistive switching memory device reduces the required current and voltages required to reliably set, reset and / or determine desired "on" and " off & , The power consumption of the device, the resistance heating of the device, and the cross-talk between adjacent devices.

In view of the foregoing, non-volatile resistive switching memory devices having reduced current and voltage requirements are desired in the art.

summary

Embodiments of the present invention provide a ReRAM nonvolatile memory device having a novel variable resistance layer and a method of forming the same. The novel variable resistive layer may comprise a metal nitride, an oxide-nitride, a two-metal oxide-nitride, or a multilayer stack thereof.

According to one embodiment of the present invention, a nonvolatile memory device includes a first electrode layer formed on a substrate, a second electrode layer, and a variable resistance layer disposed between the first electrode layer and the second electrode layer, The variable resistance layer includes a metal nitride layer, a metal oxide-nitride layer, a bimetal oxide-nitride layer, or a combination thereof.

According to another embodiment of the present invention, a method of forming a variable resistance layer in a nonvolatile memory device includes forming a first electrode layer on a substrate, depositing a first electrode layer on the first electrode layer using an atomic layer deposition (ALD) Depositing a first metal layer on the oxidized first metal layer using an ALD process, depositing a second metal layer on the first metal layer using an ALD process, heating the first metal layer while exposing the first metal layer to an oxygen- Depositing a layer of nitrogen on the first and second metal layers, exposing the second metal layer to a nitrogen-containing gas to diffuse nitrogen into the second metal layer, and forming a first metal layer and a second metal layer between the first and second electrode layers To form a second electrode layer.

According to another embodiment of the present invention, a method of forming a variable resistance layer in a nonvolatile memory device includes forming a first electrode layer on a substrate, depositing a first metal layer on the first electrode layer using an ALD process, , Heating the first metal layer to oxidize the first metal layer while exposing the first metal layer to an oxygen containing gas, exposing the first metal layer to a reactive nitrogen containing gas to form nitrogen And forming a second electrode layer such that the first metal layer is disposed between the first electrode layer and the second electrode layer.

According to still another embodiment of the present invention, a method of forming a variable resistance layer in a nonvolatile memory device includes the steps of forming a first electrode layer on a substrate, forming a metal nitride layer on the first electrode layer, - performing an oxidation process on the metal nitride layer to form a nitride layer, and forming a second electrode layer such that a metal oxide-nitride layer is disposed between the first and second electrode layers do.

According to another embodiment of the present invention, a method includes forming a first electrode layer on a substrate, depositing a metal oxide layer on the first electrode layer, nitriding the metal oxide layer to form a metal oxide- And forming a second electrode layer such that the metal oxide-nitride nitride layer is disposed between the first electrode layer and the second electrode layer.

A more particular description of embodiments of the invention, briefly summarized above, may be had by reference to the accompanying drawings, in order that the above-recited features of the embodiments of the present invention may be understood in detail. It should be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments do.
1 is a perspective view of a memory array of memory devices constructed in accordance with embodiments of the present invention.
2A is a schematic cross-sectional view of a memory device constructed in accordance with an embodiment of the present invention.
Figure 2B schematically illustrates a memory device configured to allow current to flow in a forward direction through a memory device, in accordance with embodiments of the present invention.
Figure 3 schematically illustrates exemplary log-log plots of measured current (I) values for an applied voltage (V) in an exemplary embodiment of a memory device having a resistive switching memory element.
4 is a schematic cross-sectional view of a memory device formed from a series of deposited layers, including a novel variable resistive layer, in accordance with embodiments of the present invention.
5 presents a flowchart of method steps in a process sequence for forming a memory device, in accordance with one embodiment of the present invention.
Figure 6 illustrates a flowchart of method steps in a process sequence for forming a variable resistance layer using an interlayer deposition procedure, in accordance with one embodiment of the present invention.
7A schematically illustrates a cross-sectional view of a variable resistance layer formed before a heat treatment, according to an embodiment of the present invention.
Fig. 7B schematically illustrates a cross-sectional view of a variable resistance layer formed after heat treatment according to an embodiment of the present invention. Fig.
8A schematically illustrates a cross-sectional view of another variable resistance layer formed before heat treatment, according to an embodiment of the present invention.
8B schematically illustrates a cross-sectional view of another variable resistance layer formed after heat treatment, according to an embodiment of the present invention.
Figure 9A schematically illustrates a cross-sectional view of a variable resistive layer comprising a multilayer stack having a first layer and a second layer, prior to the heat treatment step, in accordance with an embodiment of the present invention.
FIG. 9B schematically illustrates a cross-sectional view of a variable resistance layer formed after a heat treatment step, in accordance with an embodiment of the present invention. FIG.
10 presents a flowchart of method steps in a process sequence for forming a variable resistance layer using an intralayer deposition procedure, in accordance with embodiments of the present invention.
11 presents a flowchart of method steps in a process sequence for forming a variable resistance layer, in accordance with an embodiment of the present invention.
12 presents a flowchart of method steps in a process sequence for forming a variable resistance layer, in accordance with an embodiment of the present invention.
For clarity, the same reference numerals have been used, where applicable, to designate the same elements that are common to the drawings. It is contemplated that features of one embodiment may be included in other embodiments without additional recitation.

The materials used as the variable resistance layer of the nonvolatile resistance memory element generally need to have bistable characteristics and are preferably capable of operating with a low switching voltage and switching current. Embodiments of the present invention provide a resistive random access memory (ReRAM) nonvolatile memory device having a novel variable resistance layer that meets these requirements. The novel variable resistive layer may comprise a metal nitride, an oxide-nitride, a two-metal oxide-nitride, or a multilayer stack thereof.

1 is a perspective view of a memory array 100 of memory devices 200 constructed in accordance with embodiments of the present invention. The memory array 100 may be part of a larger memory device or other integrated circuit structure, such as a system-on-a-chip type device. The memory array 100 may be formed as part of a high capacity non-volatile memory integrated circuit that may be used in various electronic devices such as digital cameras, mobile phones, portable computers, and music players. For clarity, the memory array 100 is illustrated as a single layer memory array structure. However, memory arrays, such as memory array 100, may also be stacked vertically to create multi-layer memory array structures.

Each of the memory devices 200 includes a non-volatile resistive switching memory device, such as a resistive random access memory (ReRAM) device. The memory device 200 includes a novel memory element 112 that may be formed from one or more material layers 114. The material layers 114 include a novel variable resistive layer comprising a metal nitride, a metal oxide-nitride, or a combination of each, and is described below in conjunction with FIG. In some embodiments, the memory device 200 also includes a current steering device as described below with Figures 2A and 2B.

A read and write circuit (not shown) is connected to memory device 200 using electrodes 102 and orthogonally disposed electrodes 118. Electrodes 102 and electrodes 118 are also referred to as "bit lines" and "word lines" and are used to read and write data from memory devices 200 to memory devices 112. The individual memory devices 200 or groups of memory devices 200 may be addressed using the appropriate sets of electrodes 102 and electrodes 118. [

2A is a schematic diagram of a memory device 200 configured in accordance with an embodiment of the present invention. The memory device 200 includes a memory element 112 and in some embodiments a current steering device 216 which are both disposed between the electrodes 102 and the electrodes 118. [ In one embodiment, the current steering device 216 includes a pn junction diode, a pin diode, a transistor (not shown) disposed between the electrode 102 and the memory element 112, or between the electrode 118 and the memory element 112. In one embodiment, , ≪ / RTI > or other similar devices. In some embodiments, the current steering device 216 includes two or more layers of semiconductor material, such as two or more doped silicon layers, configured to permit or inhibit current flow in different directions through the memory element 112 . The read and write circuit 150 is also connected to the memory device 200 through the electrodes 102 and electrodes 118 as shown. The read and write circuit 150 is configured to sense the resistance state of the memory device 200 as well as set its resistance state.

2B schematically illustrates a memory device 200 configured to allow current to flow in a forward direction ( " I ⁺ ") through a memory device 200, in accordance with embodiments of the present invention. However, due to the design of the current steering device 216, the reduced current may also flow in the opposite direction through the device by application of a reverse bias to the electrodes 102 and electrodes 118 have.

3 illustrates exemplary log-log plots of measured current (I) values for an applied voltage (V) in an exemplary embodiment of a memory device 200 having a resistive switching memory element 112 Are schematically illustrated. The resistance switching memory element may be placed in two stable resistance states: LRS along the IV curve of the low resistance state (LRS) curve 320, or LRS along the IV curve of the high resistance state (HRS) HRS.

Typically, the memory device 200 is operated between two applied voltages (e.g., V _SET (e.g., -3 volts) and V _RESET (e. G., +4 volts) The LRS curve 320 is obtained by sweeping the voltage applied to the electrode layers 102 and 118. [ On the other hand, by sweeping the voltages applied to the electrode layers 102 and 118 between the two applied voltages (e.g., between V _SET and V _RESET ) while the memory device 200 is in the high-resistance state, A curve 310 is obtained. Accordingly, the resistance switching memory element 112 may be in either the high resistance state (HRS) or the low resistance state (LRS). The resistive switching memory element 112 in the memory device 200 may be selectively selected by the read and write circuit 150 to switch between its resistive states. The current steering element 216 is used to adjust (e.g., allow or inhibit) the current so that current flows through only the desired memory cells when the appropriate set of word lines and bit lines and / or electrodes are selected do.

During a "set" operation, when a "set" switching pulse (e.g., a pulse at the V _SET voltage level) is applied and propagated through the memory device due to the physical and electrical characteristics of the variable resistive layer 206, The resistance switching memory element 112 of the memory device 200 may switch from HRS to LRS (e.g. along the path of arrow 330). The current flowing through the memory device 200 by applying a "set" switching pulse to the memory device 200 is set to an initial "set" Current level, I _{SET (i)} , to the final "set" current level, I _{SET (f)} .

During the "reset" operation, the variable resistive layer 206 also generates a reset signal when the "reset" switching pulse (e.g., a pulse at the V _RESET voltage level) (Along the path of arrow 340) from the LRS to the HRS. The current flowing through the memory device 200 varies from an initial "reset" current level, I _{RESET (i)} , to a final " _{reset & (f)} . < / RTI >

During a read operation, the logic state of the resistive switching memory element 112 in the memory device 200 is controlled by applying a sense voltage to the appropriate set of electrodes 102 and 118 (i.e., Quot; read "voltage _VREAD (e.g., applying a sense pulse of about +0.5 volts (V) voltage level). Depending on its history, the resistive switching memory element 112 addressed in this manner may be in either the high resistance state (HRS) or the low resistance state (LRS). Thus, the resistance of the resistive switching memory element 112 determines what digital data is stored in the resistive switching memory element 112. For example, if the resistance switching memory element 112 is in the low resistance state LRS, the resistance switching memory element 112 may be said to include a logic one (i.e., a "1" bit). On the other hand, when the resistance switching memory element 112 is in the high resistance state (HRS), the resistance switching memory element 112 may be said to include a logic zero (i.e., a "0" bit).

During a programming operation, the state of the memory element may be changed by application of appropriate programming signals to the appropriate sets of electrode layers 102 and 118. [ In one example, initially, the resistance switching memory element 112 may be in a high resistance state (e.g., store a logic "0 "). The high resistance state (HRS) of the resistance switching memory element 112 may be sensed by the read and write circuitry 150 using electrodes 102 and 118 (Figure 2a). For example, the read and write circuit 150 may apply a read voltage pulse of the V _READ voltage level (e.g., +0.5 V) to the resistance switching memory element 112, the resulting "off" current level (I _oFF) flowing through can be detected.

Next, when it is desired to store a logic "1" in the memory device 200, the resistance switching memory element 112 needs to be placed in its low resistance state LRS. This is accomplished by applying a "set" voltage pulse of voltage level V _SET (e.g., -2 V to -4 V) across electrodes 102 and 118 using read and write circuitry 150 . In one configuration, applying a negative voltage pulse of the V _SET voltage level to the resistive switching memory element 112 causes the resistive switching memory element 112 to operate in its low resistance state LRS, . The resistance switching memory element 112 is changed so that after the elimination of the "set" voltage pulse V _SET , the resistance switching memory element 112 is characterized to be in the low resistance state LRS). The change in the resistance state of the resistance switching memory element 112 causes the de-biasing of the device to cause traps formed in the variable resistance layer in the memory element to be redistributed or charged (i.e., "trap-mediated" ). V _SET and V _RESET are generally referred to herein as "switching voltage ". The low resistance state (L RS) of the resistance switching memory element can be sensed using the read and write circuitry 150. When a read voltage pulse of the V _READ level is applied to the resistive switching memory element 112, the read and write circuit 150 determines whether the resistive switching memory element 112 is in its low resistance state LRS, Quot; ON "current value (I _ON ).

In the memory cells when they want to store a logic "0" at 200, a resistance switching memory element 112 back to its high resistance state once (HRS), V _RESET (e.g., +2 V to +5 V) By applying a positive "reset" voltage pulse of the voltage level to the memory device. When the read and write circuit 150 applies V _RESET to the resistance switching memory element 112, it switches to its high resistance state (HRS), along arrow 340. When the reset voltage pulse V _RESET is removed from the resistance switching memory element 112, the resistance switching memory element 112 is once again determined whether it is in the high resistance state HRS by applying a read voltage pulse at the V _READ voltage level Can be tested.

Some discussion of resistive switching memory devices here mainly provides bipolar switching examples, but some embodiments of resistive switching memory devices may use unipolar switching where the "set" and "reset" Without departing from the scope of the invention described herein.

In embodiments of the present invention in which the novel variable resistance layer comprises a metal nitride or oxide-nitride, the defects or traps that provide multiple resistance capabilities for the variable resistance layer may be nitrogen bacillus do. Embodiments of the variable resistance layer, that is, the variable resistance layer 206 are described below in conjunction with FIG. The change in the resistance state of the memory element 112 may result in a change in the resistance state of the memory element 112, such as, for example, "trap-adjustment " due to redistribution or charging of traps or defects in the variable resistance layer of the memory element 112 when the memory device 200 is reverse- "I think. Defects or traps, generally considered oxygen vacancies, are formed during film deposition and / or post processing of the variable resistance layer. For example, oxygen vacancies are likewise produced by non-stoichiometric material composition of the host oxide material in the variable resistance layer.

4 is a schematic cross-sectional view of a memory device 200 formed from a series of deposited layers, including a novel variable resistive layer 206, in accordance with embodiments of the present invention. In the embodiment illustrated in Figure 4, the memory device 200 is formed on portions of the surface of a substrate 201 (e.g., a silicon substrate or an SOI substrate), or is integrated do. It is noted that the terms of relative orientation used herein in relation to embodiments of the present invention are intended to be illustrative only and not to limit the scope of the present invention. In particular, terms such as " on ", "on "," below ", etc. are intended to mean that the substrate 201 on which embodiments are formed is a " lower " Used under the assumption.

In the embodiment illustrated in FIG. 4, the memory device 200 includes a memory element 112 disposed between the electrodes 102, 118. The memory element 112 is a non-volatile resistive memory element that includes a variable resistive layer 206. In other embodiments, the memory device 200 further includes a selective intermediate electrode and optional current steering device 216 disposed between the electrode 118 and the variable resistive layer 206.

The electrodes 102 and 118 are formed from conductive materials having a desired work function that is matched to the band gap of the material constituting the variable resistance layer 206. [ In some configurations, electrodes 102 and 118 are formed from different materials such that electrodes 102 and 118 have a work function that is different by a desired value, e. G., 0.1 eV, 0.5 eV, 1.0 eV, do. For example, in one embodiment, electrode 102 is comprised of TiN having a work function of 4.5-4.6 eV, while electrode 118 is an n-type polysilicon having a work function of approximately 4.1-4.15 eV . Other electrode materials suitable for use in electrode 102 and / or electrode 118 are p-type polysilicon (4.9-5.3 eV), n-type polysilicon, transition metal, transition metal alloy, transition metal nitride, (4.5-4.6 eV), tantalum nitride (4.7-4.8 eV), molybdenum oxide (~ 5.1 eV), molybdenum nitride (4.0-5.0 eV), iridium (4.6-5.3 eV), iridium oxide 4.2 eV), ruthenium (~ 4.7 eV), and ruthenium oxide (~ 5.0 eV). Other possible electrode materials include titanium / aluminum alloys (4.1-4.3 eV), nickel (~ 5.0 eV), tungsten nitride (~ 4.3-5.0 eV), tungsten oxide (5.5-5.7 eV), aluminum (4.2-4.3 eV) , Copper or silicon doped aluminum (4.1-4.4 eV), copper (~4.5 eV), hafnium carbide (4.8-4.9 eV), hafnium nitride (4.7-4.8 eV), niobium nitride (~4.9 eV), tantalum carbide 5.1 eV), tantalum silicon nitride (~4.4 eV), titanium (4.1-4.4 eV), vanadium carbide (~5.15 eV), vanadium nitride (~5.15 eV), and zirconium nitride (~4.6 eV). In some embodiments, the electrode 102 is made of a material selected from the group consisting of Ti, W, Ta, Co, Mo, Ni, V, ) Metal, a metal alloy, or a metal formed from an element selected from the group consisting of aluminum (Al), copper (Cu), platinum (Pt), palladium (Pd), iridium (Ir), ruthenium (Ru) Metal nitride or metal carbide. In one example, the electrode 102 comprises a metal alloy selected from the group consisting of titanium / aluminum alloys (Ti _x Al _y ), or silicon doped aluminum (AlSi).

The variable resistance layer 206 includes a dielectric material that can be switched between two or more stable resistance states. In some embodiments, the variable resistive layer 206 has a thickness between about 10 and about 100 Angstroms. Many materials are available in variable resistance layers for nonvolatile resistive memory devices, including various oxides and all transition metals, such as hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum It was explored for use. In contrast to such materials, according to embodiments of the present invention, the variable resistive layer 206 comprises a metal nitride, a metal oxide-nitride, a bimetal oxide-nitride, or a multi-layer stack thereof, Quot; set "voltage V _SET and a " reset " voltage V _RESET . For example, a memory device having a variable resistive layer 206 comprised of hafnium nitride (HfN _x ) may provide a better switching performance than a substantially identical memory device in which the variable resistive layer 206 is composed of hafnium oxide (HfO _x ) Performance.

Metal nitrides suitable for use as a resistance variable layer 206 are, in particular, HfN _x, ZrN _X, SiN _X, AlN _X, TiN _X, V _X N _Y (for example, V ₂ N), NbN _X (e. Nb ₂ N, Nb ₄ N ₃ , NbN), WN _X (e.g., WN ₂ ). Suitable metal nitrides can be deposited by reactive physical vapor deposition (PVD) and chemical vapor deposition (CVD) processes known in the art. In some embodiments, an atomic layer deposition (ALD) process may be used to deposit such metal nitrides.

Suitable metal oxide-nitrides for use as the variable resistance layer 206 include, among others, HfO _x N _y , ZrO _x N _y , AlO _x N _y , and TaO _x N _y . As used herein, the term "metal oxide-nitride" refers to a metal that is a combination of metal oxides and metal nitrides, as opposed to metal oxynitride, where the metallic chemical element is bonded to the ON structure. According to embodiments of the present invention, such metal oxide-nitride films may be deposited using an "interlayer deposition" ALD process; "Intralayer deposition" ALD process; A combination of metal oxide deposition, nitridation, and annealing processes; Or a combination of metal nitride deposition, oxidation and anneal processes. These different processes are described below in conjunction with Figures 6-12.

Bimetal oxide-nitrides suitable for use as the variable resistance layer 206 include two metallic or semi-metallic elements and include the following films: Hf _x Si _y O _z N _(1-xyz) , Zr _x Si _y O _z N _(1-xyz) , Hf _x Zr _y O _z N _(1-xyz) , and Hf _x Al _y O _z N _(1-xyz) . The bimetallic oxide-nitrides may be deposited by a co-sputtering PVD process or by a series of ALD processes similar to those used for the deposition of metal oxide-nitride. Alternatively, the bimetallic oxide-nitrides may be deposited via an interlayer deposition ALD process or an in-situ deposition ALD process. Such ALD processes are described below in conjunction with Figures 6-12. Suitable metals for such bimetallic oxide-nitride include hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), vanadium (V), niobium (Nb), and tungsten ) And suitable semi-metallic elements include silicon (Si).

Figure 5 illustrates a flowchart of method steps in a process sequence 500 for forming a memory device 200, in accordance with one embodiment of the present invention. Although method steps have been described in conjunction with memory device 200 in FIG. 4, those skilled in the art will appreciate that the formation of other resistive switching memory devices using process sequence 500 is within the scope of the present invention.

As shown, the method 500 begins at step 502, where the electrode 118 is formed on the substrate 201. In one embodiment, the electrode 118 is a highly doped polysilicon layer formed on the substrate 201 using conventional CVD or ALD type polysilicon deposition techniques. In one embodiment, the electrode 118 comprises polysilicon and is between about 50 and about 5000 Angstroms thick.

In step 504, a variable resistive layer 206 is formed on the electrode 118 using one or more deposition processes. Embodiments of the present invention include various methods of depositing the variable resistive layer 206 and are dependent in part on the particular composition of the variable resistive layer 206. [ Exemplary methods of depositing the variable resistance layer 206 are described below in conjunction with Figures 6-12.

At step 506, the electrode 102 is formed over the variable resistive layer 206 as shown in FIG. 4 using one or more materials suitable for the electrodes 102 listed above in conjunction with FIG. Electrode 102 may be formed using a deposition process such as PVD, CVD, ALD, or other similar process. In one embodiment, the electrode 102 is between about 500 Å thick and about 1 urn thick.

In step 508, the formed memory device 200 is heat treated, for example, through an anneal process. The temperature and duration of the anneal process are a function of the configuration of the memory device 200 and the materials contained in the memory device 200. For example, in some embodiments, the anneal process occurs at a temperature greater than about 550 < 0 > C. In other embodiments, the anneal process occurs at a temperature greater than about 600 < 0 > C. In yet other embodiments, the anneal process occurs at a temperature greater than about 1000 < 0 > C. The duration of the anneal process may also vary widely, for example, between about 30 seconds and 20 minutes, depending on the configuration of the memory device 200. [ In addition, annealing using a gas mixture such as vacuum anneal, oxygen anneal, hydrogen / argon mixture, and other anneal processes known in the art are within the scope of the present invention. Similarly, multiple heat treatment steps may be performed on the memory device 200 without departing from the scope of the present invention. For example, a thermal process may be performed during or after multiple steps of method 500.

As noted above, the variable resistive layer 206 may comprise a metal nitride, a metal oxide-nitride, a bimetal oxide-nitride, or a multi-layer stack thereof. Various techniques can be used to deposit metal nitrides such as PVD, ALD, and CVD processes known in the art. On the other hand, multilayer stacks of metal oxide-nitride, bimetallic oxide-nitride, and metal oxide-nitride are described in the "interlayer deposition" process described in conjunction with FIGS. 6-9; The " in-layer deposition " process described in conjunction with Figure 10; A combination of the metal oxide film forming process, the nitriding process, and the optional annealing process described in conjunction with Fig. 11; Or a combination of the metal nitride film formation process, the oxidation process, and the optional anneal process, which are described in conjunction with FIG. 12, in accordance with various embodiments of the present invention.

Figure 6 illustrates a flow chart of method steps in a process sequence 600 for forming a variable resistive layer 206 using an "interlayer deposition" procedure, in accordance with one embodiment of the present invention. In method 600, a metal oxide-nitride layer is formed by sequentially interleaving different ALD processes wherein metal nitride layers are disposed between the metal oxide layers and then converted to a substantially homogeneous layer by an anneal process . Although method steps have been described in conjunction with memory device 200 in FIG. 4, those skilled in the art will appreciate that the formation of other variable resistive layers using process sequence 600 is within the scope of the present invention.

As shown, method 600 begins at step 601, where a metal layer is formed on a suitably prepared and activated surface, such as the surface of electrode 118 after being hydroxylated. The metal layer is formed by exposing the prepared and activated surface of the electrode 118 to a suitable precursor. For example, for deposition of hafnium (Hf) layer, tetrakis (dimethylamido) hafnium (Hf (NMe _{2) 4),} tetrakis (ethylmethylamido) hafnium (Hf (NMeEt) _4), and / or tetrakis (diethylamido) hafnium (Hf (NEt _{2) 4)} it may be a precursor to such. In another example, tetrakis (dimethylamido) zirconium (Zr (NMe ₂ ) ₄ ), tetrakis (ethylmethylamido) zirconium (Zr (NMeEt) ₄ ) and / Or tetrakis (diethylamido) zirconium (Zr (NEt ₂ ) ₄ ) may be used. Generally, the metal layer formed in step 601 is on the order of one monolayer thickness. In some embodiments, a selective purge process is performed at the completion of step 601 to remove residual precursors from the ALD chamber.

In step 602, the metal layer deposited in step 601 is subjected to an oxidation process to form a metal oxide (MO _x ) layer. For example, the metal layer is exposed to an oxygen source such as water vapor or ozone (O _3). In some embodiments, the oxidation process is performed for a duration and at an oxygen concentration level that completely oxidizes the metal layer. In some embodiments, a selective purge process is performed at the completion of step 602 to remove residual oxygen source gas from the ALD chamber.

In step 603, a second metal layer is deposited on the metal oxide layer formed in step 602 using the process described in step 601. [ In some embodiments, the second metal layer deposited in step 603 has the same composition as the first metal layer deposited in step 601. In some embodiments,

In step 604, the metal layer deposited in step 603 undergoes a nitridation process to form a metal nitride layer MN _x . For example, the metal layer is exposed to reactive nitrogen-containing gas such as ammonia (NH _3). When exposed to the metal layer, nitrogen in the reactive nitrogen-containing gas diffuses into the metal layer. In some embodiments, the nitridation process is performed for a duration and at a nitrogen concentration level that completely nitride the metal layer. In some embodiments, a selective purge process is performed at the completion of step 604 to remove residual reactive nitrogen-containing gas from the ALD chamber.

At step 605, a determination is made as to whether the desired thickness of the variable resistive layer 206 has been reached. Since the ALD process is used to form metal layers in method 600, each metal oxide and metal nitride layer is on the order of a single monolayer. Consequently, in order to form the variable resistive layer 206 with a suitable thickness (e.g., 10-100 A), multiple cycles of steps 601-604 are generally performed (e.g., 2 To 20 times or more). If the required number of metal layers have been deposited, the method 600 proceeds to step 606. [ If not, the method 600 returns to step 601.

At step 606, the stack of alternating metal oxides and metal nitride is heat treated, for example, by a heat treatment at step 508 of method 500. The duration and temperature of the heat treatment step 606 depends on the particular metal and thickness of the variable resistive layer 206 formed in steps 601-605. Upon completion of step 606, the stack of alternating metal oxides and metal nitride is converted into a substantially homogeneous layer of metal oxide-nitride.

Figure 7A schematically illustrates a cross-sectional view of a variable resistive layer 206 formed in steps 601-604 of method 600 prior to the heat treatment of step 606, in accordance with an embodiment of the present invention. As shown, the variable resistive layer 206 includes a metal oxide (MO _x ) layer 701 and a metal nitride (MN _x ) layer 702. According to different embodiments of the present invention, the variable resistive layer 206 comprises a plurality of alternating layers of a metal oxide (MO _x ) layer 701 and a metal nitride (MN _x ) layer 702, wherein The metal contained therein may be selected from the group consisting of hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), vanadium (V), niobium (Nb), tungsten , And may be any metal suitable for use as the variable resistance layer 206 in the memory device 200. [ 7A includes only a single metal oxide (MO _x ) layer 701 and a single metal nitride (MN _x ) layer 702. For simplicity, the variable resistance layer 206 in FIG. Indeed, the number of alternating metal oxide (MO _x ) layers 701 and metal nitride (MN _x ) layers 702 may be selected such that the variable resistance layer 206 has a desired thickness for proper operation of the memory device 200 , 2 to 20 or more. Also, in some embodiments, after the metal nitride (MN _X ) layer 702 is first deposited, a metal oxide (MO _x ) layer 701 is deposited.

FIG. 7B schematically illustrates a cross-sectional view of variable resistance layer 206 formed after heat treatment step 606 in method 600, in accordance with an embodiment of the present invention. As shown, after such heat treatment, the variable resistive layer 206 comprises a substantially homogeneous metal oxide-nitride (MO _x N _y ) layer 703, which includes a metal oxide layer (MO _x ) 701 ) And a metal nitride (MN _x ) layer 702 are thermally annealed. Thus, in such embodiments, the variable resistive layer 206 comprises a metal oxide-nitride formed on the electrode 118 by annealing alternating layers of metal oxide and metal nitride after depositing the alternate layers.

In some embodiments, the method 600 may be used to form a bimetallic oxide-nitride. In such embodiments, a first metal oxide (M1O _x ) layer is formed at the desired surface in steps 601 and 602 and a second metal nitride (M2O _x ) layer is formed at steps 603 and 604, where The first metal and the second metal may be any metal suitable for use as the variable resistance layer 206 in the memory device 200. The first metal oxide (M1O _x) layer and a second metal nitride (M2O _x) layer is then combined in the annealing process, the second metal oxide - to form a substantially homogeneous layer of nitride material. In some embodiments, either the first metal or the second metal is a semi-metallic element such as silicon, and after the anneal process in step 606, a metal silicon oxide-nitride (e.g., Hf _x Si _y O _z N _(1-xyz) ) layer is formed.

Figure 8A schematically illustrates a cross-sectional view of a variable resistance layer 206 formed in steps 601-604 of method 600 prior to the heat treatment of step 606, in accordance with an embodiment of the present invention. As shown, the variable resistance layer 206 includes a first metal oxide (M1O _x ) layer 801 and a second metal nitride (M2N _x ) layer 802. For clarity, the variable resistance layer 206 includes only a single first metal oxide (M1O _x ) layer 801 and a single second metal nitride (M2N _x ) layer 802, but in fact, The number of layers of oxide (M1O _x ) layers 801 and second metal nitride (M2N _x ) layers 802 may range from 2 to 100 nm so that the variable resistance layer 206 has a desired thickness for proper operation of the memory device 200. 20 or more. Further, in some embodiments, after the second metal nitride (M2N _x ) layer 802 is first deposited, a first metal oxide (M1O _x ) layer 801 is deposited. FIG. 8B schematically illustrates a cross-sectional view of variable resistance layer 206 formed after heat treatment step 606 in method 600, in accordance with an embodiment of the present invention. Like the illustrated bar, after such heat treatment, the resistance variable layer 206, a substantially homogeneous second metal oxide-containing nitride (M1 _x M2 _y O _z N _(1-xyz)) layer 803, which is the 1 metal oxide layer (M1O _x ) 801 and a second metal nitride (M2N _x ) layer 802 are annealed. The second metal nitride (M2N _x ) layer 802 is a silicon nitride (SiN) layer, and the second metal nitride (M2N _x ) layer 802 is a silicon nitride (SiN) layer. In an exemplary embodiment, the first metal oxide (MlO _x ) layer 801 is a hafnium oxide (HfO _x ) a metal oxide-nitride (M1 _x M2 _y O _z N _(1-xyz)) layer 803 is a substantially homogeneous layer of _{Hf x Si y O z N (} 1-xyz).

The inclusion of silicon in the bimetallic oxide-nitride in layer 803 can improve the switching characteristics of variable resistance layer 206 by increasing the crystalline-limit temperature of variable resistance layer 206 . This is because the addition of silicon to the variable resistance layer 206 forms thermally metastable amorphous nitride. In the case of Hf _x Si _y O _z N _(1-xyz) , HfO _x is a metal bond and SiN is a covalent bond. The combination of two amorphous nitrides, one having a metal bond and one having a covalent bond, provides a relatively higher crystallization temperature, which is higher than the thermal budget for the memory device 200. Thus, in such embodiments, after the thermal anneal takes place in an integration flow for the memory device 200, the variable resistive layer 206 remains in an amorphous state.

In some embodiments, the interlayer deposition procedure of method 600 may be used to form a multi-layer stack of materials for the variable resistance layer 206. For example, the multilayer stack may include a metal oxide or nitride as the first layer and a metal oxide-nitride as the second layer. In such embodiments, the first layer may be deposited using techniques currently known in the art, such as ALD, PVD, and CVD, while the second layer may be deposited using the method 600 have. In one embodiment, after the ALD process is used to deposit the first layer of metal oxide or metal nitride, the interlayer deposition process of method 600 is performed as a continuation of the ALD process in the same chamber, - Form a nitride layer. In an alternate embodiment, the interlayer deposition procedure of method 600 is used to form a metal oxide-nitride layer as a first layer in the variable resistive layer 206, and a subsequent ALD process is performed in the same ALD chamber to form a variable resistance layer 206, a metal oxide or a metal nitride is formed as a second layer. In another embodiment, the multi-layer stack of materials for the variable resistive layer 206 may comprise a bimetal oxide-nitride as one layer and a metal oxide or metal nitride as the second layer. For example, the second metal oxide shown in Fig. 8b-nitride similar to the second metal oxide and (M1 _x M2 _y O _z N _(1-xyz)) layer 803-nitride layer, a first layer of a multilayer stack on the Or a metal oxide or metal nitride layer similar to the metal oxide layer (MO _x ) 701 or the metal nitride (MN _x ) layer 702, as shown in Figure 7, Or may be formed as two layers. Each layer of such a multilayer stack may be formed by a plurality of ALD deposition cycles (e.g., 2 to 20 or more).

9A schematically illustrates a cross-sectional view of a variable resistive layer 206 including a multi-layer stack having a first layer 901 and a second layer 902 prior to a heat treatment step, in accordance with an embodiment of the present invention. The first layer 901 is a metal oxide (MO _x ) or a metal nitride (MN _X ) layer and the second layer 902 is a metal oxide-nitride layer. The first layer 901 may be a single layer of metal oxide or metal nitride deposited by various techniques known in the art. As shown, the second layer 902 includes a plurality of alternating layers, that is, a metal oxide layer (MO _x ) 701 and a metal nitride (MN _X ) ≪ / RTI > FIG. 9B schematically illustrates a cross-sectional view of a variable resistive layer 206 formed after a heat treatment step such as step 606 in method 600, in accordance with an embodiment of the present invention. Like the illustrated bar, after such heat treatment, the second layer 902, a metal oxide (MO _x) layer 701 and a metal nitride (MN _X) layer 702, when annealed, formed a metal oxide-nitride (MO _x N _y ) layer 703. Thus, in such embodiments, the variable resistive layer 206 comprises a multi-layer stack of materials that may have advantageous properties when used as a resistive switching material. For example, in some embodiments, each layer in a multi-layer stack may advantageously have different functions. In particular, one or more layers of the multi-layer stack may serve as a variable resistance layer while other layers of the multi-layer stack may assist the variable resistance layer portion of the multi-layer stack in performing the switching function. This assistance may be in the form of acting as a current limiter layer or providing a doping source for the variable resistance layer portion of the multilayer stack.

In some embodiments, the variable resistive layer 206 may comprise different ALD processes in an "in-layer deposition" procedure to deposit a single layer of metal oxide-nitride or other desired nitride containing material as part of the variable resistive layer 206 And sequentially interleaving. The sequence of different ALD processes is repeated until a desired thickness of the nitride containing material is achieved.

Figure 10 illustrates a flow chart of method steps in a process sequence 1000 for forming a variable resistance layer 206 using an in-layer deposition procedure, in accordance with embodiments of the present invention. In method 1000, two different layers of material are formed and subsequently annealed to form a substantially uniform layer of material (e. ≪ RTI ID = 0.0 > Forming a material layer. Although method steps have been described in conjunction with memory device 200 in FIG. 4, those skilled in the art will appreciate that the formation of other variable resistive layers using process sequence 1000 is within the scope of the present invention.

As shown, the method 1000 begins at step 1001, where a metal layer is formed on a suitably dispensed and activated surface, such as the surface of the electrode 118 after being hydroxylated. The ALD metal layer deposition in step 1001 may be substantially similar to that in step 601 described above in method 600 and forms a metal layer whose thickness is formed on the order of one single layer.

In step 1002, the metal layer deposited in step 1001 is subjected to an oxidation process to form a metal oxide (MO _x ) layer. The oxidation process of step 1002 may be substantially similar to that described in step 602 of method 600, except that the oxidation process of step 1002 is not designed to completely oxidize the metal layer have. Instead, step 1003 begins before the metal layer can be fully oxidized. In this way, the deposited metal oxide (MO _x ) layer may comprise a combination of a metal oxide and a metal nitride.

In step 1003, the partially oxidized metal layer is exposed to a reactive nitrogen-containing gas such as ammonia. Note that step 1003 only begins shortly after the start of step 1002, so that the metal layer can be nitrided and oxidized. Depending on the particular metal layer being deposited in step 1001 and the particular oxygen and nitrogen sources used in steps 1002 and 1003, the relative rates of oxidation and nitridation processes may be controlled by controlling the concentration of oxygen source and nitrogen containing gas . In this way, a metal layer, i.e., an oxide-nitride layer, comprising a combination of a metal oxide (MO _x ) and a metal nitride (MN _x ) is formed. In some embodiments, at the end of step 1003, a selective purge process is performed to remove residual oxygen source gas and nitrogen containing gas from the ALD chamber. It is noted that in some embodiments of method 1000, the nitridation process at step 1003 may be initiated prior to the oxidation process at step 1002.

At step 1004, a determination is made as to whether the desired thickness of the variable resistive layer 206 has been reached. Since the ALD process is used to form the metal oxide-nitride layer in method 1000, each metal oxide-nitride layer is of a single monolayer thickness. Consequently, in order to form the variable resistance layer 206 with a suitable thickness (e.g., 10 to about 100 ANGSTROM), a large number of cycles of steps 1001-1003 are generally performed (e.g., , 2 to 20 times or more). Once the required number of metal layers has been deposited, the method 1000 ends. Otherwise, 1000 returns to step 1001.

In some embodiments, the in-layer deposition procedure of method 1000 may be used to form a bimetal oxide-nitride. In such embodiments, at step 1001, a second metal layer is formed on the first metal layer using a second ALD process. For example, after the hafnium layer has been deposited using any technically feasible ALD process known in the art, a silicon layer is deposited on the hafnium layer using any ALD process known in the art. Along therewith, the oxidation process of step 1002 and the nitridation process of step 1003 form a layer of hafnium silicon oxide-nitride (Hf _x Si _y O _z N _(1-xyz) ).

In some embodiments, the in-layer deposition procedure of the method 1000 may be used to form a multi-layer stack of materials for the variable resistance layer 206. For example, the multilayer stack may include a metal oxide or metal nitride as the first layer and a metal oxide-nitride or bimetallic oxide-nitride as the second layer. In such embodiments, the first layer may be deposited using techniques currently known in the art, such as ALD, PVD, and CVD, while the second layer may be deposited using the method 1000 have. For example, in one embodiment, after the ALD process is used to deposit the first layer of metal oxide or metal nitride, the in-layer deposition procedure of method 1000 is performed as a continuation of the ALD process in the same chamber, To form a metal oxide-nitride layer or a bimetallic oxide-nitride layer. Each layer in the multilayer stack may be formed by a plurality of ALD deposition cycles (e.g., 2 to 20 times or more).

In an alternative embodiment, an in-layer deposition procedure of method 1000 is performed to form a metal oxide-nitride layer as a first layer in the variable resistive layer 206, and a subsequent ALD process is performed in the same ALD chamber, And a metal oxide or a metal nitride is formed as a second layer in the second insulating layer 206. In another embodiment, the multi-layer stack of materials for the variable resistance layer 206 may comprise a bimetal oxide-nitride as one layer and a metal oxide or metal nitride as the second layer, wherein the bimetal oxide- The layer is formed using method 1000 and the metal oxide or metal nitride layer is formed using standard ALD or other known deposition process.

In some embodiments, the variable resistive layer 206 is formed by a combination of a metal nitride film deposition process, an oxidation process, and an optional anneal process. One such embodiment is described below in conjunction with FIG.

11 presents a flowchart of method steps in a process sequence 1100 for forming a variable resistance layer 206, in accordance with an embodiment of the present invention. Although the method steps have been described in conjunction with memory device 200 in FIG. 4, those skilled in the art will appreciate that the formation of other variable resistive layers using process sequence 1100 is within the scope of the present invention.

As shown, method 1100 begins at step 1101, where the metal nitride layer is deposited on a desired surface, such as the surface of electrode 118 in FIG. A metal nitride layer, in particular, comprise any metal nitrides suitable for use in the variable resistance layer (206) including a HfN, ZrN, SiN, AlN, TiN _X, V _X N _Y, NbN _X, and WN _X It is possible. Deposition of the metal nitride layer may be performed using any suitable deposition method known in the art, including reactive PVD, CVD, and ALD. In some embodiments, the metal nitride layer is deposited as a single layer using PVD or CVD processes, and in other embodiments, the metal layer is deposited as an ALD metal layer < RTI ID = 0.0 > Is deposited using multiple cycles of the deposition process.

In step 1102, the metal nitride layer formed in step 1102 is subjected to an oxidation process to form a metal oxide-nitride. Suitable oxidation processes include thermal oxidation, rapid thermal oxidation (RTO) and oxygen plasma treatment in an oxide furnace. The process parameters of the oxidation process of step 1103 may be selected based on the composition and thickness of the metal layer deposited in step 1101. [

In optional step 1103, a thermal anneal process is used to form a substantially homogeneous metal oxide-nitride layer. The temperature and duration of the anneal process is a function of the material and thickness of the variable resistive layer 206. In some embodiments, the thermal annealing process occurs immediately after step 1102. [ In other embodiments, the thermal anneal process in step 1103 occurs later in the fabrication of the memory device 200, such as during the thermal process described in step 508 of method 500.

In some embodiments, the variable resistive layer 206 is formed by a combination of a metal oxide deposition process, a nitridation process, and an optional anneal process. One such embodiment is described below in conjunction with FIG.

12 presents a flowchart of method steps in a process sequence 1200 for forming a variable resistive layer 206, in accordance with an embodiment of the present invention. Although method steps have been described in conjunction with memory device 200 in FIG. 4, those skilled in the art will appreciate that the formation of other variable resistive layers using process sequence 1200 is within the scope of the present invention.

As shown, method 1200 begins at step 1201, where the metal oxide layer is deposited on a desired surface, such as the surface of electrode 118 in FIG. The metal layer may comprise any metal oxide suitable for use in the variable resistance layer 206 comprising HfO, ZrO, SiO, and AlO. Deposition of the metal oxide layer may be performed using any suitable deposition method known in the art, including PVD, CVD, and ALD processes.

In step 1202, the metal oxide layer deposited in step 1201 undergoes a nitridation process to form a metal oxide-nitride. Suitable nitridation processes include decoupled plasma nitridation (DPN) and rapid thermal nitridation (RTN). The process parameters of the nitridation process of step 1202 may be selected based on the composition and thickness of the metal oxide layer deposited in step 1201. [

In step 1203, an optional thermal anneal process is used to form a substantially homogeneous metal oxide-nitride layer. The temperature and duration of the anneal process is a function of the material and thickness of the variable resistive layer 206. In some embodiments, the thermal annealing process occurs immediately after step 1202. [ In other embodiments, the thermal anneal process in step 1203 occurs later in the fabrication of the memory device 200, such as during the thermal process described in step 508 of method 500.

Although embodiments of the present invention have been described herein with respect to resistive switching memory elements used to form memory arrays, embodiments of the present invention may be implemented in other resistive memory devices Lt; / RTI >

In short, embodiments of the present invention provide a non-volatile resistive memory element having a novel variable resistance layer comprising a metal nitride, a metal oxide-nitride, a bimetallic oxide-nitride, or a combination thereof. One advantage of the present invention is that the use of metal nitride and / or metal oxide-nitride as the variable resistance layer can provide low programming and erase voltage and current. Another advantage is that the present invention provides a large number of additional materials that can be used as a variable resistance layer and each additional material has its own physical properties, e.g., work function, crystalline limit temperature, resistivity, etc. . As a result, materials for the variable resistance layers suitable for integration into a specific device can be selected more easily. In addition, the desired film properties of the variable resistive layer may be obtained by varying process parameters during film formation of the variable resistive layer, and / or by varying the composition of the switching layer (e.g., by using a multi- , By using a multilayer film stack, or by changing the order of the layers disposed in such a stack).

While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims (20)

As a nonvolatile memory element,
A first layer operable as an electrode layer;
A second layer operable as an electrode layer; And
And a third layer operable as a variable resistance layer disposed between the first layer and the second layer,
Wherein the third layer comprises a metal nitride layer, a metal oxide-nitride layer, a bimetal oxide-nitride layer, or a combination thereof,
The metal is a group of chemical elements consisting of hafnium (Hf), zirconium (Zr), tantalum (Ta), titanium (Ti), vanadium (V), niobium (Nb), tungsten (W) / RTI > The method according to claim 1,
Wherein the third layer comprises a multi-layer stack. 3. The method of claim 2,
Wherein the multi-layer stack comprises a metal oxide-nitride layer. The method according to claim 1,
Wherein the bimetallic oxide-nitride layer comprises silicon and other metallic chemical elements. The method according to claim 1,
The third _{layer, HfN X, ZrN X, SiN} X, AlN X, HfO x N y, ZrO x N y, AlO x N y, TaO x N y, Hf x Si y O z N (1-xyz) , of at least one material selected from the group consisting of _{Zr x Si y O z N (} 1-xyz), Hf x Zr y O z N (1-xyz), and _{Hf x Al y O z N (} 1-xyz) Wherein the non-volatile memory device comprises a non-volatile memory device. The method according to claim 1,
And the third layer has a thickness between about 10 and 100 Angstroms (A). As a method for forming a nonvolatile memory element,
Forming a first layer, wherein the first layer is operable as an electrode; forming the first layer;
Depositing a second layer comprising a metal layer over the first layer using an atomic layer deposition (ALD) process;
Heating the metal layer while exposing the metal layer to an oxygen-containing gas to oxidize the metal layer of the second layer;
Depositing a third layer comprising a metal layer over the oxidized second layer using an ALD process;
Exposing the metal layer of the third layer to a nitrogen containing gas to diffuse nitrogen into the metal layer of the third layer; And
Forming a fourth layer operable as an electrode, wherein the second layer and the third layer are disposed between the first layer and the fourth layer. A method of forming a nonvolatile memory device. 8. The method of claim 7,
Wherein oxidizing the metal layer of the second layer comprises completely oxidizing the metal layer. 8. The method of claim 7,
Wherein diffusing nitrogen into the metal layer of the third layer comprises completely nitriding the metal layer of the third layer. 8. The method of claim 7,
Further comprising performing a thermal anneal process to form a substantially homogeneous material from the third metal nitride layer and the second metal oxide layer. ≪ RTI ID = 0.0 > 11. < / RTI > 8. The method of claim 7,
Wherein the metal of the second layer and the metal of the third layer comprise different metallic chemical elements. ≪ RTI ID = 0.0 > 18. < / RTI > 12. The method of claim 11,
Wherein one of the second layer and the third layer comprises silicon. 12. The method of claim 11,
The second layer and the third layer may be formed of at least one of hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), vanadium (V), niobium (Nb), and tungsten W). ≪ RTI ID = 0.0 > 11. < / RTI > As a method for forming a nonvolatile memory element,
Forming a first layer operable as a first electrode layer;
Depositing a second layer comprising a metal layer over the first layer using an ALD process;
Heating the metal layer while exposing the metal layer to an oxygen-containing gas to oxidize the metal layer of the second layer;
Exposing the metal layer to a reactive nitrogen containing gas to diffuse nitrogen into the metal layer of the second layer; And
Forming a third layer operable as an electrode layer, wherein the metal layer of the second layer is disposed between the first layer and the third layer. A method of forming a nonvolatile memory device. 15. The method of claim 14,
Exposing the metal layer of the second layer to a reactive nitrogen containing gas is performed simultaneously with exposing the metal layer to an oxygen containing gas. 15. The method of claim 14,
Further comprising depositing a fourth layer over the second layer and between the first layer and the third layer, the fourth layer comprising a metal layer, wherein the fourth layer is deposited using an ALD process, / RTI > 17. The method of claim 16,
Wherein depositing the metal layer of the fourth layer over the second layer is performed prior to the step of oxidizing the metal layer of the second layer and before diffusing nitrogen into the metal layer of the second layer Of the nonvolatile memory element. 17. The method of claim 16,
Wherein depositing the metal layer of the fourth layer over the second layer is performed after the step of oxidizing the metal layer of the second layer and after diffusing nitrogen into the metal layer of the second layer And wherein the metal layer of the fourth layer comprises a chemical element different from the metal layer of the second layer. 19. The method of claim 18,
And exposing the metal layer of the fourth layer to a reactive nitrogen containing gas to diffuse nitrogen into the metal layer of the fourth layer. As a method for forming a nonvolatile memory element,
Forming a first layer operable as an electrode;
Depositing a second layer comprising a metal oxide layer over the first layer;
Performing a nitridation process on the metal oxide layer of the second layer to form a metal oxide-nitride layer; And
Forming a third layer operable as an electrode layer, the step of forming the third layer, wherein the metal oxide-nitride layer of the second layer is disposed between the first layer and the third layer, / RTI > A method of forming a non-volatile memory device,

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