KR20100014713A - Methods for forming nonvolatile memory elements with resistive-switching metal oxides - Google Patents

Abstract

Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed by depositing a metal-containing material on a silicon-containing material. The metal-containing material may be oxidized to form a resistive-switching metal oxide. The silicon in the silicon-containing material reacts with the metal in the metal-containing material when heat is applied. This forms a metal suicide lower electrode for the nonvolatile memory element. An upper electrode may be deposited on top of the metal oxide. Because the silicon in the silicon-containing layer reacts with some of the metal in the metal-containing layer, the resistive-switching metal oxide that is formed is metal deficient when compared to a stoichiometric metal oxide formed from the same metal.

Description

METHODS FOR FORMING NONVOLATILE MEMORY ELEMENTS WITH RESISTIVE-SWITCHING METAL OXIDES

This application claims priority to US Patent Application No. 11 / 714,334 filed March 5, 2007 and US Patent Application No. 11 / 714,326 filed March 5, 2007.

background

The present invention relates to a nonvolatile memory device, and more particularly, to a nonvolatile resistance switching memory device.

Nonvolatile memory devices are used in systems where persistent storage is required. For example, digital cameras use nonvolatile memory cards to store images and digital music players use nonvolatile memory to store audio data. Nonvolatile memory is also used to permanently store data in a computer environment.

Nonvolatile memory is often formed using electrically erasable programmable read only memory (EEPROM) technology. Nonvolatile memories of this type include floating gate transistors, which can be selectively programmed or erased by applying an appropriate voltage to their terminals.

As manufacturing techniques improve, it becomes possible to manufacture nonvolatile memory devices with smaller and smaller dimensions. However, as device dimensions shrink, scaling issues pose challenges for conventional nonvolatile memory technologies. This has led to the study of alternative nonvolatile memory technologies, including resistive switching nonvolatile memory.

Resistive switching nonvolatile memories are formed using memory elements having two or more stable states with different resistivity (ie, resistance). Bistable memory has two stable states. Bistable memory devices can be placed in a high or low resistance state by the application of an appropriate voltage or current. Voltage pulses are typically used to switch memory elements from one resistance state to another. A non-destructive read operation may be performed to verify the value of the data bits stored in the memory cell.

Resistance switching based on nickel oxide switching devices and other transition metal oxide switching devices has been described. Nickel oxide films for these devices were formed using a sputtering technique. With these techniques, it has become possible to produce nickel oxide (Ni _x O) films with sub-stoichiometric compositions ranging from Ni _0.8 O to Ni _0.95 O. Membranes such as these show promise for resistive switching applications, but film densities (eg, 5.4 to 5.8 g / cm ^{3 for} nickel oxide), which are typically stoichiometric metal oxides of at least 80%, and relatively low films Resistivity (eg, generally less than 10 ohm-cm for nickel oxide). With conventional manufacturing techniques, it was not possible to produce super-stoichiometric metal oxide films (ie, highly metal deficient Ni _x O with x <0.8 or x <0.65). Since metal defective metal oxide films may have beneficial properties for resistive switching applications such as high resistance (and low density), it would be desirable if there were improved methods of forming such films for nonvolatile memory devices.

summary

According to the present invention, a nonvolatile memory device and a manufacturing method are provided. The nonvolatile memory device may have a resistive switching metal oxide layer. There may also be provided a nonvolatile memory element having a stacked nonvolatile memory element arrangement and a resistive switching metal oxide in series with a current steering element such as a diode and a transistor.

The nonvolatile memory device may be formed by depositing a silicon-containing layer on an integrated circuit substrate. The integrated circuit board may be formed of silicon or other suitable material. One or more stacked layers of nonvolatile memory devices may be fabricated on an integrated circuit substrate before the silicon-containing layer is deposited. The silicon-containing layer may be formed from polysilicon or any other suitable material containing silicon.

A metal-containing layer may be deposited on the silicon-containing layer. The metal-containing layer may contain a metal such as nickel or other suitable transition metal. One or more dopant materials, such as phosphors, may be deposited with the metal-containing layer or added to the metal-containing layer (eg, by ion implantation, electroless deposition, etc.). Suitable techniques for depositing metal-containing layers include physical vapor deposition techniques, chemical vapor deposition techniques, atomic layer deposition (ALD) techniques, and electrochemical deposition techniques (e.g., electroless deposition techniques or electroplating techniques). It includes.

The metal-containing layer may be oxidized to form a resistive switching metal oxide layer. Suitable oxidation techniques that may be used to form the metal oxide layer include ion implantation of oxygen ions, thermal oxidation and plasma oxidation (eg, using rapid thermal oxidation techniques, laser induced thermal oxidation, or furnace oxidation). It includes.

During thermal oxidation or during one or more separate heating operations, heat is applied such that the metal in the metal-containing layer reacts with the silicon in the silicon-containing layer. This reaction forms a metal silicide layer. The metal silicide layer is conductive and can be used to form lower electrodes for nonvolatile memory devices. Since some of the metal in the metal-containing layer reacts with silicon, there is an increase in metal deficiency in the metal oxide layer compared to the absence of the silicon-containing layer. Thus, the metal oxide layer formed in this way can be compared with either i) as-deposited metal oxide containing the same metal or ii) deposited metal with subsequent oxidation without the presence of a silicon-containing layer. When there are more metal defects. In one embodiment, the simultaneous reaction of silicidation and oxidation limits the amount of metal available for oxidation, which is i) highly metal defective, ii) excess stoichiometric, and iii) low density. This results in a metal oxide film.

Since the metal in the metal oxide and the metal in the metal silicide layer are derived from the same metal in the metal-containing layer, these metals are generally the same metal.

Further features, nature and various advantages of the present invention will become more apparent from the accompanying drawings and the following detailed description.

Brief description of the drawings

1 is a diagram of an exemplary array of resistive switching memory elements in accordance with one embodiment of the present invention.

2A is a cross-sectional view of an exemplary resistive switching nonvolatile memory device in accordance with one embodiment of the present invention.

2B is a cross-sectional view of an exemplary resistive switching nonvolatile memory device in accordance with another embodiment of the present invention.

3 is a graph illustrating how a resistive switching nonvolatile memory device of the type shown in FIGS. 2A and 2B exhibits bistable behavior in accordance with one embodiment of the present invention.

4 is a schematic diagram of an exemplary resistive switching memory device in series with a diode according to one embodiment of the invention.

5 is a schematic diagram of an exemplary resistance switching memory element in series with an electrical device in accordance with one embodiment of the present invention.

6 is a schematic diagram of an exemplary resistive switching memory element in series with two electrical devices in accordance with one embodiment of the present invention.

FIG. 7 is a cross-sectional view showing how a metal defective metal oxide is formed on a metal silicide electrode by oxidizing a layer containing a metal deposited on a material containing silicon in accordance with an embodiment of the present invention.

FIG. 8 is a cross-sectional view similar to the cross-sectional view of FIG. 7 illustrating how one or more intermediate layers are formed between the metal oxide layer and the metal silicide layer in accordance with one embodiment of the present invention.

9 is a cross-sectional view illustrating how metal oxides on metal silicide structures may be formed using separate rapid thermal annealing and oxidation operations in accordance with one embodiment of the present invention.

10 is a flowchart of exemplary steps involved in forming a nonvolatile memory device including a metal defective resistance switching metal oxide in accordance with an embodiment of the present invention.

details

Embodiments of the present invention relate to a nonvolatile memory formed from a resistive switching element. Embodiments of the invention also relate to a manufacturing method that may be used to form a nonvolatile memory having a resistive switching memory element.

The resistive switching element may be formed on any suitable type of integrated circuit. Most typically, the resistive switching memory element may be formed as part of a high capacity nonvolatile memory integrated circuit. Nonvolatile memory integrated circuits are often used in portable devices such as digital cameras, mobile phones, handheld computers and music players. In some configurations, the nonvolatile memory device may be embedded in mobile equipment, such as a cellular telephone. In another configuration, the nonvolatile memory device is packaged in a memory card or a memory key that can be detachably installed in electronic equipment by a user.

The use of a resistive switching memory element to form a memory array on a memory device is merely illustrative. In general, any suitable integrated circuit may be formed using the resistive switching structure of the present invention. Fabrication of memory arrays formed of resistive switching memory elements is described herein as an example.

An exemplary memory array 10 of nonvolatile resistive switching memory element 12 is shown in FIG. 1. Memory array 10 may be part of a memory device or other integrated circuit. Read and write circuits are connected to the nonvolatile resistance switching memory element 12 using conductors 16 and quadrature conductors 18. Conductors such as conductors 16 and 18 are sometimes referred to as word lines and bit lines and are used to read and write data to the nonvolatile resistive switching memory elements 12 of the memory array 10. Individual memory elements 12 or groups of memory elements 12 may be processed using an appropriate set of conductors 16 and 18. Memory element 12 may be formed from one or more layers of material, as schematically shown by line 14 in FIG. In addition, memory arrays such as memory array 10 may be stacked in a vertical fashion to create a multilayer memory array structure.

During the read operation, the state of the memory element 12 can be sensed by applying a sensing voltage to the appropriate set of conductors 16 and 18. Depending on its history, memory devices processed in this manner may be in high or low resistance states. Thus, the resistance of the memory element determines what digital data is being stored by the memory element. For example, if a memory element has a high resistance, it may be said that the memory element includes a logic 1 (ie, "1" bit). On the other hand, when a memory element has a low resistance, it may be said that the memory element includes a logic 0 (ie, "0" bit). During a write operation, the state of the memory element can be changed by application of the appropriate write signal to the appropriate set of conductors 16 and 18.

A cross-sectional view of an exemplary embodiment of a resistive switching memory element is shown in FIG. 2A. In the example of FIG. 2A, memory element 12 is formed from metal oxide 22 and has conductive electrodes 20 and 24. When configured as part of an array such as array 10 of FIG. 1, conductive lines, such as lines 16 and 18, may be physically and electrically connected to electrodes 20 and 24. Such conductive lines may be formed from any suitable metal (eg, tungsten, aluminum, copper, metal silicides, etc.). Conductive lines 16 and 18 may also be formed from other conductive materials (eg, doped polysilicon, doped silicon, etc.) or a combination of conductive materials. If desired, the conductive line 16 and the conductive line 18 may both serve as conductive lines and serve as electrodes. In this type of configuration, line 16 may serve as electrode 20, so that no separate conductor is needed to form an upper electrode for memory element 12. Similarly, line 18 may serve as electrode 24, so that no separate conductor for the bottom electrode of memory element 12 is needed.

In the drawing of FIG. 2A, conductive lines 16 and 18 are schematically shown as formed in connection with electrodes 20 and 24. Other configurations may be used if desired. For example, an intervening electrical component (eg, diode, pin diode, silicon diode, silicon pin diode, transistor, etc.) formed between line 16 and electrode 20 or between line 18 and electrode 24. ) May be present.

If desired, there may be an electrical component connected in series between the electrode conductor and the resistance switching metal oxide. An exemplary configuration in which an intervening electrical component 38 is present between the conductor 24 and the metal oxide 22 is shown in FIG. 2B.

As schematically shown by dashed line 21, a conductive material such as electrodes 24 and 20 may be formed from one or more layers of material. Examples of materials that may be used to form the electrodes 20 and 24 include metals (eg, refractory metals or transition metals), metal alloys, metal nitrides (eg, refractory metal nitrides), metal silicon nitride (ie And materials containing refractory metals, transition metals, or other metals, together with silicon and nitrogen), metal silicides, or other conductors. Metal oxide 22 may be formed from a metal oxide, such as a transition metal oxide (eg, nickel-based oxide).

According to the present invention, a metal defective metal oxide may be formed on a metal silicide electrode by heating a structure having a top layer formed from a metal-containing material and a bottom layer formed from a silicon-containing material.

The resistive switching memory element 12 exhibits a bistable resistance. When the resistive switching memory element 12 is in a high resistance state, the resistive switching memory element 12 may be said to include a logic one. When the resistive switching memory element 12 is in a low resistance state, it may be said that the resistive switching memory element 12 includes a logic zero (if desired, a high resistance can represent a logic zero and a low resistance can represent a logic one). Can be displayed). The state of the resistive switching memory element 12 may be sensed by the application of a sense voltage. When it is desired to change the state of the resistive switching memory element 12, the read and write circuit may apply an appropriate control signal to the appropriate lines 16 and 18.

A plot of current (I) vs. voltage (V) for device 12 is shown in FIG. 3. Initially, element 12 may be in a high resistance state (eg, storing logic 1). In this state, the current versus voltage characteristic of the element 12 is represented by the solid line HRS 26. The high resistance state of element 12 can be sensed by read and write circuits associated with the array of element 12. For example, the read and write circuit may apply a read voltage V _READ to element 12 and sense the low current I _L as a result of flowing through element 12. When it is desired to store logic 0 in device 12, device 12 may be placed in a low resistance state. This may be accomplished by applying a voltage V _SET across the terminals 16 and 18 of the element 12 using the read and write circuit. Applying V _SET to element 12 causes element 12 to enter a low resistance state, as indicated by dashed line 30. In this region, the structure of the element 12 is changed (for example, through the formation of a current filament through the metal oxide 22 or other suitable mechanism) so that after removal of the voltage V _SET , the element 12 is lowered. Characterized by the resistance curve LRS 28.

The low resistance state of element 12 can be sensed using read and write circuitry. When the read voltage V _READ is applied to the resistive switching memory element 12, the read and write circuit will sense a relatively high current value I _H indicating that the element 12 is in a low resistance state. When wishing to store logic 1 in device 12, device 12 can be put into a high resistance state once again by applying voltage V _RESET to device 12. When the read and write circuit applies V _RESET to element 12, element 12 enters a high resistance state HRS as indicated by dashed line 32. When voltage V _RESET is removed from device 12, device 12 will once again be characterized by high resistance line HRS 26.

The bistable resistance of the resistive switching memory element 12 makes the memory element 12 suitable for storing digital data. Since no change occurs in the stored data in the absence of application of the voltages V _SET and V _RESET , the memory formed from elements such as element 12 is nonvolatile.

Any suitable read and write circuit and array layout scheme may be used to construct the nonvolatile memory device from a resistive switching memory device such as memory device 12. For example, the horizontal line 16 and the vertical line 18 may be directly connected to the terminals of the resistive switching memory element 12. This is just an example. If desired, other electrical devices may be associated with each element 12.

One example is shown in FIG. 4. As shown in FIG. 4, the diode 36 may be placed in series with the resistive switching memory element 12. Diode 36 may be a Schottky diode, a p-n diode, a p-i-n diode or any other suitable diode.

If desired, other electrical components can be formed in series with the resistive switching memory element 12. As shown in FIG. 5, a series connected electrical device 38 may be coupled to the resistive switching memory element 12. Device 38 may be a diode, a transistor, or any other suitable electronic device. Because devices such as these can rectify or otherwise alter the current flow, these devices are sometimes referred to as rectifying elements or current driving elements. As shown in FIG. 6, two electrical devices 38 may be placed in series with the resistive switching memory element 12. The electrical device 38 may be formed as part of a nonvolatile memory element or may be formed as a separate device, perhaps at a remote location relative to the resistive switching metal oxide and its associated electrode.

The memory element 12 may be made of a single layer in the array 10 or may be made of multiple layers forming a three dimensional stack. The advantage of forming a memory array such as the memory array 10 of FIG. 1 using a multilayer memory device approach is that this type of approach allows the memory device density to be maximized for a given chip size.

If desired, a resistive switching metal oxide layer may be formed above or below the current drive element, such as a diode. Conductive lines 16 and 18 may be electrically coupled to metal oxide 22 through multiple layers of conductive material. In general, there may be any suitable number of conductive layers associated with the resistive switching memory element 12. These conductive layers include adhesion promotion, seed layers for subsequent electrochemical deposition, diffusion barriers to prevent unwanted material from diffusing into adjacent structures, and contact materials to form ohmic contacts with the metal oxides 22. (E.g., metals, metal alloys, metal nitrides, etc.), contact materials (e.g., metals, metal alloys, metal nitrides, etc.) for forming Schottky contacts on metal oxides 22, etc. May be

The conductive layer in the element 12 may be formed from the same conductive material or different conductive materials. For example, the conductive layer in device 12 may include two nickel layers or may include (as an example) a nickel layer and a titanium nitride layer. In addition, the conductive layer in the element 12 may be formed using the same technique or different techniques. As one example, the conductive layer may include a metal layer formed using physical vapor deposition (PVD) technology (eg, sputter deposition) and a metal layer formed using electrochemical deposition technology.

The portion of the conductive layer in the element 12 that is immediately adjacent to or otherwise in close contact with the metal oxide 22 is sometimes referred to as the electrode of the resistive switching memory element 12.

In general, the electrodes of the resistive switching memory element 12 may each comprise a single material, each may comprise a plurality of materials, and may comprise a material formed using a single technique or a series of different techniques. Or combinations of these materials.

Certain metals are particularly suitable for forming metal oxides 22. These metals may include, for example, transition metals and their alloys. Examples of transition metals that may be used to form metal oxides include Ni, Ti, Co, Cu, Ta, W, and Mo.

In one particularly suitable configuration, the metal for forming the metal oxide 22 comprises nickel. The metal oxide 22 may contain other elements in addition to nickel. For example, metal oxide 22 may be formed from a metal such as nickel doped with a dopant material such as phosphorus. In this situation, the metal oxide 22 will contain nickel, phosphorus and oxygen. Other dopant materials that may be used include P, As, F, Cl, Al and B.

Any suitable conductive material may be used to form the electrodes 20 and 24 of the resistive switching memory element 12. Exemplary conductive materials include transition metals (and transition metal nitrides), refractory metals (and refractory metal nitrides), and precious metals. Illustrative examples of metals that may be used as the conductive material include Ni, Ti, Co, Cu, Ta, W, and Mo. These are only illustrative examples of materials that may be used. If desired, two or more combinations of these metals may be used or other suitable conductive material may be used as the electrodes 20 and 24.

The layer of material formed when manufacturing device 12 may be deposited using any suitable technique. Exemplary deposition techniques include physical vapor deposition (eg, sputter deposition or evaporation), chemical vapor deposition, atomic layer deposition, and electrochemical deposition (eg, electroless deposition or electroplating). Metal oxide 22 may be formed by oxidizing one or more deposited layers.

Metals such as transition metals can form stable stoichiometric oxides. For example, nickel forms stoichiometric metal oxide NiO. Titanium forms the stoichiometric metal oxide TiO ₂ . Although stoichiometric metal oxides may sometimes be suitable for forming resistive switching metal oxides, there is an advantage to forming a stoichiometric resistive switching metal oxide. A stoichiometric resistive switching metal oxide (sometimes referred to as a metal defective metal oxide) has a lower density and higher resistivity, and better resistive switching properties (e.g., a lower on / off current than a stoichiometric oxide). , Lower V _SET / V _RESET voltage, lower I _SET / I _RESET current, lower forming voltage, and the like. Higher resistivity may be beneficial when forming an array of nonvolatile memory elements on an integrated circuit. If the resistance of the device is too low, it may be difficult to detect a state change. Thus, resistive switching oxides having relatively large resistivities (eg, above 10 ohm-cm or above 100 ohm-cm) may be desirable or may even be required by certain nonvolatile memory architectures.

In conventional manufacturing techniques such as sputtering, the amount of metal defects that can be achieved in resistive switching metal oxides has been limited. For example, in a nickel-based system, the lowest nickel to oxygen ratio achieved was about 0.8: 1 (ie, Ni _0.8 O). Nickel oxide films of this type exhibited relatively high densities (ie, about 5.4-5.8 g / cm ³ ) and low resistivity (ie, less than 10 ohm-cm).

In accordance with the present invention, the nonvolatile memory device is formed from excess stoichiometric resistive switching metal oxide. Using the techniques of the present invention, highly metal defective resistive switching metal oxides having a density of 3 to 4 g / cm ³ or lower and resistivity of 10 ohm-cm to 100 ohm-cm or higher can be produced. These densities may be less than 65% to less than 80% of the stoichiometric metal oxide density.

A high degree of metal defects may be obtained by using silicon to otherwise consume some of the metal to be incorporated into the resistive switching metal oxide. Silicon reacts with the metal to form metal silicides. Metal silicides may be used to form all or part of an electrode for a nonvolatile memory device.

A typical manufacturing process is shown in FIG. Initially, silicon-containing layer 40 is formed. The silicon-containing layer may be formed from crystalline silicon, polysilicon, amorphous silicon, n-type silicon, p-type silicon, or any suitable material containing silicon. The thickness of the silicon-containing layer 40 depends on the type of fabrication process being used and the type of device architecture used for the nonvolatile memory device. Typical silicon layers have a thickness in the range of less than 1 micron (eg, 10-1500 angstroms or 500-1500 angstroms). For example, a typical polysilicon layer may be 700 angstroms.

The layer of material containing silicon may be prepared using any suitable technique (eg, physical vapor deposition, chemical vapor deposition, etc.). Silicon-containing layer 40 may be formed (eg, in a stacked memory) on a previously manufactured layer of the device, and may be formed on a substrate (eg, a silicon substrate with or without an intervening material layer). Or may be formed on any other suitable base layer.

After forming layer 40, metal-containing layer 44 may be formed on top of layer 40 as shown on the left side of FIG. 7. Layer 44 may have a thickness no greater than 10 times the thickness of layer 40, no greater than 5 times the thickness of layer 40, no greater than 2 times the thickness of layer 40, or no greater than layer 40 thickness. Layer 44 thickness will typically be in the range of 100-5000 angstroms and will be no greater than layer 40 thickness or no greater than twice the layer 40 thickness. Layer 44 may be a metal (eg, a transition metal such as Ni, Ti, Co, Cu, Ta, W, or Mo), or may be formed from a combination of one or more such metals. Layer 44 may also contain optional dopant material (eg, P, As, F, Cl, Al, or B). As one example, layer 44 may be formed from Ni or Ni and P.

Any suitable manufacturing technique may be used to form layer 44. For example, one or more metals may be deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition, or electrochemical deposition (eg, electroless deposition or electroplating). The dopant may be deposited simultaneously with the metal (eg, by co-sputtering the metal and the dopant or using alloy sputtering techniques, or by depositing the metal and the dopant material together as part of an electroless deposition process), or at different times May be deposited (eg, by implanting dopant material into layer 44 via ion implantation). When the dopant is incorporated into layer 44 as part of the layer forming process, deposited layer 44 contains a mixture of metal and one or more other materials (eg, dopant materials). If desired, layer 44 may be formed by depositing a separate sublayer of material. For example, the phosphorus-doped nickel layer may be formed by forming a nickel layer on top of the phosphorus-containing layer and heating the layer (when forming layer 44 or during subsequent process steps). .

An exemplary electroless deposition process that may be used to form layer 44 is based on an electroless solution containing nickel sulphate reactant (ie, when the layer being deposited is nickel containing phosphorus dopant). The substrate on which layer 44 is being formed may be placed in a water bath containing nickel sulfate (NiSO ₄ ) at a concentration of 0.015M to 0.15M. In addition to the nickel sulfate reactant, the electroless solution may comprise a reducing agent such as ammonium hypophosphite (NH ₄ H ₂ PO ₂ ) at a concentration of up to about 0.15 M. Ammonium hypophosphite supplies phosphorus to the deposited layer of electroless conductive material and serves as a reducing agent for the deposition of nickel. In a typical scenario, the phosphorus concentration in the deposited layer is approximately 1-10%.

After forming the metal-containing layer 44 on the silicon-containing layer 40, the metal-containing layer 44 is oxidized to form the metal oxide 46. The silicon-containing layer 40 is heated to form metal silicides 48. Metal silicide 48 is formed from silicon in layer 40 and at least a portion of the metal in metal-containing layer 44. Since silicon 40 reacts with the metal in layer 44, a portion of the metal that would otherwise be available for oxidation to consume metal oxide 46 is consumed. This reduces the metal concentration in the metal oxide 46 such that the metal oxide 46 becomes metal defective. If enough silicon is used, metal oxide 46 may be highly metal defective. For example, when metal oxide 46 has a composition of M _x O _y , where M is a metal and O is oxygen, and M _a O _b represents a stoichiometric metal oxide formed from metal M and oxygen , the ratio of x / y may be less than 80% of a / b, or even less than 65% of a / b.

Any suitable configuration may be used to form the oxides 46 and silicides 48. Oxidation may be performed using Rapid Thermal Oxidation (RTO) in a temperature range of 350 ° C. to 750 ° C. (eg, at 550 ° C. for 1 to 10 minutes) for less than 20 minutes. Oxidation may also be performed in a furnace of higher temperature, or using laser induction heating. If desired, oxidation may also be formed by implanting oxygen ions into layer 44 (typically followed by an annealing operation). Combinations of these techniques may also be used.

The silicide 48 may be formed by heating the layer 40 in the presence of the metal or other material of the layer 44. The heat treatment used to form the metal silicide layer 48 may be part of the same heat treatment used to form the metal oxide 46 or may be part of a separate heat treatment. One or more heat treatment operations may be used to form layers 46 and 48. When it is desired to perform thermal oxidation to form layer 46, at least one of these operations is preferably performed in an oxygen environment.

In a typical configuration, after layer 44 is formed on layer 40, a rapid thermal oxidation operation is performed (ie, both layers 40 and 44 in the RTO tool in the presence of a gas mixture containing oxygen). Heating). In this type of scenario, the metal and other materials of layer 44 are oxidized by oxygen while at the same time the silicon of layer 40 reacts with the metal and potentially other materials of layer 44.

As shown in FIG. 8, one or more intermediate layers 50 may be formed during the heat treatment applied subsequent to the formation of layers 40 and 44. Layer 50 may be associated with metal oxide 46 and is sometimes referred to as a sublayer of metal oxide 46. Sublayer 50 formed between metal oxide 46 and metal silicide 48 may each contain metal, oxygen and phosphorus (or other dopant material) in different proportions. The metal in layer 50 may be the same as the metal in the metal oxide and the underlying metal silicide.

As shown in FIG. 9, metal silicide 48 and metal oxide layer 46 may be formed during separate steps. Initially, a metal-containing layer 44 may be formed on the silicon-containing layer 40 as shown on the left side of FIG. 9. During the rapid thermal annealing (RTA) process (or other heat treatment), the metal of the metal-containing layer 44 reacts with the silicon of the silicon-containing layer 40 to show the metal silicide layer 48 as shown in the middle of FIG. 9. To form. In a conventional rapid thermal annealing process, the layer is 350-750 ° C. for 1-10 minutes in an atmosphere containing argon, nitrogen, hydrogen, or forming gas, or a combination of such non-oxygen-containing (and / or reducing) gases. It is easy to be affected by heat.

During the heat treatment, all or part of the silicon-containing layer 40 may be consumed (in a process of the type shown in FIG. 9 or in a process of the type shown in FIGS. 7 and 8). In the example shown in FIG. 9, only a portion of the silicon-containing layer 40 has been consumed. This is just an example.

As shown in the middle of FIG. 9, a portion of the metal layer 44 (eg, 0 to 2500 angstroms) may not be converted to a metal silicide. This residual layer may be removed (eg, using a chemical bath) or may be retained as shown in FIG. 9.

After the annealing process is complete (and if present at all) and optional stripping is performed on the remaining metal layer 44, rapid thermal oxidation (or other thermal oxidation) is shown on the right side of FIG. 9. It may be performed to form).

Exemplary steps involved in forming a nonvolatile memory device using the type of technique shown in FIGS. 7, 8, and 9 are shown in FIG.

In step 52, one or more underlying layers for the integrated circuit are formed. The bottom layer is a substrate (e.g. a silicon wafer), a layer that forms an underlayer of a nonvolatile memory device (e.g., when the integrated circuit being formed is a stacked memory device), a conductive layer for routing, conductive routing It may comprise an insulating layer, or any other suitable material layer, that insulates the line and the nonvolatile memory device from each other. Silicon-containing layer 40 is formed on top of these layers. For example, if silicon-containing layer 40 is a polysilicon layer, polysilicon may be deposited on the underlying circuit layer. Silicon-containing layer 40 may be formed by PVD, CVD, or any other suitable manufacturing technique.

After forming the silicon-containing layer 40, layer 44 may be deposited in step 54. As described in connection with FIGS. 7, 8, and 9, layer 44 may contain one or more dopant materials and one or more metals. Layer 44 may be formed by PVD, CVD, atomic layer deposition, electrochemical deposition, or the like. The dopant material can be deposited using ion implantation techniques, simultaneously depositing the metal and the dopant material (e.g., using PVD co-sputtering, PVD alloy sputtering, or electroless co-evaporation, etc.), or depositing sublayers of many different materials. It may be incorporated into layer 44 by depositing a layer 44 that includes.

After forming layers 40 and 44, a portion of layer 44 (eg, top of layer 44) is oxidized to form layer 46, and a portion of layer 44 is a silicon-containing layer React with 40 to form layer 48 (step 56). Oxidation may be performed via ion implantation or using thermal oxidation. The heat may be applied during step 56 in one or more operations (eg, as a single RTO operation or as an RTA operation followed by or more). Heat may be applied (if desired) to cause thermal oxidation and to convert metals and silicon to metal silicides. Since layer 44 provides the same metal to both metal oxide 46 and metal silicide 48, the resulting nonvolatile memory element will have a metal oxide having the same metal as its underlying metal silicide layer 48 will be. The metal silicide layer 48 may form all or part of the lower electrode, such as the electrode 24 of FIG. 2A.

The resistivity of the metal oxide 46 may be greater than 10 ohm-cm or greater than 100 ohm-cm. The density of the metal oxide 46 may be less than ³ g / cm ³ or less than 4 g / cm ³ (as an example). The thickness of the metal oxide 46 may be 10 to 5000 angstroms (as an example). Since the silicide layer 48 consumes metal from the metal oxide 46, the metal oxide 46 may be highly metal defective. For example, metal oxide 46 may be compared to that found in either i) a stoichiometric metal oxide formed from the same metal or ii) a stoichiometric metal oxide formed from the same metal using conventional means. It may have a metal content (or film density) of only 80% (or less) or 65% (or less).

It should be appreciated that another benefit of the present invention is in-situ formation of the conductive bottom electrode.

In another embodiment, an appropriate dopant (such as P) may be implanted into the metal layer (eg, Ni) in step 54. The metal layer can be deposited using PVD. The dopant energy may be adjusted so that the dopant peak is approximately 0 to 250 Hz from the Si interface. The dopant dose is preferably> 1E15 / cm ² . This doped metal layer can then be oxidized in the manner described above.

Alternatively, the dopant may be added after the metal oxide is formed using ion implantation and appropriate activation heat treatment. For example, P or fluorine can be activated by rapid thermal annealing at a temperature in the range of approximately 550-750 ° C. in an inert atmosphere after being injected with Ni _x O.

In step 58, the top electrode may be formed on the metal oxide (eg, using PVD, CVD, ALD, electrochemical deposition, etc.). The top electrode may be formed from the same metal as the bottom electrode (eg, the same metal in metal oxide 46 and metal silicide 48) or from a different metal. Suitable metals for the upper electrode include transition metals such as Ni, Ti, Co, Cu, Ta, W and Mo. If desired, a series-connected current drive element (e.g., a diode or transistor, etc.) may be a metal oxide above and / or below (e.g., i) a metal element as shown in Figures 2b, 4, 5 and 6. Or ii) above and / or below the upper or lower electrode coupled to the metal oxide.

According to one embodiment, depositing a metal containing layer on a silicon containing material and thermally oxidizing a first portion of the deposited layer to form a resistive switching metal oxide for the resistive switching memory device. A method of manufacturing a resistive switching memory device is provided, wherein a metal silicide layer is formed from the material and a second portion of the deposited layer.

According to another embodiment, a method of manufacturing a resistive switching memory element is provided, wherein a metal silicide layer is formed below the metal oxide and serves as an electrode for the resistive switching memory element.

According to another embodiment, a method of manufacturing a resistive switching memory element is provided, wherein a metal oxide and a metal silicide are formed simultaneously.

According to another embodiment, a method of manufacturing a resistive switching memory device is provided, wherein thermally oxidizing a first portion of the deposited layer includes forming a resistive switching metal oxide having a composition of M _x O _y , Where M is a metal and O is oxygen, M _a O _b represents a stoichiometric metal oxide and x / y is less than 80% of a / b.

According to another embodiment, a method of manufacturing a resistive switching memory device is provided, wherein the thermally oxidizing the first portion of the deposited layer comprises forming a resistive switching metal oxide having a composition of M _x O _y , Where M is a metal and O is oxygen, M _a O _b represents a stoichiometric metal oxide and x / y is less than 65% of a / b.

According to another embodiment, a method of manufacturing a resistive switching memory element is provided, wherein the metal comprises a transition metal.

According to another embodiment, a method of manufacturing a resistive switching memory device is provided, wherein the metal comprises a transition metal selected from the group consisting of Ni, Ti, Co, Cu, Ta, W and Mo.

According to another embodiment, a method of manufacturing a resistive switching memory device is provided, wherein the deposited layer comprises at least one dopant material selected from the group consisting of P, As, F, Cl, Al, and B.

According to another embodiment, a method of fabricating a resistive switching memory device is provided wherein the deposited layer comprises at least one dopant material.

According to another embodiment, a method of manufacturing a resistive switching memory device is provided, wherein at least one dopant material is co-deposited with a metal to form a deposited layer.

According to another embodiment, a method of manufacturing a resistive switching memory device is provided wherein the deposition of both metal and at least one dopant material of the deposited layer is selected from the group of electroless deposition, electroplating and electrochemical deposition.

According to another embodiment, a method of manufacturing a resistive switching memory device is provided wherein at least one dopant material is implanted into a deposited layer through ion implantation.

According to another embodiment, a method of manufacturing a resistive switching memory device is provided, wherein the deposited layer is deposited using a method selected from the group consisting of chemical vapor deposition, atomic layer deposition, and physical vapor deposition.

According to another embodiment, a method of fabricating a resistive switching memory device is provided, wherein at least one dopant material is phosphorus, which phosphorus is implanted into a portion of the deposited layer.

According to another embodiment, a method of fabricating a resistive switching memory device is provided, and depositing the layer includes depositing the layer using physical vapor deposition of nickel and implantation of phosphorus.

According to another embodiment, a method of fabricating a resistive switching memory device is provided, and depositing the layer comprises depositing a first sublayer containing phosphorus and containing nickel on the first sublayer containing phosphorus. And depositing a second sublayer.

According to another embodiment, a method is provided for manufacturing a resistive switching memory device that also includes depositing an electrode over a metal oxide, wherein the electrode is formed from a material containing the same metal as the metal in the deposited layer.

According to another embodiment, a method is provided for manufacturing a resistive switching memory device that also includes depositing an electrode over a metal oxide, wherein the electrode is formed from a material that does not contain the same metal as the metal in the deposited layer.

According to another embodiment, a method of fabricating a resistive switching memory device is provided, wherein depositing the layer includes depositing a homogeneous layer of a single material.

According to another embodiment, a method of fabricating a resistive switching memory device is provided, and depositing the layer includes depositing the layer to a thickness of less than 5000 angstroms.

According to another embodiment, a method of manufacturing a resistive switching memory device is provided, wherein the material comprises a material selected from the group consisting of crystalline silicon, polysilicon, and amorphous silicon.

According to another embodiment, a method of manufacturing a resistive switching memory device is provided, wherein the material comprises a material selected from the group consisting of n-type silicon and p-type silicon.

According to another embodiment, a method of manufacturing a resistive switching memory device is provided wherein a material containing silicon has a predetermined thickness and the deposited layer has a thickness that is less than 10 times the thickness of the material containing silicon.

According to another embodiment, a method of manufacturing a resistive switching memory device is provided, wherein thermal oxidation forms at least one additional layer of material between the metal silicide and the metal oxide.

According to another embodiment, a method of manufacturing a resistive switching memory device is provided, wherein depositing a layer includes electrolessly depositing a layer, wherein at least one additional layer comprises a phosphorus.

According to another embodiment, a method of manufacturing a resistive switching memory device is provided wherein thermal oxidation forms a plurality of sublayers between a metal silicide and a metal oxide.

According to another embodiment, a method of manufacturing a resistive switching memory device is provided, wherein thermal oxidation forms a plurality of sublayers between a metal silicide and a metal oxide, each of the plurality of sublayers being a metal, oxygen and at least one dopant. It contains materials in different proportions.

According to another embodiment, a method of fabricating a resistive switching memory device is provided, and depositing the layer includes electrolessly depositing the layer from an electroless solution.

According to another embodiment, a method of fabricating a resistive switching memory device is provided wherein thermally oxidizing a first portion of a deposited layer to form a resistive switching metal oxide comprises a resistive switching metal having a density of less than 4 g / cm ^3. Forming an oxide.

According to another embodiment, a method of manufacturing a resistive switching memory device is provided, wherein there is a stoichiometric metal oxide density associated with the metal oxide, the metal oxide having a density that is less than 80% of the stoichiometric metal oxide density.

According to another embodiment, a method of manufacturing a resistive switching memory device is provided, wherein there is a stoichiometric metal oxide density associated with the metal oxide, the metal oxide having a density that is less than 65% of the stoichiometric metal oxide density.

According to another embodiment, a method of fabricating a resistive switching memory device is provided wherein thermally oxidizing a first portion of a deposited layer to form a resistive switching metal oxide wherein the resistive switching metal has a resistivity greater than 10 ohm-cm. Forming an oxide.

According to another embodiment, a method of fabricating a resistive switching memory device is provided wherein thermally oxidizing a first portion of a deposited layer to form a resistive switching metal oxide comprises a resistive switching metal having a resistivity greater than 100 ohm-cm. Forming an oxide.

According to another embodiment, a method of fabricating a resistive switching memory device is provided, wherein thermally oxidizing the first portion of the deposited layer performs thermal oxidation in a temperature range of 350 ° C to 750 ° C for 1 to 10 minutes. Steps.

According to another embodiment, a method of fabricating a resistive switching memory device is provided, wherein thermal oxidizing a first portion of the deposited layer includes performing rapid thermal oxidation comprising a plurality of sequential thermal processes; At least one of the sequential multiple thermal processes is performed in an atmosphere containing oxygen.

According to another embodiment, a method of fabricating a resistive switching memory device is provided, wherein thermally oxidizing a first portion of the deposited layer comprises performing oxidation in a furnace.

According to one embodiment, a method of fabricating a resistive switching memory device on a material containing silicon is provided, the method comprising depositing a layer containing a metal on the material, depositing the layer and the material. Forming a metal silicide electrode layer from at least a portion of the deposited layer and at least a portion of the material by heating and forming a resistive switching metal oxide on the metal silicide electrode layer.

According to another embodiment, a method of fabricating a resistive switching memory device on a silicon-containing material is provided, wherein forming the metal oxide comprises using thermal oxidation.

According to another embodiment, a method of manufacturing a resistive switching memory device on a material containing silicon is provided, wherein the metal silicide electrode layer and the metal oxide are simultaneously formed while heating the deposited layer.

According to another embodiment, a method of manufacturing a resistive switching memory element on a material containing silicon is provided, wherein the metal silicide electrode layer and the metal oxide are not formed at the same time.

According to another embodiment, a method of fabricating a resistive switching memory device on a material containing silicon is provided, wherein forming the resistive switching metal oxide comprises exposing the deposited layer to oxygen during at least a portion of the heating of the deposited layer. To thermally oxidize the deposited layer.

According to another embodiment, a method of fabricating a resistive switching memory device on a silicon-containing material is provided, wherein at least a portion of the heating of the deposited layer performs rapid thermal annealing on the deposited layer in an oxygen free gas environment. It includes a step.

According to one embodiment, there is provided a nonvolatile memory device comprising an electrode containing a metal silicide and a resistance switching metal oxide containing the same metal as the electrode.

According to another embodiment, a nonvolatile memory device is provided wherein the resistive switching metal oxide has a composition of M _x O _y , where M is a metal and O is oxygen and M _a O _b represents a stoichiometric metal oxide , x / y is less than 80% of a / b.

According to another embodiment, a nonvolatile memory device is provided wherein the resistive switching metal oxide has a composition of M _x O _y , where M is a metal and O is oxygen and M _a O _b represents a stoichiometric metal oxide , x / y is less than 65% of a / b.

According to another embodiment, a nonvolatile memory device is provided, wherein the resistive switching metal oxide contains phosphorus.

According to another embodiment, a nonvolatile memory device is provided, wherein the metal is a transition metal.

According to another embodiment, a nonvolatile memory device is provided, wherein the resistive switching metal oxide comprises transition metal, phosphorus and oxygen.

According to another embodiment, a nonvolatile memory device is provided, wherein the transition metal comprises a metal selected from the group consisting of Ni, Ti, Co, Cu, Ta, W and Mo.

According to another embodiment, there is provided a nonvolatile memory element that also includes a series of current drive elements.

According to another embodiment, a nonvolatile memory device is provided, wherein the resistive switching metal oxide has a thickness of 10 to 5000 angstroms.

According to another embodiment, a nonvolatile memory device is provided wherein the resistive switching metal oxide has a density of less than 4 g / cm ³ .

According to another embodiment, a nonvolatile memory device is provided wherein there is a stoichiometric metal oxide density associated with the metal oxide and the metal oxide has a density that is less than 80% of the stoichiometric metal oxide density.

According to another embodiment, a nonvolatile memory device is provided wherein there is a stoichiometric metal oxide density associated with the metal oxide, and the metal oxide has a density that is less than 65% of the stoichiometric metal oxide density.

According to another embodiment, a nonvolatile memory device is provided wherein the resistive switching metal oxide has a resistivity greater than 10 ohm-cm.

According to another embodiment, a nonvolatile memory device is provided wherein the resistive switching metal oxide has a resistivity greater than 100 ohm-cm.

According to another embodiment, there is provided a nonvolatile memory device that also includes an additional electrode, the electrode and the additional electrode being coupled to opposite sides of the metal oxide, the additional electrode being the same metal contained within the metal oxide and the electrode. It includes.

According to another embodiment, there is provided a nonvolatile memory device that also includes an additional electrode, the electrode and the additional electrode being coupled to opposite sides of the metal oxide, wherein the additional electrode is made of a different metal than the metal oxide and the electrode. Include.

According to another embodiment, there is provided a nonvolatile memory device that also includes at least one layer between a metal silicide and a metal oxide, wherein the at least one layer comprises the same metal as the metal oxide.

According to one embodiment, there is provided a nonvolatile memory device comprising a resistive switching metal oxide having a composition of M _x O _y , wherein M is a metal and O is oxygen and M _a O _b is _a stoichiometric metal oxide. X / y is less than 80% of a / b, and the electrode is coupled to the resistive switching metal oxide.

According to another embodiment, a nonvolatile memory device is provided, where x / y is less than 65% of a / b.

According to another embodiment, a nonvolatile memory device is provided, wherein the metal comprises a transition metal.

According to another embodiment, a nonvolatile memory device is provided, wherein the metal comprises nickel.

According to another embodiment, a nonvolatile memory device is provided, wherein at least one of the electrodes is formed from a metal silicide containing a metal.

The foregoing descriptions are merely illustrative of the principles of the invention and various modifications may be made by those skilled in the art without departing from the scope and spirit of the invention.

Claims (11)

A method of manufacturing a resistance switching memory device on a material containing silicon, Depositing a layer containing a metal on the material; Heating the deposited layer and the material to form a metal silicide electrode layer from at least a portion of the deposited layer and at least a portion of the material; And Forming a resistive switching metal oxide on the metal silicide electrode layer. The method of claim 1, Forming the resistive switching metal oxide comprises using thermal oxidation. The method of claim 1, And the metal silicide electrode layer and the resistance switching metal oxide are simultaneously formed while heating the deposited layer. The method of claim 1, And the metal silicide electrode layer and the resistance switching metal oxide are not formed at the same time. The method of claim 1, Forming the resistive switching metal oxide comprises exposing the deposited layer to oxygen during at least a portion of the heating of the deposited layer to thermally oxidize the deposited layer. . The method of claim 1, At least a portion of the heating of the deposited layer comprises performing rapid thermal annealing on the deposited layer in an oxygen free gas environment. A resistive switching metal oxide having a composition of M _x O _y , where M is a metal and O is oxygen, M _a O _b represents a stoichiometric metal oxide, and x / y is 80% of a / b Less than, said resistive switching metal oxide; And And electrodes coupled to the resistance switching metal oxide. The method of claim 7, wherein x / y is less than 65% of a / b. The method of claim 7, wherein And the metal comprises a transition metal. The method of claim 7, wherein And the metal comprises nickel. The method of claim 7, wherein At least one of the electrodes is formed from a metal silicide containing the metal.

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