KR20150005426A - transmitting apparatus and signal processing method thereof - Google Patents

Abstract

A transmitting apparatus is disclosed. The transmitting apparatus includes: an encoder to generate an LDPC codeword by performing LDPC encoding; an interleaver to interleave the LDPC codeword; and a modulator to map the interleaved LDPC codeword to a modulation symbol. The modulator maps bits included in a preset group among a plurality of groups constituting the LDPC codeword to a preset bit in a modulation symbol.

Description

TECHNICAL FIELD [0001] The present invention relates to a transmission apparatus and a signal processing method thereof,

BACKGROUND OF THE INVENTION 1. Field of the Invention [0002] The present invention relates to a transmission apparatus and a signal processing method thereof, and more particularly, to a transmission apparatus that processes and transmits data and a signal processing method thereof.

In the information society of the 21st century, broadcasting and communication services are in the era of full-scale digitalization, multi-channelization, broadband and high-quality. In particular, with the spread of high-definition digital TVs, PMPs, and mobile broadcasting devices, demand for supporting various receiving methods of digital broadcasting services is increasing.

In accordance with these requirements, the standard group has established various standards and provided various services that satisfy the needs of the users. Therefore, in order to provide a better service through better decryption and reception performance, do.

It is an object of the present invention to provide a transmission apparatus capable of mapping a bit included in a predetermined group among a plurality of groups constituting an LDPC codeword to a predetermined bit in a modulation symbol and transmitting the bit, And a method for processing the same.

According to an aspect of the present invention, there is provided a transmission apparatus including an encoder for performing LDPC encoding to generate an LDPC codeword, an interleaver for interleaving the LDPC codeword, and a modulator for modulating the interleaved LDPC codeword, Wherein the modulator maps a bit included in a predetermined group among a plurality of groups constituting the LDPC codeword to a predetermined bit in the modulation symbol.

Here, each of the plurality of groups may be configured with 360 bits.

The interleaver includes a parity interleaver for interleaving parity bits constituting the LDPC codeword, a group interleaver for grouping the parity interleaved LDPC codewords into the plurality of groups, And a block interleaver for interleaving the plurality of groups in which the order is rearranged.

Here, the group interleaver may rearrange the order of the plurality of groups on a group basis based on Equation (11).

In this case, in Equation (11),? (J) may be determined based on at least one of the length of the LDPC codeword, the modulation scheme, and the coding rate.

Herein,? (J) can be defined as shown in Table 37 when the length of the LDPC codeword is 64800, the modulation scheme is 256-QAM, and the coding rate is 6/15.

(J) can be defined as shown in Table 38 when the length of the LDPC codeword is 64,800, the modulation scheme is 256-QAM, and the code rate is 8/15.

(J) can be defined as shown in Table 39 when the length of the LDPC codeword is 64,800, the modulation scheme is 256-QAM, and the code rate is 10/15.

(J) can be defined as shown in Table 40 when the length of the LDPC codeword is 64,800, the modulation scheme is 256-QAM, and the code rate is 10/15.

(J) can be defined as shown in Table 41 when the length of the LDPC codeword is 64,800, the modulation scheme is 256-QAM, and the code rate is 12/15.

On the other hand, the block interleaver writes the plurality of groups in a column direction to each of a plurality of columns in a group unit, reads each row of the plurality of columns in which the plurality of groups are written in a group unit in the row direction and performs interleaving can do.

Here, the block interleaver sequentially writes at least a part of groups each of which can be written in each of the plurality of columns into each of the plurality of columns, in each of the plurality of columns, and then, in each of the plurality of columns, The group is written in the group unit, and the remaining group can be divided and written in the remaining area.

The group interleaver rearranges the order of the plurality of groups so that at least one group including bits mapped to the same positions of different modulation symbols are sequentially arranged, The block interleaver may cause the predetermined group to be written to the predetermined column.

Here, the modulator may generate the modulation symbol by mapping a bit output from the predetermined column to a predetermined bit in the modulation symbol.

Meanwhile, a signal processing method of a transmission apparatus according to an embodiment of the present invention includes generating LDPC codewords by performing LDPC coding, interleaving the LDPC codewords, mapping the interleaved LDPC codewords to modulation symbols Wherein the mapping to the modulation symbol maps bits included in a predetermined group among a plurality of groups constituting the LDPC codeword to predetermined bits in the modulation symbol.

Here, each of the plurality of groups may be configured with 360 bits.

The interleaving may include interleaving parity bits constituting the LDPC codeword, separating the parity interleaved LDPC codeword into the plurality of groups, and rearranging the order of the plurality of groups into groups And interleaving the plurality of groups in which the order is rearranged.

Here, the step of rearranging the order of the plurality of groups on a group basis may rearrange the order of the plurality of groups on a group basis based on Equation (11).

In this case, in Equation (11),? (J) may be determined based on at least one of the length of the LDPC codeword, the modulation scheme, and the coding rate.

(J) can be defined as shown in Table 37 when the length of the LDPC codeword is 64,800, the modulation scheme is 256-QAM, and the code rate is 6/15.

(J) can be defined as shown in Table 38 when the length of the LDPC codeword is 64,800, the modulation scheme is 256-QAM, and the code rate is 8/15.

(J) can be defined as shown in Table 39 when the length of the LDPC codeword is 64,800, the modulation scheme is 256-QAM, and the code rate is 10/15.

(J) can be defined as shown in Table 40 when the length of the LDPC codeword is 64,800, the modulation scheme is 256-QAM, and the code rate is 10/15.

(J) can be defined as Table 41 when the length of the LDPC codeword is 64800, the modulation scheme is 256-QAM, and the code rate is 12/15.

The interleaving of the plurality of groups may include writing the plurality of groups in a column direction to each of the plurality of columns in the column direction and arranging each row of the plurality of columns written in the group unit in the column direction And interleaving can be performed.

Here, the interleaving of the plurality of groups may be performed by sequentially writing at least a part of groups each of which can be written in each of the plurality of columns in the plurality of columns into each of the plurality of columns, The at least a part of the groups may be written in a group unit, and the remaining groups may be divided and written in the remaining area.

The step of rearranging the order of the plurality of groups on a group basis may include the step of rearranging the order of the plurality of groups so that the array units in which at least one group including bits mapped to the same positions of different modulation symbols are arranged adjacent to each other, The order of the groups may be rearranged in units of groups so that the predetermined group is written in the predetermined column.

Here, the step of mapping to the modulation symbol may generate the modulation symbol by mapping a bit output from the predetermined column to a predetermined bit in the modulation symbol.

According to various embodiments of the present invention, it is possible to provide better decoding and reception performance.

1 is a block diagram illustrating a configuration of a transmitting apparatus according to an embodiment of the present invention;
2 and 3 are views for explaining the structure of a parity check matrix according to an embodiment of the present invention,
4 is a block diagram illustrating a structure of an interleaver according to an embodiment of the present invention.
5 to 7 are diagrams illustrating a method of processing an LDPC codeword group by group according to an embodiment of the present invention,
8 to 11 are views for explaining the structure and interleaving method of a block interleaver according to an embodiment of the present invention,
12 and 13 are diagrams for explaining the operation of the demultiplexer according to an embodiment of the present invention,
FIG. 14 is a diagram for explaining an example of a uniform constellation modulation method according to an embodiment of the present invention;
FIGS. 15 to 19 are diagrams for explaining an example of a non-uniform constellation modulation method according to an embodiment of the present invention;
20 to 22 are diagrams illustrating performance of a signal processing method according to an embodiment of the present invention,
23 is a block diagram illustrating a structure of an interleaver according to another embodiment of the present invention.
FIGS. 24 to 26 are views for explaining the structure and interleaving method of a block-row interleaver according to an embodiment of the present invention,
27 is a block diagram illustrating a configuration of a receiving apparatus according to an embodiment of the present invention;
28 and 29 are block diagrams for explaining a structure of a deinterleaver according to an embodiment of the present invention, and Fig.
30 is a flowchart for explaining a signal processing method according to an embodiment of the present invention.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

1 is a block diagram illustrating a configuration of a transmitting apparatus according to an embodiment of the present invention. 1, a transmitting apparatus 100 includes an encoding unit 110, an interleaver 120, and a modulating unit 130 (or a constellation mapper).

The encoding unit 110 performs Low Density Parity Check (LDPC) encoding to generate an LDPC codeword. To this end, the encoding unit 110 may include an LDPC encoder (not shown) for performing LPDC encoding.

Specifically, the encoding unit 110 may perform LDPC encoding of input bits with information bits to generate an LDPC codeword composed of information bits and parity bits (i.e., LDPC parity bits) . In this case, since the LPDC code is a systematic code, information bits can be directly included in the LDPC codeword.

In this case, the LDPC codeword consists of information bits and parity bits. For example, it consists LDPC codeword is N _ldpc bits and may comprise K _ldpc of bits comprising information bits and _parity N = N -K _{ldpc ldpc} parity bits consisting of bits.

In this case, the encoding unit 110 may perform LDPC encoding based on a parity check matrix (PCM) to generate an LDPC codeword. That is, the process for performing LDPC encoding is in terms of generating a LDPC code words to satisfy the H and C ^T = 0, the encoding unit 110 may be used when LDPC encoding parity check matrix. Here, H denotes a parity check matrix, and C denotes an LDPC codeword.

To this end, the transmitting apparatus 100 may have a separate memory and store various types of parity check matrices.

For example, the transmitting apparatus 100 may be a DVB-C2 (Digital Video Broadcasting-Cable version 2), a DVB-S2 (Digital Video Broadcasting-Satellite-Second Generation) Or a parity check matrix defined in the ATSC (Advanced Television Systems Committee) 3.0 standard, which is currently being standardized, may be stored in the parity check matrix. However, this is only an example, and the transmitting apparatus 100 may store various types of parity check matrices in addition to the above.

Hereinafter, the structure of the parity check matrix will be described in detail with reference to FIG. 2 and FIG.

2, the parity check matrix 200 includes an information word partial matrix 210, which is a partial matrix corresponding to information word bits, and a parity partial matrix 220, which is a partial matrix corresponding to parity bits. do. Elements of the parity check matrix 200 excluding 1 are 0.

The information word _sub- matrix 210 includes K _ldpc columns and the parity submatrix 220 includes N _parity = N _ldpc- K _ldpc columns. On the other hand, the number of rows of the parity check matrix 200 is equal to the number of columns N _parity = N _ldpc- K _ldpc of the parity partial matrix 220.

In the parity check matrix 200, N _ldpc denotes the length of the LDPC codeword, K _ldpc denotes the length of the information bits, and N _parity = N _ldpc -K _ldpc denotes the length of the parity bits. Here, the length of the LDPC codeword, information word bits, and parity bits means the number of bits included in each of the LDPC codeword, information word bits, and parity bits.

Hereinafter, the structure of the information word partial matrix 210 and the parity partial matrix 220 will be described.

The information word submatrix 210 is a matrix including K _ldpc columns (i.e., the 0th column to the K _ldpc - 1th column), and follows the following rules.

First, the K _ldpc columns constituting the information word submatrix 210 belong to the same M groups, and are divided into a total of K _ldpc / M column groups. The columns belonging to the same column group have cyclic shift by Q _ldpc .

Here, M is the interval at which the column pattern is repeated at the information word _sub- matrix 210 (M = 360 for example), and Q _ldpc is the size at which each column is cyclically shifted in the information word _sub- matrix 210. M and Q _ldpc are integers and are determined such that Q _ldpc = (N _{ldpc -} K _ldpc ) / M holds. At this time, K _ldpc / M is also an integer. Meanwhile, M and Q _ldpc can have various values according to the length of the LDPC codeword and the code rate.

For example, M = 360, and if the case of the LDPC codeword length N _ldpc is 64800 Q _ldpc is defined as shown in Table 1 below, M = 360 and the LDPC codeword length N _ldpc is 16200 to the Q _ldpc As shown in Table 2 below.

이라 하면, i 번째 열 그룹 내의 j 번째 열에서 k 번째 무게-1(weight-1)이 위치한 행의 인덱스

(즉, i 번째 열 그룹 내의 j 번째 열에서 k 번째 1이 위치한 행의 인덱스)는 하기의 수학식 1과 같이 결정된다.Second, the degree of the 0th column of the i-th (i = 0,1, .., K _ldpc / M-1) column group (where the degree is the number of 1 values existing in the column, (Or the index of all the rows belonging to is the same) is _denoted by D _i , and the position (or index) of each row having 1 in the 0th column of the i-th column group is

, The index of the row where the kth weight -1 (weight-1) is located in the jth column in the i-th column group

(I. E., The index of the row in which the kth < th > 1 in the jth column in the ith column group is located) is determined as follows:

Here, k = 0,1,2, ..., D _i -1, i = 0,1, ..., K _ldpc / M-1, j = 1,2, ..., M-1.

Meanwhile, Equation 1 can be expressed equally as Equation 2 below

Here, k = 0,1,2, ..., D _i -1, i = 0,1, ..., K _ldpc / M-1, j = 1,2, ..., M-1.

는 i 번째 열 그룹 내의 j 번째 열에서 k 번째 무게-1이 위치한 행의 인덱스, N_ldpc는 LDPC 부호어의 길이, K_ldpc는 정보어 비트들의 길이, D_i는 i 번째 열 그룹에 속하는 열들의 차수, M은 하나의 열 그룹에 속하는 열의 개수, Q_ldpc는 각 열이 시클릭 쉬프트되는 크기를 의미한다.In these equations,

Of the i-th column belonging to the index of the row in the k-th weight-1 in the j-th column in the column group, N _ldpc length, K is the length _ldpc, D _i of information bits of the LDPC codeword is the i th column group, Order, M is the number of columns belonging to one column group, and Q _ldpc is the size by which each column is _cyclically shifted.

값만을 알면 i 번째 열 그룹 내의 j 번째 열에서 k 번째 무게-1이 있는 행의 인덱스

를 알 수 있게 된다. 그러므로, 각각의 열 그룹 내의 첫 번째 열에서 k 번째 무게-1이 있는 행의 인덱스 값을 저장하면, 도 2의 구조를 갖는 패리티 검사 행렬(200)(즉, 패리티 검사 행렬(200)의 정보어 부분 행렬(210))에서 무게-1이 있는 열과 행의 위치가 파악될 수 있다.As a result, referring to these equations

If the value is known only, the index of the row having the kth weight -1 in the jth column in the ith column group

. Therefore, if the index value of the row having the kth weight -1 in the first column in each column group is stored, the parity check matrix 200 having the structure of FIG. 2 (i.e., the information word of the parity check matrix 200) The partial matrix 210), the position of the row and column with weight -1 can be grasped.

According to the above rules, the orders of the columns belonging to the ith column group are all the same as D _i . Accordingly, an LDPC code storing information on a parity check matrix according to the above rules can be briefly expressed as follows.

For example, the N _ldoc 30, K _ldpc is 15, Q _ldpc the case of three, position information of the rows are in weight -1 in the 0th column of the three columns group to represented by a sequence such as the equation (3) , Which may be referred to as a " weight-1 position sequence ".

는 i번째 열 그룹 내의 j번째 열에서 k번째 무게-1이 있는 행의 인덱스를 의미한다.From here,

Denotes an index of a row having the kth weight -1 in the jth column in the ith column group.

The weight-1 position sequences such as Equation (3) representing the index of the row where 1 is located in the 0th column of each column group can be expressed more simply as shown in Table 3 below.

Table 3 shows the position of the weight-1, that is, the one having the value 1 in the parity check matrix. In the i-th weight-1 position sequence, Lt; / RTI >

The information word sub-matrix 210 of the parity check matrix according to an embodiment of the present invention may be defined by the following Tables 4 to 26 based on the above description.

Specifically, Tables 4 to 26 show indices of a row in which 1 is located in the 0th column of the i-th column group of the information word submatrix 210. [ That is, the information word sub-matrix 210 is composed of a plurality of column groups each including M columns, and the position of 1 in the 0th column of each of the plurality of column groups can be defined by Tables 4 to 26 .

Here, the indexes of the row where 1 is located in the 0th column of the i-th column group means "addresses of parity bit accumulators". In the meantime, the "addresses of parity bit accumulators" have the same meanings as those defined in the DVB-C2 / S2 / T2 standard or the ATSC 3.0 standard currently being established.

For example, when the length N _ldpc of the LDPC codeword is 16200, the coding rate R is 5/15, and M is 360, the index of the row where 1 is located in the 0th column of the i-th column group of the information word submatrix 210 Are shown in Table 4 below.

As another example, when the length N _ldpc of the LDPC codeword is 16200, the coding rate R is 6/15, and M is 360, the index of the row where 1 is located in the 0th column of the i-th column group of the information word submatrix 210 Are shown in Table 5 below.

As another example, when the length N _ldpc of the LDPC codeword is 16200, the coding rate R is 7/15, and M is 360, a row of the row where 1 is located in the 0th column of the i-th column group 210 of the information word submatrix 210 The indices are shown in Table 6 below.

As another example, when the length N _ldpc of the LDPC codeword is 16200, the coding rate R is 8/15, and M is 360, the number of rows of the row where the 1 is located in the 0th column of the i-th column group 210 of the information word submatrix 210 The indices are shown in Table 7, Table 8, or Table 9 below.

As another example, when the length N _ldpc of the LDPC codeword is 16200, the code rate R is 9/15, and the number of codes M is 360, the number of rows of the row where 1 is located in the 0th column of the i- The indices are shown in Table 10 below.

As another example, when the length N _ldpc of the LDPC codeword is 16200, the coding rate R is 10/15, and M is 360, a row of the row where the 1 is located in the 0th column of the i-th column group 210 of the information word submatrix 210 The indices are shown in Table 11, Table 12, or Table 13 below.

As another example, when the length N _ldpc of the LDPC codeword is 16200, the coding rate R is 11/15, and M is 360, the row of the row where 1 is located in the 0th column of the i-th column group 210 of the information word submatrix 210 The indices are shown in Table 14 below.

As another example, when the length N _ldpc of the LDPC codeword is 16200, the coding rate R is 12/15, and M is 360, the row of the row where 1 is located in the 0th column of the i-th column group 210 of the information word submatrix 210 The indices are shown in Table 15 or Table 16 below.

As another example, when the length N _ldpc of the LDPC codeword is 16200, the coding rate R is 13/15, and M is 360, the number of rows of the row where the 1 is located in the 0th column of the i-th column group 210 of the information word submatrix 210 The indexes are shown in Table 17 below.

As another example, when the length N _ldpc of the LDPC codeword is 64800, the code rate R is 5/15, and the number of codes is M 360, a row of the row where the 1 is located in the 0th column of the i-th column group 210 of the information word sub- The indices are shown in Table 18 below.

As another example, when the length N _ldpc of the LDPC codeword is 64,800, the coding rate R is 6/15, and M is 360, the number of rows of the row where the 1 is located in the 0th column of the i-th column group 210 of the information word submatrix 210 The indices are shown in Table 19 below.

As another example, when the length N _ldpc of the LDPC codeword is 64800, the code rate R is 7/15, and the number of codes M is 360, the number of rows of the row where 1 is located in the 0th column of the i- The indices are shown in Table 20 or Table 21 below.

As another example, when the length N _ldpc of the LDPC codeword is 64,800, the coding rate R is 8/15, and M is 360, the number of rows of the row where the 1 is located in the 0th column of the i-th column group 210 of the information word submatrix 210 The indexes are shown in Table 22 below.

As another example, when the length N _ldpc of the LDPC codeword is 64800, the coding rate R is 9/15, and M is 360, a row of the row where 1 is located in the 0th column of the i-th column group 210 of the information word sub- The indexes are shown in Table 23 below.

As another example, when the length N _ldpc of the LDPC codeword is 64800, the coding rate R is 10/15, and M is 360, the number of rows of the row where the 1 is located in the 0th column of the i-th column group 210 of the information word sub- The indexes are shown in Table 24 or Table 25 below.

As another example, when the length N _ldpc of the LDPC codeword is 64800, the code rate R is 12/15, and the number of codes M is 360, the row of the row where the 1 is located in the 0th column of the ith column group of the information word submatrix 210 The indices are shown in Table 26 below.

In Table 4 to Table 26, even though the order of the numbers in the sequence corresponding to each i-th column group is changed, it is the parity check matrix of the same sign. In the tables 4 to 26, May be an example of codes considered in the present invention.

In addition, even if the order of the sequences corresponding to each column group is changed in Tables 4 to 26, since the algebraic characteristics such as the cycle characteristics and the order distributions on the graph of the sign do not change, the order of the sequences shown in Tables 4 to 26 An example of a change is an example.

In addition, since the algebraic properties such as the cycle characteristic and the order distribution on the graph of the sign do not change as a result of adding a multiple of Q _ldpc to all the sequences corresponding to arbitrary column groups in Tables 4 to 26, The results obtained by adding a multiple of Q _ldpc to all of the sequences shown in Table 26 may be one example. Note that if a value is greater than (N _ldpc -K _ldpc ) by a factor of Q _ldpc times the given sequence, then the modulo operation (N _ldpc -K _ldpc ) To the value applied.

On the other hand, if the position of a row in which 1 exists in the 0th column of the i-th column group of the information word sub-matrix 210 is defined as shown in Tables 4 to 26, it is _cyclically shifted by Q _ldpc , The position of the row where a 1 exists in the column can be defined.

For example, in the case of Table 4, in the 0th column of the 0th column group of the information word partial matrix 210, the 245th row, the 449th row, the 491st row, 1 is present.

In this case, the index of the row where 1 is located in the first column of the 0th column group is 275 (= 245 + 30) because Q _ldpc = (N _ldpc -K _ldpc ) / M = (16200-5400) / 360 = , 479 (= 449 + 30), 521 (= 491 + 30), ... And the index of the row where 1 is located in the second column of the 0th column group may be 305 (= 275 + 30), 509 (= 479 + 30), and 551 (= 521 + 30).

In the parity check matrix 200 shown in FIG. 2, the parity partial matrix 220 may be defined as follows.

The parity partial matrix 220 is a partial matrix including N _ldpc- K _ldpc columns (i.e., K _ldpc th column to N _ldpc -1 th column), and has a dual diagonal structure. Therefore, the order of the remaining columns excluding the last column (i.e., N _ldpc- 1) in the parity part matrix 220 is 2, and the order of the last column is 1. [

As a result, in the parity check matrix 200, the information word partial matrix 210 is defined by Tables 4 to 26, and the parity partial matrix 220 may have a double diagonal structure.

2 is permutated based on the following equations (4) and (5), the parity check matrix 200 shown in FIG. 2 corresponds to the parity check matrix shown in FIG. 3 May be expressed in the form of a parity check matrix 300 shown in FIG.

A method of performing permutation based on Equation (4) and Equation (5) is as follows. Here, the low permutation and the column permutation are applied to the same principle. Hereinafter, the low permutation will be described as an example.

In the case of the low permutation, i, j satisfying X = Q _ldpc x i + j for the X th row is calculated, and the calculated i, j is substituted into M x j + i, . For example, in the case of the seventh row, since i and j satisfying 7 = 2 x i + j are 3,1, respectively, the seventh row is permutated to 10 x 1 + 3 = thirteenth row.

When the low permutation and the column permutation are performed in this manner, the parity check matrix of FIG. 2 can be expressed as shown in FIG.

Referring to FIG. 3, the parity check matrix 300 includes a parity check matrix 300 divided into a plurality of partial blocks, and a quasi-cyclic (M × M) Matrix.

Accordingly, the parity check matrix 300 having the structure as shown in FIG. 3 is configured in matrix units of M × M size. That is, the parity check matrix 300 is constructed by arranging partial matrices having M × M sizes in a plurality of partial blocks.

As described above, since the parity check matrix 300 is composed of M × M sub-matrixes, it is possible to designate M columns as a column-block and M rows as a row-block have. Thus, parity check matrix 300 has a structure as shown in FIG. 3 used in the present invention is N _{qc _ column} = N _ldpc / M column blocks and N _{qc _ row} = N _parity / M of which consists of a block of lines .

Hereinafter, a partial matrix having an M × M size will be described.

First, the 0-th block of lines (N _{_ column qc} - 1) th column block in the form of equation (6) below.

As described above, the A 330 is an M × M matrix, and the values of the 0th row and the (M-1) th column are both '0' 1) th row is '1' and all other values are '0'.

Second, in the parity part matrix _{(320) 0≤i≤ (N ldpc -K} ldpc) with respect to _{/ M-1 (K ldpc /} M + i) i -th row block of the first column block is a unit matrix I _{M × M} ( 340). Further, in _{0≤i≤ (N ldpc -K ldpc) /} M-2 with respect to the (K _ldpc / M + i) th column of the block (i + 1) th row block is an identity matrix I _{M × M} (340) .

또는, 순환 행렬 P가 시클릭 쉬프트된 행렬

이 합해진 형태(또는, 중첩된 형태)가 될 수 있다. Third, the block 350 composing the information word partial matrix 310 is a block in which the circulating matrix P is a cyclic shifted form

Alternatively, if the cyclic matrix P is a cyclic shifted matrix

(Or a superimposed form).

For example, the form in which the circulation matrix P is cyclically shifted by 1 in the right direction can be expressed by Equation (7).

The circulating matrix P is a square matrix having an M × M size, and the circulating matrix P represents a matrix in which the weight of each of the M rows is 1 and the weight of each of the M columns is also 1. When the superscript a _ij is 0, ie, P ⁰ represents the identity matrix I _{M × M} , and the superscript a _ij is ∞, ie, P ^∞ represents a zero matrix.

가 될 수 있다. 따라서, i와 j는 정보어 부분에 해당하는 부분 블록들의 행 블록과 열 블록의 개수를 나타낸다. 따라서, 패리티 검사 행렬(300)은 전체 열의 개수가 N_ldpc=M×N_{qc _ column}이고, 전체 행의 개수가 N_parity=M×N_{qc _ row}가 된다. 즉, 패리티 검사 행렬(300)은 N_{qc _ column} 개의 "열 블록"과 N_{qc _ row} 개의 "행 블록"으로 구성된다.3, a partial matrix existing at the intersection of the i-th row block and the j-th column block of the parity check matrix 300

. Thus, i and j represent the number of row blocks and column blocks of partial blocks corresponding to the information word portion. Thus, parity check matrix 300 is the total number of columns N _ldpc = M × N _{_ qc column,} the number of the entire line is the _parity N = M × N _{_ qc row.} That is, the parity check matrix 300 is composed of N _{_ qc column} of "column block" and N _{qc _ row} of "line block".

Returning to FIG. 1, the encoding unit 110 may encode various codes such as 5/15, 6/15, 7/15, 8/15, 9/15, 10/15, 11/15, 12/15, 13/15, Rate can be used to perform LDPC encoding. The encoding unit 110 may generate LDPC codewords having various lengths such as 16200 and 64800 based on the length of the information word bits and the code rate.

In this case, the encoding unit 110 uses the parity check matrix (i.e., the parity check matrix shown in FIG. 2) in which the information word partial matrix is defined by Tables 4 to 26 and the parity partial matrix has the double diagonal structure, 2, or a parity check matrix shown in FIG. 2 can perform LDPC encoding using a row and column permutated parity check matrix (i.e., a structure as shown in FIG. 3) based on Equations 4 and 5 have.

In addition, the encoding unit 110 may perform BCH (Bose, Chaudhuri, Hocquenghem) encoding as well as LDPC encoding. For this, the encoding unit 110 may further include a BCH encoder (not shown) for performing BCH encoding.

In this case, the encoding unit 110 can perform encoding in the order of BCH encoding and LDPC encoding. Specifically, the encoding unit 110 performs BCH encoding on the input bits to add a BCH parity bit, performs LDPC encoding on the bits to which the BCH parity bit is added, as information bits, and generates an LDPC codeword You may.

The interleaver 120 interleaves the LDPC codeword. That is, the interleaver 120 receives the LDPC codeword from the encoding unit 110 and interleaves the LDPC codeword based on various interleaving rules.

In particular, the interleaver 120 is configured so that the bits included in the predetermined group among the plurality of groups (or the plurality of bit groups or the plurality of blocks) constituting the LDPC codeword are mapped to predetermined bits in the modulation symbol, Can be interleaved.

Hereinafter, the interleaving rules used in the interleaver 120 will be described more specifically.

Example 1: Interleaver  When to use

In the first embodiment of the present invention, the interleaver 120 interleaves the LDPC codeword by the following method, and the bits included in the predetermined group among the plurality of groups constituting the interleaved LDPC codeword are interleaved in the modulation symbol It can be mapped to a set bit. Reference is made to Fig. 4 for a detailed description.

4 is a block diagram illustrating the structure of an interleaver according to an embodiment of the present invention. 4, the interleaver 120 includes a parity interleaver 121, a group interleaver (or a group-wise interleaver 122), a group twisted interleaver 123, and a block interleaver 124.

The parity interleaver 121 interleaves the parity bits constituting the LDPC codeword.

Specifically, when the LDPC codeword is generated based on the parity check matrix 200 having the structure as shown in FIG. 2, the parity interleaver 121 interleaves only the parity bits among the LDPC codewords using the following equation (8) .

)에 대해 패리티 인터리빙을 수행하여 U=(u₀,u₁,…,

)를 출력할 수 있다.Here, M is the interval at which the pattern of the column is repeated in the information word _sub- matrix 210, that is, the number of columns included in the column group (for example, M = 360), Q _ldpc is the The size of the column is the cyclic shift. That is, the parity interleaver 121 receives the LDPC codeword c = (c ₀ , c ₁ ,

) Are subjected to parity interleaving to obtain U = (u ₀ , u ₁ , ...,

Can be output.

When the LDPC codeword coded based on the parity check matrix 200 shown in FIG. 2 is parity interleaved based on Equation (8), the parity interleaved LDPC codeword is encoded by the parity check matrix 300 as shown in FIG. LDPC codeword. Therefore, when the LDPC codeword is generated based on the parity check matrix 300 shown in FIG. 3, the parity interleaver 121 can be omitted.

On the other hand, the LDPC coders that are encoded based on the parity check matrix 200 having the form of FIG. 2 and then parity-interleaved, or the LDPC coders that are encoded based on the parity check matrix 300 having the form of FIG. 3, The successive bits may be configured to have similar decoding properties (cycle distribution, order of columns, etc.).

For example, an LDPC codeword may have the same characteristics in consecutive M bits. Here, M may be 360, for example, at a repetition interval of the pattern of columns in the information word submatrix.

Specifically, LDPC codeword, and bits and the parity check matrix should be a product of '0', which i is from 0 to N-th i _ldpc -1 LDPC codeword bit _{c i (i = 0,1, ...} , N _ldpc -1) and the sum of the products of the columns of the i-th parity check matrix should be a '0' vector. Therefore, the i-th LDPC codeword bit can be regarded as corresponding to the i-th column of the parity check matrix.

On the other hand, the parity check matrix belongs to the same group of M columns, and the order of M columns belonging to the same column group is the same, and generally has a large cycle characteristic. Thus, the M consecutive bits in the LDPC codeword correspond to the same column group in the parity check matrix, and since the cycles between consecutive M bits are substantially large, these bits can be regarded as having a low decoding relevance.

Specifically, in the case of the parity check matrix 200 shown in FIG. 2, the information word sub-matrix 210 has the same characteristics (for example, the columns in the same column group have the same degree distribution in units of column groups including M columns The information word bits of the LDPC codeword coded based on the parity check matrix 200 are composed of consecutive M bits having the same codeword property. When the parity bits of the LDPC codeword are interleaved by the parity interleaver 121, the parity bits of the LDPC codeword may be composed of consecutive M bits having the same codeword characteristics.

3, the information word partial matrix 310 and the parity partial matrix 320 of the parity check matrix 300 may include M columns by row and column permutation, The information bits and the parity bits of the LDPC codeword coded based on the parity check matrix 300 are composed of consecutive M bits having the same codeword characteristics.

Here, the low permutation has no influence on the algebraic properties of the LDPC code itself, such as cycle characteristics, order distribution, and minimum distance, in that the row permutation is merely to rearrange the order of the rows in the parity check matrix. The column permutation is performed for the parity partial matrix 320 so as to correspond to the parity interleaving performed in the parity interleaver 121. In the column permutation, the LDPC codes coded by the parity check matrix 300 shown in FIG. The parity bits of the codeword may be composed of consecutive M bits such as parity bits of the LDPC codeword coded by the parity check matrix 200 as shown in FIG.

Accordingly, the bits constituting the LDPC codeword can have the same characteristics in units of consecutive M bits.

The group interleaver 122 may classify the parity interleaved LDPC codewords into a plurality of groups and rearrange the order of the plurality of groups into group wise. That is, the group interleaver 122 can interleave the plurality of groups in units of groups.

For this, the group interleaver 122 divides the parity-interleaved LDPC codewords into a plurality of groups using Equation (9) or Equation (10) below.

는 k/360 이하의 가장 큰 정수를 나타낸다. In these equations, N _group represents the total number of groups, X _j represents the j-th group, and u _k represents the k-th LDPC codeword bit input to the group interleaver 122. And,

Represents the largest integer of k / 360 or less.

On the other hand, in these equations, 360 represents an example of M, which is an interval in which a column pattern is repeated in an information word partial matrix. In these equations, 360 can be changed to M.

On the other hand, LDPC codewords divided into a plurality of groups can be represented as shown in FIG.

Referring to FIG. 5, it can be seen that the LDPC codewords are divided into a plurality of groups, and each group consists of M consecutive bits.

Specifically, since the LDPC codeword is divided into consecutive M bits, the K _ldpc information bits are divided into (K _ldpc / M) groups, and the N _ldpc -K _ldpc parity bits (N _ldpc -K _ldpc ) / M groups. Accordingly, the LDPC codeword can be divided into a total of (N _ldpc / M) groups.

For example, if M = 360, the number of groups N _group is 180 when the length N _ldpc of the LDPC codeword is 64800, and the number N _group of _groups becomes 45 when the length _Nldpc of the LDPC codeword is 16200 .

The reason why the group interleaver 122 divides the LDPC codeword into the same group of consecutive M bits is that the LDPC coders have the same codeword characteristics in consecutive M bits as described above. Accordingly, when the LDPC codeword is divided into consecutive M bits, bits having the same codeword characteristics can be included in the same group.

Then, the group interleaver 122 interleaves the LDPC codeword group by group. That is, the group interleaver 122 can rearrange the order of a plurality of groups constituting the LDPC codeword group by changing positions of a plurality of groups constituting the LDPC codeword.

In this case, the group interleaver 122 can rearrange the order of the plurality of groups into groups using the following equation (11).

Here, X _j denotes the j-th group before the group interleaving, Y _j represents the j th group after group interleaving.

Further,? (J) is a parameter indicating an interleaving sequence and may be determined by at least one of the length, the coding rate and the modulation method of the LDPC codeword.

Meanwhile, a specific example of? (J) according to an embodiment of the present invention can be defined as shown in Tables 27 to 41 below.

For example, when the LDPC codeword length _Nldpc is 16200 and the coding rates are 10/15, 11/15, 12/15, and 13/15 and the modulation scheme is 16-QAM, π (j) Or Table 28. < tb >< TABLE >

In the case of Table 27, Equation 11 is expressed as Y ₀ = X _{? (0)} = X ₇ , Y ₁ = X _{? (1)} = X ₁₇ , Y ₂ = X _{? (2)} = X ₃₃ , , Y ₄₃ = X _{? (43)} = X ₁₃ , Y ₄₄ = X _{? (44)} = X ₄₄ . Accordingly, the group interleaver 122 sets the seventh group to the 0th, the 17th group to the 1st, the 33rd to the 2nd, and so on. , The thirteenth group to the 43rd group, and the 44th group to the 44th order, so that the order of the plurality of groups can be rearranged in groups.

In the case of Table 28, Equation 11 is expressed as Y ₀ = X _{? (0)} = X ₆ , Y ₁ = X _{? (1)} = X ₃₄ , Y ₂ = X _{? (2)} = X ₁₁ , ... , Y ₄₃ = X _{? (43)} = X ₂₇ , Y ₄₄ = X _{? (44)} = X ₂₉ . Accordingly, the group interleaver 122 sets the sixth group to the 0th, the 34th group to the first, the 11th group to the second, and so on. The 27th group to the 43rd group, and the 29th group to the 44th order, the order of the plurality of groups can be rearranged in groups.

As another example, when the LDPC codeword length _Nldpc is 16200 and the coding rates are 6/15, 7/15, 8/15, 9/15 and the modulation scheme is 64-QAM, π (j) Or Table 30.

In the case of Table 29, Equation 11 is expressed as Y ₀ = X _{? (0)} = X ₃₂ , Y ₁ = X _{? (1)} = X ₄ , Y ₂ = X _{? (2)} = X ₂₃ , , Y ₄₃ = X _{? (43)} = X ₄₃ , Y ₄₄ = X _{? (44)} = X ₄₄ . Accordingly, the group interleaver 122 sets the 32nd group to the 0th, the 4th group to the 1st, the 23rd group to the 2nd, ... The 43rd group to the 43rd group, and the 44th group to the 44th order, the order of the plurality of groups can be rearranged in a group unit.

In the case of Table 30, Equation 11 is expressed as Y ₀ = X _{? (0)} = X ₃₂ , Y ₁ = X _{? (1)} = X ₁₆ , Y ₂ = X _{? (2)} = X ₁₈ , , Y ₄₃ = X _{? (43)} = X ₄₃ , Y ₄₄ = X _{? (44)} = X ₄₄ . Accordingly, the group interleaver 122 sets the 32nd group to the 0th, the 16th group to the 1st, the 18th to the 2nd, and so on. The 43rd group to the 43rd group, and the 44th group to the 44th order, the order of the plurality of groups can be rearranged in a group unit.

As another example, when the LDPC codeword length _Nldpc is 16200 and the coding rates are 10/15, 11/15, 12/15, 13/15 and the modulation scheme is 256-QAM, π (j) Or Table 32. < tb >< TABLE >

In the case of Table 31, Equation 11 is expressed as Y ₀ = X _{? (0)} = X ₂₈ , Y ₁ = X _{? (1)} = X ₆ , Y ₂ = X _{? (2)} = X ₁₅ , , Y ₄₃ = X _{? (43)} = X ₄₃ , Y ₄₄ = X _{? (44)} = X ₄₄ . Accordingly, the group interleaver 122 sets the 28th group to the 0th, the 6th group to the 1st, the 15th group to the 2nd, ... The 43rd group to the 43rd group, and the 44th group to the 44th order, the order of the plurality of groups can be rearranged in a group unit.

In the case of Table 32, Equation 11 is expressed as Y ₀ = X _{? (0)} = X ₂₁ , Y ₁ = X _{? (1)} = X ₈ , Y ₂ = X _{? (2)} = X ₃₀ , , Y ₄₃ = X _{? (43)} = X ₂₈ , and Y ₄₄ = X _{? (44)} = X ₂₉ . Accordingly, the group interleaver 122 sets the 21st group to the 0th, the 8th group to the 1st, the 30th to the 2nd, and so on. , The 28th group to the 43rd group, and the 29th group to the 44th order, so that the order of the plurality of groups can be rearranged in groups.

As another example, when the LDPC codeword length _Nldpc is 16200 and the coding rates are 6/15, 7/15, 8/15, 9/15 and the modulation scheme is 1024-QAM, π (j) Or Table 34. < tb >< TABLE >

In the case of Table 33, Equation 11 is expressed as Y ₀ = X _{? (0)} = X ₁₆ , Y ₁ = X _{? (1)} = X ₁₃ , Y ₂ = X _{? (2)} = X ₁ , ... , Y ₄₃ = X _{? (43)} = X ₄₃ , Y ₄₄ = X _{? (44)} = X ₄₄ . Accordingly, the group interleaver 122 sets the 16th group to the 0th, the 13th group to the 1st, the 1st to the 2nd, and so on. The 43rd group to the 43rd group, and the 44th group to the 44th order, the order of the plurality of groups can be rearranged in a group unit.

For Table 34, Equation 11 _{Y 0 = X π (0)} = X 16, Y 1 = X π (1) = X 12, Y 2 = X π (2) = X 14, ... , Y ₄₃ = X _{? (43)} = X ₃₈ , Y ₄₄ = X _{? (44)} = X ₃₉ . Accordingly, the group interleaver 122 sets the 16th group to the 0th, the 12th group to the 1st, the 14th to the 2nd, and so on. , The 38th group to the 43rd group, and the 39th group to the 44th order, so that the order of the plurality of groups can be rearranged in groups.

As another example, when the LDPC codeword length N _ldpc is 64800 and the coding rates are 6/15, 7/15, 8/15, 9/15 and the modulation method is 256-QAM, π (j) Or Table 36. < tb >< TABLE >

In the case of Table 35, Equation 11 is expressed as Y ₀ = X _{? (0)} = X ₄₈ , Y ₁ = X _{? (1)} = X ₄ , Y ₂ = X _{? (2)} = X ₁₅ , , Y ₁₇₈ = X _{17 (178)} = X ₁₇₈ , Y ₁₇₉ = X _{17 (179)} = X ₁₇₉ . Accordingly, the group interleaver 122 sets the 48th group to the 0th, the 4th group to the 1st, the 15th group to the 2nd, ... , The 178th group is changed to the 178th group, and the 179th group is changed to the 179th group, so that the order of the plurality of groups can be rearranged in groups.

In the case of Table 36, Equation 11 is expressed as Y ₀ = X _{? (0)} = X ₄₈ , Y ₁ = X _{? (1)} = X ₆₁ , Y ₂ = X _{? (2)} = X ₆₅ , , Y ₁₇₈ = X _{17 (178)} = X ₁₇₈ , Y ₁₇₉ = X _{17 (179)} = X ₁₇₉ . Accordingly, the group interleaver 122 sets the 48th group to 0, 61st to 1, 65th to 2 < th > , The 178th group is changed to the 178th group, and the 179th group is changed to the 179th group, so that the order of the plurality of groups can be rearranged in groups.

As another example, if the length _Nldpc of the LDPC codeword is 64800 and the coding rate is 6/15 and the modulation scheme is 256-QAM,? (J) can be defined as shown in Table 37 below.

For Table 37, Equation 11 _{Y 0 = X π (0)} = X 53, Y 1 = X π (1) = X 3, Y 2 = X π (2) = X 28, ... , Y ₁₇₈ = X ₍₁₇₈₎ = X ₂₆ , Y ₁₇₉ = X ₍₁₇₉₎ = X ₃₁ . Accordingly, the group interleaver 122 sets the 53rd group to the 0th, the 3rd group to the 1st, the 28th to the 2nd group, , The 26th group is changed to the 178th group, and the 31st group is changed to the 179th group, so that the order of a plurality of groups can be rearranged in groups.

As another example, if the length N _ldpc of the LDPC codeword is 64800, the coding rate is 8/15, and the modulation scheme is 256-QAM,? (J) can be defined as shown in Table 38 below.

In the case of Table 38, Equation 11 is expressed as Y ₀ = X _{? (0)} = X ₇₁ , Y ₁ = X _{? (1)} = X ₁₀₄ , Y ₂ = X _{? (2)} = X ₈₄ , , Y ₁₇₈ = X ₍₁₇₈₎ = X ₁₆ , and Y ₁₇₉ = X ₍₁₇₉₎ = X ₁₈ . Accordingly, the group interleaver 122 sets the 71st group to 0, the 104th group to the 1st, the 84th to the 2nd group, , The 16th group is changed to the 178th group, and the 18th group is changed to the 179th group, so that the order of the plurality of groups can be rearranged in groups.

As another example, when the LDPC codeword length _Nldpc is 64,800, the coding rate is 10/15 and the modulation scheme is 256-QAM,? (J) can be defined as shown in Table 39 below. In particular, when the encoding unit 110 performs LDPC encoding based on the parity check matrix defined by Table 24, the group interleaver 122 performs group interleaving using? (J) defined as Table 39 can do.

In the case of Table 39, Equation 11 shows that Y ₀ = X _{π (0)} = X ₁₁₁ , Y ₁ = X _{π (1)} = X ₆₅ , Y ₂ = X _{π (2)} = X ₇₈ , , Y ₁₇₈ = X ₍₁₇₈₎ = X ₈₅ , and Y ₁₇₉ = X ₍₁₇₉₎ = X ₁₁₈ . Accordingly, the group interleaver 122 sets the 111th group to the 0th, the 65th group to the 1st, the 78th to the 2nd, and so on. , The 85th group is changed to the 178th group, and the 118th group is changed to the 179th group, so that the order of the plurality of groups can be rearranged in groups.

As another example, if the length _Nldpc of the LDPC codeword is 64800, the coding rate is 10/15, and the modulation scheme is 256-QAM,? (J) can be defined as shown in Table 40 below. In particular, when the encoding unit 110 performs LDPC encoding based on the parity check matrix defined by Table 25, the group interleaver 122 performs group interleaving using? (J) defined as Table 40 can do.

In the case of Table 40, Equation 11 is expressed as Y ₀ = X _{? (0)} = X ₈₉ , Y ₁ = X _{? (1)} = X ₆₄ , Y ₂ = X _{? (2)} = X ₅₀ , , Y ₁₇₈ = X ₍₁₇₈₎ = X ₂₇ , and Y ₁₇₉ = X ₍₁₇₉₎ = X ₂₉ . Accordingly, the group interleaver 122 sets the 89th group to 0, the 64th group to the 1st, the 50th to the 2nd group, , The 27th group is changed to the 178th group, and the 29th group is changed to the 179th group, so that the order of the plurality of groups can be rearranged in groups.

As another example, if the length _Nldpc of the LDPC codeword is 64800 and the coding rate is 12/15 and the modulation scheme is 256-QAM,? (J) can be defined as shown in Table 41 below.

In the case of Table 41, Equation 11 is expressed as Y ₀ = X _{? (0)} = X ₅₁ , Y ₁ = X _{? (1)} = X ₁₂₂ , Y ₂ = X _{? (2)} = X ₉₁ , ... , Y ₁₇₈ = X ₍₁₇₈₎ = X ₁₈ , and Y ₁₇₉ = X ₍₁₇₉₎ = X ₂₅ . Accordingly, the group interleaver 122 sets the 51st group to 0, the 122nd group to the 1st, the 91st to the 2nd, and so on. , The 18th group is changed to the 178th group, and the 25th group is changed to the 179th order so that the order of the plurality of groups can be rearranged in groups.

In this way, the group interleaver 12 can rearrange the order of the plurality of groups in units of a group by using Equation (11) and Tables 27 to 41 above.

On the other hand, the groups constituting the LDPC codeword are reordered in group units by the group interleaver 122 and then block interleaved by a block interleaver 124, which will be described later. In Table 27 to Table 41, ) With respect to " Order of bits group to be block interleaved ".

Also, the group interleaver 122 may interleave the LDPC codewords on a group basis using Equation (12).

Here, X _j denotes the j-th group before the group interleaving, Y _j represents the j th group after group interleaving.

Further,? (J) is a parameter indicating an interleaving sequence and may be determined by at least one of the length, the coding rate and the modulation method of the LDPC codeword.

Meanwhile, a specific example of? (J) according to an embodiment of the present invention can be defined as shown in Tables 42 to 51 below.

For example, when the LDPC codeword length N _ldpc is 16200 and the coding rates are 10/15, 11/15, 12/15, and 13/15 and the modulation method is 16-QAM, π (j) Or Table 43. < tb >< TABLE >

For Table 42, the expression (12) is _{X 0 = Y π (0)} = Y 35, X 1 = Y π (1) = Y 31, X 2 = Y π (2) = Y 39, ... , Can be expressed as _{X 43 = Y π (43)} = Y 15, X 44 = Y π (44) = Y 44. Accordingly, the group interleaver 122 sets the 0 th group to the 35 th, the 1 st group to the 31 th, the 2 nd group to the 39 th, and so on. , The 43rd group is changed to the 15th group, and the 44th group is changed to the 44th group, so that the order of the plurality of groups can be rearranged in groups.

For Table 43, the expression (12) is _{X 0 = Y π (0)} = Y 34, X 1 = Y π (1) = Y 40, X 2 = Y π (2) = Y 9, ... , Can be expressed as _{X 43 = Y π (43)} = Y 24, X 44 = Y π (44) = Y 30. Accordingly, the group interleaver 122 sets the 0th group to the 34th, the 1st group to the 40th, the second group to the 9th, and so on. , The 43rd group is changed to the 24th group, and the 44th group is changed to the 30th group, so that the order of the plurality of groups can be rearranged in groups.

As another example, when the LDPC codeword length _Nldpc is 16200 and the coding rates are 6/15, 7/15, 8/15, 9/15 and the modulation scheme is 64-QAM, π (j) Or Table 45. < tb >< TABLE >

For Table 44, the expression (12) is _{X 0 = Y π (0)} = Y 18, X 1 = Y π (1) = Y 31, X 2 = Y π (2) = Y 41, ... , Can be expressed as _{X 43 = Y π (43)} = Y 43, X 44 = Y π (44) = Y 44. Accordingly, the group interleaver 122 sets the 0th group to the 18th, the 1st group to the 31st, the 2 nd group to the 41st, ... The 43rd group to the 43rd group, and the 44th group to the 44th order, the order of the plurality of groups can be rearranged in a group unit.

For Table 45, Equation (12) is _{X 0 = Y π (0)} = Y 3, X 1 = Y π (1) = Y 12, X 2 = Y π (2) = Y 41, ... , Can be expressed as _{X 43 = Y π (43)} = Y 43, X 44 = Y π (44) = Y 44. Accordingly, the group interleaver 122 sets the 0th group to the 3rd, the 1st group to the 12th, the 2nd group to the 41st, ... The 43rd group to the 43rd group, and the 44th group to the 44th order, the order of the plurality of groups can be rearranged in a group unit.

As another example, when the LDPC codeword length _Nldpc is 16200 and the coding rates are 10/15, 11/15, 12/15, and 13/15 and the modulation method is 256-QAM,? (J) Or Table 47. < tb >< TABLE >

For Table 46, the expression (12) is _{X 0 = Y π (0)} = Y 4, X 1 = Y π (1) = Y 13, X 2 = Y π (2) = Y 31, ... , Can be expressed as _{X 43 = Y π (43)} = Y 43, X 44 = Y π (44) = Y 44. Accordingly, the group interleaver 122 sets the 0th group to the fourth, the first group to the 13th, the second to the 31st, ... The 43rd group to the 43rd group, and the 44th group to the 44th order, the order of the plurality of groups can be rearranged in a group unit.

For Table 47, Equation (12) is _{X 0 = Y π (0)} = Y 3, X 1 = Y π (1) = Y 6, X 2 = Y π (2) = Y 19, ... , X ₄₃ = Y ₍₄₃₎ = Y ₃₃ , X ₄₄ = Y ₍₄₄₎ = Y ₃₀ . Accordingly, the group interleaver 122 sets the 0th group to the 3rd, the 1st group to the 6th, the 2nd group to the 19th, and so on. , The 43rd group is changed to the 33rd group, and the 44th group is changed to the 30rd order, so that the order of the plurality of groups can be rearranged in groups.

As another example, when the LDPC codeword length _Nldpc is 16200 and the coding rates are 6/15, 7/15, 8/15, 9/15 and the modulation method is 1024-QAM,? (J) Or Table 49. < tb >< TABLE >

For Table 48, Equation (12) is _{X 0 = Y π (0)} = Y 10, X 1 = Y π (1) = Y 2, X 2 = Y π (2) = Y 28, ... , Can be expressed as _{X 43 = Y π (43)} = Y 43, X 44 = Y π (44) = Y 44. Accordingly, the group interleaver 122 sets the 0th group to the tenth, the first group to the second, the second to the 28th, and so on. The 43rd group to the 43rd group, and the 44th group to the 44th order, the order of the plurality of groups can be rearranged in a group unit.

For Table 49, Equation (12) is _{X 0 = Y π (0)} = Y 32, X 1 = Y π (1) = Y 16, X 2 = Y π (2) = Y 40, ... , X ₄₃ = Y ₍₄₃₎ = Y ₃₉ , X ₄₄ = Y ₍₄₄₎ = Y ₁₃ . Accordingly, the group interleaver 122 sets the 0th group to 32nd, the 1 st group to 16th, the 2 nd group to 40th, and so on. , The 43rd group is changed to the 39th group, and the 44th group is changed to the 13th group, so that the order of a plurality of groups can be rearranged in groups.

As another example, when the LDPC codeword length _Nldpc is 64800 and the coding rates are 6/15, 7/15, 8/15, 9/15 and the modulation scheme is 256-QAM,? (J) Or Table 51. < tb >< TABLE >

For Table 50, Equation (12) is _{X 0 = Y π (0)} = Y 9, X 1 = Y π (1) = Y 6, X 2 = Y π (2) = Y 160, ... _{, X 178 = Y π (178} ) = Y 177, can be expressed as _{X 179 = Y π (179)} = Y 176. Accordingly, the group interleaver 122 sets the 0th group to the ninth, the first group to the sixth, the second to the 160th, and so on. , The 178th group to the 177th group, and the 179th group to the 176th order, so that the order of the plurality of groups can be rearranged in groups.

For Table 51, Equation (12) is _{X 0 = Y π (0)} = Y 23, X 1 = Y π (1) = Y 132, X 2 = Y π (2) = Y 20, ... _{, X 178 = Y π (178} ) = Y 178, can be expressed as _{X 179 = Y π (179)} = Y 179. Accordingly, the group interleaver 122 sets the 0th group to the 23rd, the 1 st group to the 132nd, the 2 nd group to the 20th, and so on. , The 178th group is changed to the 178th group, and the 179th group is changed to the 179th group, so that the order of the plurality of groups can be rearranged in groups.

As another example, when the LDPC codeword length _Nldpc is 64,800 and the coding rate is 6/15 and the modulation scheme is 256-QAM,? (J) can be defined as shown in Table 52 below.

For Table 52, Equation (12) is _{X 0 = Y π (0)} = Y 9, X 1 = Y π (1) = Y 13, X 2 = Y π (2) = Y 130, ... _{, X 178 = Y π (178} ) = Y 47, can be expressed as _{X 179 = Y π (179)} = Y 90. Accordingly, the group interleaver 122 sets the 0th group to the 9th, the 1st group to the 13th, the 2nd group to the 130th, and so on. , The 178th group to the 47th group, and the 179th group to the 90th, so that the order of the plurality of groups can be rearranged in groups.

As another example, if the length _Nldpc of the LDPC codeword is 64800, the coding rate is 8/15, and the modulation scheme is 256-QAM,? (J) can be defined as shown in Table 53 below.

For Table 53, Equation (12) is _{X 0 = Y π (0)} = Y 171, X 1 = Y π (1) = Y 43, X 2 = Y π (2) = Y 85, ... _{, X 178 = Y π (178} ) = Y 109, can be expressed as _{X 179 = Y π (179)} = Y 106. Accordingly, the group interleaver 122 sets the 0th group to 171st, the 1 st group to 43rd, the 2 nd group to 85th, and so on. , The 178th group is changed to the 109th group, and the 179th group is changed to the 106th, so that the order of the plurality of groups can be rearranged in groups.

As another example, if the length _Nldpc of the LDPC codeword is 64800 and the coding rate is 10/15 and the modulation scheme is 256-QAM,? (J) can be defined as shown in Table 54 below.

For Table 54, Equation (12) is _{X 0 = Y π (0)} = Y 71, X 1 = Y π (1) = Y 112, X 2 = Y π (2) = Y 72, ... _{, X 178 = Y π (178} ) = Y 129, can be expressed as _{X 179 = Y π (179)} = Y 151. Accordingly, the group interleaver 122 sets the 0th group to 71st, the 1 st group to 112st, the 2 nd group to 72nd, and so on. , The 178th group is changed to the 129th group, and the 179th group is changed to the 151st order, so that the order of the plurality of groups can be rearranged in groups.

As another example, if the length _Nldpc of the LDPC codeword is 64800 and the coding rate is 10/15 and the modulation scheme is 256-QAM,? (J) can be defined as shown in Table 55 below.

For Table 55, Equation (12) is _{X 0 = Y π (0)} = Y 130, X 1 = Y π (1) = Y 33, X 2 = Y π (2) = Y 69, ... _{, X 178 = Y π (178} ) = Y 134, can be expressed as _{X 179 = Y π (179)} = Y 124. Accordingly, the group interleaver 122 sets the 0 th group to 130 th, the 1 st group to 33 th, the 2 nd group to 69 th, and so on. , The 178th group is changed to the 134th group, and the 179th group is changed to the 124th group, so that the order of the plurality of groups can be rearranged in groups.

As another example, when the LDPC codeword length _Nldpc is 64,800 and the coding rate is 12/15 and the modulation scheme is 256-QAM,? (J) can be defined as shown in Table 56 below.

For Table 56, Equation (12) is _{X 0 = Y π (0)} = Y 29, X 1 = Y π (1) = Y 176, X 2 = Y π (2) = Y 28, ... _{, X 178 = Y π (178} ) = Y 163, can be expressed as _{X 179 = Y π (179)} = Y 166. Accordingly, the group interleaver 122 sets the 0th group to the 29th, the 1st group to the 176th, the 2nd group to the 28th, and so on. , The 178th group is changed to the 163rd group, and the 179th group is changed to the 166th order, so that the order of the plurality of groups can be rearranged in groups.

In this manner, the group interleaver 122 can rearrange the order of the plurality of groups in units of a group using Equation (12) and Table 42 to Table 56 above.

On the other hand, the groups constituting the LDPC codeword are rearranged in group units by the group interleaver 122 and are then block interleaved by a block interleaver 124, which will be described later. In Table 42 to Table 56, ) With respect to " Order of bits group to be block interleaved ".

According to this scheme, the group interleaved LDPC codeword is shown in FIG. Comparing the LDPC codeword shown in FIG. 6 with the LDPC codeword before the group interleaving shown in FIG. 5, it can be seen that the order of a plurality of groups constituting the LDPC codeword is rearranged.

That is, as shown in FIGS. 5 and 6, the LDPC codeword is divided into groups X ₀ , X ₁ ,... , Group X _{Ngroup 1} , and group interleaved to group Y ₀ , group Y ₁ , ... , And group Y _{Ngroup- 1} . In this case, the order in which the groups are arranged by group interleaving can be determined based on Tables 27 to 56. [

The group twisted interleaver 123 interleaves the bits in the same group. That is, the group twist interleaver 123 may rearrange the order of the bits in the same group by changing the order of the bits existing in the same group.

In this case, the group twisted interleaver 123 may cyclically shift the bits in the same group by a predetermined number of bits to rearrange the order of the bits in the same group.

For example, as shown in FIG. 7, the group twist interleaver 123 may cyclically shift the bits included in the group Y ₁ by one bit in the right direction. In this case, as shown in FIG. 7, in the group Y ₁ , 0 th, 1 st, 2 nd, , 358 th, 359 positioned who bit in the second are 1 is clicking shift when the right by bit, cyclic shift of 359 th position 0 before the bit is a group Y ₁ is located at the front side is shifted cyclic in was prior to First, first, second, ... , And the bits located at the 358th position are sequentially shifted by one bit to the right.

In addition, the group twist interleaver 123 may rearrange the order of the bits in each group by cyclically shifting a different number of bits for each group.

For example, the group twist interleaver 123 may cyclically shift the bits included in the group Y ₁ by one bit in the right direction and cyclically shift the bits included in the group Y ₂ by three bits in the right direction .

Thus, a change in the order of bits in the same group is called a group twist. The group twist can be performed to prevent the bits mapped to one modulation symbol from being connected to one check node. Therefore, the group twist interleaver 123 may be omitted in some cases.

Further, in the above-described example, the group twist interleaver 123 is described as being disposed after the group interleaver 122, but this is also only an example. That is, the group twist interleaver 123 may be arranged before the group interleaver 122 in that it changes the order of the bits constituting the group in the group but does not change the order of the groups themselves.

The block interleaver 124 interleaves a plurality of ordered reordering groups. Specifically, the block interleaver 124 may interleave a plurality of groups in which the order of the groups is rearranged by the group interleaver 122, on a group basis.

That is, the interleaving performed in the group twisted interleaver 123 changes the order of the bits in the group, and does not change the order of the groups themselves by interleaving. Accordingly, the order of the groups to be block interleaved in the block interleaver 124 can be determined by the group interleaver 122. [ Specifically, the order of the groups to be block interleaved by the block interleaver 124 can be determined by? (J) defined in Tables 27 to 56. [

In this case, the block interleaver 124 may interleave a plurality of groups, which are reordered in order, using at least one column composed of a plurality of rows, on a group basis.

Specifically, the block interleaver 124 writes a plurality of groups in column direction in each column in a group unit, and interleaving is performed by reading each row of a plurality of columns in which a plurality of groups are written in a group unit in the row direction have.

Hereinafter, for convenience of explanation, the group located at the j-th position after being interleaved by the group interleaver 122 is referred to as a group Y _j .

If the number of groups constituting the LDPC codeword is an integer multiple of the number of columns, the block interleaver 124 can perform interleaving by writing groups of values obtained by dividing the number of groups divided by the number of columns into groups in a sequential manner in each column have.

For example, a block interleaver 124 as shown in FIG. 8 is a group from the first row R _1-th row of the first column (Y _0), the group (Y _1), ..., a group (Y _{p -1)} included in the respective light from the bits included in each, the first row of the second column in the first row R ₁ group (Y _p), the group (Y _{p +1),} ..., a group (Y _{q -1)} Light of the bits, ..., the C 1 to the second row of the column R ₁ groups to the second row (Y _z), the group (Y _{z +1),} ..., to each group (Y _{Ngroup -1)} Write the included bits. Then, the block interleaver 124 can read each row of the plurality of columns in the row direction. Here, each column may include a row from 1 to R ₁ . That is, each column may be composed of R ₁ rows.

However, if the number of groups constituting the LDPC codeword is not an integral multiple of the number of columns, the block interleaver 124 divides each column into N parts (where N is an integer of 2 or more) and performs interleaving can do.

Specifically, the block interleaver 124 divides each column into a part including a row including a number of bits as many as the number of bits included in a group writable in each column in each column and a part including the remaining rows, So that interleaving can be performed. Here, a part including a row as many as the number of bits included in a group writable in a group unit may be composed of a row of an integer multiple of M.

In this case, the block interleaver 124 sequentially writes at least a part of the plurality of groups, each of which can be written in the plurality of columns, into each of the plurality of columns, and then at least some of the groups in the plurality of columns are group And the remaining group can be divided and written in the remaining area. That is, the block interleaver 124 writes the bits included in at least some writeable groups into the first part (i.e., part 1) of each column in a group unit, divides the bits included in the remaining groups, Can be written to the part (i. E., Part 2).

For example, it is assumed that the block interleaver 124 divides each column into a first part including R ₁ rows and a second part including R ₂ rows as shown in FIGS. 9 and 10. Here, R ₁ may be the number of bits included in a group writable in each column in each column, and R ₂ may be a value excluding R ₁ from the number of rows constituting each column.

In this case, the block interleaver 124 writes the bits included in the group writable into each column in the column into the first part of each column in the column direction.

That is, as shown in FIGS. 9 and 10, the block interleaver 124 divides the group (Y ₀ ), the group (Y ₁ ), ..., and the group (Y ₁ ) into rows from the first row to the R ₁ row constituting the first part of the first column, group (Y _{n -1)} and light the bits included in each of the first group from the row R ₁ row constituting a first part of the second column (Y _n), the group (Y _{n +1)} ,. ., a group (Y _{m -1)} and light the bits included in respective, ..., the first group from the row R ₁ row constituting a first part of the column C (Y _e), group ( Y _{e +1} ), ..., and a group (Y _{Ngroup- 2} ).

In this way, the block interleaver 124 writes the bits included in the group writable in each column in each column into the first part of each column in a group unit.

Thereafter, the block interleaver 124 may divide the bits included in the remaining groups except for the group written in the first part of each column among the plurality of groups, and write the bits into the second part of each column in the column direction. At this time, the block interleaver 124 divides the bits included in the remaining groups except for the group written in the first part of each column into the number of columns so that the same number of bits are written in the second part of each column, Can be written in the column direction in each column of the second part.

For example, as shown in FIG. 9, when the group (Y _Ngroup-1 ) which is the last group of the LDPC codeword remains, the block interleaver 124 divides the bits included in the group (Y _{Ngroup- 1} ) Each divided bit can be sequentially written to the second part of each column.

That is, a block interleaver 124 from the first line to write a bit from the first line constituting the second part of the first column to the R _2-th row, and constituting a second part of the second column R ₂ row , And write the bits from the first row to the R ₂ -th row constituting the second part of the column C of the second column. At this time, the block interleaver 124 can write the bits in the column direction to the second part of each column as shown in FIG.

In the above example, the block interleaver 124 writes bits in the column direction in the second part, but this is merely an example. That is, the block interleaver 124 may write bits in a plurality of columns of the second part in the row direction. In this case, the block interleaver 124 can write the bits for the first part in the same manner as described above.

10, the block interleaver 124 writes bits in the first column from the first row to the first column constituting the second part in the first column to the first column constituting the second part in the first column, Writes bits from the second row to the second column constituting the second part from the column C to the second part constituting the second part, , It is possible to write the bits from the first row R ₂ constituting the second part from the first column to the second row R ₂ constituting a second part in the C column.

On the other hand, the block interleaver 124 sequentially reads the bits written in each row of each part in the row direction. 9 and 10, the block interleaver 124 sequentially reads the bits written in the respective rows of the first part of the plurality of columns in the row direction and sequentially writes the bits written to each row of the second part of the plurality of columns Can be sequentially read out in the row direction.

As described above, the block interleaver 124 can interleave a plurality of groups using the method described with reference to FIG. 8 to FIG.

In particular, in the case of FIG. 9, the bits included in the group not belonging to the first part are written in the column direction in the second part and read in the row direction, . In this manner, the bit error rate (FER) / frame error rate (FER) performance can be improved as compared with the case where interleaving is not performed because the bits included in the group not belonging to the first part are interleaved.

However, a group not belonging to the first part as shown in FIG. 10 may not be interleaved. In other words, as shown in FIG. 10, the block interleaver 124 writes and reads the bits included in the group not belonging to the first part in the row direction to the second part, so that the bits included in the group not belonging to the first part The order can be output to the modulation unit 130 sequentially without changing the order. In this case, the bits included in the group not belonging to the first part may be sequentially output and mapped to the modulation symbol.

9 and 10, the last one of the plurality of groups is written to the second part. However, this is only an example, and the number of groups written in the second part is the same as that of the group constituting the LDPC codeword The number of columns, the number of rows, and the like.

On the other hand, the block interleaver 124 may have a different structure depending on whether the bits included in the same group are mapped to one bit in the modulation symbol or the bits included in the same group are mapped to two bits in the modulation symbol .

First, when the bits included in the same group are mapped to one bit in the modulation symbol, the block interleaver 124 may have a structure as shown in Tables 57 and 58 below.

Here, C (or N _c ) is the number of columns constituting the block interleaver 124, R ₁ is the number of rows constituting the first part in each column, R ₂ is the number of rows constituting the second part in each column The number of rows to be processed.

Table 57 and referring to Table 58, constituting the case where the number of groups constituting the LDPC codeword times the integer number of rows block interleaver 124 R ₁ in that it performs the interleaving does not separate each column, each column The number of rows to be processed is R ₂ = 0. On the contrary, if the number of the group constituting the LDPC codeword that is not an integral multiple of the number of columns, the block interleaver 124, the second part consisting of a first part and R ₂ rows which make up each column to the R1 rows, And interleaving is performed.

On the other hand, when the number of columns of the block interleaver 124 is equal to the number of bits constituting the modulation symbol, as shown in Tables 57 and 58, the bits included in the same group can be mapped to one bit in the modulation symbol.

For example, when N _ldpc = 64800 and the modulation scheme is 16-QAM, the block interleaver 124 may be composed of four columns each including 16,200 rows. In this case, a plurality of groups are written into four columns in a group unit, and the bits written to the same row in each column are sequentially output. In this case, when the modulation scheme is 16-QAM, the bits included in the same group, that is, the bits output from one column, can be mapped to one bit in the modulation symbol in that 4 bits constitute one modulation symbol have. For example, the bits contained in the group written to the first column may be mapped to the first bit of each modulation symbol.

On the other hand, when the bits included in the same group are mapped to two bits in the modulation symbol, the block interleaver 124 may have a structure as shown in Tables 59 and 60 below.

Here, C (or N _c ) is the number of columns constituting the block interleaver 124, R ₁ is the number of rows constituting the first part in each column, R ₂ is the number of rows constituting the second part in each column The number of rows to be processed.

Table 59 and referring to Table 60, constituting the case where the number of groups constituting the LDPC codeword times the integer number of rows block interleaver 124 R ₁ in that it performs the interleaving does not separate each column, each column The number of rows to be processed is R ₂ = 0. On the contrary, if the number of the group constituting the LDPC codeword that is not an integral multiple of the number of columns, the block interleaver 124, the second part consisting of a first part and R ₂ rows which make up each column to the R1 rows, And interleaving is performed.

As shown in Tables 59 and 60, when the number of columns of the block interleaver 124 is half the number of bits constituting the modulation symbol, the bits included in the same group can be mapped to two bits in the modulation symbol.

For example, when N _ldpc = 64800 and the modulation scheme is 16-QAM, the block interleaver 124 may be composed of two columns each including 32400 rows. In this case, a plurality of groups are written into two columns in a group unit, and the bits written to the same row in each column are sequentially output. On the other hand, in the case where the modulation scheme is 16-QAM, bits output from two rows constitute one modulation symbol because 4 bits constitute one modulation symbol. Therefore, the bits included in the same group, i.e., the bits output from one column, can be mapped to two bits in the modulation symbol. For example, the bits contained in the group written to the first column may be mapped to bits present in any two positions in the modulation symbol.

Referring to Tables 57 to 60, it can be seen that the number of all the rows of the block interleaver 124, that is, R ₁ + R ₂ is N _ldpc / C.

이고, 제2 파트의 행의 개수인 R₂는 N_ldpc/C-R₁이 될 수 있다. 여기에서,

는 N_ldpc/C 이하의 가장 큰 정수를 나타낸다. 이와 같이, R1은 각 그룹에 포함된 비트의 개수인 M의 정수 배가 된다는 점에서 R1에는 그룹 단위의 비트들이 라이트될 수 있다. R ₁ , the number of rows of the first part, is an integer multiple of M (for example, M = 360), which is the number of bits included in each group

And R ₂ , the number of rows of the second part, can be N _ldpc / CR ₁ . From here,

_Represents the largest integer less than or equal to N _ldpc / C. In this way, R1 can be written into groups of bits in R1 in that R1 is an integral multiple of M, which is the number of bits included in each group.

Referring to Tables 57 to 60, when the number of groups constituting the LDPC codeword is not a multiple of the number of columns, the block interleaver 124 recognizes that each column is divided into two parts and performs interleaving .

Specifically, the value obtained by dividing the length of the LDPC codeword by the number of columns is the total number of rows included in each column. At this time, when the number of groups constituting the LDPC codeword is a multiple of the number of columns, each column is not divided into two parts. However, if the number of groups constituting the LDPC codeword is not a multiple of the number of columns, each column can be divided into two parts.

For example, as shown in Table 57, it is assumed that the number of columns of the block interleaver 124 is equal to the number of bits constituting the modulation symbol, and the LDPC codeword is composed of 64800 bits. At this time, the LDPC codeword is composed of 64 groups of 64800/360 = 180.

When the modulation method is 16-QAM, each column may be composed of 64800/4 = 16200 rows. At this time, if the number of groups constituting the LDPC codeword is divided by the number of columns, 180/4 = 45, so that the bits can be written into each column in each column without dividing each column into two parts. That is, in each column, bits included in 45 groups, that is, 45 x 360 = 16200 bits, can be written.

However, when the modulation method is 256-QAM, each column may be composed of 64800/8 = 8100 rows. At this time, the value obtained by dividing the number of groups constituting the LDPC codeword by the number of columns is 180/8 = 22.5, so each column can be divided into two parts.

At this time, since the bits must be written in groups in the first part of each column, the first part of each column is composed of 22 x 360 = 7920 rows, so that 7920 bits included in 22 groups can be written. On the other hand, the second part of each column is composed of a row excluding all the rows constituting the first part in the entire row of each column. Thus, the second part of each column contains 8100-7920 = 180 rows, and 180 bits can be written. In this case, the bits included in the remaining groups that have not been written to the first part in the second part of each column can be divided and written.

As another example, it is assumed that the number of columns of the block interleaver 124 is half of the number of bits constituting the modulation symbol and the LDPC codeword is composed of 16200 bits as shown in Table 60. [ At this time, the LDPC codeword is composed of 16200/360 = 45 groups.

When the modulation method is 64-QAM, each column may be composed of 16200/3 = 5400 rows. At this time, if the number of groups constituting the LDPC codeword is divided by the number of columns, 45/3 = 15, so that the bits can be written to each column in each column without dividing each column into two parts. That is, bits included in 15 groups, that is, 15 x 360 = 5400 bits, can be written in each column.

However, if the modulation scheme is 256-QAM, each column may be composed of 16200/4 = 4050 rows. At this time, the value obtained by dividing the number of groups constituting the LDPC codeword by the number of columns is 45/4 = 11.25, so that each column can be divided into two parts.

In this case, since the bits must be written in groups in the first part of each column, the first part of each column is composed of 11 × 360 = 3960 rows, and 3960 bits included in 11 groups can be written. On the other hand, the second part of each column is composed of a row excluding all the rows constituting the first part in the entire row of each column. Thus, the second part of each column contains 4050-3960 = 90 rows, and 90 bits can be written. In this case, the bits included in the remaining groups that have not been written to the first part in the second part of each column can be divided and written.

Hereinafter, a concrete example of the block interleaver of FIG. 4 will be described in more detail with reference to FIG.

)는 V={Y₀,Y₁,…,

}과 같이 Y_j가 연속적으로 배치될 수 있다. The group interleaved LDPC codeword (v ₀ , v ₁ , ...,

) Is expressed as V = {Y ₀ , Y ₁ , ... ,

Y _j} is such as may be placed consecutively.

After group interleaving, the LDPC codeword can be interleaved by the block interleaver 124 as shown in FIG. Specifically, the input bits v _i are serially written in column wise starting from the first part to the second part, and are sequentially written in row wise from the first part to the second part Lead.

In this case, the number of columns and the number of rows of the first and second parts of the block interleaver 124 according to the modulation scheme may be as shown in Table 61 below.

Here, the sum of N _r1 , which is the number of rows of the first part, and N _r2 , which is the number of rows of the second part, is equal to N _ldpc / N _c (where N _c is the number of columns). Since N _r1 is a multiple of 360, a plurality of bit groups can be written in the first part.

Hereinafter, the operation of the block interleaver 124 will be described in more detail.

, r_i=(i mod N_r1)와 같다.Specifically, as shown in FIG. 11, the input bit v _i (0? I <N _c × N _r1 ) is written to the r _i row of the c _i column of the first part of the block interleaver 124. Here, c _i and r _i are

, and r _i = (i mod N _r1 ).

, r_i=N_r1+{(i-N_c×N_r1) mod N_r2}와 같다.Then, the input bits, _{v i (N c × N r1} ≤i <N ldpc) are written into the second part of the column c _i r _i rows of the block interleaver (124). Here, c _i and r _i are

, r _i = N _r1 + {(iN _c × N _r1 ) mod N _r2 }.

, c_j=(j mod N_c)와 같다.On the other hand, the output bit q _j (0≤j <N _ldpc) are read out from the column c _j r _j of the line. Here, c _j and r _j are

, c _j = (j mod N _c ).

For example, when the length N _LDPC of the LDPC codeword is 64800 and the modulation scheme is 256-QAM, the order of bits output from the block interleaver 124 is (q ₀ , q ₁ , q ₂ , q ₆₃₃₅₇ , q ₆₃₃₅₈ , q ₆₃₃₅₉ , q ₆₃₃₆₀ , q ₆₃₃₆₁ , ..., q ₆₄₇₉₉ ) = (v ₀ , v ₇₉₂₀ , v ₁₅₈₄₀ , ..., v ₄₇₅₁₉ , v ₅₅₄₃₉ , v ₆₃₃₅₉ , v ₆₃₃₆₀ , v ₆₃₅₄₀ , ..., v ₆₄₇₉₉ ). Here, if the index in the right-hand term is described in more detail for all eight columns, 0, 7920, 15840, 23760, 31680, 39600, 47520, 55440, 1, 7921, 15841, 23761, 31681, 39601, 47521, 55441, ... , 7919, 15839, 23759, 31679, 39599, 47519, 55439, 63359, 63360, 63540, 63720, 63900, 64080, 64260, 64440, 64620, ... ... , 63539, 63719, 63899, 64079, 64259, 64439, 64619, 64799.

Returning to FIG. 1, the modulator 130 maps the interleaved LDPC codeword to a modulation symbol. Specifically, the modulator 130 demultiplexes the interleaved LDPC codeword, modulates the demultiplexed LDPC codeword, and maps the constellation.

First, the modulator 130 can demultiplex the interleaved LDPC codeword. For this, the modulator 130 may include a demultiplexer (not shown) for demultiplexing the interleaved LDPC codeword.

A demultiplexer (not shown) demultiplexes the interleaved LDPC codeword. Specifically, a demultiplexer (not shown) performs a serial-to-parallel conversion on an interleaved LDPC codeword to convert an interleaved LDPC codeword into a cell having a predetermined number of bits Or a data cell).

12, a demultiplexer (not shown) receives the LDPC codeword Q = (q ₀ , q ₁ , q ₂ , ...) output from the interleaver 120 and receives The LDPC codeword bits may be sequentially output to one of the plurality of sub-streams, and the input LDPC codeword bits may be converted into cells and output.

Here, the number of _substreams N _substreams is equal to the number of bits η _MOD constituting the modulation symbol, and the number of bits constituting the cell may be equal to N _ldpc / η _MOD . Meanwhile, the number of cells generated according to the length of the η _MOD and the length of the LDPC codeword N _ldpc according to the modulation scheme may be as shown in Table 62 below.

On the other hand, bits having the same index in each of a plurality of sub-streams can constitute the same cell. That is, in each cell 12 _{(y 0, 0, y 1} , 0, ..., y η MOD -1,0), (y 0,1, y 1,1, ..., y η MOD _-1 , 1, ..., and so on.

Meanwhile, a method of demultiplexing the LDPC codeword bits input to the demultiplexer (not shown) may be various. That is, the demultiplexer (not shown) may change the order of the LDPC codeword bits and output the LDPC codeword bits to each of the plurality of sub-streams, or sequentially output the LDPC codeword bits to the plurality of streams without changing the order of the LDPC codeword bits. This operation can be determined according to the number of columns used for interleaving in the block interleaver 124. [

Specifically, when the block interleaver 124 includes a column of half the number of bits constituting the modulation symbol, the demultiplexer (not shown) changes the order of the input LDPC codeword bits so that the sub- And an example of how to change the order is shown in Table 63 below.

For example, in the case of the 16-QAM modulation scheme in Table 63, in the case of 16-QAM, the number of bits constituting the modulation symbol is four, so that the number of sub-streams is four. In this case, a demultiplexer (not shown) outputs bits sequentially satisfying i mod 4 = 0 to the 0th sub-stream among the sequentially input bits, and outputs bits satisfying i mod 4 = 1 The bits satisfying i mod 4 = 2 are outputted as the first sub stream, and the bits satisfying the index i i mod 4 = 3 are output as the third sub stream. have.

Accordingly, the LDPC codeword bits q ₀ , q ₁ , q ₂ , ... input to the demultiplexer (not shown) are (y _{0 , 0} , y _{1 , 0} , y _{2 , 0} , y _{3 , 0) = (q 0, q} 2, q 1, q 3), (y 0,1, y 1,1, y 2,1, y 3,1) = (q 4, q 6, q 5, q ₇ ), ... &lt; / RTI &gt;

If the block interleaver 124 includes the same number of bits as the number of bits constituting the modulation symbol, the demultiplexer (not shown) may sequentially change the order of the input LDPC codeword bits . That is, as illustrated in Figure 13, and sequentially output to a demultiplexer (not shown) is input LDPC codeword bits (q _0, q _1, q _2, ...), each sub-stream, and thus, each cell _{(y 0,0, y 1,0, ...} , y η MOD -1,0) = (q 0, q 1, ..., q η MOD -1), (y 0, 1, y 1, ₁ , ..., y _{η MOD -1,1} ) = (q _{η MOD} , q _{η MOD +1} , ..., q _{2 × ηMOD-1} ) _,.

In the above example, the demultiplexer (not shown) sequentially outputs the LDPC codeword bits to the plurality of streams without changing the order of the input LDPC codeword bits, but this is merely an example. That is, according to an embodiment of the present invention, when the block interleaver 124 includes the same number of columns as the number of bits constituting the modulation symbol, the demultiplexer (not shown) may be omitted.

Meanwhile, the modulator 130 may map the demultiplexed LDPC codeword to the modulation symbol. However, if the demultiplexer (not shown) is omitted as described above, the modulator 130 may map the LDPC codeword bits output from the interleaver 120, i.e., the block interleaved LDPC codeword bits to the modulation symbol have.

Specifically, the modulator 130 modulates bits (i.e., cells) output from the demultiplexer (not shown) into various modulations such as QPSK, 16-QAM, 64-QAM, 256-QAM, 1024- Modulation scheme can be used. Here, when the modulation method is QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM and 4096-QAM, the number of bits η _MOD (ie, modulation order) , 4, 6, 8, 10, and 12, respectively.

In this case, since each cell output from the demultiplexer (not shown) is composed of as many bits as the number of bits constituting the modulation symbol, the modulator 130 sequentially outputs each cell output from the demultiplexer (not shown) To generate a modulation symbol. Here, the modulation symbol corresponds to a constellation point in the constellation.

However, if the demultiplexer (not shown) is omitted, the modulator 130 may sequentially generate a modulation symbol by dividing the interleaved bits by a predetermined number of bits and mapping the interleaved bits to the property points. In this case, the modulator 130 can generate modulation symbols by sequentially using the bits of eta _MOD in accordance with the modulation scheme.

Meanwhile, the modulator 130 may perform modulation by mapping the cells output from the demultiplexer (not shown) to sexual points using a uniform constellation (UC) scheme.

Here, the uniform constellation scheme refers to a scheme of mapping a modulation symbol to a store point so that the real component Re (z _q ) and imaginary component Im (z _q ) of the store point are symmetrical and the modulation symbol is formed at equal intervals. Accordingly, at least two of the modulation symbols mapped to the constellation in the uniform constellation scheme can have the same demodulation performance.

Meanwhile, an example of a method of generating a modulation symbol in a uniform constellation scheme according to an embodiment of the present invention can be shown in the following Tables 64 to 71, and an example of a case of a uniform constellation 64-QAM is shown in FIG. 14 Respectively.

Herein, Tables 64 and 65 are used to determine the real component Re (z _q ) and the imaginary component Im (z _q ) in the case of performing modulation in the QPSK scheme, and Tables 66 and 67 are respectively used to determine the 16- (Z _q ) and imaginary component Im (z _q ) in the case of performing modulation in the QAM system, and Table 68 and Table 69 are used to determine the real component (Z _q ) and the imaginary component Im (z _q ) in the case of performing modulation in the 256-QAM method, and Table 70 and Table 71 show the real component Re (z _q ) and the imaginary component Im _q ).

Referring to Tables 64 to 71, performance (e.g., reliability) varies depending on whether a plurality of bits constituting a modulation symbol correspond to a most significant byte (MSB) and a least significant bit (LSB) Able to know.

For example, in the case of 16-QAM, the first bit and the second bit of the four bits constituting the modulation symbol are the real number component Re (z _q ) and the imaginary number Im (z _q ) are the bits for determining each symbol, and the third and fourth bits are the bits for determining the size of the constellation point to which the modulation symbol is mapped.

In this case, it can be seen that the reliability is higher than the third bit, which is the bits for determining the sign, and the fourth bit, which determine the size, among the four bits constituting the modulation symbol.

As another example, in the case of 64-QAM, the first bit and the second bit of the six bits constituting the modulation symbol are the real number component Re (zq) and imaginary number component Im (zq) of the property point to which the modulation symbol is mapped, respectively Lt; / RTI &gt; The third to sixth bits are bits for determining the size of a property to which a modulation symbol is mapped. Of these, the third bit and the fourth bit determine a relatively large size, and the fifth bit and the sixth bit (E.g., -7, -5) or (-3, -1) to which the modulation symbol is mapped by the third bit is determined, If the third bit determines (-7, -5), the fourth bit determines whether -7 or -5.

In this case, among the six bits constituting the modulation symbol, the first bit, which is a code determining bit, and the third bit and the fourth bit, which are the second most reliable bits and determine a relatively large size, are relatively It can be seen that the reliability is higher than the fifth bit and the sixth bit, which determine the small size.

As described above, in the case of the uniform constellation scheme, the bits constituting the modulation symbol may have different reliability depending on the position mapped in the modulation symbol.

Meanwhile, the modulator 130 may perform modulation by mapping the cells output from the demultiplexer (not shown) to sex points using a non-uniform constellation (NUC) scheme.

Specifically, the modulator 130 demultiplexes the bits output from the demultiplexer (not shown) into non-uniform 16-QAM, non-uniform 64-QAM, non-uniform 256-QAM, non-uniform 1024- 4096-QAM, and the like.

Hereinafter, a method of generating a modulation symbol using a non-uniform constellation scheme according to an embodiment of the present invention will be described.

First, the characteristics of the non-uniform constellation method will be described as follows.

Unlike the uniform constellation scheme, in the non-uniform constellation scheme, the stores may not be regularly arranged. Accordingly, when the non-uniform constellation scheme is used, the SNR of a specific value or less can be improved and a high SNR gain can be obtained as compared with the uniform constellation scheme.

On the other hand, the constellation can be determined by one or more parameters such as the spacing between storages, and the like. In the uniform constellation method, the number of parameters required to specify uniform constellation method can be 1, in that the distribution points are regularly distributed. On the other hand, in the case of the nonuniform constellation method, the number of parameters required to specify the nonuniform constellation method And the number of parameters can be increased as the constellation (for example, the number of stores) increases.

On the other hand, in the case of non-uniform constellatoin, the x-axis and y-axis can be designed symmetrically or non-symmetrically. Designing without symmetric can provide better performance, but may increase decoding complexity.

Hereinafter, an example of the case where the design is not simulated is suggested. In this case, if only the sex shop in the first quadrant is defined, the location of the sex shop in the other three quadrants can be determined by the following method. For example, if the set of stores defined for the first quadrant is X, then -conj (X) for the second quadrant, conj (X) for the third quadrant, and - (X) for the fourth quadrant .

In other words, if you define the first quadrant, the other quadrants can be expressed as:

1 Quarter (= 1 quadrant) = X

2 Quarter = -conj (X)

3 Quarter = conj (X)

4 Quarter = -X

Specifically, when non-uniform M-QAM is used, _{M storages} can be defined as z = {z ₀ , z ₁ , ..., z _{M -1} }. In this case, the sex shop in the first quadrant is {x ₀ , x ₁ , x ₂ , ... , x _{M / 4-1} }, z can be defined as follows.

z ₀ to z _{M / 4-1} = x ₀ to x _{M / 4}

z _{M / 4} to z _{2 x M / 4-1} = -conj (x ₀ to x _{M / 4} )

z _{2 x M / 4} to z _{3 x M / 4-1} = conj (x ₀ to x _{M / 4} )

z _{3 x M / 4} to z _{4 x M / 4-1} = - (x ₀ to x _{M / 4} )

을 인덱스로 하는 z_L로 매핑하여, 출력 비트들을 non-uniform constellation 방식으로 성성점에 맵핑할 수 있다. 이러한 방식에 따라 non-uniform constellation 방식에 따른 성상도의 일 예는 도 15 내지 도 19와 같다.Therefore, the modulating unit 130 outputs the output bits [y ₀ , ..., y ₀ ) output from the demultiplexer , y _{m -1} ]

To an index z _L to map output bits to sexual points in a non-uniform constellation scheme. An example of the constellation according to the non-uniform constellation scheme according to this scheme is shown in FIGS. 15 to 19. FIG.

Meanwhile, an example of a concrete method of performing modulation in a non-uniform constellation scheme without modulating in the modulator 130 is shown in Tables 72 to 77 below. That is, according to an embodiment of the present invention, a sex store existing in the first quadrant is defined through Tables 72 to 77, a sex store existing in the remaining quadrants is defined by the above method, and a non-uniform constellation method Modulation can be performed.

In Tables 72 to 77, Table 72 shows non-uniform 16-QAM, Tables 73 to 75 show non-uniform 64-QAM, Table 76 and Table 77 show non-uniform 256-QAM, It can be seen that different mapping schemes can be applied.

On the other hand, when non-uniform constellation is designed to be symmetric with respect to the x-axis and the y-axis, it can be expressed similarly to the uniform QAM.

In Tables 78 to 81, Tables 78 and 79 are tables for determining the real component Re (z _q ) and the imaginary component Im (z _q ) in the case of performing modulation by the non-uniform 1024-QAM method. That is, Table 78 shows the real part of 1024-QAM, and Table 79 shows the imaginary part of 1024-QAM. Tables 80 and 81 show an example of performing modulation using the non-uniform 1024-QAM method, and show x _i values in Table 78 and Table 79.

In the non-uniform constellation scheme shown in Tables 72 to 77, modulation symbols mapped to the property points may have different demodulation performances in that the modulation symbols can be mapped to the property points without being symmetric. That is, the bits constituting the modulation symbol may have different performances.

For example, non-uniform if 64-QAM, see FIG. 15 showing an example of the case of performing modulation in such a manner, the modulation symbols (10) _{(y 0, y 1, y} 2, y 3, y 4, y ₅₎ may be of a = (0,0,1,0,1,0), the modulation performance of the bits configuring the symbol 10 (e.g., capacity) is _{C (y 0)> C (} y 1 )> C (y ₂ )> C (y ₃ )> C (y ₄ )> C (y ₅ )

On the other hand, the constellation in the uniform constellation scheme and the non-uniform constellation scheme can be rotated and / or scaled (where the scaling factors applied to the real and imaginary axes can be the same or different from each other) It is self-evident that it can be applied. In addition, the constellation shown represents the relative position of the constellation point, which may be derived by rotation, scaling and / or other suitable transformations.

In this manner, the modulator 130 can map the modulation symbols to the ST points using a uniform constellation scheme and a non-uniform constellation scheme. In this case, the performance of the bits constituting the modulation symbol may be different from each other as described above.

Meanwhile, the LDPC codeword bits may have different codeword characteristics according to the structure of the parity check matrix. That is, the LDPC codeword bits may have different codeword characteristics according to the number of 1s in the column of the parity check matrix, that is, the column order.

Accordingly, in the present invention, the interleaver 120 performs interleaving so that LDPC codeword bits can be mapped to modulation symbols considering both the codeword characteristics of the LDPC codeword bits and the reliability of the bits constituting the modulation symbol.

In particular, when non-uniform QAM is used, since the bits constituting the modulation symbol are different from each other, the number of columns of the block interleaver 124 is made equal to the number of bits constituting the modulation symbol, So that one of the plurality of groups can be mapped to a bit existing at the same position in each modulation symbol.

That is, when mapping the LDPC codeword bits having excellent decoding performance to the bits having high reliability among the bits constituting the modulation symbol, the decoding performance may be improved at the receiving side, but the LDPC codeword bits A problem that can not be solved can occur. When the LDPC codeword bits having excellent decoding performance are mapped to the bits having poor reliability among the bits constituting the modulation symbol, the initial reception performance is excellent and the overall performance may be excellent. However, Error propagation may occur.

Therefore, when mapping LDPC codeword bits to modulation symbols, LDPC codeword bits having specific codeword characteristics are considered in consideration of both the codeword characteristics of the LDPC codeword bits and the reliability of the bits constituting the modulation symbol. Mapped to a specific bit in the modulation symbol and transmitted to the receiving side. Thus, it is possible to achieve both excellent reception performance and decoding performance on the receiving side.

In this case, in the present invention, the LDPC codeword is divided into groups each consisting of M (= 360) bits having the same codeword characteristics, and the bits are mapped to the bits at specific positions of the modulation symbols on a group basis. It is possible to effectively map the bits having a specific codeword characteristic to a specific position in the modulation symbol.

That is, the modulator 130 may map at least one bit included in a predetermined group among a plurality of groups constituting the LDPC codeword to predetermined bits in the modulation symbol. Here, each of the plurality of groups may be constituted by 360 bits.

For example, in case of 16-QAM, at least one bit included in a predetermined group among a plurality of groups may be mapped to the first bit in the modulation symbol, or may be mapped to the first bit and the second bit.

The reason why the modulator 130 maps at least one bit included in a predetermined group among a plurality of groups to a predetermined bit in a modulation symbol is as follows.

As described above, the block interleaver 124 interleaves a plurality of groups constituting the LDPC codeword group by group, a demultiplexer (not shown) demultiplexes the bits output from the block interleaver 124, 130 sequentially map demultiplexed bits (i.e., cells) to modulation symbols.

Therefore, the group interleaver 122 disposed before the block interleaver 124 may be configured such that groups including bits to be mapped to bits in a specific position in the modulation symbol are allocated to the block interleaver 124 (FIG. 1), considering the demultiplexing operation performed in the demultiplexer The LDPC codeword is interleaved on a group basis.

Specifically, the group interleaver 122 rearranges the order of the plurality of groups so that at least one group including the bits mapped to the same positions of the different modulation symbols are arranged in order adjacent to each other, So that the block interleaver 124 writes the predetermined group into the predetermined column. That is, the group interleaver 122 interleaves a plurality of groups constituting the LDPC codeword on a group basis based on the above-mentioned Tables 27 to 56 and outputs at least one Groups are adjacent to each other, and the block interleaver 124 performs interleaving by writing at least one adjacent group to the same column.

Accordingly, the modulator 130 may generate a modulation symbol by mapping the bits output from the predetermined column of the block interleaver 124 to predetermined bits in the modulation symbol. In this case, the bits included in one group may be mapped to one of the bits constituting the modulation symbol or may be mapped to two of the bits constituting the modulation symbol.

For the sake of more detailed explanation, a case of modulating an LDPC codeword having a length of 16200 with a non-uniform 64-QAM will be described as an example.

The group interleaver 122 divides the LDPC codeword into 16200/360 = 45 groups, and performs interleaving of a plurality of groups on a group basis.

In this case, the group interleaver 122 determines the number of groups that can be written in each column of the block interleaver 124 based on the number of columns of the block interleaver 124, and determines a plurality of groups based on the determined number of groups Interleaving can be performed on a group basis.

Here, since the group written in the same column in the block interleaver 124 is mapped to a specific one bit or two specific bits among the bits constituting the modulation symbol according to the number of columns of the block interleaver 124, the group interleaver 122 Takes into account the bit attribute of the modulation symbol, arranges the groups including the bits that need to be mapped to the corresponding bits adjacent to each other, and arranges the plurality of groups so that the array units adjacent to each other are sequentially arranged. Lt; / RTI &gt; In this case, the group interleaver 122 can use Table 27 to Table 56 described above.

Accordingly, the groups adjacent to each other in the interleaved LDPC codeword group can be written in the same column of the block interleaver 124, and the bits written in the same column can be modulated by a modulation unit 130 into a specific one or It is mapped to two bits.

For example, it is assumed that the block interleaver 124 includes as many columns as the number of bits constituting the modulation symbol, i.e., includes six columns. In this case, as shown in Table 58 or Table 61, each column of the block interleaver 124 can be divided into a first part including 2520 rows and a second part including 180 rows.

Accordingly, the group interleaver 122 includes 2520/360 = 7 groups written in the first part of each column of the block interleaver 124 among the plurality of groups and adjacent to each other, Are sequentially arranged. Accordingly, the block interleaver 124 can write the first bits of each column in seven groups, and write the bits included in the remaining three groups into the second part of each column.

Thereafter, the block interleaver 124 may read the bits written in each row of the first part of the plurality of columns in the row direction and read the bits written to each row of the second part of the plurality of columns in the row direction.

That is, the block interleaver 124 writes the bits written in the respective rows of the plurality of columns in the order of the bits written in the first row of the first column to the first row of the sixth column (q ₀ , q ₁ , q ₂ , q ₃ , q ₄ , q ₅ , q ₆ , q ₇ , q ₈ , q ₉ , q ₁₀ , q ₁₁ , ...).

In this case, when the demultiplexer (not shown) is not used or the order of the input bits is not changed in the demultiplexer (not shown), the LDPC codeword bits q ₀ , _{q 1, q 2, q 3} , q 4, q 5), (q 6, q 7, q 8, q 9, q 10, q 11), ... it is modulated by the modulation unit 130. the Q ₆ , q ₇ , q ₈ , q ₉ , q ₁₀ (q ₀ , q ₁ , q ₂ , q ₃ , q ₄ , q ₅ ) output from the block interleaver 124, , q _11), ... are respectively the cells _{(y 0, 0, y 1} , 0, ..., y 5, 0), (y 0, 1, y 1, 1, ..., y 5, 1) ,. And the modulator 130 may generate modulation symbols by mapping the cells to the property points.

Accordingly, the modulator 130 may map the bits output from the same column of the block interleaver 124 to a specific one of the bits constituting the modulation symbol. For example, the modulation unit 130 maps the bits (q ₀ , q ₆ , ...) included in the group written in the first column in the block interleaver 124 to the first bit in the modulation symbol And the bits written in the first column may be the bits determined to be mapped to the first bit of each modulation symbol according to the codeword characteristics of the LDPC codeword bits and the reliability of the bits constituting the modulation symbol.

As described above, the group interleaver 122 divides a plurality of groups constituting the LDPC codeword into groups such that groups including bits to be mapped to one bit at a specific position in the modulation symbol are written in a specific column of the block interleaver 124 Interleaving.

On the other hand, it is assumed that the block interleaver 124 includes the number of bits that constitute the modulation symbol, that is, the number of bits, that is, three columns. In this case, as shown in Table 60, each column of the block interleaver 124 is not divided into parts, and 5400 bits can be written in each column.

Accordingly, in the group interleaver 122, 5400/360 = 15 groups written in each column of the block interleaver 124 among the plurality of groups are adjacent to each other, and the group interleaving is performed so that the array units each composed of 15 groups are sequentially arranged. . Accordingly, the block interleaver 124 can write to each column by 15 groups.

The block interleaver 124 may then read the bits written in each row of the plurality of columns in the row direction.

That is, the block interleaver 124 writes the bits (q ₀ , q ₁ , q (n)) written in each row of the plurality of columns in the order of bits written in the first row of the first column to the first row of the third column ₂ , q ₃ , q ₄ , q ₅ , q ₆ , q ₇ , q ₈ , q ₉ , q ₁₀ , q ₁₁ , ...).

In this case, the demultiplexer (not shown) demultiplexes the LDPC codeword bits output from the block interleaver 124 (y _{0 , 0} , y _{1 , 0} , ..., y _5,0 ) _{= (q 0, q 2,} q 4, q 1, q 3, q 5), (y 0, 1, y 1, 1, ..., y 5, 1) = (q 6, q 8, q 10, q ₇ , q ₉ , q ₁₁ ,..., and the modulator 130 may generate modulation symbols by mapping cells to the property points.

Accordingly, the modulator 130 may map the bits output from the same column of the block interleaver 124 to specific two bits among the bits constituting the modulation symbol. For example, the modulator 130 is the bits contained in the first column that was light group in the block interleaver 124, the _{(q 0, q 3, q} 6, q 9, ...) from (q _0, q ₆ , ...) to the first bit in the modulation symbol and (q ₃ , q ₉ , ...) to the fifth bit in the modulation symbol, and the bits written in the first column are mapped to the LDPC codeword Bits determined to be mapped to the first and fifth bits of each modulation symbol according to the codeword characteristics of the bits and the reliability of the bits constituting the modulation symbol. Here, the first bit in the modulation symbol is a bit that determines the sign of the real component Re (z _q ) of the mobility point to which the modulation symbol is mapped, and the fifth bit in the modulation symbol is the relative position of the mobility point to which the modulation symbol is mapped It is a bit that determines the small size.

As described above, the group interleaver 122 groups a plurality of groups constituting the LDPC codeword so that groups including bits to be mapped to two bits at a specific position in the modulation symbol are written in a specific column of the block interleaver 124, Interleaving.

Hereinafter, the present invention will be described in more detail with reference to specific examples.

First, in the first embodiment of the present invention, the encoder 110 performs LDPC encoding with a coding rate of 10/15, 11/15, 12/15, and 13/15 to generate an LDPC codeword N _ldpc = 16200), and the modulator 130 uses a non-uniform 16-QAM modulation scheme corresponding to the coding rate based on Table 72. [

In this case, the group interleaver 122 may perform group interleaving using Equation (11) and Table 82 below.

Table 82 defines? (J) in Equation (11) and is the same as Table 27 described above.

Meanwhile, the group interleaver 122 may perform group interleaving using Equation (12) and Table 83 below.

Table 83 defines π (j) in Equation 12 and is the same as Table 42 described above.

Here, the result of group interleaving based on Equation (11) and Table (82) and the result of group interleaving based on Equation (12) and Table (83) are the same. This is because equations (11) and (12) are mathematical expressions in an inverse relationship, and tables 82 and 83 are also in an inverse relation. This can be similarly applied to the following embodiments.

In these cases, according to Table 57 or Table 61, the number of columns is 4, the number of rows of the first part is 3960 (= 360x11), and the number of rows of the second part is 180, the block interleaver 124 .

Accordingly, the 11 groups (X ₇ , X ₁₇ , X ₃₃ , X ₃₁ , X ₂₆ , X ₁₀ , X ₃₂ , X ₄₁ , X ₂₈ , X ₈ , and X ₂₄ ) constituting the LDPC codeword are allocated to the block interleaver (X ₄₂ , X ₂₀ , X ₉ , X ₃₅ , X ₄₃ , X ₂₂ , X ₁₂ , X ₃₈ , X ₃ , X ₅ , and X ₁₄ ) two is input to the first part-th column of the block interleaver 124, 11 groups _{(X 37, X 40, X} 19, X 16, X 27, X 39, X 25, X 4, X 21, X 1 , X ₂₃₎ are input to the first part the third column of the block interleaver 124, 11 groups _{(X 18, X 36, X} 0, X 6, X 11, X 34, X 2, X 29, X ₁₅ , X ₃₀ , and X ₁₃ are input to the first part of the fourth column of the block interleaver 124.

Then, the group X ₄₄ is input to the second part of the block interleaver 124. Specifically, the bits constituting the group X ₄₄ are sequentially input into the rows of the first column of the second part, sequentially input to the rows of the second column, sequentially inputted to the rows of the third column, Are sequentially input to the rows of the column.

The block interleaver 124 may successively output the bits input from the first row to the last row of each column and the bits output from the block interleaver 124 may be sequentially input to the modulator 130 . In this case, the demultiplexer (not shown) may be omitted or the demultiplexer (not shown) may sequentially output the input bits without changing the order of the input bits.

Accordingly, one modulation symbol is constituted by one bit included in each of the group X ₇ , the group X ₄₂ , the group X _37, and the group X ₁₈ .

In one embodiment of the present invention, one bit included in each of group X ₇ , group X ₄₂ , group X _37, and group X ₁₈ based on group interleaving and block interleaving includes configuring one modulation symbol , Other methods in which one modulation symbol is composed of one bit included in each of the group X ₇ , the group X ₄₂ , the group X _37, and the group X _{18 in} addition to the above-described method may also be included within the scope of the present invention.

On the other hand, the performance in the case of using the method according to the first embodiment is shown in Fig. Referring to FIG. 20, it can be seen that the non-uniform 16-QAM modulation scheme according to an embodiment of the present invention has excellent BER / FER performance in a specific SNR (Signal to Noise Ratio) region.

A receiving apparatus (not shown) corresponding to the transmitting apparatus 100 performing such an operation includes a demodulator (not shown), an interleaver 120 (i.e., a parity interleaver 121, a group interleaver 122 and block interleaver 124) and a decoding unit (not shown) corresponding to the encoding unit 110.

In the second embodiment of the present invention, the encoding unit 110 performs LDPC encoding with a coding rate of 6/15, 7/15, 8/15, and 9/15 to generate an LDPC codeword (N _ldpc = 16200), and the modulator 130 uses a non-uniform 64-QAM modulation scheme corresponding to the coding rate based on Table 73 or Table 75. [

In this case, the group interleaver 122 may perform group interleaving using Equation (11) and Table 84 below.

Table 84 defines? (J) in Equation (11) and is the same as Table 29 described above.

Meanwhile, the group interleaver 122 may perform group interleaving using Equation (12) and Table 85 below.

Table 85 defines π (j) in Equation (12) and is the same as Table 44 described above.

In these cases, according to Table 58 or Table 61, the number of columns is 6, the number of rows of the first part is 2520 (= 360 x 7), and the number of rows of the second part is 180, have. In this case, the output of the block interleaver 124 is input to the modulator 133, and a demultiplexer (not shown) may be omitted or a demultiplexer (not shown) may sequentially output have.

The operations of the block interleaver 124 and the modulator 130 are the same as those described in the first embodiment, and a detailed description thereof will be omitted.

A receiving apparatus (not shown) corresponding to the transmitting apparatus 100 performing such an operation includes a demodulator (not shown), an interleaver 120 (i.e., a parity interleaver 121, a group interleaver 122 and block interleaver 124) and a decoding unit (not shown) corresponding to the encoding unit 110.

On the other hand, the performance in the case of using the method according to the second embodiment is shown in Fig. Referring to FIG. 21, it can be seen that the non-uniform 64-QAM modulation scheme according to an embodiment of the present invention has excellent BER / FER performance in a specific SNR region.

In the third embodiment of the present invention, the coding unit 110 performs LDPC coding with a coding rate of 10/15, 11/15, 12/15, and 13/15 to generate an LDPC codeword (N _ldpc = 16200 And a non-uniform 256-QAM modulation scheme corresponding to the coding rate is used in the modulator 130 based on Table 76 and Table 77. [

In this case, the group interleaver 122 may perform group interleaving using Equation (11) and Table 86 below.

Table 86 defines π (j) in Equation (11) and is the same as Table 31 described above.

Meanwhile, the group interleaver 122 may perform group interleaving using Equation (12) and Table 87 below.

Table 87 defines &lt; RTI ID = 0.0 &gt; (j) &lt; / RTI &gt;

In these cases, according to Table 58 or Table 61, the number of columns is 8, the number of rows of the first part is 1800 (= 360 x 5), and the number of rows of the second part is 225 . In this case, the output of the block interleaver 124 is input to the modulator 133, and a demultiplexer (not shown) may be omitted or a demultiplexer (not shown) may sequentially output have.

The operations of the block interleaver 124 and the modulator 130 are the same as those described in the first embodiment, and a detailed description thereof will be omitted.

A receiving apparatus (not shown) corresponding to the transmitting apparatus 100 performing such an operation includes a demodulator (not shown), an interleaver 120 (i.e., a parity interleaver 121, a group interleaver 122 and block interleaver 124) and a decoding unit (not shown) corresponding to the encoding unit 110.

In the fourth embodiment of the present invention, the encoding unit 110 performs LDPC encoding with a code rate of 6/15, 7/15, 8/15, and 9/15 in order to generate an LDPC codeword (N _ldpc = 16200 And a modulator 130 uses a non-uniform 1024-QAM modulation scheme corresponding to the coding rate based on Tables 78 to 81. [

In this case, the group interleaver 122 may perform group interleaving using Equation (11) and Table 88 below.

Table 88 defines? (J) in Equation (11) and is the same as Table 33 described above.

Meanwhile, the group interleaver 122 may perform group interleaving using Equation (12) and Table 89 below.

Table 89 defines? (J) in Equation (12) and is the same as Table 48 described above.

In these cases, according to Table 58 or Table 61, the number of columns is 10, the number of rows of the first part is 1440 (= 360 x 4), and the number of rows of the second part is 180, have. In this case, the output of the block interleaver 124 is input to the modulator 133, and a demultiplexer (not shown) may be omitted or a demultiplexer (not shown) may sequentially output have.

The operations of the block interleaver 124 and the modulator 130 are the same as those described in the first embodiment, and a detailed description thereof will be omitted.

A receiving apparatus (not shown) corresponding to the transmitting apparatus 100 performing such an operation includes a demodulator (not shown), an interleaver 120 (i.e., a parity interleaver 121, a group interleaver 122 and block interleaver 124) and a decoding unit (not shown) corresponding to the encoding unit 110.

On the other hand, the performance in the case of using the method according to the fourth embodiment is shown in Fig. Referring to FIG. 22, it can be seen that the non-uniform 1024-QAM modulation scheme according to an embodiment of the present invention has excellent BER / FER performance in a specific SNR region.

In the fifth embodiment of the present invention, the LDPC coding is performed at the coding rate of 6/15, 7/15, 8/15, 9/15 in the coding unit 110 to obtain LDPC codewords N _ldpc = 16200 And the modulator 130 uses a non-uniform 256-QAM modulation scheme corresponding to the coding rate based on Table 76 or Table 77. [

In this case, the group interleaver 122 may perform group interleaving using Equation (11) and Table 90 below.

Table 90 defines? (J) in Equation (11) and is the same as that in Table 35 described above.

Meanwhile, the group interleaver 122 may perform group interleaving using Equation (12) and Table 91 below.

Table 91 defines? (J) in Equation (12) and is the same as Table 50 described above.

In these cases, according to Table 58 or Table 61, the number of columns is 8, the number of rows of the first part is 7920 (= 360x22), and the number of rows of the second part is 180 can be used have. In this case, the output of the block interleaver 124 is input to the modulator 133, and a demultiplexer (not shown) may be omitted or a demultiplexer (not shown) may sequentially output have.

The operations of the block interleaver 124 and the modulator 130 are the same as those described in the first embodiment, and a detailed description thereof will be omitted.

A receiving apparatus (not shown) corresponding to the transmitting apparatus 100 performing such an operation includes a demodulator (not shown), an interleaver 120 (i.e., a parity interleaver 121, a group interleaver 122 and block interleaver 124) and a decoding unit (not shown) corresponding to the encoding unit 110.

In the above-described first to fifth embodiments, when group interleaving is performed using Equation (11), an index of an input group is applied to a value of pi (j), and group interleaving is performed using Equation (J) is applied to the index of the output group, they are inversely related to each other.

In addition, the above-described first to fifth embodiments are merely examples for explaining the inverse relationship, and the various tables described in the present invention may be in an inverse relationship as in the first to fifth embodiments described above. have.

On the other hand, the transmitting apparatus 200 can modulate the signal mapped to the constellation and transmit it to the receiving apparatus (e.g., 2700 in Fig. 27). For example, the transmitter 200 may map a signal mapped to constellation to an OFDM frame using an Orthogonal Frequency Division Multiplexing (OFDM) scheme and transmit the mapped signal to the receiver 2700 through the allocated channel

Example 2: Block- low Interleaver  When to use

In another embodiment of the present invention, the interleaver 120 interleaves the LDPC codeword by a method other than the method described in the first embodiment, so that bits included in a predetermined group among a plurality of groups constituting the interleaved LDPC codeword To be mapped to predetermined bits in the modulation symbol. Reference is made to Fig. 23 for a detailed description.

23, the interleaver 120 includes a parity interleaver 121, a group interleaver (or a group-wise interleaver 122), a group twist interleaver 123, and a block-row interleaver 125 do. Here, the parity interleaver 121 and the group twist interleaver 123 perform the same functions as those described in the first embodiment, so that a detailed description of these components will be omitted.

The group interleaver 122 may classify the parity interleaved LDPC codewords into a plurality of groups, and rearrange the order of the plurality of groups into groups.

In this case, the operation of dividing the parity-interleaved LDPC codewords into a plurality of groups is the same as that described in the first embodiment, and a detailed description thereof will be omitted.

Meanwhile, the group interleaver 122 interleaves the LDPC codeword group by group. That is, the group interleaver 122 can rearrange the order of a plurality of groups in the LDPC codeword group by changing positions of a plurality of groups constituting the LDPC codeword.

In this case, the group interleaver 122 can interleave the LDPC codewords on a group basis using Equation (13) below.

Here, X _j denotes the j-th group before the group interleaving, Y _j represents the j th group after group interleaving.

Further,? (J) is a parameter indicating an interleaving sequence and may be determined by at least one of the length, the coding rate and the modulation method of the LDPC codeword.

Meanwhile, a specific example of? (J) according to an embodiment of the present invention can be defined as Tables 92 to 106 below.

For example, when the LDPC codeword length _Nldpc is 16200 and the coding rates are 10/15, 11/15, 12/15, and 13/15 and the modulation method is 16-QAM,? (J) Or Table 93. &lt; tb &gt;&lt; TABLE &gt;

In the case of Table 92, equation (13) is expressed as Y ₀ = X _{? (0)} = X ₇ , Y ₁ = X _{? (1)} = X ₄₂ , Y ₂ = X _{? (2)} = X ₃₇ , , Y ₄₃ = X _{? (43)} = X ₁₃ , Y ₄₄ = X _{? (44)} = X ₄₄ . Accordingly, the group interleaver 122 sets the seventh group to the 0th, the 42nd group to the 1st, the 37th to the 2nd, ... , The thirteenth group to the 43rd group, and the 44th group to the 44th order, so that the order of the plurality of groups can be rearranged in groups.

In the case of Table 93, Equation (13) shows that Y ₀ = X _{? (0)} = X ₆ , Y ₁ = X _{? (1)} = X ₁₅ , Y ₂ = X _{? (2)} = X ₂₅ , , Y ₄₃ = X _{? (43)} = X ₂₇ , Y ₄₄ = X _{? (44)} = X ₂₉ . Accordingly, the group interleaver 122 sets the sixth group to the 0th, the 15th group to the first, the 25th to the second, and so on. The 27th group to the 43rd group, and the 29th group to the 44th order, the order of the plurality of groups can be rearranged in groups.

As another example, when the LDPC codeword length _Nldpc is 16200 and the coding rates are 6/15, 7/15, 8/15, 9/15 and the modulation scheme is 64-QAM,? (J) Or Table 95. &lt; tb &gt;&lt; TABLE &gt;

In the case of Table 94, Equation (13) shows that Y ₀ = X _{? (0)} = X ₃₂ , Y ₁ = X _{? (1)} = X ₃₉ , Y ₂ = X _{? (2)} = X ₈ , , Y ₄₃ = X _{? (43)} = X ₄₃ , Y ₄₄ = X _{? (44)} = X ₄₄ . Accordingly, the group interleaver 122 sets the 32nd group to the 0th, the 39th group to the 1st, the 8th to the 2nd group, and so on. The 43rd group to the 43rd group, and the 44th group to the 44th order, the order of the plurality of groups can be rearranged in a group unit.

For Table 95, the equation (13) is _{Y 0 = X π (0)} = X 32, Y 1 = X π (1) = X 4, Y 2 = X π (2) = X 23, ... , Y ₄₃ = X _{? (43)} = X ₄₃ , Y ₄₄ = X _{? (44)} = X ₄₄ . Accordingly, the group interleaver 122 sets the 32nd group to the 0th, the 4th group to the 1st, the 23rd group to the 2nd, ... The 43rd group to the 43rd group, and the 44th group to the 44th order, the order of the plurality of groups can be rearranged in a group unit.

As another example, when the LDPC codeword length _Nldpc is 16200 and the coding rates are 10/15, 11/15, 12/15, and 13/15 and the modulation scheme is 256-QAM, π (j) Or Table 97. &lt; tb &gt;&lt; TABLE &gt;

For Table 96, the equation (13) is _{Y 0 = X π (0)} = X 28, Y 1 = X π (1) = X 22, Y 2 = X π (2) = X 7, ... , Y ₄₃ = X _{? (43)} = X ₄₃ , Y ₄₄ = X _{? (44)} = X ₄₄ . Accordingly, the group interleaver 122 sets the 28th group to the 0th, the 22nd group to the 1st, the 7th to the 2nd, and so on. The 43rd group to the 43rd group, and the 44th group to the 44th order, the order of the plurality of groups can be rearranged in a group unit.

For Table 97, the equation (13) is _{Y 0 = X π (0)} = X 21, Y 1 = X π (1) = X 9, Y 2 = X π (2) = X 13, ... , Y ₄₃ = X _{? (43)} = X ₂₈ , and Y ₄₄ = X _{? (44)} = X ₂₉ . Accordingly, the group interleaver 122 sets the 21st group to the 0th, the 9th group to the 1st, the 13th to the 2nd, and so on. , The 28th group to the 43rd group, and the 29th group to the 44th order, so that the order of the plurality of groups can be rearranged in groups.

As another example, when the LDPC codeword length _Nldpc is 16200 and the coding rates are 6/15, 7/15, 8/15, 9/15 and the modulation method is 1024-QAM,? (J) Or Table 99. &lt; tb &gt;&lt; TABLE &gt;

For Table 98, the equation (13) is _{Y 0 = X π (0)} = X 16, Y 1 = X π (1) = X 24, Y 2 = X π (2) = X 32, ... , Y ₄₃ = X _{? (43)} = X ₄₃ , Y ₄₄ = X _{? (44)} = X ₄₄ . Accordingly, the group interleaver 122 sets the 16th group to the 0th, the 24th group to the 1st, the 32th to the 2nd, and so on. The 43rd group to the 43rd group, and the 44th group to the 44th order, the order of the plurality of groups can be rearranged in a group unit.

In the case of Table 99, Equation (13) shows that Y ₀ = X _{? (0)} = X ₁₆ , Y ₁ = X _{? (1)} = X ₃₄ , Y ₂ = X _{? (2)} = X ₈ , , Y ₄₃ = X _{? (43)} = X ₃₈ , Y ₄₄ = X _{? (44)} = X ₃₉ . Accordingly, the group interleaver 122 sets the 16th group to the 0th, the 34th group to the 1st, the 8th to the 2nd group, and so on. , The 38th group to the 43rd group, and the 39th group to the 44th order, so that the order of the plurality of groups can be rearranged in groups.

As another example, when the length N _ldpc of the LDPC codeword is 64800 and the coding rates are 6/15, 7/15, 8/15, and 9/15 and the modulation method is 256-QAM,? (J) Or Table 101. &lt; tb &gt;&lt; TABLE &gt;

In the case of table 100, the equation (13) is _{Y 0 = X π (0)} = X 48, Y 1 = X π (1) = X 152, Y 2 = X π (2) = X 156, ... , Y ₁₇₈ = X _{17 (178)} = X ₁₇₈ , Y ₁₇₉ = X _{17 (179)} = X ₁₇₉ . Accordingly, the group interleaver 122 sets the 48th group to the 0th, the 152th group to the 1st, the 156th to the 2nd, and so on. , The 178th group is changed to the 178th group, and the 179th group is changed to the 179th group, so that the order of the plurality of groups can be rearranged in groups.

In the case of table 101, the equation (13) is _{Y 0 = X π (0)} = X 48, Y 1 = X π (1) = X 4, Y 2 = X π (2) = X 15, ... , Y ₁₇₈ = X _{17 (178)} = X ₁₇₈ , Y ₁₇₉ = X _{17 (179)} = X ₁₇₉ . Accordingly, the group interleaver 122 sets the 48th group to the 0th, the 4th group to the 1st, the 15th group to the 2nd, ... , The 178th group is changed to the 178th group, and the 179th group is changed to the 179th group, so that the order of the plurality of groups can be rearranged in groups.

As another example, when the length _Nldpc of the LDPC codeword is 64800 and the coding rate is 6/15 and the modulation scheme is 256-QAM,? (J) can be defined as shown in Table 102 below.

In the case of table 102, the equation (13) is _{Y 0 = X π (0)} = X 53, Y 1 = X π (1) = X 71, Y 2 = X π (2) = X 135, ... , Y ₁₇₈ = X ₍₁₇₈₎ = X ₂₆ , Y ₁₇₉ = X ₍₁₇₉₎ = X ₃₁ . Accordingly, the group interleaver 122 sets the 53rd group to the 0th, the 71st to the 1st, the 135th to the 2nd, and so on. , The 26th group is changed to the 178th group, and the 31st group is changed to the 179th group, so that the order of a plurality of groups can be rearranged in groups.

As another example, if the length _Nldpc of the LDPC codeword is 64800 and the coding rate is 8/15 and the modulation scheme is 256-QAM,? (J) can be defined as shown in Table 103 below.

In the case of table 103, the equation (13) is _{Y 0 = X π (0)} = X 71, Y 1 = X π (1) = X 36, Y 2 = X π (2) = X 38, ... , Y ₁₇₈ = X _{17 (178)} = X ₁₆ , and Y ₁₇₉ = X _{17 (179)} = X ₁₈ . Accordingly, the group interleaver 122 sets the 71st group to the 0th, the 36th group to the 1st, the 38th to the 2nd, and so on. , The 16th group is changed to the 178th group, and the 18th group is changed to the 179th group, so that the order of the plurality of groups can be rearranged in groups.

As another example, when the LDPC codeword length _Nldpc is 64,800, the coding rate is 10/15 and the modulation scheme is 256-QAM,? (J) can be defined as shown in Table 104 below.

In the case of table 104, the equation (13) is _{Y 0 = X π (0)} = X 111, Y 1 = X π (1) = X 39, Y 2 = X π (2) = X 34, ... , Y ₁₇₈ = X ₍₁₇₈₎ = X ₈₅ , and Y ₁₇₉ = X ₍₁₇₉₎ = X ₁₁₈ . Accordingly, the group interleaver 122 sets the 111th group to the 0th, the 39th group to the 1st, the 34th to the 2nd group, and so on. , The 85th group is changed to the 178th group, and the 118th group is changed to the 179th group, so that the order of the plurality of groups can be rearranged in groups.

As another example, if the length _Nldpc of the LDPC codeword is 64800, the coding rate is 10/15 and the modulation scheme is 256-QAM,? (J) can be defined as shown in Table 105 below.

In the case of table 105, the equation (13) is _{Y 0 = X π (0)} = X 89, Y 1 = X π (1) = X 20, Y 2 = X π (2) = X 72, ... , Y ₁₇₈ = X ₍₁₇₈₎ = X ₂₇ , and Y ₁₇₉ = X ₍₁₇₉₎ = X ₂₉ . Accordingly, the group interleaver 122 sets the 89th group to the 0th, the 20th group to the 1st, the 72th to the 2nd, and so on. , The 27th group is changed to the 178th group, and the 29th group is changed to the 179th group, so that the order of the plurality of groups can be rearranged in groups.

As another example, if the length _Nldpc of the LDPC codeword is 64800 and the coding rate is 12/15 and the modulation scheme is 256-QAM,? (J) can be defined as shown in Table 106 below.

In the case of Table 106, Equation (13) shows that Y ₀ = X _{? (0)} = X ₅₁ , Y ₁ = X _{? (1)} = X ₆ , Y ₂ = X _{? (2)} = X ₇₅ , , Y ₁₇₈ = X ₍₁₇₈₎ = X ₁₈ , and Y ₁₇₉ = X ₍₁₇₉₎ = X ₂₅ . Accordingly, the group interleaver 122 sets the 51st group to the 0th, the 6th group to the 1st, the 75th to the 2nd group, and so on. , The 18th group is changed to the 178th group, and the 25th group is changed to the 179th order so that the order of the plurality of groups can be rearranged in groups.

In this manner, the group interleaver 122 can rearrange the order of the plurality of groups into groups using Equation (13) and Table 92 to Table 106. [

On the other hand, the groups constituting the LDPC codeword are rearranged in group units by the group interleaver 122 and then block interleaved by a block interleaver 124, which will be described later. In Table 19 to Table 106, ) With respect to " Order of bits group to be block interleaved ".

Meanwhile, the group interleaver 122 may interleave the LDPC codewords group by group using Equation (14).

Here, X _j denotes the j-th group before the group interleaving, Y _j represents the j th group after group interleaving.

Further,? (J) is a parameter indicating an interleaving sequence and may be determined by at least one of the length, the coding rate and the modulation method of the LDPC codeword.

Meanwhile, a specific example of? (J) according to an embodiment of the present invention can be defined as shown in Tables 107 to 121 below.

For example, when the LDPC codeword length _Nldpc is 16200 and the coding rates are 10/15, 11/15, 12/15, and 13/15 and the modulation scheme is 16-QAM, π (j) Or Table 108. &lt; tb &gt;&lt; TABLE &gt;

In the case of table 107, Equation (14) is _{X 0 = Y π (0)} = Y 11, X 1 = Y π (1) = Y 38, X 2 = Y π (2) = Y 27, ... , Can be expressed as _{X 43 = Y π (43)} = Y 17, X 44 = Y π (44) = Y 44. Accordingly, the group interleaver 122 sets the 0th group to 11th, the 1st group to 38th, the 2nd group to 27th, and so on. , The 43rd group is changed to the 17th group, and the 44th group is changed to the 44th group, so that the order of the plurality of groups can be rearranged in groups.

In the case of table 108, Equation (14) is _{X 0 = Y π (0)} = Y 7, X 1 = Y π (1) = Y 31, X 2 = Y π (2) = Y 36, ... , X ₄₃ = Y _{? (43)} = Y ₁₀ , X ₄₄ = Y _{? (44)} = Y ₃₄ . Accordingly, the group interleaver 122 sets the 0th group to 7th, the 1st group to 31st, the 2nd group to 36th, and so on. , The 43rd group is changed to the 10th group, and the 44th group is changed to the 44th group, so that the order of the plurality of groups can be rearranged in groups.

As another example, when the LDPC codeword length _Nldpc is 16200 and the coding rates are 6/15, 7/15, 8/15, 9/15 and the modulation scheme is 64-QAM,? (J) Or Table 110. &lt; tb &gt;&lt; TABLE &gt;

In the case of table 109, equation (14) are _{X 0 = Y π (0)} = Y 26, X 1 = Y π (1) = Y 22, X 2 = Y π (2) = Y 41, ... , Can be expressed as _{X 43 = Y π (43)} = Y 43, X 44 = Y π (44) = Y 44. Accordingly, the group interleaver 122 sets the 0th group to 26th, the 1st group to 22nd, the 2nd group to 41st, ... The 43rd group to the 43rd group, and the 44th group to the 44th order, the order of the plurality of groups can be rearranged in a group unit.

In the case of table 110, equation (14) are _{X 0 = Y π (0)} = Y 18, X 1 = Y π (1) = Y 31, X 2 = Y π (2) = Y 41, ... , Can be expressed as _{X 43 = Y π (43)} = Y 43, X 44 = Y π (44) = Y 44. Accordingly, the group interleaver 122 sets the 0th group to the 18th, the 1st group to the 31st, the 2 nd group to the 41st, ... The 43rd group to the 43rd group, and the 44th group to the 44th order, the order of the plurality of groups can be rearranged in a group unit.

In another example, when the LDPC codeword length _Nldpc is 16200 and the coding rates are 10/15, 11/15, 12/15, and 13/15 and the modulation scheme is 256-QAM,? (J) Or Table 112. &lt; tb &gt;&lt; TABLE &gt;

In the case of table 111, equation (14) are _{X 0 = Y π (0)} = Y 32, X 1 = Y π (1) = Y 26, X 2 = Y π (2) = Y 14, ... , Can be expressed as _{X 43 = Y π (43)} = Y 43, X 44 = Y π (44) = Y 44. Accordingly, the group interleaver 122 sets the 0th group to 32nd, the 1st group to 26th, the 2nd group to 14th, and so on. The 43rd group to the 43rd group, and the 44th group to the 44th order, the order of the plurality of groups can be rearranged in a group unit.

In the case of table 112, equation (14) are _{X 0 = Y π (0)} = Y 24, X 1 = Y π (1) = Y 9, X 2 = Y π (2) = Y 35, ... , X ₄₃ = Y ₍₄₃₎ = Y ₃₀ , X ₄₄ = Y ₍₄₄₎ = Y ₆ . Accordingly, the group interleaver 122 sets the 0th group to the 24th, the 1st group to the 9th, the 2nd group to the 35th, and so on. , The 43rd group is changed to the 30th group, the 44th group is changed to the 6th, and the order of the plurality of groups can be rearranged in groups.

As another example, when the LDPC codeword length _Nldpc is 16200 and the coding rates are 6/15, 7/15, 8/15, 9/15 and the modulation scheme is 1024-QAM,? (J) Or Table 114. &lt; tb &gt;&lt; TABLE &gt;

In the case of table 113, equation (14) are _{X 0 = Y π (0)} = Y 22, X 1 = Y π (1) = Y 20, X 2 = Y π (2) = Y 7, ... , Can be expressed as _{X 43 = Y π (43)} = Y 43, X 44 = Y π (44) = Y 44. Accordingly, the group interleaver 122 sets the 0th group to the 22nd, the 1st group to the 20th, the 2nd group to the 7th, ... The 43rd group to the 43rd group, and the 44th group to the 44th order, the order of the plurality of groups can be rearranged in a group unit.

In the case of table 114, Equation (14) is _{X 0 = Y π (0)} = Y 8, X 1 = Y π (1) = Y 4, X 2 = Y π (2) = Y 40, ... , X ₄₃ = Y _{π (43)} = Y ₃₉ , X ₄₄ = Y _{π (44)} = Y ₁₃ . Accordingly, the group interleaver 122 sets the 0th group to the 8th, the 1st group to the 4th, the 2nd group to the 40th, and so on. , The 43rd group is changed to the 39th group, and the 44th group is changed to the 13th group, so that the order of a plurality of groups can be rearranged in groups.

As another example, when the LDPC codeword length _Nldpc is 64,800 and the coding rates are 6/15, 7/15, 8/15, 9/15 and the modulation scheme is 256-QAM,? (J) Or Table 116. &lt; tb &gt;&lt; TABLE &gt;

In the case of table 115, equation (14) are _{X 0 = Y π (0)} = Y 72, X 1 = Y π (1) = Y 48, X 2 = Y π (2) = Y 55, ... _{, X 178 = Y π (178} ) = Y 178, can be expressed as _{X 179 = Y π (179)} = Y 179. Accordingly, the group interleaver 122 sets the 0th group to 72nd, the 1st group to 48th, the 2nd group to 55th, and so on. , The 178th group is changed to the 178th group, and the 179th group is changed to the 179th group, so that the order of the plurality of groups can be rearranged in groups.

In the case of table 116, equation (14) are _{X 0 = Y π (0)} = Y 9, X 1 = Y π (1) = Y 6, X 2 = Y π (2) = Y 160, ... _{, X 178 = Y π (178} ) = Y 178, can be expressed as _{X 179 = Y π (179)} = Y 179. Accordingly, the group interleaver 122 sets the 0th group to the ninth, the first group to the sixth, the second to the 160th, and so on. , The 178th group is changed to the 178th group, and the 179th group is changed to the 179th group, so that the order of the plurality of groups can be rearranged in groups.

As another example, when the LDPC codeword length _Nldpc is 64,800 and the coding rate is 6/15 and the modulation scheme is 256-QAM,? (J) can be defined as shown in Table 117 below.

In the case of table 117, equation (14) are _{X 0 = Y π (0)} = Y 72, X 1 = Y π (1) = Y 104, X 2 = Y π (2) = Y 165, ... _{, X 178 = Y π (178} ) = Y 26, can be expressed as _{X 179 = Y π (179)} = Y 20. Accordingly, the group interleaver 122 sets the 0th group to 72nd, the 1st group to 104th, the 2nd group to 165th, and so on. , The 178th group is changed to 26th, and the 179th group is changed to 20th, so that the order of the plurality of groups can be rearranged in groups.

As another example, if the length N _ldpc of the LDPC codeword is 64800, the coding rate is 8/15, and the modulation scheme is 256-QAM,? (J) can be defined as shown in Table 118 below.

In the case of table 118, Equation (14) is _{X 0 = Y π (0)} = Y 143, X 1 = Y π (1) = Y 169, X 2 = Y π (2) = Y 155, ... _{, X 178 = Y π (178} ) = Y 172, can be expressed as _{X 179 = Y π (179)} = Y 148. Accordingly, the group interleaver 122 sets the 0th group to 143th, the 1st group to 169th, the 2nd group to 155th, and so on. The 178th group to the 172nd group, and the 179th group to the 148th order, so that the order of the plurality of groups can be rearranged in groups.

As another example, if the length N _ldpc of the LDPC codeword is 64800, the coding rate is 10/15, and the modulation scheme is 256-QAM,? (J) can be defined as shown in Table 119 below.

In the case of table 119, equation (14) are _{X 0 = Y π (0)} = Y 43, X 1 = Y π (1) = Y 21, X 2 = Y π (2) = Y 51, ... _{, X 178 = Y π (178} ) = Y 157, can be expressed as _{X 179 = Y π (179)} = Y 158. Accordingly, the group interleaver 122 sets the 0th group to the 43rd, the 1 st group to the 21st, the 2 nd group to the 51st, and so on. , The 178th group is changed to the 157th group, and the 179th group is changed to the 158th order, so that the order of the plurality of groups can be rearranged in groups.

As another example, if the length _Nldpc of the LDPC codeword is 64800 and the coding rate is 10/15 and the modulation scheme is 256-QAM,? (J) can be defined as shown in Table 120 below.

In the case of table 120, Equation (14) is _{X 0 = Y π (0)} = Y 165, X 1 = Y π (1) = Y 89, X 2 = Y π (2) = Y 27, ... _{, X 178 = Y π (178} ) = Y 22, can be expressed as _{X 179 = Y π (179)} = Y 117. Accordingly, the group interleaver 122 sets the 0th group to 165th, the 1st group to 89th, the 2nd group to 27th, and so on. , The 178th group is changed to the 22nd group, and the 179th group is changed to the 117th order so that the order of the plurality of groups can be rearranged in groups.

As another example, if the length _Nldpc of the LDPC codeword is 64800, the coding rate is 12/15, and the modulation scheme is 256-QAM,? (J) can be defined as shown in Table 121 below.

In the case of table 121, equation (14) are _{X 0 = Y π (0)} = Y 57, X 1 = Y π (1) = Y 176, X 2 = Y π (2) = Y 49, ... _{, X 178 = Y π (178} ) = Y 79, can be expressed as _{X 179 = Y π (179)} = Y 103. Accordingly, the group interleaver 122 sets the 0th group to 57th, the 1st group to 176th, the 2nd group to 49th, and so on. , The 178th group is changed to the 79th group, and the 179th group is changed to the 103rd group, so that the order of the plurality of groups can be rearranged in groups.

In this way, the group interleaver 122 can rearrange the order of the plurality of groups into groups using Equation (14) and Table 107 to Table 121. [

The groups constituting the LDPC codeword are reordered in group units by the group interleaver 122 and then block interleaved by a block interleaver 124 to be described later. In Table 107 to Table 121, π (j ) With respect to " Order of bits group to be block interleaved ".

When group interleaving is performed in this manner, the order of the groups constituting the group interleaved LDPC codeword is different from that of the first embodiment.

This is because the block-row interleaver 125 is used instead of the block interleaver 124 in this embodiment. In other words, since the interleaving method used in the block interleaver 124 is different from the interleaving method used in the block-row interleaver 125, the group interleaver 122 in the present embodiment performs the LDPC code The order of the plurality of groups constituting the word is rearranged.

Specifically, the group interleaver 122 may rearrange the order of the plurality of groups so that the at least one group including the bits mapped to the same modulation symbol is repeatedly arranged in units of groups.

That is, the group interleaver 122 may include one of a plurality of first groups including bits mapped to a specific first position of the modulation symbol, a plurality of second groups including bits mapped to a specific second position of the modulation symbol One of a plurality of nth groups including a bit mapped to a specific n-th position of the modulation symbol, ..., and the remaining groups may be repeatedly arranged in the same manner.

The block-row interleaver 125 interleaves a plurality of ordered reordering groups. In this case, the block-row interleaver 125 can interleave a plurality of groups, which are reordered in order, using at least one row composed of a plurality of columns in a group unit. Reference is made to Figs. 24 to 26 for a more detailed description.

FIGS. 24 to 26 are diagrams for explaining a structure of a block-row interleaver and a method of performing interleaving according to an embodiment of the present invention.

First, when N _group / m is an integer, the block-row interleaver 125 includes an interleaver 125-1 composed of m rows each including M columns as shown in FIG. 24, and a block-row interleaver 125-1 125 may perform interleaving using N _group / m interleavers 125-1 having the structure as shown in FIG.

Here, N _group is the total number of groups constituting the LDPC codeword. M is the number of bits included in one group, and may be 360, for example. M may be equal to the number of bits constituting the modulation symbol or may be 1/2 of the number of bits constituting the modulation symbol have. For example, when non-uniform QAM is used, since the bits constituting the modulation symbol are different from each other, the value of m is made equal to the number of bits constituting the modulation symbol, To be mapped to one bit.

Specifically, the block-row interleaver 125 writes each of the plurality of groups constituting the LDPC codeword in the row direction on each row in the group unit, and writes each column of the plurality of rows written in the plurality of groups in the group It is possible to perform interleaving by reading in the column direction.

For example, as shown in FIG. 24, the block-row interleaver 125 writes consecutive m groups out of a plurality of groups in row direction to each of m rows constituting the interleaver 125-1, Each row of the m number of rows can be read in the column direction. In this case, the number of interleavers 125-1 corresponding to the number of groups divided by the number of rows, that is, N _group / m, can be used.

In this manner, when the number of groups constituting the LDPC codeword is an integral multiple of the number of rows, the block-row interleaver 125 can perform interleaving by sequentially writing groups as many as the number of rows among a plurality of groups .

On the other hand, when the number of groups constituting the LDPC codeword does not become an integer multiple of the number of rows, the block-row interleaver 125 outputs N (N is an integer of 2 or more) interleavers including a different number of columns So that interleaving can be performed.

×m이고,

는 N_group/m 이하의 가장 큰 정수를 나타낸다.For example, as shown in FIGS. 25 and 26, the block-row interleaver 125 includes a first interleaver 125-2 including m rows each including M columns, and a first interleaver 125-2 including a × M / Interleaving can be performed using a second interleaver 125-3 including m rows. Here, a is an N _group -

X m,

_Represents the largest integer of N _group / m or less.

개가 이용될 수 있고, 제2 인터리버(125-3)는 1 개가 이용될 수 있다. In this case, the first interleaver 125-2

And one of the second interleaver 125-3 can be used.

×m 개 그룹 각각을 그룹 단위로 각 행에 행 방향으로 라이트하고,

×m 개 그룹이 그룹 단위로 라이트된 복수의 행의 각 열을 열 방향으로 리드하여 인터리빙을 수행할 수 있다.Specifically, the block-row interleaver 125 selects one of a plurality of groups constituting the LDPC codeword

X m groups are written in the row direction in each row in groups,

X m groups can be interleaved by reading each column of a plurality of rows written in group units in the column direction.

×m 개 그룹 중에서 행의 개수와 동일한 개수의 연속된 m 개의 그룹을 제1 인터리버(125-2)의 각 행에 행 방향으로 라이트하고, m 개의 그룹이 라이트된 제1 인터리버(125-2)의 복수의 행의 각 열을 열 방향으로 리드할 수 있다. 이 경우, 도 25 및 도 26과 같은 구조를 갖는 제1 인터리버(125-2)가

개만큼 이용될 수 있다.For example, as shown in FIGS. 25 and 26, the block-row interleaver 125

M consecutive groups of the same number as the number of rows among the m groups are written in each row of the first interleaver 125-2 in the row direction and the first interleaver 125-2 in which m groups are written, Each column of the plurality of rows of columns can be read in the column direction. In this case, the first interleaver 125-2 having the structure as shown in Figs. 25 and 26

&Lt; / RTI &gt;

Thereafter, the block-row interleaver 125 divides the bits included in the remaining groups except for the group written in the first interleaver 125-2, and writes the bits in the row direction in each row of the second interleaver 125-3 . At this time, the same number of bits can be written in each row of the second interleaver 125-3.

For example, as shown in FIG. 25, the block-row interleaver 125 divides the bits included in the remaining groups except for the group written in the first interleaver 125-2 into m bits constituting the second interleaver 125-3 M × m / m in the row direction for each row, and each column of m rows of the second interleaver 125-3 in which the bits are written can be read in the column direction. In this case, one second interleaver 125-3 having the structure as shown in Fig. 25 can be used.

However, according to another embodiment of the present invention, as shown in FIG. 26, the block-row interleaver 125 writes bits in the same manner as described in FIG. 25 for the first interleaver 125-2 , And the second interleaver 125-3 may write the bits in a manner different from the method described with reference to FIG.

That is, the block-row interleaver 125 can write the bits in the column direction to the second interleaver 125-3.

For example, as shown in FIG. 26, the block-row interleaver 125 transmits the bits included in the remaining groups except for the group written in the first interleaver 125-2 to each of the second interleaver 125-3 it is possible to write the bits in each column of m rows consisting of a 占 M / m columns in the column direction and to read each column of m rows of the bits of the second interleaver 125-3 in the column direction. In this case, one second interleaver 125-3 having the structure as shown in Fig. 26 may be used.

26, the block-row interleaver 125 writes the bits to the second interleaver in the column direction, reads the bits in the column direction, and performs interleaving. Accordingly, the bits included in the group interleaved by the second interleaver are read in the written order and output to the modulation unit 130. [ Accordingly, the bits included in the group belonging to the second interleaver can be sequentially mapped to the modulation symbols without being rearranged in order by the block-row interleaver 125.

As described above, the block-row interleaver 125 can interleave a plurality of groups using the method described in FIGS.

In accordance with such a scheme, the output of the block-row interleaver 125 may be the same as the output of the block interleaver 124. Specifically, when the block-row interleaver 125 performs interleaving as shown in FIG. 24, the block interleaver 125 outputs the same value as the block interleaver 124 performing interleaving as shown in FIG. 8, and the block- 9, interleaving is performed in the same manner as the block interleaver 124 performing the interleaving as shown in FIG. 9, and when the block-row interleaver 125 performs the interleaving as shown in FIG. 26, And outputs the same value as the block interleaver 124 to be performed.

Specifically, if the group interleaver 122 is used and the block interleaver 124 is used based on Equation (11), the output groups of the group interleaver 122 are denoted by Y _i (0? J <N _group ) When the group interleaver 122 is used and the block-row interleaver 125 is used, if the output groups of the group interleaver 122 are Z _i (0? J &lt; N _group ) The relationship between Z _i and Y _i can be expressed as Equation (15) and Equation (16) below, so that the same value can be output in the block interleaver (124).

로, 블록 인터리버(124)를 사용할 경우 제 1 파트의 하나의 열에 입력되는 그룹의 개수를 의미하며,

는 N_group/m 이하의 가장 큰 정수이다. 그리고, m은 변조 심볼을 구성하는 비트의 개수와 동일하거나, 변조 심볼을 구성하는 비트의 절반일 수 있다. 또한, m은 블록 인터리버(124)의 열의 개수를 의미하고, m은 블록-로우 인터리버(125)의 행의 개수를 의미한다.Here, α =

Means the number of groups input to one column of the first part when the block interleaver 124 is used,

Is the largest integer less than or equal to N _group / m. And, m may be equal to the number of bits constituting the modulation symbol, or may be one-half of the bits constituting the modulation symbol. M denotes the number of rows of the block interleaver 124, and m denotes the number of rows of the block-row interleaver 125. [

Therefore, when performing block interleaving by the block interleaver 124 after group interleaving by the group interleaver 122 based on Equation (11) and when performing block interleaving by the group interleaver 122 based on Equation (12) The block interleaving by the block interleaver 124 may be in an inverse relationship.

In addition, when performing block-row interleaving by the block row interleaver 125 after group interleaving by the group interleaver 122 based on Equation (13) and when performing group interleaving by the group interleaver 122 based on Equation (14) It may be in an inverse relationship when performing block-row interleaving by the block row interleaver 125 after interleaving.

Accordingly, the modulator 130 can map the bits output from the block-row interleaver 125 to the modulation symbols in the same manner as using the block interleaver 124. [

4, the bit interleaving method proposed in the present invention is composed of a parity interleaver 121, a group interleaver 122, a group twisted interleaver 123 and a block interleaver 124 , And the group twisted interleaver 123 may be omitted). However, the present invention is not limited to the above-described three or four modules.

For example, in the present invention, when a block interleaver is used and a group interleaving scheme expressed by Equation (11) is used, bit groups X _j (0? _J <N _group ) defined as Equation (9) with respect to, the m number of bit groups, for _{example, {X π (i),} X π (α + i), ..., X π ((m-1) × α + i)} (0≤i <α) So that the bits belonging to the modulation symbol constitute one modulation symbol.

이다. 그리고, m은 블록 인터리버의 열의 개수를 의미하며, 이는 변조 심볼을 구성하는 비트의 개수 또는 변조 심볼을 구성하는 비트의 개수의 절반일 수 있다.Here,? Is the number of bit groups constituting the first part of the block interleaver,? =

to be. And m denotes the number of columns of the block interleaver, which may be half the number of bits constituting the modulation symbol or the number of bits constituting the modulation symbol.

Thus, one embodiment, with respect to interleaved parity bits _{u i, {u π (i} ) + j, u π (α + i) + j, ..., u π ((m-1) × α + i _{) + j} } (0 <i? m, 0 < _j ? M) can constitute one modulation symbol. As described above, there are various methods for constructing one modulation symbol.

23, the bit interleaving scheme proposed in the present invention is composed of a parity interleaver 121, a group interleaver 122, and a group twisted interleaver 123 block-row interleaver 125 as shown in FIG. 23 Accordingly, the group twisted interleaver 123 may be omitted). However, the present invention is not limited to the above-described three or four modules.

For example, in the present invention, when a block-row interleaver is used and a group interleaving scheme expressed by Equation 13 is used, bit groups X _j (0? _J < N with respect to the _group), m bits of the group, for _{example, {X π (m × i} ), X π (m × i + 1), ..., X π (m × i + (m-1))} (0 &Lt; i &lt; a) constitute one modulation symbol.

이다. 그리고, m은 블록 인터리버의 열의 개수를 의미하며, 이는 변조 심볼을 구성하는 비트의 개수 또는 변조 심볼을 구성하는 비트의 개수의 절반일 수 있다.Here,? Is the number of bit groups constituting the first part of the block interleaver,? =

to be. And m denotes the number of columns of the block interleaver, which may be half the number of bits constituting the modulation symbol or the number of bits constituting the modulation symbol.

Thus, one embodiment, with respect to the parity interleaved bits _{u i, {u π (m} × i) + j, u π (m × i + 1) + j, ..., u π (m × i + (m _{-1)) + j} } (0 <i? M, 0 < _j ? M) can constitute one modulation symbol. As described above, there are various methods for constructing one modulation symbol.

In the following, a method for determining? (J), which is a parameter used for group interleaving in various embodiments of the present invention, will be described.

Hereinafter, a method of designing the group interleaver 122 of FIG. 4 or FIG. 23 will be described.

First, the criteria to consider are as follows.

Criteria 1) Determine different interleaving sequences according to the modulation scheme and coding rate.

criteria 2) The performance characteristics of the LDPC codeword bits for each group and the performance characteristics of the bits constituting the modulated signal are considered at the same time. For example, in the case of an LDPC codeword, the bits with the best performance are the leftmost bits, and the leftmost bits of the bits constituting the modulation symbol can be excellent in performance. That is, with respect to the performance P (y _i ) of each bit for six bits y ₀ , y ₁ , y ₂ , y ₃ , y ₄ , y ₅ constituting non-uniform 64- ₀ )> P (y ₁ )> P (y ₂ )> P (y ₃ )> P (y ₄ )> P (y ₅ ).

Therefore, when 64800 code is used and non-uniform 64-QAM (hereinafter, 64-NUQ) is used. Considering the characteristics of the code and the modulation scheme, considering which of the six bits constituting the 64-NUQ the 180 LDPC groups are to be mapped, a method of density evolution is used to determine the case where the expected performance is the best .

In other words, considering various cases where 180 groups can be mapped to 6 bits, a threshold value that can theoretically be predicted by the density evolution method can be obtained for each case. Here, the threshold means that when the LDPC code is transmitted with the SNR value, the error probability becomes '0' in the SNR region higher than the threshold value. Therefore, when the LDPC code is transmitted according to the method shown in the case where the threshold value is small among the various mappable cases, excellent performance can be guaranteed. On the other hand, designing an interleaver based on density evolution is the theoretical approach. Therefore, not only the theoretical approach of density evolution but also the verification of code performance based on the actually designed parity check matrix and the design of the interleaver based on the cycle distribution

Here, several cases that can be mapped to six bits include the case where the groups are grouped by the degree of parity check matrix degroup into groups associated with the same row and a few groups of each group are divided into six 64 QAM bits To be mapped.

The group interleaver 122 of FIG. 4 or FIG. 23 can be designed in this manner.

27 is a block diagram for explaining the configuration of a receiving apparatus according to an embodiment of the present invention. 27, a receiving apparatus 2700 includes a demodulator 2710, a multiplexer 2720, a deinterleaver 2730, and a decoder 2740.

The demodulation unit 2710 receives and demodulates the signal transmitted from the transmission apparatus 100. Specifically, the demodulator 2710 demodulates the received signal to generate a value corresponding to the LDPC codeword, and outputs the value to the multiplexer 2720. In this case, the demodulator 2710 can perform demodulation so as to correspond to the modulation scheme used in the transmitter 100.

Here, the value corresponding to the LDPC codeword can be expressed by the channel value for the received signal. There are various methods for determining the channel value, for example, a method of determining a log likelihood ratio (LLR) value.

The LLR value can be represented by a value obtained by taking a log as a ratio of the probability that the bits transmitted from the transmitting apparatus 100 are 0 and the probability of one day. Alternatively, the LLR value may be a bit value determined according to a hard decision, and the LLR value may be a representative value determined according to a period in which the probability that the bit transmitted from the transmitting apparatus 100 is 0 or 1 .

The multiplexer 2720 multiplexes the output value of the demodulator 2710 and outputs it to the deinterleaver 2730.

Specifically, the multiplexer 2720 is a component corresponding to a demultiplexer (not shown) included in the transmission apparatus 100, and performs an operation corresponding to a demultiplexer (not shown). Therefore, when the demultiplexer (not shown) is omitted from the transmitting apparatus 100, the multiplexer 2720 of the receiving apparatus 2700 can be omitted.

That is, the multiplexer 2720 can perform cell-to-bit conversion of the output value of the demodulator 2710 and output the LLR value in units of bits.

In this case, when the demultiplexer (not shown) does not change the order of the LDPC codeword bits as shown in FIG. 13, the multiplexer 2720 does not change the order of the LLR values corresponding to the bits constituting the cell, LLR values can be sequentially output. Alternatively, the multiplexer 2720 may rearrange the order of the LLR values corresponding to the bits that make up the cell to be the inverse of the demultiplexing operation performed in the demultiplexer (not shown) based on Table 50. [

The deinterleaver 2730 deinterleaves the output value of the multiplexer 2720 and outputs it to the decoding unit 2740.

Specifically, the deinterleaver 2730 corresponds to the interleaver 120 of the transmission apparatus 100, and performs an operation corresponding to the interleaver 120. FIG. That is, the deinterleaver 2730 deinterleaves the LLR value by performing the interleaving operation performed by the interleaver 120 inversely.

In this case, the deinterleaver 2730 may include components as shown in FIG. 28 or 29.

28, the deinterleaver 2730 may include a block deinterleaver 2731, a group twist deinterleaver 2732, a group deinterleaver 2733, and a parity deinterleaver 2734.

The block deinterleaver 2731 deinterleaves the output of the multiplexer 2720 and outputs it to the group twist deinterleaver 2732.

Specifically, the block deinterleaver 2731 is a component corresponding to the block interleaver 124 included in the transmitting apparatus 100, and can perform the interleaving operation performed in the block interleaver 124 inversely.

That is, the block deinterleaver 2731 writes the LLR value output from the multiplexer 2720 in each row in the row direction, using at least one row composed of a plurality of columns, It is possible to perform deinterleaving by reading the column in the column direction.

In this case, when the block interleaver 124 divides a column into two parts and performs interleaving, the block deinterleaver 2731 can perform deinterleaving by dividing a row into two parts.

When the block interleaver 124 writes and reads in a row direction to a group not belonging to the first part, the block deinterleaver 2731 writes the value corresponding to the group not belonging to the first part in the row direction, And perform the de-interleaving.

The group twisted deinterleaver 2732 deinterleaves the output value of the block deinterleaver 2731 and outputs it to the group deinterleaver 2733.

Specifically, the group twist deinterleaver 2732 is a component corresponding to the group twist interleaver 123 provided in the transmission apparatus 100, and can inversely perform the interleaving operation performed in the group twist interleaver 123 .

That is, the group twist deinterleaver 2732 can rearrange the LLR values in the same group by changing the order of the LLR values existing in the same group. On the other hand, if the group twist operation is not performed in the transmitting apparatus 100, the group twist deinterleaver 2732 may be omitted.

The group deinterleaver 2733 (or group-wise deinterleaver) deinterleaves the output value of the group twist deinterleaver 2732 and outputs it to the parity deinterleaver 2734.

Specifically, the group deinterleaver 2733 is a component corresponding to the group interleaver 122 provided in the transmitting apparatus 100, and can perform the interleaving operation performed in the group interleaver 122 inversely.

That is, the group deinterleaver 2733 can rearrange the order of the plurality of groups into groups. In this case, the group deinterleaver 2733 can rearrange the order of a plurality of groups in groups by applying the interleaving scheme of Tables 27 to 56 in accordance with the length, modulation method, and coding rate of the LDPC codeword.

The parity deinterleaver 2734 performs parity deinterleaving on the output value of the group deinterleaver 2733 and outputs it to the decoding unit 2740.

Specifically, the parity deinterleaver 2734 is a component corresponding to the parity interleaver 121 provided in the transmitting apparatus 100, and can perform the interleaving operation performed in the parity interleaver 121 inversely. That is, the parity deinterleaver 2734 can deinterleave the LLR values corresponding to the parity bits among the LLR values output from the group deinterleaver 2733. In this case, the parity deinterleaver 2734 can deinterleave the LLR values corresponding to the parity bits inverse to the parity interleaving method of Equation (8).

 However, the parity deinterleaving can be performed only when the transmitting apparatus 100 generates an LDPC codeword using the parity check matrix 200 as shown in FIG. 2, and the parity deinterleaver 2734 performs parity deinterleaving And may be omitted when the LDPC codeword is coded based on the check matrix 300. [

The deinterleaver 2730 of FIG. 27 may be composed of three or four components as shown in FIG. 28, but the operation of the components may be performed by one component. For example, when one bit belonging to each of the bit groups constitutes one modulation symbol for the bit groups Xa, Xb, Xc, and Xd, the deinterleaver divides the bit group Interleaving can be performed to a position corresponding to the &lt; RTI ID = 0.0 &gt;

28, the deinterleaver 2730 may include a block-low deinterleaver 2735, a group twist deinterleaver 2732, a group deinterleaver 2733, and a parity deinterleaver 2734. In this case, since the group twist deinterleaver 2732 and the parity deinterleaver 2734 perform the same functions as those of FIG. 27, a detailed description of the overlapping portions will be omitted.

The block-row deinterleaver 2735 deinterleaves the output value of the multiplexer 2720 and outputs it to the group twist deinterleaver 2732.

Specifically, the block-low deinterleaver 2735 is a component corresponding to the block-row interleaver 125 included in the transmitting apparatus 100, and performs the interleaving operation performed in the block-row interleaver 125 inversely can do.

That is, the block-row deinterleaver 2735 writes the LLR value output from the multiplexer 2720 in the column direction in the column direction, using at least one column of the plurality of rows, It is possible to carry out deinterleaving by reading each row in the column direction.

However, if the block-row interleaver 125 writes and reads in the column direction for a group not belonging to the first part, the block-row deinterleaver 2735 outputs the value corresponding to the group not belonging to the first part as a column Lt; RTI ID = 0.0 &gt; and / or &lt; / RTI &gt;

The group deinterleaver 2733 deinterleaves the output value of the group twist deinterleaver 2732 and outputs it to the parity deinterleaver 2734.

Specifically, the group deinterleaver 2733 is a component corresponding to the group interleaver 122 provided in the transmitting apparatus 100, and can perform the interleaving operation performed in the group interleaver 122 inversely.

That is, the group deinterleaver 2733 can rearrange the order of the plurality of groups into groups. In this case, the group deinterleaver 2733 may reverse the interleaving scheme of Tables 92 to 121 according to the length of the LDPC codeword, the modulation scheme, and the coding rate, thereby rearranging the order of the plurality of groups into groups.

The decoding unit 2740 can perform LDPC decoding using the output value of the deinterleaver 2730. For this, the decoding unit 2740 may include an LDPC decoder (not shown) for performing LDPC decoding.

More specifically, the decoding unit 2740 is a component corresponding to the encoding unit 110 of the transmission apparatus 200, and performs LDPC decoding using the LLR value output from the deinterleaver 2730 to correct errors have

For example, the decoding unit 2740 may perform LDPC decoding using iterative decoding based on a sum-product algorithm. Here, the summing algorithm is a kind of message passing algorithm, and the message passing algorithm is a method of exchanging messages (e.g., LLR values) via edges on a bipartite graph, It shows an algorithm for calculating and updating an output message from input messages.

 Meanwhile, the decoding unit 2740 may use a parity check matrix for LDPC decoding. In this case, the information word sub-matrix in the parity check matrix is defined as shown in Tables 4 to 26 according to the coding rate and the length of the LDPC codeword, and the parity sub-matrix may have a double diagonal structure.

Information on the parity check matrix used in the LDPC decoding, information on the coding rate, and the like may be stored in the receiving apparatus 2700 or may be provided from the transmitting apparatus 100.

30 is a flowchart for explaining a signal processing method of a transmitting apparatus according to an embodiment of the present invention.

First, LDPC coding is performed to generate an LDPC codeword (S3010). In this case, a parity check matrix (i.e., a parity check matrix as shown in FIG. 2) in which an information word partial matrix is defined by Tables 4 to 26 and a parity partial matrix has a double diagonal structure is used at the time of LDPC coding, And a parity check matrix (i.e., a structure as shown in FIG. 3) based on Equation (4) and Equation (5) may be used.

Thereafter, the LDPC codeword is interleaved (S3020).

Then, the interleaved LDPC codeword is mapped to the modulation symbol (S3030). In this case, the bits included in the predetermined group among the plurality of groups constituting the LDPC codeword can be mapped to predetermined bits in the modulation symbol.

Here, each of the plurality of groups may be constituted by 360 bits.

In operation S3020, the parity bits constituting the LDPC codeword are interleaved, the parity interleaved LDPC codeword is divided into the plurality of groups, the order of the plurality of groups is rearranged in units of groups, Groups can be interleaved.

Specifically, the order of a plurality of groups can be rearranged on a group basis based on Equation (11). In this case, in Equation (11),? (J) may be determined based on at least one of the length of the LDPC codeword, the modulation scheme, and the coding rate.

As a specific example, π (j) can be defined as shown in Table 37 when the length of the LDPC codeword is 64800, the modulation scheme is 256-QAM, and the coding rate is 6/15.

In another example, π (j) can be defined as Table 38 above when the length of the LDPC codeword is 64800 and the modulation scheme is 256-QAM and the code rate is 8/15.

In another example, π (j) can be defined as shown in Table 39 when the length of the LDPC codeword is 64800, the modulation scheme is 256-QAM, and the coding rate is 10/15.

In another example, π (j) can be defined as shown in Table 40 when the LDPC codeword length is 64800, the modulation scheme is 256-QAM, and the coding rate is 10/15.

As another example, π (j) can be defined as shown in Table 41 when the length of the LDPC codeword is 64800, the modulation scheme is 256-QAM, and the coding rate is 12/15.

However, these are merely examples, and? (J) can be defined as shown in Tables 27 to 36 according to the length, modulation scheme, and coding rate of the LDPC codeword.

In addition, Equation (12) may be used to rearrange the order of a plurality of groups on a group basis. In this case,? (J) may be defined as shown in Tables 42 to 56 above.

On the other hand, in the case of interleaving a plurality of groups in which the sequences are rearranged, a plurality of groups are written in a column direction in each of a plurality of columns in a group unit, and each row of a plurality of columns in which a plurality of groups are group- And interleaving can be performed.

 In this case, after at least a part of groups which can be written in units of a plurality of columns in each of a plurality of columns are sequentially written into each of the plurality of columns, at least some of the groups in each of the plurality of columns are written in groups, The remaining groups can be divided and written in the area.

If the order of a plurality of groups is rearranged in a group unit, a plurality of groups are arranged such that at least one group including bits mapped to the same positions of different modulation symbols are arranged adjacent to each other, The order may be rearranged on a group basis so that the preset group is written to a predetermined column.

In this case, the step S3030 may generate the modulation symbol by mapping the bits output from the predetermined column to predetermined bits in the modulation symbol.

Meanwhile, in step S3020, interleaving may be performed by a method other than the above-described method.

Specifically, interleaving may be performed using Equation (13) and Tables 92 to 106 described above, or interleaving may be performed using Table 14 and Tables 107 to 121 described above.

In these cases, the order of the plurality of groups may be rearranged in groups so that at least one group including the bits mapped to the same modulation symbol is repeatedly arranged in units of groups.

Here, when a plurality of groups are interleaved, at least one group including bits mapped to the same modulation symbol among a plurality of ordered groups is written in each row in the row direction, and at least one group is written in a row And interleaving can be performed.

Meanwhile, a non-transitory computer readable medium may be provided in which a program for sequentially performing the signal processing method according to the present invention is stored.

A non-transitory readable medium is a medium that stores data for a short period of time, such as a register, cache, memory, etc., but semi-permanently stores data and is readable by the apparatus. In particular, various applications or programs may be stored on non-volatile readable media such as CD, DVD, hard disk, Blu-ray disk, USB, memory card, ROM,

Although the buses are not shown in the above-described block diagrams for the transmitting apparatus and the receiving apparatus, the communication between the respective elements in each apparatus may be performed via the bus. Further, each apparatus may further include a processor such as a CPU, a microprocessor, or the like that performs the various steps described above.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the present invention.

100: transmitting apparatus 110:
120: interleaver 130:

Claims (28)

In the transmitting apparatus,
An encoding unit for performing LDPC encoding to generate an LDPC codeword;
An interleaver for interleaving the LDPC codeword; And
And a modulator for mapping the interleaved LDPC codeword to a modulation symbol,
Wherein the modulator comprises:
Wherein a bit included in a predetermined group among a plurality of groups constituting the LDPC codeword is mapped to a predetermined bit in the modulation symbol. The method according to claim 1,
Wherein each of the plurality of groups comprises:
And wherein the transmission unit comprises 360 bits. The method according to claim 1,
The interleaver includes:
A parity interleaver for interleaving parity bits constituting the LDPC codeword;
A group interleaver for classifying the parity interleaved LDPC codewords into the plurality of groups and rearranging the order of the plurality of groups into groups; And
And a block interleaver for interleaving the plurality of groups in which the order is rearranged. The method of claim 3,
Wherein the group interleaver comprises:
And rearranging the order of the plurality of groups on a group basis on the basis of the following equation:

Here, X _j is a _jth group before group interleaving, Y _j is a _jth group after group interleaving, N _group is a total number of the plurality of groups, and? (J) is a parameter indicating an interleaving sequence. 5. The method of claim 4,
The? (J)
The length of the LDPC codeword, the modulation scheme, and the coding rate. 6. The method of claim 5,
The? (J)
Wherein the length of the LDPC codeword is 64800, the modulation scheme is 256-QAM, and the coding rate is 6/15.

6. The method of claim 5,
The? (J)
Wherein the length of the LDPC codeword is 64800, the modulation scheme is 256-QAM, and the coding rate is 8/15.

6. The method of claim 5,
The? (J)
Wherein the length of the LDPC codeword is 64800, the modulation scheme is 256-QAM, and the coding rate is 10/15.

6. The method of claim 5,
The? (J)
Wherein the length of the LDPC codeword is 64800, the modulation scheme is 256-QAM, and the coding rate is 10/15.

6. The method of claim 5,
The? (J)
Wherein the length of the LDPC codeword is 64800, the modulation scheme is 256-QAM, and the coding rate is 12/15.

The method of claim 3,
Wherein the block interleaver comprises:
And the interleaving is performed by reading each row of the plurality of columns written in groups in the plurality of groups in the row direction and writing the plurality of groups in the column direction in each of the plurality of columns in a group unit Device. 12. The method of claim 11,
Wherein the block interleaver comprises:
At least a group of at least some writable groups in each of the plurality of columns is sequentially written to each of the plurality of columns of the plurality of groups and then at least some of the groups are written in a group unit in each of the plurality of columns And writes the remaining group into the remaining region by dividing the remaining group. 12. The method of claim 11,
Wherein the group interleaver comprises:
Wherein the order of the plurality of groups is rearranged in groups so that at least one group including at least one group including bits mapped to the same position of different modulation symbols are arranged adjacent to each other, And writes the group into the predetermined column. 14. The method of claim 13,
Wherein the modulator comprises:
And generates the modulation symbol by mapping a bit output from the predetermined column to a predetermined bit in the modulation symbol. A signal processing method of a transmitting apparatus,
Performing LDPC coding to generate an LDPC codeword;
Interleaving the LDPC codeword; And
Mapping the interleaved LDPC codeword to a modulation symbol,
Wherein mapping to the modulation symbol comprises:
Wherein a bit included in a predetermined group among a plurality of groups constituting the LDPC codeword is mapped to a predetermined bit in the modulation symbol. 16. The method of claim 15,
Wherein each of the plurality of groups comprises:
Wherein the signal processing unit comprises 360 bits. 16. The method of claim 15,
Wherein the interleaving comprises:
Interleaving parity bits constituting the LDPC codeword;
Dividing the parity-interleaved LDPC codeword into the plurality of groups, and rearranging the order of the plurality of groups into groups; And
And interleaving the plurality of groups in which the order is rearranged. 18. The method of claim 17,
The step of rearranging the order of the plurality of groups on a group basis includes:
And rearranging the order of the plurality of groups on a group basis on the basis of the following equations:

Here, X _j is a j-th group before group interleaving, Y _j is a j-th group after group interleaving, N _group is a total number of the plurality of groups, and? (J) is a parameter indicating an interleaving sequence. 19. The method of claim 18,
The? (J)
The length of the LDPC codeword, the modulation scheme, and the code rate. 20. The method of claim 19,
The? (J)
Wherein the length of the LDPC codeword is 64,800, the modulation scheme is 256-QAM, and the coding rate is 6/15.

20. The method of claim 19,
The? (J)
Wherein the length of the LDPC codeword is 64800, the modulation scheme is 256-QAM, and the coding rate is 8/15.

20. The method of claim 19,
The? (J)
Wherein the length of the LDPC codeword is 64800, the modulation method is 256-QAM, and the coding rate is 10/15.

20. The method of claim 19,
The? (J)
Wherein the length of the LDPC codeword is 64800, the modulation method is 256-QAM, and the coding rate is 10/15.

20. The method of claim 19,
The? (J)
Wherein the length of the LDPC codeword is 64,800, the modulation method is 256-QAM, and the coding rate is 12/15.

18. The method of claim 17,
Wherein the interleaving of the plurality of groups comprises:
Wherein said plurality of groups are interleaved by reading each row of said plurality of columns written in a group unit in a row direction in a column direction in each of a plurality of columns in a group unit, Processing method. 26. The method of claim 25,
Wherein the interleaving of the plurality of groups comprises:
At least a group of at least some writable groups in each of the plurality of columns is sequentially written to each of the plurality of columns of the plurality of groups and then at least some of the groups are written in a group unit in each of the plurality of columns And dividing the remaining group into remaining regions and writing the divided data. 26. The method of claim 25,
The step of rearranging the order of the plurality of groups on a group basis includes:
The order of the plurality of groups is rearranged in groups so that at least one group including bits mapped to the same position of the different modulation symbols are arranged adjacent to each other in sequence, And the signal is written to the column. 28. The method of claim 27,
Wherein mapping to the modulation symbol comprises:
And mapping the bits output from the predetermined column to predetermined bits in the modulation symbol to generate the modulation symbol.

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