KR20150000807A - Method of driving a display panel, display panel driving apparatus for performing the method and display apparatus having the display panel driving apparatus - Google Patents

Abstract

A device for driving a display panel comprises an image pattern analyzing unit, a clock signal generating unit, and a data driving unit. The image pattern analyzing unit analyzes an image pattern of image data to output a clock control signal. The clock signal generating unit outputs a clock signal to control a pulse width in response to the clock control signal. The data driving unit drives a data line of a display panel in response to the clock signal. Therefore, the device is able to reduce power consumption and heat of the data driving unit.

Description

TECHNICAL FIELD [0001] The present invention relates to a display panel driving method, a display panel driving apparatus for performing the same, and a display device including the display panel driving apparatus. [0002]

The present invention relates to a display panel driving method, a display panel driving apparatus for performing the same, and a display apparatus including the display panel driving apparatus, and more particularly to a display panel driving method used for a display apparatus, A panel drive device, and a display device including the display panel drive device.

A display device such as a liquid crystal display device includes a display panel, a data driver, and a gate driver.

The display panel includes an image including gate lines to which gate signals are applied, data lines to which data signals are applied, and a plurality of pixels defined by the gate lines and the data lines.

In recent years, the size of the display panel has been increased, and the frequency of image frames for improving image quality has been increasing. Therefore, power consumption and heat generation of the data driver driving the data lines included in the display panel are increased.

Accordingly, it is an object of the present invention to provide a display panel driving method capable of reducing power consumption and heat generation of a data driver.

Another object of the present invention is to provide a display panel driving apparatus suitable for carrying out the display panel driving method.

It is still another object of the present invention to provide a display device including the display panel drive device.

In the method of driving a display panel according to one embodiment for realizing the object of the present invention described above, an image pattern of image data is analyzed and a clock control signal is output. In response to the clock control signal, the pulse width of the clock signal provided to the data driver for driving the data line of the display panel is controlled.

In one embodiment of the present invention, the precharge voltage may be further charged to the data line in response to activation of the clock signal.

In one embodiment of the present invention, if the clock signal has a first pulse width, the data line may be charged with the pre-charge voltage for a first time corresponding to the first pulse width, The precharge voltage may be charged to the data line for a second time corresponding to the second pulse width when the second precharge voltage has a second pulse width greater than the first pulse width.

In one embodiment of the present invention, if the clock signal has a first pulse width, the data line may be charged with a first precharge voltage, and the clock signal may have a second pulse width greater than the first pulse width The data line may be charged with a second precharge voltage that is greater than the first precharge voltage.

In one embodiment of the present invention, the data line may be further charged to a target voltage in response to deactivation of the clock signal.

In one embodiment of the present invention, the data line is charged with the target voltage and the current charged in the load capacitor of the display panel by the target voltage is shared with the charge sharing capacitor so that the charge sharing capacitor is charged with the analog voltage The precharge voltage can be charged to the data line by charging the data line with the precharge voltage using the analog voltage.

In one embodiment of the present invention, when the image pattern is a black image or a white image, when the pulse width of the clock signal is reduced and the image pattern is a stripe pattern in which black and white alternately appear, the pulse width of the clock signal is So that the pulse width of the clock signal can be controlled.

In one embodiment of the present invention, the image pattern of the image data is analyzed and a slew rate control signal for controlling a slew rate of a data signal applied to the data line may be further output.

In one embodiment of the present invention, a precharge voltage may be further charged to the data line in response to activation of the clock signal, and in response to deactivation of the clock signal, the data line And can be further charged with the target voltage.

According to another aspect of the present invention, there is provided a display panel driving apparatus including a video pattern analyzer, a clock signal generator, and a data driver. The image pattern analyzing unit analyzes the image pattern of the image data and outputs a clock control signal. The clock signal generator outputs a clock signal whose pulse width is controlled in response to the clock control signal. The data driver drives the data line of the display panel in response to the clock signal.

In an embodiment of the present invention, the data driver may charge the data line in response to activation of the clock signal.

In one embodiment of the present invention, if the clock signal has a first pulse width, the data line may be charged with the pre-charge voltage for a first time corresponding to the first pulse width, The precharge voltage may be charged to the data line for a second time corresponding to the second pulse width when the second precharge voltage has a second pulse width greater than the first pulse width.

In an embodiment of the present invention, the data driver may charge the data line to a target voltage in response to deactivation of the clock signal.

In one embodiment of the present invention, the data driver may include a charge sharing unit charging the data line with the precharge voltage and a data driving integrated circuit charging the data line with the target voltage, And the data driving integrated circuit may include an amplifier for outputting the target voltage, and the amplifier for outputting the target voltage, and the data driving integrated circuit may include an amplifier for outputting the target voltage, And a switch for selectively connecting the charge sharing capacitor to the data line of the display panel.

In one embodiment of the present invention, the charge sharing unit includes a first charge sharing capacitor selectively connected to a first data line of the data line, and a second charge sharing capacitor selectively coupled to a second data line of the data line. And the data driving integrated circuit may include a first amplifier for outputting a first target voltage to the first data line, a second amplifier for outputting a second target voltage to the second data line, An amplifier and a first switch for selectively connecting said first charge sharing capacitor to said first data line and a second switch for selectively connecting said second amplifier and said second charge sharing capacitor to said second data line, .

In one embodiment of the present invention, the charge sharing portion includes a first charge sharing capacitor and a second charge sharing capacitor, which are connected to the first charge sharing capacitor and the second charge sharing capacitor and selectively connected to the first data line and selectively connected to the second data line 3 charge sharing capacitors.

In an embodiment of the present invention, the charge sharing capacitor may be selectively coupled to a first data line of the data line and selectively coupled to a second data line of the second data line.

In an embodiment of the present invention, the clock signal generator may reduce the pulse width of the clock signal when the image pattern is a black image or a white image, and when the image pattern is a stripe pattern in which black and white alternately appear The pulse width of the clock signal can be increased.

In one embodiment of the present invention, the image pattern analyzing unit analyzes the image pattern of the image data and further outputs a slew rate control signal for controlling a slew rate of a data signal applied to the data driver have.

According to another aspect of the present invention, there is provided a display apparatus including a display panel and a display panel driving apparatus. The display panel receives the data signal based on the image data and displays the image. The display panel driving apparatus includes an image pattern analyzing unit for analyzing an image pattern of the image data and outputting a clock control signal, a clock signal generator for outputting a clock signal whose pulse width is controlled in response to the clock control signal, And a data driver for driving a data line of the display panel in response to a clock signal.

According to the display panel driving method, the display panel driving apparatus for performing the method, and the display apparatus including the display panel driving apparatus, the image pattern of the image data is analyzed, and the pulse width of the clock signal, Control according to the image pattern. Therefore, the charge sharing time of the data line can be adaptively adjusted to the image pattern, and the data signal can be charged to the data line adaptively to the image pattern, thereby reducing power consumption and heat generation of the data driver Can be reduced.

1 is a block diagram showing a display device according to an embodiment of the present invention.
2 is a block diagram showing the timing controller of Fig.
3 is a block diagram showing the data driver of FIG.
4 is a block diagram showing the charge sharing unit of Fig.
5 is a timing diagram showing the first clock signal and the analog voltage of FIG.
6A and 6B are timing diagrams showing data signals applied to data lines according to the pulse width of the first clock signal of FIG.
7 is a flowchart showing a display panel driving method performed by the display panel driving apparatus of FIG.
8 is a block diagram of a display device according to another embodiment of the present invention.
FIG. 9 is a block diagram showing the timing control unit of FIG. 8. FIG.
10 is a block diagram showing the data driver of FIG.
11 is a block diagram showing the charge sharing unit of Fig.
12 is a timing chart showing a data signal according to the slew rate control signal.
13 is a flowchart showing a display panel driving method performed by the display panel driving apparatus of Fig.
14A and 14B are graphs showing power consumption of the data driver shown in FIG. 8 according to an image pattern.
15 is a circuit diagram showing a display panel and a data driver according to another embodiment of the present invention.
FIG. 16 is a flowchart showing a display panel driving method performed by the display panel driving apparatus including the data driver of FIG. 15;
17 is a circuit diagram showing a display panel and a data driver according to another embodiment of the present invention.
18 is a circuit diagram showing a display panel and a data driver according to still another embodiment of the present invention.
19 is a circuit diagram showing a display panel and a data driver according to another embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Example 1

1 is a block diagram showing a display device according to an embodiment of the present invention.

1, a display device 100 according to the present embodiment includes a display panel 200, a data driver 300, a gate driver 400, a timing controller 500, and a voltage generator 600 . The data driver 300, the gate driver 400 and the timing controller 500 may be a display panel driver for driving the display panel 200.

The display panel 200 receives the data signal DS based on the image data DATA and displays the image. For example, the image data (DATA) may be two-dimensional plane image data. In addition, the image data (DATA) may include left eye image data and right eye image data for displaying the three-dimensional image.

The display panel 200 includes gate lines GL, data lines DL, and a plurality of pixels P. [ The gate line GL extends in a first direction D1 and the data line DL extends in a second direction D2 perpendicular to the first direction D1. The first direction D1 may be parallel to the long side of the display panel 200 and the second direction D2 may be parallel to the short side of the display panel 200. [ Each of the pixels P includes a thin film transistor 210 electrically connected to the gate line GL and the data line DL, a liquid crystal capacitor 220 connected to the thin film transistor 210, and a storage capacitor 230, .

The data driver 300 generates the data signal DS based on the video data DATA in response to the data start signal STH and the first clock signal CLK1 provided from the timing controller 500 And outputs it to the data line DL.

The gate driver 400 generates the gate signal GS using the gate start signal STV and the second clock signal CLK2 provided from the timing controller 500 and outputs the gate signal GS to the gate And outputs it to the line GL.

The timing controller 500 receives the image data DATA and the control signal CON from the outside. The control signal CON may include a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, and a clock signal CLK. The timing controller 500 generates the data start signal STH using the horizontal synchronization signal Hsync and outputs the data start signal STH to the data driver 300. [ The timing controller 500 generates the gate start signal STV using the vertical synchronization signal Vsync and then outputs the gate start signal STV to the gate driver 400. [ The timing controller 500 generates the first clock signal CLK1 and the second clock signal CLK2 by using the clock signal CLK and then outputs the first clock signal CLK1 To the data driver 300 and outputs the second clock signal CLK2 to the gate driver 400. [ The timing controller 500 may further output a polarity control signal POL to the data driver 300 to control the polarity of the data signal DS output from the data driver 300. [

The timing controller 500 analyzes the image pattern of the image data DATA and calculates a pulse width of the first clock signal CLK1 output to the data driver 300 based on the image pattern .

More specifically, the timing controller 500 reduces the pulse width of the first clock signal CLK1 when the image pattern is a white image. Also, the timing controller 500 reduces the pulse width of the first clock signal CLK1 when the image pattern is a black image. In addition, the timing controller 500 increases the pulse width of the first clock signal CLK1 when the image pattern is a stripe pattern in which black and white alternately appear. For example, the stripe pattern may be a horizontal stripe pattern in which the black and the white alternate in the direction in which the data line DL extends. Alternatively, the stripe pattern may be a sub-vertical stripe pattern in which the black and the white alternate in the direction in which the gate line GL extends.

The voltage providing unit 600 provides the analog voltage QAVDD to the data driver 300. The voltage providing unit 600 may generate a gate-on voltage, a gate-off voltage, and a common voltage to further provide the gate-on voltage and the gate-off voltage to the gate driver 400, Panel 200 as shown in FIG.

2 is a block diagram showing the timing controller 500 of FIG.

Referring to FIGS. 1 and 2, the timing controller 500 includes a memory 510, a clock signal generator 520, a data start signal generator 530, and a gate start signal generator 540.

The memory 510 receives the image data (DATA) applied from the outside and outputs the image data (DATA) to the data driver (300).

The clock signal generator 520 includes an image pattern analyzer 521, a first clock signal generator 523, and a second clock signal generator 525.

The image pattern analyzer 521 receives the image data DATA and analyzes the image pattern of the image data DATA to calculate the pulse width of the first clock signal CLK1 according to the image pattern And generates a clock control signal (CCS) to be controlled. For example, the image pattern may include at least one of the horizontal stripe pattern, the sub-vertical stripe pattern, the vertical stripe pattern, the black pattern, and the white pattern.

The first clock signal generator 523 generates the first clock signal CLK1 using the clock signal CLK received from the outside and outputs the first clock signal CLK1 to the data driver 300 . The first clock signal generator 523 controls the pulse width of the first clock signal CLK1 according to the clock control signal CCS provided from the image pattern analyzer 521. [

The second clock signal generator 525 generates the second clock signal CLK2 using the clock signal CLK received from the outside and outputs the second clock signal CLK2 to the gate driver 400 .

The data start signal generator 530 generates the data start signal STH by using the horizontal synchronizing signal Hsync applied from the outside and then transmits the data start signal STH to the data driver 300 Output.

The gate start signal generator 540 generates the gate start signal STV using the vertical synchronization signal Vsync applied from the outside and then transmits the gate start signal STV to the gate driver 400 Output.

3 is a block diagram showing the data driver 300 of FIG.

1 to 3, the data driver 300 includes a shift register 310, a serial / parallel converter 320, a latch 330, a polarity controller 340, a digital / analog converter 350, And a charge sharing portion 360. [

The serial / parallel converter 320 receives the image data DATA and converts the image data DATA into parallel data to output parallel data DATA1, ..., DATAk.

The shift register 310 sequentially provides the parallel data DATA1, ..., DATAk to the latch 330 while shifting the data start signal STH. Specifically, the shift register 310 sequentially outputs the first activation signal En1 to the last activation signal Enk among the activation signals En1, ..., Enk to generate the parallel data DATA1, ..., Enk. (DATA1) to the last parallel data (DATAk) in the latch (330). The latch 330 outputs the parallel data DATA1, ..., DATAk to the polarity controller 340. [

The polarity control unit 340 controls the polarities of the parallel data DATA1 to DATAk based on the polarity control signal POL provided from the timing controller 500 to generate polarity data PDATA1, , PDATAk) and outputs the polarity data PDATA1, ..., PDATAk to the digital / analog converter 350. [

The polarity control unit 340 converts the polarity data PDATA1, ..., PDATAk into analog data to generate analog data ADATA1, ..., ADATAk, To the charge sharing unit (360).

The charge sharing unit 360 may apply the analog data ADATA1 to ADATAk to the data lines DL according to the first clock signal CLK1 provided from the timing controller 500. [ And applies the data signals DS1, DS2, ..., DSk.

4 is a block diagram showing the charge sharing unit 360 of FIG.

1 to 4, the charge sharing unit 360 includes a first amplifier 361, a second amplifier 362, a first switch 371, a second switch 372, a third switch 373, And a fourth switch 374.

The first amplifier 361 includes a first input terminal 3611, a second input terminal 3612, and an output terminal 3613. The first input terminal 3611 of the first amplifier 361 receives the first analog data ADATA1 output from the digital-to-analog converter 350. The second input terminal 3612 of the first amplifier 361 selectively receives the analog voltage QAVDD through the second switch 372. The output terminal 3613 of the first amplifier 361 is connected to the second input terminal 3612 and is connected to the data line DL of the display panel 200 through the first switch 371, Lt; / RTI >

The second amplifier 362 includes a first input terminal 3621, a second input terminal 3622, and an output terminal 3623. The first input terminal 3621 of the second amplifier 362 receives the second analog data ADATA2 output from the digital-to-analog converter 350. The second input terminal 3622 of the second amplifier 362 selectively receives the analog voltage QAVDD via the fourth switch 374. The output terminal 3623 of the second amplifier 362 is connected to the second input terminal 3622 and is connected to the data line DL of the display panel 200 via the third switch 373, Lt; / RTI >

The first switch 371 is connected to the output terminal 3613 of the first amplifier 361 and the data line DL of the display panel 200 in response to deactivation of the first clock signal CLK1 Connect electrically. The data line DL electrically connected to the first amplifier 361 through the first switch 371 may be a first data line DL1.

The second switch 372 is responsive to the activation of the first clock signal CLK1 to connect the output terminal 3613 of the first amplifier 361, the terminal to which the analog voltage QAVDD is applied, And electrically connects the first data line (DL1) of the first transistor (200).

The third switch 373 is connected to the output terminal 3623 of the second amplifier 362 and the data line DL of the display panel 200 in response to deactivation of the first clock signal CLK1 Connect electrically. The data line DL electrically connected to the second amplifier 362 through the third switch 371 may be a second data line DL2.

The fourth switch 374 is responsive to the activation of the first clock signal CLK1 to connect the output terminal 3623 of the second amplifier 362, the terminal to which the analog voltage QAVDD is applied, And electrically connects the second data line DL2 of the first TFT 200 to the second data line DL2.

5 is a timing diagram showing the first clock signal CLK1 and the analog voltage QAVDD of FIG.

1 to 5, the first switch 371 and the third switch 373 are turned on and the second switch 372 is turned on during a first period P1 before the first clock signal CLK1 is activated. 372 and the fourth switch 374 are turned off. The first switch 371 and the third switch 373 are turned off in response to the activation of the first clock signal CLK1 during the second interval P2 following the first interval P1, The second switch 372 and the fourth switch 374 are turned on. Therefore, the data lines DL are electrically connected to each other, and the data lines DL are precharged by the analog voltage QAVDD. The first switch 371 and the third switch 373 are turned on in response to deactivation of the first clock signal CLK1 during the third interval P3 following the second interval P2, 2 switch 372 and the fourth switch 374 are turned off. Therefore, the target voltages are applied to the data lines DL by the first amplifier 361 and the second amplifier 362.

A first data signal DS1 may be applied to the first data line DL1 and a second data signal DS2 may be applied to the second data line DL2 among the data lines DL. have. In this case, the polarity of the first data signal DS1 and the polarity of the second data signal DS2 are controlled by the polarity control signal POL provided from the timing controller 500 to the data driver 300 May be different. For example, the polarity of the first data signal DS1 may be a positive polarity, and the polarity of the second data signal DS2 may be a negative polarity. The polarity of the data signals applied to odd-numbered data lines among the data lines DL may be positive, and the polarity of data signals applied to even-numbered data lines among the data lines DL may be positive The polarity of the signals may be negative (-). Alternatively, the polarity of the data signals applied to the odd-numbered data lines among the data lines DL may be a negative polarity, and the polarity of the data signals applied to the odd- The polarity of the data signals applied to the data lines may be positive.

6A and 6B are timing charts showing the data signal DS applied to the data line DL according to the pulse width of the first clock signal CLK1 of FIG.

1 to 6A, when the first clock signal CLK1 has a first pulse width PW1, a first pulse width PW1 corresponding to the first pulse width PW1 of the first clock signal CLK1, The data line DL is charged with the first precharge voltage VPRE1 by the analog voltage QAVDD for a period of time. The data line DL is charged with the target voltage VTAR in response to the deactivation of the first clock signal CLK1 after the first time corresponding to the first pulse width PW1.

1 to 6B, when the first clock signal CLK1 has a second pulse width PW2 that is greater than the first pulse width PW1, the second clock signal CLK1 has a second pulse width PW2, The data line DL is charged with the second precharge voltage VPRE2 that is larger than the first precharge voltage VPRE1 by the analog voltage QAVDD during a second time corresponding to the pulse width PW2. The data line DL is charged with the target voltage VTAR in response to the deactivation of the first clock signal CLK1 after the second time corresponding to the second pulse width PW2.

The pulse width of the first clock signal CLK1 may be controlled by the timing controller 500. [ Specifically, the timing controller 500 may analyze the image pattern of the image data DATA and control the pulse width of the first clock signal CLK1 based on the analyzed image pattern . For example, the timing controller 500 may decrease the pulse width of the first clock signal CLK1 when the image pattern is the white image. Also, the timing controller 500 may reduce the pulse width of the first clock signal CLK1 when the image pattern is the black image. In addition, the timing controller 500 may increase the pulse width of the first clock signal CLK1 when the image pattern is the stripe pattern in which the black and the white alternately appear.

7 is a flowchart showing a display panel driving method performed by the display panel driving apparatus of FIG.

Referring to FIGS. 1 to 7, the image pattern is analyzed and the clock control signal CCS is output (step S110). Specifically, the image pattern analyzing unit 521 of the timing controller 500 receives the image data DATA, analyzes the image pattern of the image data DATA, And generates the clock control signal CCS for controlling the pulse width of the clock signal CLK1.

And generates the first clock signal CLK1 whose pulse width is changed based on the clock control signal CCS (step S120). Specifically, the first clock signal generator 523 of the timing controller 500 generates the first clock signal CLK1 using the clock signal CLK received from the outside, And controls the pulse width of the first clock signal CLK1 according to the clock control signal CCS provided from the control unit 521. [

In response to the activation of the first clock signal CLK1, the precharge voltage is charged to the data line DL (step S130). Specifically, the data line DL is charged with the precharge voltage by the analog voltage QAVDD for a time corresponding to the pulse width of the first clock signal CLK1.

The data line DL is charged to the target voltage VTAR in response to the inactivation of the first clock signal CLK1 (step S140). Specifically, after the time corresponding to the pulse width of the first clock signal CLK1, the data line DL is charged to the target voltage VTAR in response to deactivation of the first clock signal CLK1 .

According to the present embodiment, the image pattern of the image data (DATA) is analyzed and the pulse width of the first clock signal CLK1 provided to the data driver 300 is controlled according to the image pattern. Therefore, the charge sharing time of the data line DL can be adaptively adjusted to the image pattern, the data signal DL can be charged to the data line DL adaptively to the image pattern, The power consumption and heat generation of the data driver 300 can be reduced.

Example  2

8 is a block diagram of a display device according to another embodiment of the present invention.

The display device 700 of FIG. 8 according to the present embodiment is similar to the display device 100 of FIG. 1 except for the data driver 800 and the timing controller 900, Is substantially the same as the display device 100 described above. Therefore, the same members as those in Fig. 1 are denoted by the same reference numerals, and redundant detailed explanations can be omitted.

8, the display device 700 according to the present embodiment includes the display panel 200, the data driver 800, the gate driver 400, the timing controller 900, (600). The data driver 800, the gate driver 400 and the timing controller 900 may be a display panel driver for driving the display panel 200.

The data driver 800 generates the data signal DS based on the video data DATA in response to the data start signal STH and the first clock signal CLK1 provided from the timing controller 900. [ ) To the data line (DL).

The timing controller 900 receives the video data DATA and the control signal CON from the outside. The control signal CON may include the horizontal synchronization signal Hsync, the vertical synchronization signal Vsync, and the clock signal CLK. The timing controller 900 generates the data start signal STH using the horizontal synchronization signal Hsync and outputs the data start signal STH to the data driver 800. [ The timing controller 900 generates the gate start signal STV using the vertical synchronization signal Vsync and then outputs the gate start signal STV to the gate driver 400. [ The timing controller 900 generates the first clock signal CLK1 and the second clock signal CLK2 using the clock signal CLK and then outputs the first clock signal CLK1 To the data driver 800 and outputs the second clock signal CLK2 to the gate driver 400. [ The timing controller 900 may further output the polarity control signal POL for controlling the polarity of the data signal DS output from the data driver 800 to the data driver 800.

The timing controller 900 analyzes an image pattern of the image data DATA and calculates a pulse width of the first clock signal CLK1 output to the data driver 800 based on the image pattern And outputs a slew rate control signal SRCS for controlling the slew rate of the data signal DS.

More specifically, the timing controller 900 reduces the pulse width of the first clock signal CLK1 when the image pattern is a white image. In addition, the timing controller 900 reduces the pulse width of the first clock signal CLK1 when the image pattern is a black image. In addition, the timing controller 900 increases the pulse width of the first clock signal CLK1 when the image pattern is a stripe pattern in which black and white alternately appear. For example, the stripe pattern may be a horizontal stripe pattern in which the black and the white alternate in the direction in which the data line DL extends. Alternatively, the stripe pattern may be a sub-vertical stripe pattern in which the black and the white alternate in the direction in which the gate line GL extends.

The timing controller 900 may control the slew rate of the data signal DS after controlling the pulse width of the first clock signal CLK1 according to the image pattern. For example, the timing controller 900 may reduce the slew rate of the data signal DS.

9 is a block diagram showing the timing controller 900 of FIG.

The timing controller 900 of FIG. 9 according to the present embodiment is different from the timing controller 500 of FIG. 2 according to the previous embodiment in that the timing controller 900 of FIG. 2, except for the clock generator 920, 500). ≪ / RTI > Therefore, the same members as those in Fig. 2 are denoted by the same reference numerals, and redundant detailed descriptions can be omitted.

8 and 9, the timing controller 900 includes the memory 510, the clock signal generator 920, the data start signal generator 530, and the gate start signal generator 540 .

The clock signal generator 920 includes an image pattern analyzer 921, a first clock signal generator 523, and a second clock signal generator 525.

The image pattern analyzer 921 receives the image data DATA and analyzes the image pattern of the image data DATA to calculate the pulse width of the first clock signal CLK1 according to the image pattern And generates a clock control signal (CCS) to be controlled. In addition, the image pattern analyzing unit 921 generates the slew rate control signal SRCS for controlling the slew rate of the data signal DS according to the image pattern. For example, the image pattern may include at least one of the horizontal stripe pattern, the sub-vertical stripe pattern, the vertical stripe pattern, the black pattern, and the white pattern.

The first clock signal generator 923 generates the first clock signal CLK1 using the clock signal CLK received from the outside and outputs the first clock signal CLK1 to the data driver 800 . The first clock signal generator 923 controls the pulse width of the first clock signal CLK1 according to the clock control signal CCS provided from the image pattern analyzer 921. [

The second clock signal generator 925 generates the second clock signal CLK2 using the clock signal CLK received from the outside and outputs the second clock signal CLK2 to the gate driver 400 .

10 is a block diagram showing the data driver 800 of FIG.

The data driver 800 of FIG. 10 according to the present embodiment is different from the data driver 300 of FIG. 3 according to the previous embodiment in that the data driver 800 of FIG. 3, except for the charge sharing unit 860, 300). ≪ / RTI > Therefore, the same members as those in Fig. 3 are denoted by the same reference numerals, and redundant detailed explanations can be omitted.

8 to 10, the data driver 800 includes the shift register 310, the serial / parallel converter 320, the latch 330, the polarity controller 340, the digital / analog conversion Part 350 and the charge sharing part 860.

The charge sharing unit 860 uses the analog data ADATA1 to ADATAk to generate the first clock signal CLK1 and the slew rate control signal SRCS provided from the timing controller 900 And applies data signals DS1, DS2, ..., DSk to the data lines DL.

11 is a block diagram showing the charge sharing unit 860 of FIG.

The charge sharing portion 860 of FIG. 11 according to the present embodiment excludes the first amplifier 861 and the second amplifier 862 in comparison with the charge sharing portion 360 of FIG. 4 according to the previous embodiment And is substantially the same as the charge sharing portion 360 of FIG. Therefore, the same members as those in Fig. 4 are denoted by the same reference numerals, and redundant detailed explanations can be omitted.

8 to 11, the charge sharing unit 860 includes the first amplifier 861, the second amplifier 862, the first switch 371, the second switch 372, 3 switch 373, and the fourth switch 374.

The first amplifier 861 includes a first input terminal 8611, a second input terminal 8612, a third input terminal 8613, and an output terminal 8614. The first input terminal 8611 of the first amplifier 861 receives the first analog data ADATA1 output from the D / A converter 350. [ The second input terminal 8612 of the first amplifier 861 selectively receives the analog voltage (QAVDD) through the second switch 372. The third input terminal 8613 of the first amplifier 861 receives the slew rate control signal SRCS. The output terminal 8614 of the first amplifier 861 is connected to the second input terminal 8612 and is connected to the data line DL of the display panel 200 through the first switch 371, Lt; / RTI >

The second amplifier 862 includes a first input terminal 8621, a second input terminal 8622, a third input terminal 8623, and an output terminal 8624. The first input terminal 8621 of the second amplifier 862 receives the second analog data ADATA2 output from the D / A converter 350. [ The second input terminal 8622 of the second amplifier 862 selectively receives the analog voltage QAVDD via the fourth switch 374. The third input terminal 8623 of the second amplifier 862 receives the slew rate control signal SRCS. The output terminal 8624 of the second amplifier 862 is connected to the second input terminal 8622 and is connected to the data line DL of the display panel 200 via the third switch 373, Lt; / RTI >

Each of the first amplifier 861 and the second amplifier 862 controls the slew rate of the data signal DS applied to the data line DL according to the slew rate control signal SRCS. For example, the first amplifier 861 may amplify the first data signal DS1 applied to the first data line DL1 among the data lines DL according to the slew rate control signal SRCS. And the second amplifier 862 may control the slew rate of the second data signal DL2 applied to the second data line DL2 among the data lines DL according to the slew rate control signal SRCS. It is possible to control the slew rate of the DS2.

12 is a timing chart showing the data signal DS according to the slew rate control signal SRCS.

Referring to FIG. 12, the slew rate of the data signal DS may be controlled according to the slew rate control signal SRCS. Specifically, if the slew rate control signal SRCS has a value of '00', the slew rate of the data signal DS may be a first value, and if the slew rate control signal SRCS is a value of '01' , The slew rate of the data signal (DS) may be a second value less than the first value, and if the slew rate control signal (SRCS) has a value of '10' Rate may be a third value smaller than the second value and if the slew rate control signal SRCS has a value of 11, the slew rate of the data signal DS may be a fourth value smaller than the third value .

For example, the slew rate time of the data signal DS according to the slew rate control signal SRCS may be as shown in [Table 1].

SRCS 00 01 10 11 Slew rate time 0.8 μs 1.2 μs 1.6 μs 2.0 μs

The slew rate time may be a time from a time point at which the data line DS starts to rise in response to the first clock signal CLK1 to a time point at which the data line DS reaches about 90% of the target voltage. For example, if the slew rate control signal SRCS has a value of '00', the slew rate time of the data signal DS may be 0.8 μs, and if the slew rate control signal SRCS is '01' The slew rate time of the data signal DS may be 1.2 μs and if the slew rate control signal SRCS has a value of 10 the slew rate time of the data signal DS may be 1.6 mu s, and if the slew rate control signal SRCS has a value of '11', the slew rate time of the data signal DS may be 2.0 mu s.

13 is a flowchart showing a display panel driving method performed by the display panel driving apparatus of FIG.

Referring to FIGS. 8 to 13, the image pattern is analyzed to output the clock control signal CCS and the slew rate control signal SRCS (step S210). Specifically, the image pattern analyzing unit 921 of the timing controller 900 receives the image data DATA, analyzes the image pattern of the image data DATA, Generates the clock control signal (CCS) for controlling the pulse width of the clock signal (CLK1) and the slew rate control signal (SRCS) for controlling the slew rate of the data signal (DS).

And generates the first clock signal CLK1 whose pulse width is changed based on the clock control signal CCS (step S220). More specifically, the first clock signal generator 923 of the timing controller 900 generates the first clock signal CLK1 using the clock signal CLK received from the outside, And controls the pulse width of the first clock signal CLK1 according to the clock control signal CCS provided from the control unit 921. [

The precharge voltage is charged to the data line DL in response to the activation of the first clock signal CLK1 (step S230). Specifically, the data line DL is charged with the precharge voltage by the analog voltage QAVDD for a time corresponding to the pulse width of the first clock signal CLK1.

In response to the inactivation of the first clock signal CLK1, the data line DL is charged to the target voltage VTAR based on the slew rate control signal SRCS (step S240). Specifically, after the time corresponding to the pulse width of the first clock signal CLK1, the data line DL is charged to the target voltage VTAR in response to deactivation of the first clock signal CLK1 , The slew rate of the data signal DS charged in the data line DL is based on the slew rate control signal SRCS.

14A and 14B are graphs showing power consumption of the data driver 800 shown in FIG. 8 according to the image pattern.

8 to 14A, when the image pattern is the horizontal stripe pattern, the power consumption of the data driver 800 decreases as the charge sharing time corresponding to the pulse width of the first clock signal CLK1 becomes longer, do. Accordingly, when the image pattern is the horizontal stripe pattern, the pulse width of the first clock signal CLK1 may be relatively large. In this case, power consumption and heat generation of the data driver 800 may be reduced have. For example, when the image pattern is the horizontal stripe pattern, the pulse width of the first clock signal CLK1 may be 1.5 [micro] s.

Also, when the image pattern is the horizontal stripe pattern, the power consumption of the data driver 800 may be changed according to the slew rate control signal SRCS. Specifically, in a state where the pulse width of the first clock signal CLK1 is relatively large, the power consumption of the data driver 800 may be substantially reduced as the value of the slew rate control signal SRCS increases . Therefore, as the slew rate of the data signal DS decreases, the power consumption of the data driver 800 may decrease. Therefore, when the image pattern is the horizontal stripe pattern and the pulse width of the first clock signal CLK1 is relatively long, as the slew rate of the data signal DS decreases, Heat generation can be reduced.

8 to 13 and 14B, when the image pattern is the white pattern, as the charge sharing time corresponding to the pulse width of the first clock signal CLK1 is short, the power consumption of the data driver 800 becomes . Accordingly, when the image pattern is the white pattern, the pulse width of the first clock signal CLK1 may be relatively small. In this case, power consumption and heat generation of the data driver 800 may be reduced . For example, when the image pattern is the white pattern, the pulse width of the first clock signal CLK1 may be 0 [mu] s.

In addition, when the image pattern is the white pattern, the power consumption of the data driver 800 may vary according to the slew rate control signal SRCS. Specifically, in a state where the pulse width of the first clock signal CLK1 is relatively small, the power consumption of the data driver 800 may be substantially reduced as the value of the slew rate control signal SRCS increases . Therefore, as the slew rate of the data signal DS decreases, the power consumption of the data driver 800 may decrease. Therefore, when the image pattern is the white pattern and the pulse width of the first clock signal CLK1 is relatively small, as the slew rate of the data signal DS decreases, the heat of the data driver 800 Can be reduced.

According to the present embodiment, the image pattern of the image data DATA is analyzed and the pulse width of the first clock signal CLK1 provided to the data driver 800 is controlled according to the image pattern. Also, the slew rate of the data signal DS is controlled according to the image pattern. Therefore, the charge sharing time of the data line DL can be adaptively adjusted to the image pattern, the data signal DL can be charged to the data line DL adaptively to the image pattern, The power consumption and heat generation of the data driver 800 can be reduced.

Example  3

15 is a circuit diagram showing a display panel and a data driver according to another embodiment of the present invention.

The display panel 1100 and the data driver 1200 of FIG. 15 according to the present embodiment may be included in the display device 100 of FIG. 1, and the display panel 1100 and the data driver 1200 The display device including the data driver 1200 is substantially the same as the display device 100 of FIG. 1 except for the data driver 1200. Therefore, the same members as those in Fig. 1 are denoted by the same reference numerals, and redundant detailed explanations can be omitted.

15, the display panel 1100 may be substantially the same as the display panel 200 of FIG. 1, and the display panel 1100 may include a panel load resistor 1111 and a panel load capacitor 1121, . The panel load resistor 1111 and the panel load capacitor 1121 may be formed on the data line DL.

The data driver 1200 includes a data driver IC 1210 and a charge sharing unit 1230.

The data driving integrated circuit 1210 includes an amplifier 1211 and a switch 1221. The amplifier 1211 receives the analog data ADATA and outputs a target voltage VTAR. The switch 1221 selectively connects the output terminal of the amplifier 1211 and the charge sharing capacitor 1231 charged in the charge sharing portion 1230 and charged with the first analog voltage QAVDD to the data line DL, Lt; / RTI > The switch 1211 may selectively connect the amplifier 1211 and the charge sharing capacitor 1231 to the data line DL in response to the first clock signal CLK1 shown in FIG.

The charge sharing unit 1230 includes the charge sharing capacitor 1231. The charge sharing capacitor 1231 includes one end connected selectively to the data line DL by the switch 1221 and the other end connected to a terminal to which a second analog voltage HAVDD is applied. The second analog voltage HAVDD may be half of the first analog voltage QAVDD and the second analog voltage HAVDD may be provided from the voltage supplier 600 of FIG.

FIG. 16 is a flowchart showing a display panel driving method performed by the display panel driving apparatus including the data driver 1200 of FIG.

Referring to FIGS. 15 and 16, the data line DL is charged with the target voltage VTAR (step S310). Specifically, the data line DL is charged to the target voltage VTAR in response to deactivation of the first clock signal CLK1.

The current charged in the panel load capacitor 1121 is shared by the charge sharing capacitor 1231 by the target voltage VTAR to charge the charge sharing capacitor 1231 with the first analog voltage QAVDD Step S320). Here, the first analog voltage (QAVDD) may vary according to the target voltage (VTAR) charged in the data line (DL). The step of sharing the current charged in the panel load capacitor 1121 with the charge sharing capacitor 1231 is repeated several times to charge the charge sharing capacitor 1231 with the first analog voltage QAVDD .

The pre-charge voltage is charged to the data line DL using the first analog voltage QAVDD (step S330). Specifically, in response to the activation of the first clock signal CLK1, the first analog voltage QAVDD is supplied to the data line DL during a time corresponding to the pulse width of the first clock signal CLK1 And is charged with the pre-charge voltage. The pulse width of the first clock signal CLK1 may be varied according to an image pattern and the pulse width of the first clock signal CLK1 may be varied according to the image pattern analysis of the timing controller 500 shown in FIG. Can be controlled by the control unit 521.

Step 310, step 320 and step S330 of FIG. 16 may be used in step S130, which is the step of charging the precharge voltage to the data line DL in response to activation of the first clock signal CLK1 of FIG. have. In addition, steps 310, 320, and 330 of FIG. 16 may be used in step S230, which is the step of charging the data line DL with the precharge voltage in response to the activation of the first clock signal CLK1 of FIG. .

According to the present embodiment, since the charge sharing unit 1230 included in the data driver 1200 includes only the charge sharing capacitor 1231, the structure of the charge sharing unit 1230 can be simplified, The manufacturing cost of the data driver 1200 including the charge sharing unit 1230 and the display device can be reduced.

Example  4

17 is a circuit diagram showing a display panel and a data driver according to another embodiment of the present invention.

The display panel 1300 and the data driver 1400 shown in FIG. 17 according to the present embodiment may be included in the display device 100 shown in FIG. 1, and the display panel 1300 and the data driver 1400 The display device including the data driver 1400 is substantially the same as the display device 100 of FIG. 1 except for the data driver 1400. Therefore, the same members as those in Fig. 1 are denoted by the same reference numerals, and redundant detailed explanations can be omitted.

17, the display panel 1300 may be substantially the same as the display panel 200 of FIG. 1, and the display panel 1300 may include a first panel load resistor 1311, A capacitor 1321, a second panel load resistor 1312 and a second panel load capacitor 1322. The first panel load resistor 1311 and the first panel load capacitor 1321 may be formed on the first data line DL1 of the data line DL and the second panel load resistor 1312 and the first panel load capacitor 1321 may be formed on the first data line DL1. The second panel load capacitor 1322 may be formed on the second data line DL2 of the data lines DL.

The data driver 1400 includes a data driver IC 1410 and a charge sharing unit 1430.

The data driving integrated circuit 1410 includes a first amplifier 1411, a first switch 1421, a second amplifier 1412, and a second switch 1422.

The first amplifier 1411 receives the first analog data ADATA1 and outputs a first target voltage VTAR1. The first switch 1421 selectively connects the output terminal of the first amplifier 1411 and the first charge sharing capacitor 1431 included in the charge sharing part 1430 and charged with the first analog voltage QAVDD And connects to the first data line DL1. The first switch 1421 selectively connects the first amplifier 1411 and the first charge sharing capacitor 1431 to the first data line 1431 in response to the first clock signal CLK1 shown in FIG. DL1.

The second amplifier 1412 receives the second analog data ADATA2 and outputs a second target voltage VTAR2. The second switch 1422 selectively connects the output terminal of the second amplifier 1412 and the second charge sharing capacitor 1432 included in the charge sharing unit 1430 and charged with the first analog voltage QAVDD, To the second data line DL2. The second switch 1422 selectively connects the second amplifier 1412 and the second charge sharing capacitor 1432 to the second data line (not shown) in response to the first clock signal CLK1 shown in FIG. DL2.

The charge sharing portion 1430 includes the first charge sharing capacitor 1431 and the second charge sharing capacitor 1432. The first charge sharing capacitor 1431 includes one end connected selectively to the first data line DL1 by the first switch 1421 and the other end connected to a terminal to which a second analog voltage HAVDD is applied do. The second analog voltage HAVDD may be half of the first analog voltage QAVDD. The second charge sharing capacitor 1432 includes one end connected selectively to the second data line DL2 by the second switch 1422 and the other end connected to a terminal to which a ground voltage GND is applied.

The display panel driving method performed by the display panel driving apparatus including the data driving unit 1400 of Fig. 17 is substantially the same as that of the display panel driving method of Fig.

In detail, in response to the inactivation of the first clock signal CLK1, the first data line DL1 is charged with the first target voltage VTAR1 and the second data line DL2 is charged with the second target voltage VTAR1. (VTAR2).

Sharing the current charged in the first panel load capacitor 1321 by the first target voltage VTAR1 to the first charge sharing capacitor 1431 to couple the first charge sharing capacitor 1431 to the first analog charge sharing capacitor 1431, Charge with voltage (QAVDD). In response to the activation of the first clock signal CLK1, the first analog voltage QAVDD charged in the first charge sharing capacitor 1431 is used to set the pulse width of the first clock signal CLK1 to Charges the first pre-charge voltage to the first data line DL1 for a corresponding time.

The second charge sharing capacitor 1432 may be shared by the second charge sharing capacitor 1432 by sharing the current charged in the second panel load capacitor 1322 by the second target voltage VTAR2, 1 Charge with analog voltage (QAVDD). In response to activation of the first clock signal CLK1, the first analog voltage QAVDD charged in the second charge sharing capacitor 1432 is used to adjust the pulse width of the first clock signal CLK1 And charges the second data line DL2 with a second precharge voltage for a corresponding time.

The pulse width of the first clock signal CLK1 may be varied according to an image pattern and the pulse width of the first clock signal CLK1 may be varied according to the image pattern analysis of the timing controller 500 shown in FIG. Can be controlled by the control unit 521.

According to the present embodiment, since the charge sharing unit 1430 included in the data driver 1400 includes only the charge sharing capacitors 1431 and 1432, the structure of the charge sharing unit 1430 can be simplified And it is possible to reduce manufacturing cost of the data driver 1400 including the charge sharing part 1430 and the display device.

Example  5

18 is a circuit diagram showing a display panel and a data driver according to still another embodiment of the present invention.

The display panel 1300 and the data driver 1500 of FIG. 18 according to the present embodiment may be included in the display device 100 of FIG. 1 and the display panel 1300 and the data driver 1500 Is substantially the same as that of the display device 100 of FIG. 1 except for the data driver 1500. The display panel 1300 of Fig. 18 according to this embodiment is substantially the same as the display panel 1300 of Fig. The data driving integrated circuit 1410 included in the data driving unit 1500 of FIG. 18 according to the present embodiment is substantially the same as the data driving integrated circuit 1410 included in the data driving unit 1400 of FIG. same. 1 and 17 are denoted by the same reference numerals, and redundant detailed descriptions may be omitted.

The data driver 1500 includes the data driver IC 1410 and the charge sharing unit 1530.

The charge sharing portion 1530 includes the first charge sharing capacitor 1431, the second charge sharing capacitor 1432, and the third charge sharing capacitor 1433. The first charge sharing capacitor 1431 is connected to the one terminal of the first switch 1421 which is selectively connected to the first data line DL1 and the terminal to which the second analog voltage HAVDD is applied And the other end. The second charge sharing capacitor 1432 is connected between the second end of the second charge sharing capacitor 1432 and the second end of the other end connected to the terminal to which the ground voltage GND is applied, . The third charge sharing capacitor 1433 includes one end connected to the one end of the first charge sharing capacitor 1431 and the other end connected to the one end of the second charge sharing capacitor 1432.

The display panel drive method performed by the display panel drive apparatus including the data driver 1500 of FIG. 18 is substantially the same as the display panel drive method of FIG.

In detail, in response to the inactivation of the first clock signal CLK1, the first data line DL1 is charged with the first target voltage VTAR1 and the second data line DL2 is charged with the second target voltage VTAR1. (VTAR2).

Sharing the current charged in the first panel load capacitor 1321 by the first target voltage VTAR1 to the first charge sharing capacitor 1431 and the third charge sharing capacitor 1433, And charges the shared capacitor 1431 and the third charge sharing capacitor 1433 with the first analog voltage QAVDD. (QAVDD) charged in the first charge sharing capacitor (1431) and the third charge sharing capacitor (1433) in response to activation of the first clock signal (CLK1) Charges the first precharge voltage to the first data line DL1 for a time corresponding to the pulse width of the clock signal CLK1.

Also, the current charged in the second panel load capacitor 1322 is shared by the second charge sharing capacitor 1432 and the third charge sharing capacitor 1433 by the second target voltage VTAR2, 2 charge sharing capacitor 1432 and the third charge sharing capacitor 1433 with the first analog voltage QAVDD. (QAVDD) charged in the second charge sharing capacitor (1432) and the third charge sharing capacitor (1433) in response to activation of the first clock signal (CLK1) Charges the second precharge voltage to the second data line DL2 for a time corresponding to the pulse width of the clock signal CLK1.

According to the present embodiment, since the charge sharing unit 1530 included in the data driver 1500 includes only the charge sharing capacitors 1431, 1432, and 1433, the structure of the charge sharing unit 1530 can be simplified And it is possible to reduce manufacturing cost of the data driver 1500 including the charge sharing unit 1530 and the display device.

Example  6

19 is a circuit diagram showing a display panel and a data driver according to another embodiment of the present invention.

The display panel 1300 and the data driver 1600 shown in FIG. 19 according to the present embodiment may be included in the display device 100 shown in FIG. 1, and the display panel 1300 and the data driver 1600 The display device including the data driver 1600 is substantially the same as the display device 100 of FIG. 1 except for the data driver 1600. The display panel 1300 of FIG. 19 according to the present embodiment is substantially the same as the display panel 1300 of FIG. The data driving integrated circuit 1410 included in the data driving unit 1600 of FIG. 19 according to the present embodiment is substantially the same as the data driving integrated circuit 1410 included in the data driving unit 1400 of FIG. same. 1 and 17 are denoted by the same reference numerals, and redundant detailed descriptions may be omitted.

The data driver 1600 includes the data driving IC 1410 and the charge sharing unit 1630.

The charge sharing portion 1630 includes a charge sharing capacitor 1631. The charge sharing capacitor 1631 is connected to one end of the first data line DL1 by the first switch 1421 and the other end of the second data line DL2 by the second switch 1422, And the other end connected selectively.

The display panel driving method performed by the display panel driving apparatus including the data driving unit 1600 of Fig. 19 is substantially the same as that of the display panel driving method of Fig.

In detail, in response to the inactivation of the first clock signal CLK1, the first data line DL1 is charged with the first target voltage VTAR1 and the second data line DL2 is charged with the second target voltage VTAR1. (VTAR2).

Sharing the current charged in the first panel load capacitor 1321 by the first target voltage VTAR1 to the charge sharing capacitor 1631 to convert the charge sharing capacitor 1631 into the first analog voltage QAVDD, . In response to activation of the first clock signal (CLK1), the first analog voltage (QAVDD) charged in the charge sharing capacitor (1631) Charge the first pre-charge voltage to the first data line DL1.

Sharing the current charged in the second panel load capacitor 1322 by the second target voltage VTAR2 to the charge sharing capacitor 1631 to convert the charge sharing capacitor 1631 to the first analog voltage QAVDD). In response to activation of the first clock signal (CLK1), the first analog voltage (QAVDD) charged in the charge sharing capacitor (1631) Charge the second pre-charge voltage to the second data line DL2.

According to the present embodiment, since the charge sharing unit 1630 included in the data driver 1600 includes only the charge sharing capacitor 1631, the structure of the charge sharing unit 1630 can be simplified, The manufacturing cost of the data driver 1600 including the charge sharing portion 1630 and the display device can be reduced.

As described above, according to the display panel driving method, the display panel driving apparatus for performing the same, and the display apparatus including the display panel driving apparatus, the image pattern of the image data is analyzed, and the clock signal In accordance with the image pattern. Therefore, the charge sharing time of the data line can be adaptively adjusted to the image pattern, and the data signal can be charged to the data line adaptively to the image pattern, thereby reducing power consumption and heat generation of the data driver Can be reduced.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the present invention as defined by the following claims. You will understand.

100, 700: Display device
200, 1100, 1300: display panel
300, 800, 1200, 1400, 1500, and 1600:
400: Gate driver 500, 900: Timing controller
600: voltage supplier 510: memory
520, and 920: clock generating units 521 and 921: image pattern analyzing unit
523, 923: first clock signal generator 525: second clock signal generator
530: Data start signal generator 540: Gate start signal generator
310: shift register 320: serial /
330: latch 340: polarity control unit
350: Digital / analog conversion section
360, 860, 1230, 1430, 1530, 1630:
Data driving integrated circuits: 1210 and 1410

Claims (20)

Analyzing an image pattern of the image data and outputting a clock control signal; And
And controlling a pulse width of a clock signal provided to a data driver for driving a data line of the display panel in response to the clock control signal. The method according to claim 1,
And charging the pre-charge voltage to the data line in response to activation of the clock signal. 3. The method of claim 2, wherein when the clock signal has a first pulse width, the data line is charged with the precharge voltage for a first time corresponding to the first pulse width, Wherein the data line is charged with the precharge voltage for a second time corresponding to the second pulse width when the data line has a second pulse width greater than the first pulse width. The method of claim 2, wherein when the clock signal has a first pulse width, the data line is charged with a first precharge voltage, and if the clock signal has a second pulse width greater than the first pulse width, Line is charged with a second pre-charge voltage that is higher than the first pre-charge voltage. 3. The method of claim 2,
Further comprising charging the data line to a target voltage in response to deactivation of the clock signal. 6. The method of claim 5, wherein charging the data line with the pre-
Charging the data line with the target voltage;
Sharing the charge capacitor in the load capacitor of the display panel with the charge sharing capacitor by the target voltage to charge the charge sharing capacitor with the analog voltage; And
And charging the data line with the pre-charge voltage using the analog voltage. 2. The method of claim 1, wherein controlling the pulse width of the clock signal comprises:
Decreasing a pulse width of the clock signal when the image pattern is a black image or a white image; And
And increasing the pulse width of the clock signal when the image pattern is a stripe pattern in which black and white are alternately displayed. The method according to claim 1,
Further comprising the step of analyzing the image pattern of the image data to output a slew rate control signal for controlling a slew rate of a data signal applied to the data line. 9. The method of claim 8,
Charging the data line with a precharge voltage in response to activation of the clock signal; And
And charging the data line to a target voltage based on the slew rate control signal in response to deactivation of the clock signal. An image pattern analyzer for analyzing an image pattern of image data and outputting a clock control signal;
A clock signal generator for outputting a clock signal whose pulse width is controlled in response to the clock control signal; And
And a data driver for driving a data line of the display panel in response to the clock signal. 11. The display panel drive device according to claim 10, wherein the data driver charges the data line in response to activation of the clock signal. 12. The method of claim 11, wherein when the clock signal has a first pulse width, the data line is charged with the precharge voltage for a first time corresponding to the first pulse width, Wherein the data line is charged with the precharge voltage for a second time corresponding to the second pulse width when the data line has a second pulse width greater than the first pulse width. 12. The display panel drive apparatus according to claim 11, wherein the data driver charges the data line to a target voltage in response to deactivation of the clock signal. 14. The data driving circuit according to claim 13, wherein the data driver includes a charge sharing unit charging the data line with the precharge voltage and a data driving integrated circuit charging the data line with the target voltage,
Wherein the charge sharing unit includes a charge sharing capacitor charged with an analog voltage by sharing a current charged in a load capacitor of the display panel by the target voltage,
Wherein the data driving integrated circuit includes an amplifier for outputting the target voltage and a switch for selectively connecting the amplifier and the charge sharing capacitor to the data line of the display panel. 15. The display device of claim 14, wherein the charge sharing portion includes a first charge sharing capacitor selectively coupled to a first data line of the data line and a second charge sharing capacitor selectively coupled to a second data line of the data line ,
The data driving IC includes a first amplifier for outputting a first target voltage to the first data line, a second amplifier for outputting a second target voltage to the second data line, a second amplifier for outputting a second target voltage to the first data line, A first switch for selectively connecting the charge sharing capacitor to the first data line and a second switch for selectively connecting the second amplifier and the second charge sharing capacitor to the second data line. The display panel driving apparatus comprising: 16. The device of claim 15, wherein the charge sharing portion comprises a third charge coupled to the first charge sharing capacitor and the second charge sharing capacitor and selectively coupled to the first data line and selectively coupled to the second data line Further comprising a shared capacitor. 15. The display panel drive apparatus of claim 14, wherein the charge sharing capacitor is selectively connected to a first data line of the data line and selectively connected to a second data line of the second data line. The method of claim 10, wherein the clock signal generator reduces a pulse width of the clock signal when the image pattern is a black image or a white image, and when the image pattern is a stripe pattern in which black and white alternately appear, And the pulse width is increased. The apparatus of claim 10, wherein the image pattern analyzing unit analyzes the image pattern of the image data and further outputs a slew rate control signal for controlling a slew rate of a data signal applied to the data driver The display panel driving apparatus comprising: A display panel for receiving a data signal based on image data and displaying the image; An image pattern analyzing unit for analyzing an image pattern of the image data and outputting a clock control signal, a clock signal generator for outputting a clock signal whose pulse width is controlled in response to the clock control signal, And a data driver for driving a data line of the display panel.

Images