KR20140122346A - Analog digital converter, image sensor comprising this, and device comprising the image sensor - Google Patents

Abstract

The present invention relates to an analog digital converter, an image sensor including the same, and a device including the image sensor. The analog digital converter includes: a signal processing unit which generates an operational amplification output voltage by responding to an input voltage and a DAC output voltage in a sigma-delta operation section and generates the operational amplification output voltage by responding to the DAC output voltage and the operational amplification output voltage which are fed back in a cyclic operation section; a control unit which determines the number of upper level M bits by comparing the input voltage with first and second light reference voltages in a light intensity detection operating section, generates a DAC control signal and obtains data of the upper level M bits by comparing the operational amplification output voltage with a first reference voltage in the sigma-delta operation section, and generates the DAC control signal and obtains data of lower level N bits by comparing the operational amplification output voltage with second and third reference voltages in the cyclic operation section; and a digital analog converting unit which generates the DAC output voltage by responding to the DAC control signal.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog-to-digital converter, an image sensor having the analog-to-digital converter, and an image sensor having the image sensor.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor design technique, and more particularly, to an apparatus having an analog-to-digital converter, an image sensor having the analog-to-digital converter, and an image sensor.

An electronic system such as a video or biosensor system generally includes an analogue digital converter (ADC) for each column to read a large amount of data at high speed. 2. Description of the Related Art Recently, image sensors and communication technologies such as a CIS (CMOS IMAGE SENSOR) and a CCD (Charge Coupled Device) have been required to provide high-speed, high-resolution, and low power ADCs.

Commonly used ADCs include sigma-delta ADCs and cyclic ADCs.

Sigma-delta ADCs have their own noise shaping (NoISe-ShapIng) characteristics, making them suitable for use as high-resolution ADCs. However, since a sigma-delta ADC requires a large number of clocks to operate, in order for the sigma-delta ADC to operate at high speed, the operational amplifier constituting the integrator in the sigma-delta ADC must operate at high speed. As a result, implementing a sigma-delta ADC to operate at high speed increases power consumption. The sigma-delta ADC also has the disadvantage that the larger the number of clocks required, the larger the internal circuit area occupies.

The number of clocks required to implement the same resolution is smaller than that of a sigma-delta ADC. Therefore, it is easy to implement an ADC operating at high speed. However, a cyclic ADC requires a sampling capacitor with a large capacitance to reduce the influence of thermal noise generated during sampling. Therefore, the cyclic ADC requires not only a large area but also an increase in power consumption. In addition, in order to realize a high resolution ADC, a cyclic ADC requires an operational amplifier having a large gain.

An embodiment of the present invention provides an analog-to-digital converter capable of performing high-speed, low-area, low-power, high-resolution analog-to-digital conversion operations.

Another embodiment of the present invention provides an image sensor comprising the analog-to-digital converter.

Another embodiment of the present invention provides an apparatus comprising an image sensor comprising the analog-to-digital converter.

The analog-to-digital converter according to an embodiment of the present invention generates an operational amplification output voltage in response to an input voltage and a DAC output voltage in a sigma-delta operation period, and outputs the operational amplification output voltage and the DAC A signal processing unit for generating the operational amplification output voltage in response to an output voltage; And a comparator for comparing the input voltage with the first and second light reference voltages to determine the number of high-order M bits in the light intensity detecting operation period, and comparing the operational amplification output voltage with the first reference voltage in the sigma- And the DAC control signal is generated and the data of the upper M bits is obtained. In the cyclic operation period, the DAC control signal is generated by comparing the operational amplification output voltage with the second and third reference voltages, A control unit for acquiring data; And a digital to analog converter that generates the DAC output voltage in response to the DAC control signal.

According to another aspect of the present invention, there is provided an image sensor including: a pixel unit having at least one pixel for outputting an analog signal according to light input from the outside; And at least one analog digital converter for converting the analog signal into a digital signal, wherein the at least one analog digital converter is responsive to an input voltage and a DAC output voltage in a sigma- A signal processing unit for generating an operational amplification output voltage and generating the operational amplification output voltage in response to the operational amplification output voltage and the DAC output voltage fed back in the cyclic operation period; And a comparator for comparing the input voltage with the first and second light reference voltages to determine the number of high-order M bits in the light intensity detecting operation period, and comparing the operational amplification output voltage with the first reference voltage in the sigma- And the DAC control signal is generated and the data of the upper M bits is obtained. In the cyclic operation period, the DAC control signal is generated by comparing the operational amplification output voltage with the second and third reference voltages, A control unit for acquiring data; And a digital to analog converter that generates the DAC output voltage in response to the DAC control signal.

According to another embodiment of the present invention, there is provided an apparatus comprising: an image sensor as disclosed in another embodiment of the present invention; an optical unit for collecting light input from the outside and transmitting the collected light to the pixel unit; And a data processing unit for inputting and processing or storing the digital signal.

The ADC of the present invention initially operates as a sigma-delta ADC, and thereafter includes a single circuit that operates as a cyclic ADC, thereby reducing the area required to implement the ADC, reducing the consumed power, Not only can the output result be obtained, but also the operation speed and accuracy can be increased.

Further, the number of bits of the digital signal generated when the digital-analog converter operates as a sigma-delta ADC is controlled according to the intensity of the input light, thereby minimizing the amount of current consumed.

1 is a block diagram of an image sensor 1 having an ADC of the present invention.
2 is a block diagram of the analog-to-digital converter 30 of the image sensor 1 of the present invention shown in Fig.
3 is a diagram showing a configuration of the ADC conversion circuit 100 of the present invention shown in Fig.
4 is a diagram for explaining the operation of the ADC conversion circuit 100 of the present invention shown in Fig. 3 in the light intensity detection operation period.
FIG. 5 is a diagram for explaining the operation of the ADC conversion circuit 100 of the present invention shown in FIG. 3 in the sampling operation period of the sigma-delta ADC operation period.
6 is a diagram for explaining the operation of the ADC conversion circuit 100 of the present invention shown in FIG. 3 in the integral operation period of the sigma-delta ADC operation period.
FIG. 7 is a view for explaining the operation of the ADC conversion circuit 100 of the present invention shown in FIG. 3 in a ground voltage sampling operation period during a sigma-delta ADC operation period.
8 is a diagram for explaining the operation of the ADC conversion circuit 100 of the present invention shown in Fig. 3 in the sampling operation period during the operation period of the cyclic ADC.
FIG. 9 is a diagram for explaining the operation of the ADC conversion circuit 100 of the present invention shown in FIG. 3 in the amplification operation period during the cyclic ADC operation period.
Fig. 10 is a diagram showing the configuration of an embodiment of the apparatus 4 including the image sensor of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, it is to be understood that the present invention is not limited to the disclosed embodiments, but may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein, Is provided to fully inform the user.

1 is a block diagram of an image sensor 1 having an ADC of the present invention.

The image sensor 1 of the present invention may include a row driver 10, a pixel unit 20, an interrelated double sampling unit 40, and an analog-to-digital conversion unit 30.

The function of each of the blocks shown in FIG. 1 will be described as follows.

The row driver 10 outputs row driving signals RD1, RD2, ..., RD (I) for driving the pixels constituting the selected row of the pixel portion 20. [ The row driver 10 may activate one of the row driving signals RD1, RD2, ..., RD (I) in response to a row address input from the outside, RD2, ..., RD (I) sequentially in response to the row driving signals RD1, RD2, ..., RD (I).

The pixel unit 20 outputs a plurality of analog signals I1, I2, ..., I (j) in response to the row driving signals RD1, RD2, ..., RD (I). The pixel unit 20 may include a plurality of pixels (not shown) arranged in a matrix form. Each of the plurality of pixels (not shown) senses light using an optical device and outputs an electrical signal corresponding to the sensed light to one of a plurality of analog signals I1, I2, ..., I (j) Can be output. At this time, the pixels constituting one row of the plurality of pixels may be activated in response to the corresponding row driving signal among the row driving signals RD1, RD2, ..., RD (I).

The correlated double sampling unit 40 calculates a difference between an initial value of the analog signals I1, I2, ..., I (j) output from the pixel unit 20 and a value corresponding to the sensed light To the analog-to-digital conversion unit 30, a plurality of generated analog sampling signals S1, S2, ..., S (j) That is, the correlated double sampling unit 40 compares the initial values of the analog signals I1, I2, ..., I (j) outputted when no light is sensed in the pixel unit 20, (I1, I2, ..., I (j)) by detecting the difference between the values of the analog signals I1, I2, ..., I S2, ..., S (j) included in the input analog signals I (j), I (j) to the analog-digital converter 30.

The analog-to-digital converter 30 receives a plurality of analog sampling signals S1, S2, ..., S (j) and generates a plurality of analog sampling signals S1, S2, D2, ..., D (j) corresponding to each of the plurality of digital signals D1, D2, ..., D). The analog-to-digital converter 30 may include j ADCs for inputting each of a plurality of analog sampling signals S1, S2, ..., S (j). That is, the analog-to-digital conversion unit 30 may include a plurality of ADCs provided for each column of the pixel unit 20. ., D (j (j)), respectively, in the analog-to-digital conversion section 30. The analog-digital conversion section 30 converts a plurality of analog sampling signals S1, S2, (D1, D2, ..., S (j)) converted in accordance with information on the intensity of light included in the plurality of analog sampling signals S1, S2, ..., S ..., D (j) are adjusted. For example, as the intensity of light sensed by the pixel unit 20 increases, that is, the initial value of the analog signals I1, I2, ..., I (j) (J)) corresponding to the plurality of analog sampling signals S1, S2, ..., S (j) as the difference between the values of the signals I1, I2, ..., I The number of upper bits of the digital signals D1, D2, ..., D (j) is relatively reduced. Conversely, the smaller the intensity of the light sensed by the pixel unit 20 is, that is, the initial value of the analog signals I1, I2, ..., I (j) S2, ..., S (j)) as the difference between the values of the analog signals I1, I2, ..., I (j) The number of upper bits of the plurality of digital signals D1, D2, ..., D (j) to be converted respectively increases relatively.

2 is a block diagram of the analog-to-digital converter 30 of the image sensor 1 of the present invention shown in Fig.

Referring to FIG. 2, the analog-to-digital converter 30 may include a plurality of ADCs (for example, j ADCs), as illustrated in FIG. 1, May be configured the same as the ADC 30-k of the present invention. The ADC 30-k of the present invention may include an ADC conversion circuit 100 and a digital operation unit 200. The ADC conversion circuit 100 may include a sigma-delta ADC controller 110 and a cyclic ADC controller 120 ).

Functions of the blocks shown in FIG. 2 will be described as follows.

The ADC conversion circuit 100 receives a corresponding analog sampling signal S (k) among the analog sampling signals S1, S2, ..., S (j) and performs a sigma- (M_MS) of the upper M bits of the digital signal D (k) corresponding to the sampling signal S (k) and performs the cyclic ADC operation to obtain the lower N bits of the digital signal D (k) (N_LS). Therefore, the ADC conversion circuit 100 includes a sigma-delta ADC controller 110 for obtaining and outputting upper M bits of data M_MS and a cyclic ADC controller 120 for obtaining and outputting lower N bits of data N_LS Respectively. At this time, the number of M's in the upper M-bit data (M_MS) generated by the sigma-delta ADC controller 110 included in the ADC conversion circuit 100 corresponds to the intensity of the light included in the analog sampling signal S (k) It depends on the information. For example, when the intensity of the light included in the analog sampling signal S (k) is relatively large, it is assumed that the number of M's is M3 in the M-bit data M_MS corresponding to the intensity of the light, and the analog sampling signal S (M_MS) corresponding to the case where the intensity of the light included in the analog sampling signal S (k) is relatively moderate is assumed to be M2, and the intensity of the light included in the analog sampling signal S The number of M 1 is larger than the number of M 2, and the number of M 2 is larger than the number of M 3, assuming that the number of M is M in the corresponding M-bit data (M_MS).

The digital operation unit 200 receives the upper M bits of data M_MS and the lower N bits of data N_LS to output the digital signal D (k). The digital signal D (k) may be an M + N bit signal. In addition, the digital arithmetic unit 200 may perform an arithmetic operation to compensate for an error due to an offset of a comparator (not shown) in the ADC conversion circuit 100. For example, the digital arithmetic unit 200 receives the upper M bits of data (M_MS) and the lower N bits of data (N_LS), and the upper M bits are M + N-1 And the lower N bits of the first digital data (M_MS (M) M_MS (M-1) ... M_MS (1) 0 0 ... 0) 1) -th bit of the second digital data (0 0 ... 0 N_LS (N) N_LS (N-1) ... N_LS (1)), It is possible to output the + N-bit digital signal D (k). Here, M_MS (M), M_MS (M-1), ..., M_MS (1) represent the respective bits of the upper M-bit data M_MS, and N_LS (N), N_LS ..., and N_LS (1) represent the respective bits of the data N_LS of the lower N bits. As a result, the lower (N-1) -bit data of the M + N-bit digital signal D (k) is the lower (N-1) (M + 1) bits of the M + N-bit digital signal D (k) are the same as the data of the upper M bits (M_MS) And the most significant bit data N_LS (N) of N-bit data N_LS.

The number of bits to be converted for each of the plurality of digital signals D1, D2, ..., D (j) generated by the analog-to-digital converter 30 according to the embodiment of the present invention is The reason for the elasticity adjustment is that a plurality of analog signals I1, I2, ..., I (j) output from the pixel unit 20 as the intensity of light sensed by the pixel unit 20 increases, (Shot noiSe) included in the quantization noise (Shot noiSe) included in the quantization noise (Shot noiSe) included in the quantization noise is increased, . That is, the plurality of digital signals D1, D2, ..., D (j) generated by the analog-to-digital converter 30 corresponding to the relatively large intensity of the light sensed by the pixel unit 20, Even if the number of bits to be converted is reduced, the quality is not different from the result of not decreasing the number of bits. Accordingly, in the present invention, an operation of adjusting the number of bits to be converted for each of the plurality of digital signals D1, D2, ..., D (j) according to the intensity of light sensed by the pixel unit 20 The configuration of the analog-to-digital converter 30, which can greatly reduce the amount of current consumed in the conversion process while maintaining the quality of the digital signals D1, D2, ..., D (j) do.

3 is a diagram showing a configuration of the ADC conversion circuit 100 of the present invention shown in Fig.

The ADC conversion circuit 100 may include a signal processing unit 102, a control unit 104 and a digital analog converter (DAC) In Fig. 3, VIN represents the input voltage of the analog sampling signal S (k) input to the ADC 30-k.

The signal processing section 102 includes switches S1, S2, S3, S4, S5, S9, S13 and S14, a sampling capacitor C1, a first feedback capacitor C2, a second feedback capacitor C3, An amplifier OP may be provided. A ground voltage is connected to a first input terminal (for example, a non-inverting input terminal) of the operational amplifier OP. The switch S1 is connected between a terminal to which the input voltage VIN is input and an output terminal of the DAC 104, and is turned on and off in response to the first control signal PHI1_SD. One side of the sampling capacitor Cl is connected to the output node of the DAC 106. [ The switch S2 is connected between the other side of the sampling capacitor C1 and the ground voltage, and is turned on and off in response to the second control signal PHI1. The switch S3 is connected between the output terminal of the DAC 106 and the output terminal of the operational amplifier OP and is turned on and off in response to the third control signal PHI1_CY. The switch S4 is connected between the other side of the sampling capacitor C1 and the second input terminal (for example, the inverting input terminal) of the operational amplifier OP and is turned on and off in response to the fourth control signal PHI2 . The first feedback capacitor C2 is connected between the second input terminal of the operational amplifier OP and the output terminal of the operational amplifier OP. One side of the switch S5 is connected to the second input terminal of the operational amplifier OP and turned on and off in response to the sigma-delta enable signal EN_SD. The second feedback capacitor C3 is connected between the other side of the switch S5 and the output terminal of the operational amplifier OP. The switch S9 is connected between the second input terminal of the operational amplifier OP and the output terminal of the operational amplifier OP and turned on and off in response to the reset signal rSt. The switch S13 is connected between the output node of the DAC 106 and the input node of the control unit 104 and is turned on and off in response to the light detection signal LG_DEC. The switch S14 is connected between the output terminal of the operational amplifier OP and the input node of the control unit 104 and is turned on and off in response to the light detection signal LG_DEC. The sampling capacitor C1, the first feedback capacitor C2, and the second feedback capacitor C3 may have the same capacitance.

The control unit 104 includes switches S6, S7, S8, S15, S16 and S17, a first comparator CP1, a second comparator CP2, a sigma-delta ADC controller 110, a cyclic ADC controller 120 ), And a control signal generator 130, as shown in FIG. The first input terminal of the first comparator CP1 is connected to the other terminal of the switches S13 and S14 of the signal processing unit 102. [ The switch S6 is connected between the ground voltage and the second input terminal of the first comparator CP1 and is turned on and off in response to the sigma-delta enable signal EN_SD. The switch S7 is connected between the first reference voltage VREF / 4 and the second input terminal of the first comparator CP1 and turned on and off in response to the cyclic enable signal EN_CY. The switch S17 is connected between the first light reference voltage VKNEE1 and the second input terminal of the first comparator CP1 and turned on and off in response to the light detection signal LG_DEC. The switch S8 is connected between the other end of the switches S13 and S14 and the first input terminal of the second comparator CP2 and is turned on in response to the cyclic enable signal EN_CY or the light detection signal LG_DEC. Off. The switch S15 is connected between the second reference voltage -VREF / 4 and the second input terminal of the second comparator CP2, and is turned on and off in response to the cyclic enable signal EN_CY. The switch S16 is connected between the second light reference voltage VKNEE2 and the second input terminal of the second comparator CP2 and is turned on and off in response to the light detection signal LG_DEC.

The DAC 106 may include switches S10, S11, and S12. The switch S10 is connected between the third reference voltage (-VREF) and the DAC output node, and is turned on and off in response to the first DAC control signal PHI_L. The switch S11 is connected between the ground voltage and the DAC output node, and is turned on and off in response to the second DAC control signal PHI_M. The switch S12 is connected between the fourth reference voltage VREF and the DAC output node, and is turned on and off in response to the third DAC control signal PHI_H.

The third reference voltage -VREF may be four times the second reference voltage -VREF / 4, and the fourth reference voltage VREF may be four times the first reference voltage VREF / 4. The magnitude of the third reference voltage -VREF and the fourth reference voltage VREF may be determined by the magnitude of the input voltage VIN that can be input. For example, the magnitude of the third reference voltage -VREF and the fourth reference voltage VREF may be the maximum value of the input voltage VIN that can be input.

The magnitude of the first light reference voltage VKNEE1 is smaller than the magnitude of the second light reference voltage VKNEE2. In addition, the magnitude of the first light reference voltage VKNEE1 and the magnitude of the second light reference voltage VKNEE2 may be determined by the magnitude of the input voltage VIN, respectively. For example, based on the information about the intensity of light included in the analog sampling signal S (k) applied as the input voltage VIN, the magnitude of the first light reference voltage VKNEE1 and the second light reference voltage VKNEE2 can be determined, respectively.

The function of each of the blocks shown in FIG. 3 will be described as follows.

The signal processing unit 102 operates to transmit the input voltage VIN directly to the control unit 104 during a light intensity detection operation period. In the sigma-delta ADC operating period, an operational amplifier output voltage OP_OUT is generated in response to the input voltage VIN and the DAC output voltage DAC_OUT. In the cyclic ADC operation period, the operational amplifier output voltage OP_OUT is generated in response to the feedback operational amplifier output voltage OP_OUT and the DAC output voltage DAC_OUT.

The control unit 104 compares the input voltage VIN with the first light reference voltage VKNEE1 and the second light reference voltage VKNEE2 in the light intensity detection operation period and outputs the comparison result to the sigma-delta ADC controller 110 (M_MS) of the upper M bits processed in the M-bit data. In the sigma-delta ADC operation period, the output voltage OP_OUT of the operational amplifier OP is compared with the ground voltage, the first to third DAC control signals PHI_L, PHI_M and PHI_H are output according to the comparison result, And obtains M-bit data (M_MS). The control unit 104 compares the output voltage OP_OUT of the operational amplifier OP with the first and second reference voltages VREF / 4 and -VREF / 4 in the cyclic ADC operation period, Outputs the first to third DAC control signals PHI_L, PHI_M, and PHI_H, and obtains the lower N bits of data N_LS. Also, the control unit 104 may output the control signals CON. The control signals CON are supplied to the first to fourth control signals PHI1_SD, PHI1, PHI1_CY, and PHI2, the light detection signal LG_DEC, the reset signal rSt, the sigma-delta enable signal EN_SD, And a click enable signal EN_CY. In this case, the control unit 104 may output the control signals CON in response to a clock signal applied from the outside.

The first comparator CP1 compares the input voltage VIN with the first light reference voltage VKNEE1 to output the first comparator output signal CP1_OUT in the light intensity detecting operation period and outputs the first comparator output signal CP1_OUT in the sigma- The first comparator output signal CP1_OUT is compared by comparing the ground voltage and the operational amplifier output voltage OP_OUT and the first reference voltage VREF / 4 is compared with the operational amplifier output voltage OP_OUT during the cyclic ADC operation period. And outputs the first comparator output signal CP1_OUT. The second comparator CP2 compares the input voltage VIN with the second light reference voltage VKNEE2 to output the second comparator output signal CP2_OUT in the light intensity detecting operation period, 2-VREF / 4 and the operational amplifier output voltage OP_OUT to output the second comparator output signal CP1_OUT. The second comparator CP2 may be inactivated during the sigma-delta ADC operating period.

The sigma-delta ADC controller 110 adjusts the number of M in the M-bit data (M_MS) in response to the first comparator output signal CP1_OUT and the second comparator output signal CP2_OUT in the light intensity detecting operation period And performs an operation. For example, since the input voltage VIN is smaller than the first light reference voltage VKNEE1 and the second light reference voltage VKNEE2, that is, the light intensity is relatively small, the first comparator output signal CP1_OUT and the When all of the two comparator output signals CP2_OUT are inactivated, the number of M's in the M-bit data (M_MS) is set to M1, which is a relatively large value. Further, since the input voltage VIN is larger than the first light reference voltage VKNEE1 but smaller than the second light reference voltage VKNEE2, that is, the light intensity is relatively normal, the first comparator output signal CP1_OUT Is activated and the second comparator output signal CP2_OUT is deactivated, in response to it sets the number of M's in the M-bit data (M_MS) to M2, which is a relatively normal value. In addition, since the input voltage VIN is larger than the first light reference voltage VKNEE1 and the second light reference voltage VKNEE2, that is, the light intensity is relatively large, the first comparator output signal CP1_OUT and the When the two comparator output signals CP2_OUT are all activated, the number of M's in the M-bit data (M_MS) is set to M3, which is a relatively small value.

The sigma-delta ADC controller 110 generates a first digital signal DSD in response to a first comparator output signal CP1_OUT during a sigma-delta ADC operation period, acquires data M_MS of an upper M bits, do. At this time, the number of M in the data of the upper M bits (M_MS) is the number determined in the light intensity operation period. The sigma-delta ADC controller 110 generates a first digital signal DSD having a value of "-1" when the first comparator output signal CP1_OUT indicates that the operational amplifier output voltage OP_OUT is less than the ground voltage And generates a first digital signal DSD having a value of "1 " if the first comparator output signal CP1_OUT indicates that the operational amplifier output voltage OP_OUT is greater than or equal to the ground voltage. In addition, the sigma-delta ADC controller 110 may obtain the upper M bits of data (M_MS) using the sequentially generated first digital signal DSD. The sigma-delta ADC controller 110 may be activated during the sigma-delta ADC operating period and deactivated during the cyclic ADC operating period.

The cyclic ADC controller 120 generates the second digital signal DCY in response to the first comparator output signal CP1_OUT and the second comparator output signal CP2_OUT and obtains the lower N bits of data N_LS Output. The cyclic ADC controller 120 determines that the second comparator output signal CP2_OUT is less than the second reference voltage -VREF / 4, indicating that the operational amplifier output voltage OP_OUT is less than the second reference voltage- And the second comparator output signal CP2_OUT indicates that the operational amplifier output voltage OP_OUT is greater than or equal to the second reference voltage -VREF / 4 and the first comparator output signal CP1_OUT, Generates a second digital signal DCY having a value of "0 " when the output voltage of the operational amplifier is smaller than the first reference voltage VREF / 4, and outputs the first comparator output signal CP1_OUT to the operational amplifier output It can generate a second digital signal DCY having a value of "1 " if it indicates that the voltage OP_OUT is greater than or equal to the first reference voltage VREF / 4. In addition, the cyclic ADC controller 120 may obtain the lower N bits of data N_LS using the sequentially generated second digital signal DCY. The cyclic ADC controller 120 may be activated during the cyclic ADC operating period and deactivated during the sigma-delta ADC operating period.

The control signal generator 130 outputs the first to third DAC control signals PHI_L, PHI_M and PHI_H in response to the first digital signal DSD and the second digital signal DCY. The control signal generator 130 activates only the first DAC control signal PHI_L if the first digital signal DSD is "-1" and the third DAC control signal PHI_L when the first digital signal DSD is " PHI_H) can be activated and output. The control signal generator 130 activates only the first DAC control signal PHI_L when the second digital signal DCY is "-1" and the second DAC control signal PHI_L when the second digital signal DCY is " Only the signal PHI_M is activated and only the third DAC control signal PHI_H is activated when the second digital signal DCY is "1 ". In addition, the control signal generator 130 can activate and output only the second DAC control signal PHI_M in the sampling interval of the first clock cycle interval and the last clock cycle interval between the sigma-delta ADC operating points. The control signal generator 130 generates first to fourth control signals PHI1_SD, PHI1, PHI1_CY, PHI2, and a light detection signal LG_DEC ), A reset signal rSt, a sigma-delta enable signal EN_SD, and a cyclic enable signal EN_CY.

The DAC 106 outputs the DAC output voltage DAC_OUT to the DAC output terminal in response to the first to third DAC control signals PHI_L, PHI_M, and PHI_H. The DAC 106 outputs the third reference voltage -VREF to the DAC output voltage DAC_OUT when the first DAC control signal PHI_L is activated and the ground voltage to the DAC 106 when the second DAC control signal PHI_M is activated, And outputs the fourth reference voltage VREF to the DAC output when the third DAC control signal PHI_H is activated.

Figs. 4 to 8 are diagrams for explaining the operation of the ADC conversion circuit 100. Fig.

4 is a diagram for explaining the operation of the ADC conversion circuit 100 of the present invention shown in Fig. 3 in the light intensity detection operation period.

In the light intensity detection operation period, the first control signal PHI1_SD, the second control signal PHI1, and the light detection signal LG_DEC are activated. Therefore, only the switches S1, S2, S8, S13, S16, and S17 are turned on. At this time, the output terminal of the DAC 106 is in a floating state. As a result, the input voltage VIN is stored in the sampling capacitor C1 and simultaneously applied to the first comparator CP1 and the second comparator CP2. The first comparator CP1 compares the input voltage VIN with the level of the first light reference voltage VKNEE1. The second comparator CP2 compares the input voltage VIN with the level of the second light reference voltage VKNEE2. In the sigma-delta ADC controller 110, in response to the first comparator output signal CP1_OUT and the second comparator output signal CP2_OUT, the number of M's of the M-bit data (M_MS) output in the next sigma- . Specifically, in the sigma-delta ADC controller 110, since the input voltage VIN is smaller than the first light reference voltage VKNEE1 and the second light reference voltage VKNEE2, that is, the light intensity is relatively small , When the first comparator output signal CP1_OUT and the second comparator output signal CP2_OUT are both inactivated, the number of M's in the M-bit data M_MS is set to a relatively large value M1 in response thereto. Further, since the input voltage VIN is larger than the first light reference voltage VKNEE1 but smaller than the second light reference voltage VKNEE2, that is, the light intensity is relatively normal, the first comparator output signal CP1_OUT Is activated and the second comparator output signal CP2_OUT is deactivated, in response to it sets the number of M's in the M-bit data (M_MS) to M2, which is a relatively normal value. In addition, since the input voltage VIN is larger than the first light reference voltage VKNEE1 and the second light reference voltage VKNEE2, that is, the light intensity is relatively large, the first comparator output signal CP1_OUT and the When the two comparator output signals CP2_OUT are all activated, the number of M's in the M-bit data (M_MS) is set to M3, which is a relatively small value.

When the light intensity detection operation is completed through the above-described operation, the sigma-delta ADC controller 110 determines the number of M in the M-bit data (M_MS) to be generated in the sigma-delta ADC operation period. Followed by a sigma-delta ADC operation.

FIG. 5 is a diagram for explaining the operation of the ADC conversion circuit 100 of the present invention shown in FIG. 3 in the sampling operation period of the sigma-delta ADC operation period.

The first control signal PHI1_SD, the second control signal PHI1 and the sigma-delta enable signal EN_SD are activated and the light detection signal LG_DEC is inactivated during the sampling operation period of the sigma-delta ADC operation period . Therefore, only the switches S1, S2, S5, S6, and S14 are turned on. At this time, the output terminal of the DAC 106 is in a floating state. As a result, the input voltage VIN is stored in the sampling capacitor C1.

6 is a diagram for explaining the operation of the ADC conversion circuit 100 of the present invention shown in FIG. 3 in the integral operation period of the sigma-delta ADC operation period.

The fourth control signal PHI2 and the sigma-delta enable signal EN_SD are activated and the first and third DAC control signals PHI_L, PHI_M, and PHI_H are activated in the integration operation period of the sigma- One signal is activated, and the light detection signal LG_DEC is inactivated. Therefore, the switches S4, S5, S6, and S14 are turned on, and any one of the switches S10, S11, and S12 is turned on.

First, in the first integration operation period, the second control signal PHI_M of the first to third DAC control signals is activated. Accordingly, the charge charged in the sampling capacitor C1 in the sampling operation period of the sigma-delta ADC operation period is transferred to the first and second feedback capacitors C2 and C3. As a result, in the first integral operation period, charges corresponding to 1/2 of the input voltage VIN are accumulated in the first and second feedback capacitors C2 and C3, respectively, and the operational amplifier output voltage OP_OUT is input to the input Becomes half of the voltage VIN.

The first comparator CP1 compares the operational amplifier output voltage OP_OUT with the ground voltage to output the first comparator output signal CP1_OUT and the sigma-delta ADC controller 110 outputs the first comparator output signal CP1_OUT And generates a first digital signal DSD in response. In addition, the control signal generator 130 determines which one of the first to third DAC control signals PHI_L, PHI_M, and PHI_H is to be activated in the next clock cycle to the first digital signal DSD. The operation of selecting the DAC control signal to be activated is performed in the subsequent integration period in the same manner.

The fourth control signal PHI2 and the sigma-delta enable signal EN_SD are activated and the first and third DAC control signals < RTI ID = 0.0 > PHI_L, and PHI_H), the DAC control signal selected in the previous integration period is activated.

The operation when the third DAC control signal PHI_H is selected in the previous integration operation period after the first integration operation is terminated and the first DAC control signal PHI_L is selected in the previous integration operation period will be described below.

First, when the third DAC control signal PHI_H is selected in the previous integration operation period, only the switches S4, S5, S6, S12, and S14 are turned on. Charges corresponding to the input voltage VIN are stored in the sampling capacitor C1 in the immediately preceding sampling operation period. Therefore, in the integration period, the charge corresponding to the difference between the input voltage VIN and the fourth reference voltage VREF is accumulated in the first and second feedback capacitors C2 and C3.

The first and second feedback capacitors C2 and C3 may have the same capacitance. If the capacitance of the first feedback capacitor C2 and the capacitance of the second feedback capacitor C3 are equal to each other, then the input voltage VIN and the fourth reference voltage VREF are applied to the first and second feedback capacitors C2 and C3, ) Of the charge corresponding to the difference between the two charges.

If the first DAC control signal PHI_L is selected instead of the third DAC control signal PHI_H in the previous integration operation period, only the switches S4, S5, S6, S10, and S14 are turned on. In this case, in the integration period, the charge corresponding to the difference between the input voltage VIN and the third reference voltage -VREF is accumulated in the first and second feedback capacitors C2 and C3.

The first and second feedback capacitors C2 and C3 may have the same capacitance. If the capacitance of the first feedback capacitor C2 and the capacitance of the second feedback capacitor C3 are equal to each other, then the input voltage VIN and the third reference voltage (-) are applied to the first and second feedback capacitors C2 and C3, VREF) is accumulated.

The operational amplifier output voltage OP_OUT in the integral operation period of the sigma-delta ADC operation period can be expressed by Equation (1).

In Equation (1), VOUT2 is the output voltage of the operational amplifier OP in the current integration period, VOUT1 is the output voltage of the operational amplifier OP in the previous integration period, VIN is the voltage of the input signal, DSD Represents a first digital signal determined in a previous integration period.

FIG. 7 is a view for explaining the operation of the ADC conversion circuit 100 of the present invention shown in FIG. 3 in a ground voltage sampling operation period during a sigma-delta ADC operation period.

In the ground voltage sampling operation period, the second control signal PHI1, the sigma-delta enable signal EN_SD, and the second DAC control signal PHI_M are activated, and the light detection signal LG_DEC is inactivated. Accordingly, the switches S2, S5, S6, S11, and S14 are turned on. As a result, the sampling capacitor C1 is discharged.

Also, since the sampling capacitor C1 is discharged in the sampling period, the charge corresponding to the selected reference voltage among the third reference voltage (-VREF) or the fourth reference voltage (VREF) And accumulated in the second feedback capacitors C2 and C3. If the first and second feedback capacitors C2 and C3 have the same capacitance, the charge corresponding to one half of the selected reference voltage is accumulated in each of the first and second feedback capacitors C2 and C3.

During the sigma-delta ADC operation period, the ADC conversion circuit 100 performs the light intensity detection operation described with reference to FIG. 4, and then performs the sampling operation described with reference to FIG. 5 and the first integration operation described with reference to FIG. 5 once. Thereafter, the sampling operation described with reference to FIG. 5 and the integration operation after the first integration operation described with reference to FIG. 6 are repeated 2 ^ M-1 times. Lastly, the ground voltage sampling operation described in FIG. 7 and the integration operation after the first integration operation described in FIG. 6 are performed once. As a result, when the sigma-delta ADC operation region is completed, the charge corresponding to the voltage determined by Equation (2) is accumulated in each of the first and second feedback capacitors C2 and C3.

In Equation (2), each of DSD1, DSD2, ..., DSD (2 ^ M) represents a first digital signal (DSD) determined in an integration period.

As a result, each of the first and second feedback capacitors C2 and C3 is supplied with a voltage obtained by subtracting the voltage corresponding to the upper M-bit data M_MS obtained by the sigma-delta ADC controller 110 from the input voltage VIN Corresponding charges are accumulated.

Also, the sigma-delta ADC controller 110 obtains the upper M-bit data M_MS using DSD1, DSD2, ..., DSD (2 ^ M).

8 is a diagram for explaining the operation of the ADC conversion circuit 100 of the present invention shown in Fig. 3 in the sampling operation period during the operation period of the cyclic ADC.

In the sampling operation period of the cyclic ADC, the second control signal PHI1, the third control signal PHI1_CY, and the cyclic enable signal EN_CY are activated, and the light detection signal LG_DEC is inactivated. Therefore, only the switches S2, S3, S7, S8, S14, and S15 are turned on. Since the switch S5 is turned off, the second feedback capacitor C3 no longer affects the circuit. As a result, the operational amplifier output signal OP_OUT is stored in the sampling capacitor C1. At this time, the operational amplifier output signal OP_OUT has a voltage corresponding to the charge stored in the first feedback capacitor C2. In addition, the magnitude of the charge stored in the first feedback capacitor C2 does not change.

Also, in the first sampling period of the cyclic ADC, the first comparator CP1 compares the first reference voltage VREF / 4 with the operational amplifier output signal OP_OUT and outputs the first comparator output signal CP1_OUT , The second comparator CP2 compares the second reference voltage -VREF / 4 with the operational amplifier output signal OP_OUT and outputs the second comparator output signal CP2_OUT. The cyclic ADC controller 120 outputs the second digital signal DCY in response to the first and second comparator output signals CP1_OUT and CP2_OUT and the control signal generator 130 outputs the second digital signal DCY in response to the first and second comparator output signals CP1_OUT and CP2_OUT. And selectively activates one of the first to third DAC control signals PHI_L, PHI_M, and PHI_H in response.

FIG. 9 is a diagram for explaining the operation of the ADC conversion circuit 100 of the present invention shown in FIG. 3 in the amplification operation period during the cyclic ADC operation period.

The fourth control signal PHI2 and the cyclic enable signal EN_CY are activated and the light detection signal LG_DEC is inactivated and the first to third DAC control signals PHI_L, PHI_M, and PHI_H are activated. Therefore, the switches S4, S7, S8, S14, and S15 are ionized, and any one of the switches S10, S11, and S12 is turned on. The DAC 106 outputs the DAC output voltage DAC_OUT in response to the first to third DAC control signals PHI_L, PHI_M, and PHI_H. That is, in the DAC 106, any one of the first to third DAC control signals PHI_L, PHI_M, and PHI_H is activated to generate the third reference voltage -VREF, the ground voltage VSS, VREF to the DAC output voltage DAC_OUT.

At this time, the operational amplifier output voltage OP_OUT in the sampling operation period of the previous cyclic ADC is stored in the sampling capacitor C1. As a result, in the amplification period of the cyclic ADC, the operational amplifier output voltage OP_OUT and the selected reference voltage, that is, either the third reference voltage -VREF, the ground voltage VSS or the fourth reference voltage VREF The charge corresponding to the difference in voltage is accumulated in the first feedback capacitor C2.

The first and second comparators CP1 and CP2 compare the operational amplifier output voltage OP_OUT with the first and second reference voltages VREF / 4 and VREF / 4, respectively, (CP1_OUT and CP2_OUT). The cyclic ADC controller 120 generates a second digital signal DCY in response to the first and second comparator output signals CP1_OUT and CP2_OUT. The control signal generator 130 outputs the first to third DAC control signals PHI_L, PHI_M, and PHI_H in response to the second digital signal DCY. This will be easily understood with reference to FIG.

Accordingly, the operational amplifier output voltage OP_OUT in the amplification operation period of the cyclic ADC can be determined by Equation (3).

In Equation (3), VOUT2 represents the operational amplifier output voltage OP_OUT in the current amplification section, VOUT1 represents the operational amplifier output voltage OP_OUT in the immediately preceding amplification section, DCY represents the second digital signal Respectively.

The ADC conversion circuit 100 repeats the operations described in FIGS. 8 and 9 N-1 times. Also, the cyclic ADC controller 120 generates and outputs the lower N-bit data N_lS using N-1 second digital signals DCY generated in the first to (N-1) th amplifying operations. In this case, each of the N-1 second digital signals DCY may be 2-bit data, and the cyclic ADC controller 120 may control the p-th (where p is greater than or equal to 2 and less than N-1 (P-1) -th generated second digital signal DCY (p-1) using a second digital signal DCY (p) generated from the offset error compensated second digital signal DCY And extracts each bit data of the lower N bits of data (N_lS) from the signal.

The error correction circuit 200 receives the upper M bits of data M_MS and the lower N bits of data N_lS to output M + N bits of result data.

Although not shown, the ADC conversion circuit 100 of the present invention may additionally perform an operation of discharging the sampling capacitor C1 before the sampling operation. At this time, the sampling capacitor C1 can be discharged by turning on the switches S11 and S2 by activating the second DAC control signal PHI_M and the second control signal PHI1. This operation may be performed only in the cyclic ADC operation section, and may be performed in both the sigma-delta ADC operation section and the cyclic ADC operation section. Through this operation, the influence of noise can be minimized.

In addition, the ADC conversion circuit 100 of the present invention may additionally perform a reset operation in a period in which a first sampling operation is performed before a sigma-delta ADC operation period starts or during a sigma-delta ADC operation period. At this time, only the reset signal RST and the sigma-delta enable signal EN_SD are activated. Therefore, only the switches S5, S9, and S6 are turned on, and as a result, the reset operation is performed while the first and second feedback capacitors C2 and C3 are discharged.

Fig. 10 is a diagram showing the configuration of an embodiment of the apparatus 4 including the image sensor of the present invention.

An apparatus (4) comprising an image sensor of the present invention can include an image sensor (1), an optical section (2), and a data processing section (3).

The function of each of the blocks shown in FIG. 10 will be described below.

The optical unit 2 may be composed of various devices (not shown) for fixing a lens (not shown) and a lens (not shown), and collects light.

The image sensor 1 may have the same configuration as that shown in Figs. 1 to 9, and outputs a digital image signal D_data corresponding to the light lignt collected by the optical unit 2. [

The data processing unit 3 processes or stores the digital image data D_data. For example, the data processing unit 3 may input the digital image data D_data to perform an operation such as edge enhancement and / or noise reduction, And may store the digital image data or the processed image data.

The apparatus shown in Fig. 10 may be included in a digital camera, a cellular phone, or the like.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. Will be apparent to those of ordinary skill in the art.

For example, the logic gates and transistors illustrated in the above embodiments should be implemented in different positions and types according to the polarity of input signals.

1: image sensor 10: low driver
20: pixel unit 30: analog-digital conversion unit
40: correlated double sampling unit 100: ADC conversion circuit
110: sigma-delta ADC controller 120: cyclic ADC controller
200: digital operation unit 102: signal processing unit
104: control unit 106: digital-to-analog converter (DAC)

Claims (17)

In the sigma-delta operation period, the operational amplification output voltage is generated in response to the input voltage and the DAC output voltage. In the cyclic operation period, the operational amplification output voltage is generated in response to the operational amplification output voltage and the DAC output voltage ;
And a comparator for comparing the input voltage with the first and second light reference voltages to determine the number of high-order M bits in the light intensity detecting operation period, and comparing the operational amplification output voltage with the first reference voltage in the sigma- And the DAC control signal is generated and the data of the upper M bits is obtained. In the cyclic operation period, the DAC control signal is generated by comparing the operational amplification output voltage with the second and third reference voltages, A control unit for acquiring data; And
And a DAC output voltage responsive to the DAC control signal,
And an analog-to-digital converter.
The method according to claim 1,
Wherein the first reference voltage is a ground voltage, the second reference voltage is a voltage having a positive reference value, the third reference voltage is a voltage having a negative reference value, and the reference voltages of the first and second lights are positive reference values Is a voltage having a predetermined voltage.
3. The method of claim 2,
The digital-to-
And outputs a voltage having four times the second reference voltage or a voltage having four times the third reference voltage as the DAC output voltage.
3. The method of claim 2,
The digital-to-
And outputs a voltage having a double value of the second reference voltage or a voltage having a double value of the third reference voltage as the DAC output voltage.
The method according to claim 1,
The signal processing unit,
An operational amplifier having a first input terminal connected to the ground voltage terminal and outputting the operational amplification output voltage;
A first switch connected between a terminal to which the input voltage is applied and a DAC output terminal to which the DAC output voltage is applied;
A sampling capacitor having one side connected to the DAC output terminal;
A second switch connected between the other end of the sampling capacitor and the ground voltage terminal;
A third switch connected between the DAC output terminal and the output terminal of the operational amplifier;
A fourth switch connected between the other end of the sampling capacitor and the second input terminal of the operational amplifier;
A first feedback capacitor connected between a second input terminal of the operational amplifier and an output terminal of the operational amplifier;
A fifth switch having one side connected to a second input terminal of the operational amplifier;
A second feedback capacitor connected between the other side of the fifth switch and the output terminal of the operational amplifier;
A sixth switch having one side connected to an output terminal of the operational amplifier and the other side connected to an input terminal of the control unit; And
And a seventh switch having one side connected to the DAC output terminal and the other side connected to an input terminal of the control unit.
6. The method of claim 5,
The second switch is periodically turned on and off,
The fifth switch is on in the sigma-delta operation period and off in the cyclic operation period,
The fourth switch is periodically turned on and off, and is turned on and off as opposed to the second switch,
Wherein the first switch is turned on and off at the same timing as the fourth switch in the sigma-delta operation period and off in the cyclic operation period,
The third switch is turned on and off at the same timing as the fourth switch in the cyclic operation period and off in the sigma-delta operation period,
The sixth switch is off in the light intensity detection operation period and is turned on in the sigma-delta operation period and the cyclic operation period,
The seventh switch is turned on in the light intensity detecting operation section and is turned off in the sigma-delta operation section and the cyclic operation section,
Wherein the analog-to-
6. The method of claim 5,
The signal processing unit
Further comprising a reset switch connected between a second input terminal of the operational amplifier and an output terminal of the operational amplifier and turned on before the sigma-delta operation is performed.
The method according to claim 1,
Wherein,
A first comparator having an input terminal to which the input voltage or the operational amplification output voltage is applied is connected to a first input terminal;
A first switch connected between a terminal to which the first reference voltage is applied and a second input terminal of the first comparator;
A second switch connected between a terminal to which the second reference voltage is applied and a second input terminal of the first comparator;
A third switch coupled between a terminal to which the first light reference voltage is applied and a second input terminal of the first comparator;
A fourth switch having one end connected to the input terminal to which the input voltage or the operational amplification output voltage is applied;
A second comparator having the other end thereof connected to a first input terminal;
A fifth switch connected between a terminal to which the third reference voltage is applied and a second input terminal of the second comparator; And
And a sixth switch connected between a terminal to which the second light reference voltage is applied and a second input terminal of the second comparator.
9. The method of claim 8,
Wherein the first switch is on in the sigma-delta operating period and off in the cyclic operation period,
The second switch, the fourth switch, and the fifth switch are off in the sigma-delta operation period and on in the cyclic operation period,
Wherein the third switch and the sixth switch are turned on during the light intensity detecting operation period and turned off during the sigma-delta operation period and the cyclic operation period.
10. The method of claim 9,
Wherein,
A first comparator for determining a number of high-order M bits in response to an output signal of the first and second comparators, and a sigma-delta converter for outputting a first digital value and data of the high-order M bits in response to an output signal of the first comparator, A controller;
A cyclic controller for outputting the second digital value and the lower N bits of data in response to the output signals of the first and second comparators; And
And a control signal generator for receiving the first and second digital values and outputting the DAC control signal.
The method according to claim 1,
Further comprising a digital arithmetic unit for receiving the upper M bits of data and the N bits of data and correcting the error to output M + N bit result data.
A pixel unit having at least one pixel for outputting an analog signal according to light input from the outside; And
And an analog-to-digital converter having at least one or more analog-to-digital converters for converting the analog signals into digital signals,
Wherein the at least one analog-to-
In the sigma-delta operation period, the operational amplification output voltage is generated in response to the input voltage and the DAC output voltage. In the cyclic operation period, the operational amplification output voltage is generated in response to the operational amplification output voltage and the DAC output voltage ;
And a comparator for comparing the input voltage with the first and second light reference voltages to determine the number of high-order M bits in the light intensity detecting operation period, and comparing the operational amplification output voltage with the first reference voltage in the sigma- And the DAC control signal is generated and the data of the upper M bits is obtained. In the cyclic operation period, the DAC control signal is generated by comparing the operational amplification output voltage with the second and third reference voltages, A control unit for acquiring data; And
And a digital to analog converter for generating the DAC output voltage in response to the DAC control signal.
13. The method of claim 12,
The pixel unit includes:
And a plurality of pixels arranged in a matrix form.
14. The method of claim 13,
Further comprising a row driver for outputting a driving signal for driving pixels arranged in a selected row among the plurality of pixels.
14. The method of claim 13,
The analog-to-
And the analogue digital converter is provided for each row in which the plurality of pixels are arranged.
An image sensor according to claim 12;
An optical unit for collecting light input from the outside and transmitting the collected light to the pixel unit; And
And a data processing unit for inputting and processing or storing the digital signal.
17. The method of claim 16,
Characterized in that the device is a digital camera.

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