KR20140107079A - Integrated platform for improved wafer manufacturing quality - Google Patents

Integrated platform for improved wafer manufacturing quality Download PDF

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KR20140107079A
KR20140107079A KR1020130073654A KR20130073654A KR20140107079A KR 20140107079 A KR20140107079 A KR 20140107079A KR 1020130073654 A KR1020130073654 A KR 1020130073654A KR 20130073654 A KR20130073654 A KR 20130073654A KR 20140107079 A KR20140107079 A KR 20140107079A
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wet cleaning
semiconductor substrate
dry process
dry
stage
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KR1020130073654A
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Korean (ko)
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KR101563050B1 (en
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샤오-옌 쿠
차이-파오 수
웬-창 차이
치아-웬 리
유-옌 수
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타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67028—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like
    • H01L21/67034—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like for drying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67028—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67028—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like
    • H01L21/6704—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like for wet cleaning or washing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67161—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67207—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67703—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations

Abstract

The present disclosure relates to a method and apparatus for performing a dry plasma process while mitigating internal contamination of a semiconductor substrate. In some embodiments, the apparatus includes a semiconductor processing mechanism including a dry process stage having at least one dry process element for performing a dry plasma process on a semiconductor substrate received from an inlet port. The wafer transport system transports the semiconductor substrate from the dry process stage to a wet cleaning stage located downstream of the dry process stage. The wet cleaning stage has at least one wet cleaning element that performs a wet cleaning procedure to remove contaminants from the surface of the semiconductor substrate before the semiconductor substrate is provided to the outlet port. The wet cleaning procedure first improves wafer fabrication quality by removing internal contaminants of the dry process procedure from the semiconductor substrate.

Description

[0001] INTEGRATED PLATFORM FOR IMPROVED WAFER MANUFACTURING QUALITY [0002]

The present invention relates to an integrated platform for improving wafer manufacturing quality.

Current integrated chips include an enormous number of semiconductor devices formed on a semiconductor substrate (e.g., silicon). In order to improve the functionality of the integrated chip, the semiconductor industry has continually reduced the dimensions of semiconductor devices to provide integrated chips with small and dense devices. By forming an integrated chip with a small and dense device, the speed of the semiconductor device is increased because the power consumption of the device is reduced. However, since the density of the integrated chip device is reduced, the failure rate of the integrated chip due to contamination also increases. One cause of such failure increases is the exposure of the wafer to molecular contaminants in the air (e.g., dust particles in the air).

In order to minimize the failure of the integrated chip due to pollutants, the exposure of the integrated chip to the contaminant particles is limited. For example, modern integrated chips are being formed in clean rooms with low levels of environmental pollutants. For example, an ISO 1 clean room does not include particles having a size of 0.5 microns or more (compared to an outer atmosphere containing approximately 35,000,000 corresponding size particles per 3 square meters). The integrated chip is also transported between appliances in a clean room using a closed wafer carrier (e.g., a front open unified pod) that further reduces exposure of the integrated chip to contaminants.

The present disclosure relates to a method and apparatus for performing a dry plasma process while mitigating internal contamination of a semiconductor substrate. In some embodiments, the apparatus includes a semiconductor processing mechanism including a dry process stage having at least one dry process element for performing a dry plasma process on a semiconductor substrate received from an inlet port. The wafer transport system transports the semiconductor substrate from the dry process stage to a wet cleaning stage located downstream of the dry process stage. The wet cleaning stage has at least one wet cleaning element that performs a wet cleaning procedure to remove contaminants from the surface of the semiconductor substrate before the semiconductor substrate is provided to the outlet port. The wet cleaning procedure first improves wafer fabrication quality by removing internal contaminants of the dry process procedure from the semiconductor substrate.

Figure 1 shows a graph illustrating surface contamination of a wafer as a function of Q-time.
Figure 2 shows a block diagram of some embodiments of the disclosed semiconductor processing apparatus including a dry etch element incorporating a wet cleaning element.
Figure 3 shows a block diagram of some variations of the disclosed semiconductor processing apparatus including a dry etch element incorporating a wet cleaning element.
Figure 4 shows a block diagram of some variations of the disclosed semiconductor processing apparatus comprising a plurality of stacked wet cleaning elements.
Figure 5 shows a block diagram of some variations of the disclosed semiconductor processing apparatus, wherein the dry etch element comprises a plasma ashing mechanism.
6 is a flow diagram of some embodiments of a semiconductor processing method for performing a dry etching procedure followed by a wet cleaning procedure to provide a semiconductor substrate free of surface contaminants.

The description herein refers to the drawings, wherein like reference numerals are used to refer to substantially the same elements throughout the figures, and the various structures are not necessarily drawn to scale. In the following description, for purposes of explanation, numerous specific details are set forth in order to facilitate understanding. It is understood that the details of the drawings are not intended to limit the disclosure, but rather are a non-limiting embodiment. It will be apparent, however, to one skilled in the art, for example, that one or more aspects described herein may be practiced with fewer than these specific details. In other situations, well-known structures and devices are shown in block diagram form in order to facilitate understanding.

Despite the low number of contaminant particles in the manufacturing clean room, contamination of the integrated chip can not be completely prevented. Some manufacturing processes release internal contaminants directly onto the wafer that can not be prevented by a clean room procedure. For example, dry etching procedures result in surface halogen salt polymer residues that are a major cause of internal contaminants. It has been found that moisture in closed systems can exacerbate the effects of such internal contaminants and present additional problems in semiconductor reliability. For example, moisture in the front opening unified pod can accelerate the reaction of wafer surface halogen salt polymer residues, which reduces particle removal efficiency and causes condensation defects on the wafer surface or corrosion of the copper metal lines have.

To prevent contamination by internal contaminants, many modern IC manufacturing processes control the 'Q-time' of the time the wafer is exposed to open air. As the Q-time increases, the thickness of the oxide layer and the number of surface particles to which the wafer is exposed increases, thereby increasing the likelihood of integrated chip failure. For example, Figure 1 is a graph 100 illustrating surface contamination of the wafer (y-axis) as a function of Q-time (x-axis). As shown in the graph 100, as the Q-time of the wafer increases, the number of surface particles to which the wafer is exposed increases, which may reduce the yield of integrated chips formed on the wafer.

Accordingly, the present disclosure is directed to a semiconductor processing apparatus having a dry process element incorporating a wet cleaning element to provide a semiconductor substrate free of surface contamination. In some embodiments, the semiconductor device includes a dry process stage having at least one dry process element configured to perform a dry plasma process on a semiconductor substrate received from an inlet port. The wafer transport system is configured to transport from a dry process stage to a wet cleaning stage located downstream of the dry process stage. The wet cleaning stage includes at least one wet cleaning element configured to perform a wet cleaning procedure to remove contaminants from the surface of the semiconductor substrate before the semiconductor substrate is provided to the outlet port. By performing a wet cleaning procedure prior to providing the semiconductor substrate to the outlet port, internal contaminants from the dry plasma process are removed from the semiconductor substrate to improve manufacturing quality.

Figure 2 illustrates a block diagram of some embodiments of the disclosed semiconductor processing apparatus 200 having a dry process stage 208 with a wet cleaning stage 212 incorporated within a platform housing 218. The dry process stage 208 is shown in Figure 2,

The semiconductor processing apparatus 200 includes at least one inlet port 204a, ..., 204n configured to receive a semiconductor substrate. In some embodiments, the inlet ports 204a, ..., 204n are configured to connect to the inlet wafer carriers 202a, ..., 202n configured to hold one or more semiconductor substrates. For example, a first inlet port 204a may be configured to connect to a first inlet wafer carrier 202a, a second inlet port 204b may be configured to connect to a second inlet wafer carrier 202b, Respectively. In some embodiments, the incoming wafer carriers 202a, ..., 202n are forward open unified pods (FOUPs) that house one or more semiconductor substrates. In some embodiments, the at least one semiconductor substrate may be a 450 mm semiconductor wafer. The wafer transfer system 206 is configured to transfer a semiconductor substrate from the incoming wafer carriers 202a ... 202n to a dry process stage 208 comprising a plurality of dry process elements 208a ... 208n. do. In some embodiments, the wafer delivery system 206 is configured to transfer a semiconductor substrate from an inlet port 204a, ..., or 204n to an associated dry process element 208a, ..., or 208n. For example, the wafer transfer system 206 may be configured to transfer the first semiconductor substrate from the first incoming wafer carrier 202a connected to the first inlet port 204a to the first dry process element 208a, To the second dry process element 208b from the second incoming wafer carrier 202b connected to the second inlet port 204b, and so on. In some embodiments, the wafer transfer system 206 includes multiple robot elements configured to handle a semiconductor substrate during transfer from the incoming wafer carrier 202a, ..., or 202n to the dry process element 208. In some embodiments,

Each dry process element 208a, ..., 208n is configured to perform a dry plasma process on a received semiconductor substrate. In some embodiments, each dry process element 208a, ..., 208n includes a plasma etch component configured to perform, for example, a plasma etch procedure, a reactive ion etch (RIE) component configured to perform an RIE procedure, Or a plasma ashing component configured to perform a plasma ashing procedure. In some embodiments, the plurality of dry process elements 208a, ..., 208n may be configured to perform different plasma processes, such as dry etching and plasma ashing. For example, in some embodiments, the first dry process component 208a is configured to perform a dry etching process and the second dry process component 208b is configured to perform a plasma ashing process. In some embodiments, one or more of the plurality of dry process elements (e.g., 208a) may be configured to perform multiple plasma processes (e.g., both dry etch and plasma etch).

The wafer transfer system 206 is also configured to transfer the semiconductor substrate from the dry process stage 208 to the wet cleaning stage 212 by transfer bridges 210a ... 210n. The transfer bridges 210a, ..., 210n are configured to prevent the semiconductor substrate from being exposed to the surrounding environment and to maintain a vacuum in the process chamber of the dry process elements 208a, ..., 208n.

The wet cleaning stage 212 includes at least one wet cleaning stage 212a disposed on the downstream side of the one or more dry process elements 208a, ..., 208n. One or more wet cleaning elements 212a may be configured to perform a wet cleaning procedure on a received semiconductor substrate to remove contaminants (e.g., particles, metal contaminants, organic contaminants, etc.) from the semiconductor substrate by a cleaning process utilizing a liquid cleaner do. In some embodiments, the wet cleaning procedure may include RCA cleaning wherein a hydrogen peroxide solution having a high pH is used for effective removal of organic compounds (by oxidation) from the semiconductor substrate. In other embodiments, the wet cleaning procedure may include other cleaning procedures such as HF cleaning, SPM (sulfuric-peroxide mixture) cleaning, ozone (O3 / DI) cleaning in deionized water, solvent cleaning,

In some embodiments, one or more dry process elements 208a, ..., 208n are configured to provide a semiconductor substrate to the same wet cleaning element 212a. By connecting the multiple dry process elements 208a ... 208n to the same wet cleaning element 212a the throughput of the semiconductor processing apparatus 200 is increased because the dry process elements 208a, 208n is lower than the throughput of the wet cleaning element 212a.

The wafer transfer system 206 is also configured to transfer the semiconductor substrate from the wet cleaning stage 212 to an outlet port 214 that includes an outgoing wafer carrier 216 configured to hold a semiconductor substrate. By transferring the semiconductor substrate from the wet cleaning stage 212 to the output wafer carrier 216 (e.g., FOUP), the disclosed semiconductor processing apparatus 200 incorporates dry plasma processing and wet cleaning procedures into a single apparatus, After the dry plasma process, a semiconductor substrate having a surface free from contamination is output.

Figure 3 illustrates a block diagram of some embodiments of the disclosed semiconductor processing tool 300 that includes one or more dry etching elements 310 with a wet cleaning element 314 integrated therein.

The semiconductor processing apparatus 300 includes a first dry etch path 302a and a second dry etch path 302b coupled to the wet cleaning element 314. The first and second dry etch passages 302a and 302b are configured to receive a semiconductor substrate from an incoming wafer carrier, perform a dry etch procedure on the semiconductor substrate, and provide a semiconductor substrate to the wet cleaning element 314. The wet cleaning element 314 is configured to remove internal contaminants (e.g., introduced during the dry etch procedure) from the semiconductor substrate prior to providing the semiconductor substrate to the outgoing wafer carrier.

In some embodiments, each dry etch path 302 includes an inlet porch 304 that is configured to receive a semiconductor substrate (e.g., a semiconductor wafer) from an incoming wafer carrier (e.g., from a FOUP). The inlet port 304 is connected to the first factory interface 306. The first factory interface 306 is configured to transfer the semiconductor substrate into the first load lock module 308. In some embodiments, the first factory interface 306 is configured to position the incoming wafer carrier holding the semiconductor substrate within the first load lock module 308. In some embodiments, the first factory interface 306 is configured to transfer an individual semiconductor substrate between the first load lock module 308 and the inflow carrier positioned in the inlet port 304.

The first load lock module 308 is positioned between the first factory interface 306 and the dry etching element 310 and is configured to maintain a low pressure in the processing chamber of the dry etching element 310. For example, the first load lock module 308 operates at a first pressure when receiving a semiconductor substrate, reduces the pressure to a second pressure lower than the first pressure, To the processing chamber of the < / RTI >

The second load lock module 312 is positioned between the dry etching element 310 and the wet cleaning element 314. The second load lock module 312 is configured to operate as a bridge between the dry etch component 310 and the wet cleaning component 314 to maintain a low pressure within the process chamber of the dry etch component 310. For example, the second load lock module 312 operates at a second pressure (e.g., a pressure in the range of mTorr) when receiving a semiconductor substrate and compresses the pressure from a second pressure to a first pressure (e.g., Atmospheric pressure), and then to transport the semiconductor substrate to the processing chamber of the wet cleaning element 314.

The wet cleaning element 314 is configured to receive the semiconductor substrate from the second load lock module 312 and perform a wet cleaning procedure on the received semiconductor substrate. The wet cleaning procedure removes surface contaminants from the semiconductor substrate to provide a semiconductor substrate having a surface free from contamination. For example, in some embodiments, the wet cleaning procedure is configured to remove halogen salt polymer residues of the dry etching procedure from the semiconductor substrate.

The wet cleaning element 314 is connected to a second factory interface 316. The second factory interface 316 is configured to transport the semiconductor substrate from the wet cleaning element 314 to an effluent wafer carrier disposed within the outlet port 318. In some embodiments, the second factory interface 316 includes a robotic arm configured to transfer an individual semiconductor wafer between the wet cleaning element 314 and the outgoing wafer carrier.

Although the disclosed semiconductor processing apparatus (e.g., apparatus 300, 500) may be described as including a particular type of dry process element (e.g., a dry etch mechanism, a plasma ashing mechanism) It is not limited. For example, some embodiments described in connection with the semiconductor processing apparatus 300 may be applied to a semiconductor processing apparatus including, for example, one or more plasma ashing elements. Similarly, some embodiments described in connection with the semiconductor processing apparatus 500 may be applied to a semiconductor processing apparatus including, for example, one or more plasma ashing elements.

FIG. 4 illustrates a block diagram of some variations of the disclosed semiconductor processing apparatus 400.

The semiconductor processing mechanism 400 includes a plurality of wet cleaning elements 402a, ..., 402n. Each of the wet cleaning elements 402a, ..., 402n includes a wet cleaning processing chamber configured to receive a semiconductor substrate during a wet cleaning procedure. The plurality of wet cleaning elements 402a ... 402n are configured to receive an outflow wafer carrier 216 configured to receive a semiconductor substrate from a plurality of wet cleaning elements 402a ... 402n, Lt; / RTI > In some embodiments, a plurality of wet cleaning elements 402a, ..., 402n are stacked vertically to one another to form a stacked tower structure having a shared outlet port 404 at the top of the stacked tower structure.

Each of the wet cleaning elements 402a ... 402n is connected to one or more of the dry process elements 208a-208d and is configured to receive a semiconductor substrate from one or more dry process elements 208a-208d. For example, a first wet cleaning element 402a is configured to receive a semiconductor substrate from a first dry process element 208a, a second wet cleaning element 402n is configured to receive a third dry process element 208c, And is configured to receive a semiconductor substrate from element 208d.

Although the semiconductor processing mechanism 400 illustrates each wet cleaning element 402 as being connected to two dry process elements, each of the wet cleaning elements 402a, ..., 402n may include any number of dry processes Lt; / RTI > element.

Figure 5 illustrates a block diagram of some variations of the disclosed semiconductor processing apparatus 500 that includes a plasma ashing mechanism as a dry process element. Although the semiconductor processing apparatus 500 is illustrated as including three plasma ashing mechanisms 504a-504c, in some variations, the semiconductor processing apparatus 500 may include a different number of plasma ashing mechanisms and / (E. G., A dry etch mechanism).

The semiconductor processing apparatus 500 includes a first dry processing path 502a, a second dry processing path 502b, and a third dry processing path 502c connected to the wet cleaning element 314. Although the semiconductor processing apparatus 500 illustrates three dry processing paths, it will be appreciated that the disclosed semiconductor processing apparatus 500 may include any number of dry processing paths.

Each dry processing path 502 includes a plasma ashing mechanism 504 that includes one or more ashing elements 506. The ashing element 506 is configured to generate a plasma that is used to remove the photoresist from the semiconductor substrate, and the plasma ashing mechanism 504 may perform the ashing process. In some embodiments, the ashing element 506 uses a mixture of reactive gases, such as atomic oxygen, to remove the photoresist from the surface of the semiconductor substrate.

6 is a flow diagram of some embodiments of a semiconductor processing method 600 for performing a dry plasma process followed by a wet cleaning procedure to provide a semiconductor substrate without surface contamination.

While the disclosed method 600 is illustrated and described below as a series of acts or events, it will be understood that the illustrated sequence of such acts or events is not to be interpreted in a limiting sense. For example, some of the actors may be described in terms of what is illustrated and / or described herein, and may occur in different orders and / or concurrently with other act or events. In addition, not all illustrated actors may be required to practice one or more aspects or embodiments of the description herein. Also, one or more of the acts shown herein may be performed in one or more separate acts and / or phases.

In act 602, the semiconductor substrate is transferred from the incoming wafer carrier to a dry process stage comprising one or more dry process elements. The dry process element is configured to perform a dry plasma process (e.g., a dry etch process, an ashing process). In some embodiments, the inflow wafer carrier is a forward open unified pod (FOUP). In some embodiments, the semiconductor substrate is transferred from the incoming wafer carrier to the dry process element by a first load lock module configured to maintain a low pressure environment within the processing chamber of the dry process element.

In act 604, material is removed from one or more semiconductor substrates in one or more dry process elements. In some embodiments, the material is removed by performing a dry plasma process on the semiconductor substrate. In various embodiments, the dry plasma process may include a plasma etch process to etch the semiconductor substrate, a reactive ion etch process to etch the semiconductor substrate, an ashing process to remove the photoresist from the semiconductor substrate, and the like.

At act 606, the semiconductor substrate is transferred from the dry process stage to a wet cleaning stage comprising at least one wet cleaning element. The at least one wet cleaning element is configured to perform a wet cleaning procedure to remove contaminants (e.g., contaminant residues from the dry etch process) from the semiconductor substrate. In some embodiments, the semiconductor substrate is transferred from the dry process element of the dry process stage to the wet cleaning element in the wet cleaning stage by a second load lock module configured to maintain a low pressure environment within the process chamber of the dry process element.

In Act 608, a wet cleaning procedure is performed on the semiconductor substrate. In various embodiments, the wet cleaning procedure may include RCA cleaning.

In act 610, the semiconductor substrate is transferred from the wet cleaning mechanism to the outgoing wafer carrier. In some embodiments, the effluent wafer carrier is a forward open unified pod (FOUP).

As used herein, the term semiconductor substrate refers to any type of semiconductor body (e.g., silicon, SiGe, SOI), such as a semiconductor wafer and / or one or more dies on a wafer, as well as any other type of Metal layers, devices, semiconductors and / or epitaxial layers, and the like.

It will be appreciated that equivalent alterations and / or modifications may be apparent to those skilled in the art on the basis of the reading and / or understanding of the specification and the accompanying drawings. The disclosure of this specification includes all such modifications and variations and is not intended to be generally limited thereby.

Also, although a particular feature or aspect has been described with respect to one of several implementations, such feature or aspect may be combined with one or more other features and / or aspects of other implementations as desired. Furthermore, in the sense that the terms "comprises," "having," "having," "having," and / or their derivatives are used herein, such terms are intended to be inclusive as "comprising" . Also, the word "exemplary" is intended to mean not merely the best, but merely an example. In addition, the features, layers and / or elements illustrated herein are illustrated with a particular dimension and / or orientation relative to each other for ease of understanding and ease of understanding, and the actual dimensions and / It can be different.

Accordingly, the present disclosure is directed to a method and apparatus for performing a dry plasma procedure while mitigating internal contamination of a semiconductor substrate.

In some embodiments, the disclosure relates to a semiconductor processing apparatus. The semiconductor processing apparatus includes a dry process stage having one or more dry process elements coupled to the at least one inlet port and each dry process element is configured to perform a dry plasma process on a semiconductor substrate received from one of the one or more inlet ports . The semiconductor processing apparatus includes a wet cleaning apparatus having at least one wet cleaning element configured to receive a semiconductor substrate from at least one dry process element and to perform a wet cleaning process to remove contaminants from the semiconductor substrate before the semiconductor substrate is provided to the outlet port Stage. The wafer transport system is configured to transport the semiconductor substrate from the dry process stage to the wet cleaning stage.

In another embodiment, the disclosure is directed to a dry process mechanism. The dry process mechanism includes a plurality of dry process elements, each dry process element configured to remove material from a semiconductor substrate received from an incoming wafer carrier in contact with the inlet port. The dry process mechanism is configured to receive a plurality of semiconductor substrates from a plurality of dry process elements and to perform a wet cleaning procedure prior to providing a plurality of semiconductor substrates with an outflow wafer carrier that is different from the incoming wafer carrier and contacts the outlet port, Further comprising a wet cleaning element configured to remove contaminants from the substrate. The wafer transport system is configured to transport a plurality of semiconductor substrates from the plurality of dry process elements to the wet cleaning element.

In another embodiment, the disclosure relates to a method. The method includes conveying one or more semiconductor substrates from an incoming wafer carrier to a dry process stage comprising at least one dry process element. The method further includes removing material from the at least one semiconductor substrate in the at least one dry process element. The method further includes delivering the one or more semiconductor substrates to a wet cleaning stage comprising one or more cleaning elements. The method further includes wet cleaning the surface of the at least one semiconductor substrate in the at least one wet cleaning element. The method further includes transferring the one or more semiconductor substrates from the wet cleaning stage to the outgoing wafer carrier.

Claims (10)

A semiconductor processing tool comprising:
Each of the dry process elements being configured to perform a dry plasma process on a semiconductor substrate received from one of the one or more inlet ports, the dry process stage including one or more dry process elements coupled to one or more inlet ports, stage;
A wet cleaning stage comprising at least one wet cleaning element configured to receive a semiconductor substrate from at least one dry process element and to perform a wet cleaning process to remove contaminants from the semiconductor substrate prior to the semiconductor substrate being provided to an outflow port, ; And
A wafer transfer system configured to transfer the semiconductor substrate from the dry process stage to the wet cleaning stage;
And a semiconductor processing apparatus. The method according to claim 1,
Wherein a plurality of dry process elements are connected to the same wet cleaning element in the wet cleaning stage. 3. The method of claim 2,
Further comprising a first load lock module coupled between one of the plurality of dry process elements and the same wet cleaning element,
Wherein the first load lock module is configured to maintain the pressure in the processing chamber of one of the plurality of dry process elements lower than the processing chamber of the wet cleaning element. The method of claim 3,
A first factory interface coupled to one of the plurality of dry process elements and configured to provide the semiconductor substrate from the incoming wafer carrier to one of the plurality of dry process elements; And
A second factory interface coupled to the same wet cleaning element and configured to provide a semiconductor substrate to the outgoing wafer carrier from the same wet cleaning element
Further comprising:
Wherein the incoming wafer carrier and the outgoing wafer carrier are separate forward open unified pods. 3. The method of claim 2,
The wet cleaning stage having a plurality of wet cleaning elements,
Wherein each of the plurality of wet cleaning elements comprises a wet cleaning processing chamber configured to receive a semiconductor substrate from at least one of the plurality of dry processing elements. 6. The method of claim 5,
Wherein the plurality of wet cleaning elements are stacked in a vertical direction in a tower structure,
Wherein the tower structure has a shared outflow port configured to receive an outgoing wafer carrier configured to receive a semiconductor substrate from the plurality of wet cleaning elements. The method according to claim 1,
Wherein the at least one dry process element comprises a plasma ashing mechanism having at least one ashing element configured to generate a plasma to remove photoresist from the semiconductor substrate. The method according to claim 1,
Wherein the wet cleaning stage is disposed within the platform housing at a point downstream of the dry process stage. In the dry process mechanism,
A plurality of dry process elements each configured to remove material from a semiconductor substrate received from an incoming wafer carrier in contact with the inlet port;
A plurality of semiconductor substrates are received from the plurality of dry process elements and a wet cleaning procedure is performed before the plurality of semiconductor substrates are provided with an outflow wafer carrier that is different from the incoming wafer carrier and contacts the outlet port, A wet cleaning element configured to remove contaminants from the substrate; And
A wafer transport system configured to transfer the plurality of semiconductor substrates from the plurality of dry process elements to the wet cleaning element,
Wherein the dry process mechanism comprises: Transferring one or more semiconductor substrates from an incoming wafer carrier to a dry process stage comprising at least one dry process element;
Removing material from the at least one semiconductor substrate at the at least one dry process element;
Transferring the at least one semiconductor substrate to a wet cleaning stage comprising at least one wet cleaning element;
Wet cleaning the surface of the at least one semiconductor substrate in the at least one wet cleaning element; And
And transferring the at least one semiconductor substrate from the wet cleaning stage to the outgoing wafer carrier.
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