KR20140088781A - Phase Change Memory Apparatus And Write Method Of The Same - Google Patents

Phase Change Memory Apparatus And Write Method Of The Same Download PDF

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Publication number
KR20140088781A
KR20140088781A KR1020130000719A KR20130000719A KR20140088781A KR 20140088781 A KR20140088781 A KR 20140088781A KR 1020130000719 A KR1020130000719 A KR 1020130000719A KR 20130000719 A KR20130000719 A KR 20130000719A KR 20140088781 A KR20140088781 A KR 20140088781A
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KR
South Korea
Prior art keywords
write
current
phase change
change memory
data
Prior art date
Application number
KR1020130000719A
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Korean (ko)
Inventor
임상국
탁정미
Original Assignee
에스케이하이닉스 주식회사
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Priority to KR1020130000719A priority Critical patent/KR20140088781A/en
Publication of KR20140088781A publication Critical patent/KR20140088781A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0038—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods

Abstract

A phase change memory apparatus according to the present technology comprises a phase change memory cell for storing recording data using write current and a write unit for outputting the write current by receiving the recording data and for determining the generation and output of the write current by comparing data stored in the phase change memory cell with the recording data.

Description

[0001] The present invention relates to a phase change memory device and a phase change memory device,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a technique for writing a phase change memory device and a phase change memory device.

A phase change random access memory (PCRAM) device is characterized by being a non-volatile memory, but it is capable of random access and is highly integrated at a low cost. The phase change memory device (PCRAM) stores information using a phase change material. The phase change memory device (PCRAM) stores information by using a phase change material in a nonvolatile memory device Non-Volatile Memory Device).

The phase change material uses a material which can be converted into an amorphous state or a crystal state depending on a temperature condition. Typical materials include chalcogenide alloys. Since Ge 2 Sb 2 Te 5 (GST) using germanium (Ge), antimony (Sb), tellurium (Te) Describe the substance as 'GST'.

The phase change memory device (PCRAM) uses a Joule heating generated by a current of a specific condition for a phase change material (GST) or a voltage applied thereto to change the crystal state of the phase change material (GST) A reversible phase change occurs between the amorphous state and the amorphous state. The crystal state is referred to as a set state in a circuit and the phase change material GST in a set state has an electrical characteristic such as a metal having a low resistance value. In addition, the amorphous state is referred to as a reset state in a circuit state, and the phase change material GST in a reset state has a resistance value higher than a set state. That is, the phase-change memory device stores information through a change in resistance value between a crystal state and an amorphous state, detects a voltage change due to a change in current or current flowing in the phase change material (GST) And the stored information is discriminated.

1 is a block diagram of a prior art phase change memory device.

A phase change memory device according to the prior art includes a writing device 10 and a phase change memory cell 20.

Generally, the phase change memory device performs a verify operation to verify that desired data is written after performing a write operation.

Specifically, the power supply unit 11 receives the write data WDT and outputs a reset current RESET or a set current SET according to the write data WDT.

The write circuit 120 outputs the write current I_WRITE in proportion to the reset current RESET or the set current SET.

The current transfer section 13 determines whether to transfer the write current I_WRITE to the phase change memory cell 20 in response to the output signal of the comparison section 15. [

The phase change memory cell 20 stores the write data WDT in accordance with the write current I_WRITE.

The read circuit 14 reads the write data WDT stored in the phase change memory cell 20 and outputs read data RDT.

The comparison unit 15 compares the write data WDT with the read data RDT and outputs a control signal CTR for controlling the current transfer unit 13. [

The comparator 13 enables the control signal CTR when the write data WDT and the read data RDT are the same and outputs the control signal CTR when the write data WDT and the read data RDT are different Disable.

The current transfer part 13 does not transfer the write current I_WRITE to the phase change memory cell 20 in response to the enabled control signal CTR but outputs the write current I_WRITE in response to the disabled control signal CTR I_WRITE) to the phase change memory cell (20).

That is, when the write data WDT and the read data RDT are the same, the write device 10 stores the write current I_WRITE in the phase change memory cell 20 because the original write data WDT to be stored is stored in the phase change memory cell 20, The memory cell 20 is not transferred. In contrast, when the write data WDT and the read data RDT are different from each other, the write device 10 does not store the write current I_WRITE since the original write data WDT to be stored is not stored in the phase change memory cell 20 Change memory cell 20 and performs a write operation again.

At this time, the writing device 10 must continuously generate the write current I_WRITE to store the write data WDT in the phase-change memory cell when the write data WDT and the read data RDT are different, but the write data WDT And the read data RDT are the same, it is not necessary to continuously generate the write current I_WRITE.

The write device 10 of the phase change memory device according to the related art blocks the write current I_WRITE from being transferred to the phase change memory cell 20 when the write data WDT and the read data RDT are the same The write current (I_WRITE) is continuously generated and unnecessary current consumption occurs.

Further, when a plurality of write data WDT are input, the power supply unit 11 always outputs the set current SET or the reset current RESET regardless of the information of the write data WDT, .

The present invention provides a phase change memory device and a method of writing a phase change memory device that can interrupt the output of a write current when a write operation is completed.

A phase change memory device according to an embodiment of the present invention includes: a phase change memory cell storing write data using a write current; And a writing device receiving the write data and outputting the write current and comparing the write data with data stored in the phase change memory cell to determine whether to generate or output the write current.

According to another aspect of the present invention, there is provided a writing method for a phase change memory device, comprising: receiving write data to be stored in a phase change memory cell; Generating a write current in accordance with the write data and transferring the write current to the phase change memory cell; Storing the write data in the phase change memory cell using the write current; Reading data stored in the phase change memory cell and outputting the read data; Comparing the write data with the read data; And stopping the writing current generation and stopping transfer of the writing current to the phase change memory cell if the compared two data are the same.

The present invention can reduce the current consumption of the phase change memory device by blocking the output of the write current when the write operation is completed.

Figure 1 is a block diagram of a phase change memory device in accordance with the prior art;
Figure 2 is a block diagram of a phase change memory device in accordance with an embodiment of the present invention;
3 is a flowchart illustrating a writing method of a phase change memory device according to an embodiment of the present invention.
4 is a circuit diagram of a writing unit according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention.

Figure 2 is a phase change memory device 100 in accordance with an embodiment of the present invention.

The phase change memory device 100 includes a writing device 110 and a phase change memory cell 120.

The writing device 110 includes a writing unit 111, a current transmitting unit 112, a reading unit 113, and a comparing unit 114. The writing unit 111 includes a power supply unit 1110 and a write driver 1120.

The writing unit 111 receives the write data WDT in response to the control signal CTR and outputs a write current I_WRITE according to the write data WDT.

The power supply section 1110 outputs the set current SET when the bit value of the write data WDT is "0 ", and outputs the reset current RESET when the bit value of the write data WDT is" 1 & .

As described above, the resistance value of the phase-change memory device changes depending on a set state or a reset state. Therefore, the current outputted according to the bit value of the write data WDT in the power supply unit 1110 is different in order to store different data according to the resistance value of the phase change memory element.

The write driver 1120 outputs a write current I_WRITE in proportion to the set current SET or the reset current RESET output from the power supply 1110. [

The current transfer unit 112 connects the write unit 111 and the phase change memory cell 120 in the write operation of the phase change memory device 100 and transfers the write current I_WRITE to the phase change memory cell 120 .

When the write operation is completed, the current transfer unit 112 does not transfer the write current I_WRITE output from the write unit 111 to the phase change memory cell 120 in response to the control signal CTR.

The phase change memory cell 120 receives the write current I_WRITE and stores the write data WDT.

The reading unit 113 reads the write data WDT stored in the phase change memory cell 120 and outputs read data RDT.

The comparator 114 compares the write data WDT with the read data RDT and outputs the control signal CTR.

The comparator 114 disables and outputs the control signal CTR when the write data WDT and the read data RDT are the same and outputs the control signal CTR when the write data WDT and the read data RDT are different, ) And outputs it.

The power supply unit 1110 outputs the set current SET or the reset current RESET in response to the control signal CTR. The power supply unit 1110 does not output the set current SET and the reset current RESET when the disabled control signal CTR is input and outputs the set current SET or reset when the enabled control signal CTR is input, And outputs a current RESET.

The current transfer unit 112 does not transfer the write current I_WRITE to the phase change memory cell 120 when the disabled control signal CTR is input and outputs the write current I_WRITE when the enabled control signal CTR is input I_WRITE) to the phase change memory cell 120.

3 is a flowchart illustrating a writing method of the phase-change memory device 100 according to an embodiment of the present invention.

Referring to FIGS. 2 and 3, write data WDT to be stored in the phase change memory cell 120 is input (S101). The write current I_WRITE is generated in accordance with the write data WDT and the write current I_WRITE is transferred to the phase change memory cell 120 in step S102.

The write data WDT is stored in the phase change memory cell 120 in step S103 and the data stored in the phase change memory cell 120 is read to output the read data RDT in step S104.

It is determined whether the write data WDT matches the read data RDT (S105).

As a result, if the compared two data coincide (S105, YES), the generation of the write current I_WRITE is stopped, and the transfer of the write current I_WRITE to the phase change memory cell 120 is stopped.

When the compared two data are different (S105, NO), the write current I_WRITE is generated again according to the write data WDT and the write current I_WRITE is transferred to the phase change memory cell 120 (S102).

4 is a circuit diagram of a writing unit 111 according to an embodiment of the present invention.

The writing unit 111 includes a power supply unit 1110 and a write driver 1120.

The power supply unit 1110 includes a power supply unit 1111, a power source replica unit 1112, and a power source control unit 1113. The power supply unit 1111 includes a current source (ISRC).

The power supply unit 1111 includes a plurality of transistors P1 and P2 for forming a current mirror and driving a current corresponding to the voltage level of the control node ND1.

The power supply unit 1111 includes a first PMOS transistor P1 connected between the driving voltage VPP and the control node ND1 and responsive to the voltage of the control node ND1 and a driving voltage VPP and a replica node ND2, And a second PMOS transistor (P2) connected between the control node (ND1) and the control node (ND1).

The current source ISRC may include a reset current source or a set current source capable of outputting a reset current RESET or a set current SET according to a bit of the write data WDT.

Here, the current source ISRC may be a known circuit that outputs a reset current or a set current according to data.

The current source ISRC outputs the reset current RESET when the bit of the write data WDT is " 1 ", and the current source ISRC outputs the set current SET when the bit of the write data WDT is & do.

When the current source ISRC is driven to pull down the voltage of the control node ND1 toward the ground voltage VSS, the power supply unit 1111 supplies the set current SET or the reset current (RESET). At this time, the control node ND1 becomes logic low and the duplicate node ND2 becomes logic high.

When the voltage level of the control node ND1 becomes low and becomes logic low, the first and second PMOS transistors P1 and P2 turn on. The turned-on first and second PMOS transistors P1 and P2 raise the voltage level of the duplicate node ND2 to become logic high.

The power replica section 1112 includes a plurality of transistors N1 and N2 for forming a current mirror and driving a current corresponding to the voltage level of the duplicate node ND2.

The power replica section 1112 includes a first NMOS transistor N1 connected between the duplicate node ND2 and the ground voltage VSS and responsive to the voltage of the duplicate node ND2, (VSS) and a second NMOS transistor (N2) coupled in response to the voltage of the duplicate node (ND2).

When the set current SET or the reset current RESET is transferred to the duplicate node ND2, the power source replica 1112 delivers the set current SET or the reset current RESET to the first transfer node ND3 . At this time, the first transfer node ND3 becomes a logic low.

When the voltage level of the duplicate node ND2 rises to a logic high level, the first and second NMOS transistors N1 and N2 turn on. The turned-on first and second NMOS transistors N1 and N2 transfer a set current (SET) or a reset current RESET to the first transfer node ND3.

The power control unit 1113 determines whether the first transfer node ND3 and the second transfer node ND4 are connected in response to the control signal CTR.

The power control unit 1113 determines the connection edge between the power supply unit 1110 and the write driver 1120 in response to the control signal CTR.

The power control unit 1113 includes a third NMOS transistor N3 connected between the first transfer node ND3 and the second transfer node ND4 and responsive to the control signal CTR.

When the enabled control signal CTR is input, the power control unit 1113 connects the first transfer node ND3 and the second transfer node ND4. When the disabled control signal CTR is input, the power control unit 1113 cuts off the first transfer node ND3 and the second transfer node ND4.

When the enabled control signal CTR is input, the power control unit 1113 transmits a set current (SET) or a reset current (RESET) to the second transfer node ND4. The power control unit 1113 does not transmit the set current SET or the reset current RESET to the second transfer node ND4 when the disabled control signal CTR is input.

That is, the power control unit 1113 does not transmit the set current SET or the reset current RESET to the write driver 120 when the write data WDT and the read data RDT are the same. The power control unit 1113 transmits the set current SET or the reset current RESET to the write driver 120 when the write data WDT and the read data RDT are different.

The write driver 1120 includes a plurality of transistors P3 and P4 for forming a current mirror and driving a current corresponding to the voltage level of the second transfer node ND4.

The write driver 1120 includes a third PMOS transistor P3 connected between the driving voltage VPP and the second transfer node ND4 and responsive to the voltage of the second transfer node ND4, a second transfer node ND4, And a fourth PMOS transistor P4 that outputs a write current I_WRITE in response to a voltage of the driving voltage VPP.

The third and fourth PMOS transistors P3 and P4 of the write driver 1120 are turned on when the voltage level of the second transfer node ND4 becomes low. The turned on third and fourth PMOS transistors P3 and P4 output a write current I_WRITE in proportion to the set current SET or the reset current RESET delivered to the second transfer node ND4.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims and their equivalents. Only. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

10, 100: writing device 11, 1110:
12: writing circuit 13, 112:
15, 114: comparison section 14, 113: reading section
20, 120: Phase change memory cell 111:
1120: Write driver 1111: Power supply unit
1112: power replica unit 1113: power source control unit

Claims (9)

A phase change memory cell for storing write data using a write current; And
And a write device receiving the write data and outputting the write current and comparing the write data with data stored in the phase change memory cell to determine whether to generate or output the write current.
The method according to claim 1,
The writing device
A writing unit receiving the write data and outputting the write current in response to a control signal;
A current transfer unit for transferring the write current to the phase change memory cell in response to the control signal;
A reading unit that reads data stored in the phase change memory cell and outputs read data; And
And a comparator for comparing the write data with the read data and outputting the control signal.
3. The method of claim 2,
The writing unit
A power supply for outputting a set current or a reset current according to the write data; And
And a write driver for outputting the write current in proportion to the set current or the reset current.
The method of claim 3,
The power supply unit
A power supply unit for driving the current source according to the write data to output the set current or the reset current;
A power replica unit for replicating and delivering the set current or the reset current;
And transfers the set current or the reset current to the write driver in response to the control signal.
3. The method of claim 2,
The comparing unit
Comparing the write data with the read data, disabling and outputting the control signal when the compared two data match, comparing the write data with the read data, and when the compared two data are different, And outputting the enable signal.
6. The method of claim 5,
The writing unit
Outputting the write current in response to the enabled control signal and stopping outputting the write current in response to the disabled control signal.
6. The method of claim 5,
The current-
Change memory device in response to said enabled control signal and stops transferring said write current to said phase change memory device in response to said disabled control signal.
Receiving write data to be stored in the phase change memory cell;
Generating a write current in accordance with the write data and transferring the write current to the phase change memory cell;
Storing the write data in the phase change memory cell using the write current;
Reading data stored in the phase change memory cell and outputting the read data;
Comparing the write data with the read data;
And stopping generating the write current and stopping transfer of the write current to the phase change memory cell if the compared two data are the same.
9. The method of claim 8,
Further comprising generating a write current in accordance with the write data when the compared two data are different and transferring the write current to the phase change memory cell.
KR1020130000719A 2013-01-03 2013-01-03 Phase Change Memory Apparatus And Write Method Of The Same KR20140088781A (en)

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KR1020130000719A KR20140088781A (en) 2013-01-03 2013-01-03 Phase Change Memory Apparatus And Write Method Of The Same

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11636895B2 (en) 2019-11-05 2023-04-25 Samsung Electronics Co., Ltd. Non-volatile resistive memory device including a plurality of write modes

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11636895B2 (en) 2019-11-05 2023-04-25 Samsung Electronics Co., Ltd. Non-volatile resistive memory device including a plurality of write modes

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