KR102026208B1 - Nonvaltile Memory Apparatus - Google Patents

Nonvaltile Memory Apparatus Download PDF

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KR102026208B1
KR102026208B1 KR1020120153555A KR20120153555A KR102026208B1 KR 102026208 B1 KR102026208 B1 KR 102026208B1 KR 1020120153555 A KR1020120153555 A KR 1020120153555A KR 20120153555 A KR20120153555 A KR 20120153555A KR 102026208 B1 KR102026208 B1 KR 102026208B1
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South Korea
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current
current path
voltage
reference voltage
resistance component
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KR1020120153555A
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Korean (ko)
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KR20140083611A (en
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강석준
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에스케이하이닉스 주식회사
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5678—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using amorphous/crystalline phase transition storage elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0038—Power supply circuits

Abstract

A nonvolatile memory device according to the present technology includes a current path including a global line switch unit, a global line, a local line switch unit, and a bit line; A memory cell configured to receive a write voltage through the current path and store data; And a voltage output unit configured to output the write voltage whose voltage amount varies according to a resistance component included in the current path.

Description

Nonvolatile Memory Device {Nonvaltile Memory Apparatus}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly to a voltage generating circuit of a nonvolatile memory device.

Generally, phase change random access memory (PRAM) is a nonvolatile memory and randomly accesses data to be applied to various semiconductor systems and semiconductor memory devices. It is a trend of research and development.

1 is a block diagram of a nonvolatile memory device 1 according to the prior art.

The nonvolatile memory device 1 includes a driver unit 10, a comparator 20, a global line switch unit 30, a local line switch unit 40, and a memory cell 50.

The memory cell 50 includes a phase change element made of a phase change material.

The driver unit 10 outputs the write current I_CELL to the output node ND at the driving voltage VPP in response to the output signal of the comparator 20.

The memory cell 50 stores data in the phase change element by using the write current I_CELL transferred through the current path.

Here, the current path is a current path through which the write current I_CELL is transferred to the memory cell 50 through the global line switch unit 30, the global line GBL, the local line switch unit 40, and the bit line BL. Say.

The comparator 20 generates an output signal capable of driving the driver 10 by comparing the voltage of the output node ND with respect to the reference voltage VREF. The write current I_CELL is output so that the voltage of the output node ND is brought to the reference voltage VREF.

The reference voltage VREF of the general nonvolatile memory device 1 calculates a voltage required for the memory cell 50 and compares the comparator in the form of a constant voltage having a constant supply voltage regardless of a change in the current path of the load terminal. 20). At this time, the write current I_CELL supplied to the output node ND also has a fixed current level.

Meanwhile, the global line switch unit 30, the global line GBL, the local line switch unit 40, the bit line BL, and the memory cell 50 include a resistance component.

Therefore, the reference voltage VREF required for the memory cell 50 regardless of the load characteristics of the switch unit 30, the global line GBL, the local line switch unit 40, the bit line BL, and the memory cell 50. When the write current I_CELL is outputted based on the resistance current of the global line switch unit 30, the global line GBL, the local line switch unit 40, the bit line BL, and the memory cell 50, By this, the write current I_CELL changes.

In this case, there is a problem that the nonvolatile memory device 1 does not secure a certain operating characteristic due to the changed write current I_CELL.

The present invention provides a nonvolatile memory device that generates a write voltage whose voltage level can vary depending on a resistance component by a current path.

In an embodiment, a semiconductor memory device may include a current path including a global line switch unit, a global line, a local line switch unit, and a bit line; A memory cell configured to receive a write voltage through the current path and store data; And a voltage output unit configured to output the write voltage whose voltage amount varies according to a resistance component included in the current path.

A nonvolatile memory device according to another embodiment of the present invention may include a current path including a global line switch unit, a global line, a local line switch unit, and a bit line; A memory cell receiving a write current through the current path; And a reference voltage generator for varying a reference voltage voltage level according to a resistance component included in the current path.

The present invention can improve the reliability of a nonvolatile memory device by outputting a write voltage whose voltage level can be varied according to a resistance component caused by a current path.

1 is a block diagram of a nonvolatile memory device according to the prior art;
2 is a block diagram of a nonvolatile memory device according to an embodiment of the present invention;
3 is a circuit diagram of a reference voltage generator of FIG. 2;
4 is a block diagram of a nonvolatile memory device according to another embodiment of the present invention.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

2 is a block diagram of a nonvolatile memory device 100 according to an embodiment of the present invention.

The nonvolatile memory device 100 includes a voltage output unit 110, a global line switch unit 120, a local line switch unit 130, and a memory cell 140.

The voltage output unit 110 includes a reference voltage generator 111, a comparison unit 112, and a driver unit 113.

The memory cell 140 includes a phase change element made of a phase change material.

The voltage output unit 110 outputs the write current I_CELL to the output node ND1.

At this time, the voltage level of the output node ND1 becomes the write voltage V_CELL. That is, the voltage output unit 110 outputs the write current I_CELL and the write voltage V_CELL to the output node ND1.

The global line switch unit 120 is connected between the output node ND1 and the global line GBL to determine whether the output node ND1 and the global line GBL are connected. The local line switch unit 130 is connected between the global line GBL and the bit line BL to determine whether the global line GBL and the bit line BL are connected.

The memory cell 140 is connected between the bit line BL and the word line WL and the word line WL is connected to the ground voltage VSS. The memory cell 140 stores data by changing the state of the phase change element by using the write current I_CELL transmitted through the global line switch 120 and the local line switch 130 at the output node ND1. do.

Alternatively, in terms of voltage, the memory cell 140 uses the write voltage V_CELL of the output node ND1 transferred through the global line switch unit 120 and the local line switch unit 130 to determine the state of the phase change element. Change the to save the data.

Here, the transfer path of the write current I_CELL in the direction of the word line WL connection from the output node ND1 is referred to as the current path CP. The current path CP refers to a path through which the write current I_CELL of the output node ND1 is transferred to the memory cell 140. The current path CP is an accessory circuit from the output node ND1 such as the global line switch unit 120, the global line GBL, the local line switch unit 130, and the bit line BL to the memory cell 140. And memory cells 140.

The voltage output unit 110 is connected to the global line switch unit 120, the global line GBL, the local line switch unit 130, the bit line BL, and the memory cell 140 (that is, the current path CP). The write current I_CELL is varied according to the included resistance.

For example, if the resistance included in the current path CP is large, the voltage of the output node ND1 is increased to increase the amount of current of the write current I_CELL. If the resistance included in the current path CP is small, the output node is small. The voltage of (ND1) is reduced to decrease the amount of current of the write current I_CELL.

Alternatively, if the resistance included in the current path CP is large, the voltage level of the write voltage V_CELL applied to the output node ND1 is increased. If the resistance included in the current path CP is small, the output node ND1 is decreased. The voltage of the write voltage V_CELL is reduced by decreasing the voltage of.
The voltage output unit 110 may include a reference voltage generator 111, a comparison unit 112, and a driver unit 113.
The reference voltage generator 111 may include the global line switch unit 120, the global line GBL, the local line switch unit 130, the bit line BL, and the memory cell 140 (that is, the current path CP). Generates a reference voltage VREF that varies according to the resistors included in the resistor.

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For example, if the resistance included in the current path CP is large, the voltage level of the reference voltage VREF is increased and output. If the resistance included in the current path CP is small, the voltage level of the reference voltage VREF is decreased. Output

The comparator 112 compares the reference voltage VREF with the voltage of the output node ND1 and outputs the enable signal EN. When the voltage level of the output node ND1 is lower than the reference voltage VREF, the comparator 112 activates and outputs the enable signal EN, and the voltage level of the output node ND1 is higher than the reference voltage VREF. When high, the enable signal EN is deactivated and output.

The driver 113 outputs the write current I_CELL to the output node ND1 using the driving voltage VPP in response to the activated enable signal EN.

The driver unit 113 is connected between the driving voltage VPP and the output node ND1 and outputs a write current I_CELL to the output node ND1 in response to the enable signal EN. ) May be included.

The comparator 112 and the driver 113 constitute a feed-back circuit. In this manner, the feedback circuit has an advantage in that the voltage of the reference voltage VREF and the output node ND1 are the same within a relatively fast time.

3 is a circuit diagram of the reference voltage generator 111 of FIG. 2.

The reference voltage generator 111 includes a power supply 1111, a current replication unit 1112, and a current path modeling unit 1113.

The power supply 1111 may include a current source, and the current source may be connected between the control node ND2 and the ground voltage VSS. The power supply unit 1111 flows the reference current IREF through the control node ND2, and flows the reference current IREF from the current replication unit 1112 to ground.

On the other hand, when the memory cell 140 of the nonvolatile memory device 100 is a multi-level cell (hereinafter referred to as MLC) capable of storing one or more bits of data per cell, the power supply 1111 is the memory cell 140. According to the data stored in), the size of the reference current (IREF) is determined and output.

The current replica unit 1112 transmits the replica current IICOY to the current path modeling unit 1113.

The current replication unit 1112 may include a plurality of transistors connected to the control node ND2 to drive a current corresponding to the reference current IREF. The plurality of transistors may include a second transistor P2 and a third transistor P3.

The current replica 1112 is connected between the driving voltage VPP and the control node ND2. The source of the second PMOS transistor P2 is connected to the driving voltage VPP and the drain thereof is connected to the control node ND2. The gate of the second PMOS transistor P2 is connected to the control node ND2 and the gate of the third PMOS transistor P3. The source of the third PMOS transistor P3 is connected to the driving voltage VPP and the drain thereof is connected to the output node ND3.

When the power supply unit 1111 outputs the reference current IREF toward the ground voltage VSS, the voltage level of the control node ND2 is lowered. At this time, the second and third PMOS transistors P2 and P3 are turned on. When the second and third PMOS transistors P2 and P3 are turned on, the current copying unit 1112 outputs a copy current IOPOP to the reference voltage output node ND3.

The size of the copy current IOPY is determined according to the size of the reference current IREF and the channels of the second and third PMOS transistors P2 and P3.

2 and 3, the current path modeling unit 1113 is a modeling circuit that duplicates the current path CP including the memory cell 140 in the direction of the word line WL connection from the output node ND2. .

That is, the current path modeling unit 1113 is a circuit including the global line switch unit 121, the global line GBL, the local line switch unit 131, the bit line BL, and the memory cell 141. The global line switch unit 121, the global line GBL, the local line switch unit 131, the bit line BL, and the memory cell 141 are the global line switch unit 120 and the global line (shown in FIG. 2). The GBL, the local line switch unit 130, the bit line BL, and the memory cell 140 may be modeled. In addition, the resistor R1 may be a replica of a resistance component included in the current path CP.

The current path modeling unit 1113 receives the copy current IOPY from the current copying unit 1112 and outputs the reference voltage VREF to the reference voltage output node ND3.

At this time, the reference voltage VREF output from the reference voltage output node ND3 is represented by Equation 1.

Equation  One

Figure 112012107944372-pat00001

Therefore, unlike the prior art, the reference voltage VREF output from the reference voltage generator 111 does not include a voltage level required for the memory cell 140 but compensates for a voltage drop caused by the current path CP. Output As a result, the driver unit 113 outputs the write voltage V_CELL and the write current I_CELL that are varied according to the resistance component of the current path CP, so that the memory cell 140 may perform a more accurate operation. .

As those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features, the embodiments described above should be understood as illustrative and not restrictive in all aspects. Should be. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

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1, 100: nonvolatile memory device 10, 113: current driver
20, 112: comparison unit 30, 120, 121: global line switch unit
40, 130, 131: local line switch section 50, 140, 141: memory cell
110: current output unit 111: reference voltage generation unit
1111: power supply unit 1112: current replicating unit
1113: current path modeling unit

Claims (15)

A current path including a global line switch unit, a global line, a local line switch unit, and a bit line;
A memory cell configured to receive a write voltage through the current path and store data; And
And a voltage output unit configured to output the write voltage whose voltage level is changed according to a resistance component included in the current path to the current path.
Claim 2 has been abandoned upon payment of a set-up fee. The method of claim 1,
The voltage output unit
A reference voltage generator configured to output a reference voltage whose voltage level is changed according to a resistance component modeled by a resistance component included in the current path;
A comparator for comparing the reference voltage and the write voltage to output an enable signal;
And a driver unit supplying a driving voltage to the write voltage in response to the enable signal.
delete Claim 4 has been abandoned upon payment of a setup registration fee. The method of claim 2,
The enable signal is
And a voltage level of the write voltage lower than the reference voltage is activated, and is deactivated if the voltage level of the write voltage is higher than the reference voltage.
Claim 5 was abandoned upon payment of a set-up fee. The method of claim 2,
The reference voltage generator
And forming a current mirror and outputting the reference voltage using a replica current copying a reference current and a resistance component modeled by a resistance component of the current path.
Claim 6 has been abandoned upon payment of a setup registration fee. The method of claim 5,
The reference voltage generator
A power supply unit for flowing a reference current through the control node;
A current copy unit connected to the control node to output a copy current corresponding to the reference current to a reference voltage output node; And
And a current path modeling unit connected to the reference voltage output node and including a resistance component modeling a resistance component of the current path.
Claim 7 was abandoned upon payment of a set-up fee. The method of claim 6,
The power supply unit
And when the memory cell is a multi-level cell, determining and outputting the magnitude of the reference current according to data stored in the memory cell.
Claim 8 has been abandoned upon payment of a set-up fee. The method of claim 6,
The current path modeling unit
And a memory circuit and an accessory circuit included in the current path.
Claim 9 was abandoned upon payment of a set-up fee. The method of claim 6,
The current path modeling unit
And a resistance circuit of the accessory circuit and the memory cell included in the current path.
A current path including a global line switch unit, a global line, a local line switch unit, and a bit line;
A memory cell configured to receive a write current through the current path and store data; And
And a voltage output unit configured to output the write current whose current amount varies according to a resistance component included in the current path through the output node to the current path.
Claim 11 was abandoned upon payment of a set-up fee. The method of claim 10,
The voltage output unit
A reference voltage generator configured to output a reference voltage whose voltage level is changed according to a resistance component modeled by a resistance component included in the current path;
A comparator for comparing the reference voltage with the voltage of the output node and outputting an enable signal;
And a driver unit outputting the write current to the output node in response to the enable signal.
Claim 12 was abandoned upon payment of a set-up fee. The method of claim 11,
The reference voltage generator
And forming a current mirror and outputting the reference voltage using a replica current copying a reference current and a resistance component modeled by a resistance component of the current path.
Claim 13 was abandoned upon payment of a set-up fee. The method of claim 12,
The reference voltage generator
A power supply unit for flowing a reference current through the control node;
A current copy unit connected to the control node and outputting a copy current corresponding to the reference current to a reference voltage output node; And
And a current path modeling unit connected to the reference voltage output node and including a resistance component modeling a resistance component of the current path.
Claim 14 was abandoned upon payment of a set-up fee. The method of claim 13,
The power supply unit
And when the memory cell is a multi-level cell, determining and outputting the magnitude of the reference current according to data stored in the memory cell.
Claim 15 was abandoned upon payment of a set-up fee. The method of claim 13,
The current path modeling unit
And a resistance component modeled by an accessory circuit included in the current path and a resistance component of the memory cell.
KR1020120153555A 2012-12-26 2012-12-26 Nonvaltile Memory Apparatus KR102026208B1 (en)

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JP4712204B2 (en) * 2001-03-05 2011-06-29 ルネサスエレクトロニクス株式会社 Storage device
JP4890016B2 (en) * 2005-03-16 2012-03-07 ルネサスエレクトロニクス株式会社 Nonvolatile semiconductor memory device

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