KR20140088383A

KR20140088383A - Semiconductor apparatus and method of operating the same

Info

Publication number: KR20140088383A
Application number: KR1020130000206A
Authority: KR
Inventors: 이대수
Original assignee: 에스케이하이닉스 주식회사
Priority date: 2013-01-02
Filing date: 2013-01-02
Publication date: 2014-07-10

Abstract

A method of operating a semiconductor device includes the steps of: performing a first read operation of selected memory cells connected to a selected word line using a first level of read voltages of a first level to an nth level of read voltages; And if the first read operation is a failure, the second read operation of the selected memory cells is performed using the selected one of the third to n-th level read voltages according to the read path information .

Description

TECHNICAL FIELD [0001] The present invention relates to a semiconductor device and a method of operating the same,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and an operation method thereof, and more particularly to a semiconductor device capable of data input / output and an operation method thereof.

The threshold voltage of the flash memory cell is determined according to the stored data. In order to increase the degree of integration, as the cell size is reduced and the interval between the cells is narrowed, the interference phenomenon becomes serious, and the threshold voltage of the memory cell is changed by this interference phenomenon.

Meanwhile, in order to store more data in a predetermined area, the memory device operates in an MLC (Multi Level Cell) scheme or a TLC (Triple Level Cell) scheme in which two or more bits of data are stored in one memory cell. In order to store more than two bits of data in one cell, the threshold voltage distribution of the memory cells should be divided into four (erase level and three program levels) or eight (erase level and seven program levels). In such an operation method, it is difficult to secure a sufficient margin between the threshold voltage distributions because the threshold voltages must be distributed within a predetermined voltage range.

In this situation, if the threshold voltage changes due to the interference phenomenon, the margin between the threshold voltage distributions is further reduced, and it becomes difficult to distinguish the level distribution of the threshold voltage, and thus an error may occur.

Embodiments of the present invention provide a semiconductor device and a method of operation thereof that can improve the reliability of operation and improve the operation speed.

A method of operating a semiconductor device according to an embodiment of the present invention includes performing a first read operation of selected memory cells connected to a selected word line using a first level of the read voltages of the first level to the nth level Fail, and if the first read operation is a failure, the selected one of the third to n < th > level read voltages according to the read path information is used to select the pass / fail of the first read operation, And performing a second read operation of the cells.

A semiconductor device according to an embodiment of the present invention includes a memory block including memory cells connected to word lines and a read operation of selected memory cells connected to a selected word line using first to n-th level read voltages And a control circuit for controlling the read operation. When the first read operation using the first level of the read voltage is a fail, the operation of the read path And the control circuit controls the operation circuit to perform the second read operation of the selected memory cells using the selected one of the third to n-th level read voltages according to the information.

Embodiments of the present invention can improve the reliability of operation and improve the operation speed.

1 is a view for explaining a semiconductor memory device according to an embodiment of the present invention.
2 is a diagram for explaining the memory array shown in FIG.
3 is a flowchart illustrating a method of operating a semiconductor device according to an embodiment of the present invention.
4A and 4B are views for explaining a method of operating a semiconductor device according to an embodiment of the present invention.
5 is a flowchart illustrating a method of operating a semiconductor device according to another embodiment of the present invention.
6A to 6C are views for explaining a method of operating a semiconductor device according to another embodiment of the present invention.
7 is a simplified block diagram of a memory system in accordance with an embodiment of the present invention.
8 is a block diagram briefly showing a fusion memory device or a fusion memory system that performs program operation in accordance with various embodiments described above.
9 is a block diagram briefly showing a computing system including a flash memory device according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

1 is a view for explaining a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1, a semiconductor memory device includes a memory array 110 and peripheral circuits 120 to 180. The peripheral circuit includes a control circuit 120, operation circuits 134 and 150 to 170, and a check circuit 180. In the case of a flash memory device, the operation circuit may include a control circuit 120, a voltage supply circuit 134, a read / write circuit 150, a column selection circuit 160 and an input / output circuit 170.

The memory array 110 includes a plurality of memory blocks 110MB. Each memory block 110MB may include a plurality of memory strings ST. The structure of the memory block (110 MB) will be described below.

2 is a diagram for explaining the memory array shown in FIG.

Referring to FIG. 2, each memory block includes a plurality of memory strings ST connected between bit lines BLe0 to BLek, BLo0 to BLok and a common source line SL. That is, the memory strings ST are connected to the corresponding bit lines BLe0 to BLek, BLo0 to BLok, respectively, and are connected in common to the common source line SL. Each memory string ST includes a source select transistor SST having a source connected to the common source line SL, a cell string having a plurality of memory cells Ce00 to Cen0 connected in series, and a drain connected to the bit line BLe0, And a drain select transistor (DST) connected to the gate of the transistor. The memory cells Ce00 to Cen0 included in the cell string are connected in series between the select transistors SST and DST. The gate of the source select transistor SST is connected to the source select line SSL and the gates of the memory cells Ce00 to Cen0 are connected to the word lines WL0 to WLn respectively. Is connected to a drain select line (DSL).

The source select transistor SST controls the connection between the cell strings Ce00 to Cen0 and the common source line SL, Or blocking.

In a NAND flash memory device, memory cells included in a memory cell block can be divided into a physical page unit or a logical page unit. For example, memory cells (Ce00 through Ce0k, Co00 through Co0k) connected to one word line (e.g., WL0) constitute one physical page (PAGE). In addition, even-numbered memory cells Ce00 to Ce0k connected to one word line (e.g., WL0) constitute one even physical page, odd-numbered memory cells Co00 to Co0k constitute one odd physical page . These pages (or even pages and odd pages) are the basic unit of program operation or read operation.

1, the peripheral circuits 120, 134 and 150 to 170 are connected to an erase loop, a program loop and a read operation of memory cells Ce00 to Ce0k or Co00 to Co0k connected to a selected word line (e.g., WL0) . This peripheral circuit includes a control circuit 120 for controlling the program loop, a read operation, and an erase loop, and an operation circuit 134, 150-170 configured to perform a program loop, a read operation and an erase loop under the control of the control circuit 120 ). Vgsl and Vsl to the local lines (SSL, Vss, Vssl, Vsl) of the selected memory block in order to perform the program loop, the read operation and the erase loop, WL0 to WLn and DSL and a common source line SL to control the precharge / discharge of the bit lines BLe0 to BLek or BLo0 to BLok or the bit lines BL0 to BLk or BLo0 to BLo0 to BLk, BLok < / RTI > In particular, the operation circuit 134, 150-170 can be configured to perform the read operation of selected memory cells connected to the selected word line using the first to n-th level read voltages.

In the case of a NAND flash memory device, the operating circuit includes a voltage supply circuit 134, a read / write circuit 150, a column select circuit 160 and an input / output circuit 170. Each component will be described in detail as follows.

The control circuit 120 generates operating voltages Vgpm, Vread, Vpass, Vdsl, and Vssl for performing a program loop, a read operation, or an erase loop in response to a command signal CMD input from the outside through the input / (V_CONTROLs) for controlling the voltage supply circuit 130 so that a predetermined voltage (Vsl, Vsl) can be generated at a desired level. The control circuit 120 then outputs control signals PB_CONTROLs for controlling the circuits PB0 to PBk included in the read / write circuit 140 to perform a program loop, a read operation or an erase loop . When the address signal ADD is input, the control circuit 120 generates the column address signal CADD and the row address signal RADD by these signals, and outputs the same to the control circuit 120.

In particular, the control circuit 120 includes a first storage unit 121 for storing a change condition of a read voltage to be applied to the selected word line during a pre-read operation, and a second storage unit 121 for storing the read path information of the previous word line And a second storage unit 123 for storing the data.

The voltage supply circuit 134 responds to the voltage control signal V_CONTROLs of the control circuit 120 to supply the necessary operating voltages Vgpm, Vread, Vpass, Vdsl, Vssl, And outputs the operating voltages to the local lines (SSL, WL0 to WLn, DSL) and the common source line SL of the selected memory block in response to the row address signal RADD of the control circuit 120 .

In particular, the voltage supply circuit 134 performs a read operation for distinguishing between the erase level and the first program level, a read operation for distinguishing between the first program level and the second program level, the second program level and the third program level (The first level to the n-th level) in the read operation for distinguishing the read voltages from each other. In addition, the voltage supply circuit 134 applies various levels of read voltages to the word lines of selected memory cells in sequence, under control of the control circuit 120, or applies a selected one of the various levels of read voltages to the word line . Specific details will be described later.

To this end, the voltage supply circuit 134 may include a voltage generation circuit 130 and a row decoder 140. The voltage generating circuit 130 generates the operating voltages Vgpm, Vread, Vpass, Vdsl, Vssl and Vsl in response to the voltage control signal V_CONTROLs of the control circuit 120. The row decoder 140, (SSL, WL0 to WLn, DSL) and the common source line SL in response to the row address signal RADD of the selected memory block 110MB.

The output and change of the operation voltages Vgpm, Vread, Vpass, Vdsl, Vssl and Vsl described below are performed by the voltage supply circuit 130 in accordance with the voltage control signal V_CONTROLs of the control circuit 120 .

The read / write circuit 150 may include a plurality of page buffers PB0 to PBk connected to the memory array 110 through bit lines BLe0 to BLek and BLo0 to BLok, respectively. The page buffers PB0 to PBk are connected to the bit lines BLe0 to BLek and BLo0 to BLok in accordance with the PB control signals PB_CONTROLs of the control circuit 120 and the data DATA for storing in the memory cells, Lt; / RTI > (BLe0 to BLek or BLo0 to BLok) after precharging the bit lines (BLe0 to BLek or BLo0 to BLok) according to the PB control signals (PB_CONTROLs) of the control circuit 120 during a program verify operation or a read operation, And latches the data read from the memory cell.

The column selection circuit 160 selects the page buffers PB0 to PBk included in the page buffer group 150 in response to the column address CADD output from the control circuit 120. [ That is, the column selection circuit 160 sequentially transfers the data to be stored in the memory cells to the page buffers PB0 to PBk in response to the column address CADD. The column selection circuit 160 sequentially outputs the page buffers PB0 to PBk in response to the column address CADD so that the data of the memory cells latched in the page buffers PB0 to PBk can be output to the outside by the read operation. ~ PBk).

The input / output circuit 170 transfers the command signal CMD and the address signal ADD input from the outside to the control circuit 120. The input / output circuit 170 transfers externally input data (DATA) to the column selection circuit 160 during a program operation or outputs data read from the memory cells during a read operation to the outside.

The check circuit 180 determines whether a program operation or a read operation is a pass / fail operation according to threshold voltages (or data of memory cells) of the memory cells detected by the program verification operation or the read / And outputs a pass / fail signal (P / F SIGNAL) for the result.

In particular, in the read operation, the check circuit 180 outputs a pass / fail signal (P / F SIGNAL) indicating that the read operation is fail if the error bits of the data read from the memory cells are larger than the allowable value. For example, if the number of error bits of data read from the memory cells is greater than the number of error correction and correction (ECC) operations, a pass / fail signal (P / F SIGNAL) indicating that the read operation is failed do. The check circuit 180 may be an ECC circuit included in the memory controller (see 814 in FIG. 7).

If the check circuit 180 determines that the read operation is failed because the error bit of the data read from the memory cells by the read voltage of the first level is larger than the tolerance, the read path information stored in the second storage unit 123 The control circuit 120 controls the operation circuits 134 and 150 to 170 in order to perform the read operation of the memory cells using the selected one of the third to n-th level read voltages.

In the case of the read operation of the first word line WL0, the operation circuits 134 and 150 to 170 repeatedly perform the read operation while applying the read voltage to the first word line WL0 sequentially from the first level to the n-th level When the read operation is passed, the control circuit 120 controls the number of times the read operation is performed until the read operation is passed or the level of the read voltage applied to the first word line when the read operation is passed, 123 as lead path information. Here, the first level may be the highest level and the n-th level may be the lowest level. Conversely, the first level may be the lowest and the n-th level may be the highest level.

Hereinafter, a specific operation method of the semiconductor device will be described.

3 is a flowchart illustrating a method of operating a semiconductor device according to an embodiment of the present invention. 4A and 4B are views for explaining a method of operating a semiconductor device according to an embodiment of the present invention.

Referring to FIGS. 1, 3 and 4A, in step S301, a read operation of memory cells connected to the first word line WL0 of the memory block is performed. The read path information stored in the second storage unit 123 of the control unit 120 is obtained through a read operation. Therefore, the read path information can be obtained first through the read operation of the first word line WL0.

The operation circuits 134 and 150 to 170 are controlled by the read voltage Vread of the first level R1 to the first word line WL0 in accordance with the read voltage change condition stored in the first storage unit 121 of the control circuit 120, ). The read voltage change condition may include a level of the read voltage applied for the first time in the read operation, a voltage difference between the read voltages, an allowable number of times of the read operation, and the like. The read voltage of the first level R1 is applied at a level corresponding to the level between the two program levels in order to distinguish between two program levels (or threshold voltage distributions) A, B.

On the other hand, the operation circuits 134 and 150 to 170 pre-charge the bit lines BLe0 to BLek or BLo0 to BLok before applying the read voltage and apply the read pass voltage Vpass to the unselected word lines WL1 to WLn ) Can be applied.

After the read voltage is applied, the operation circuits 134 and 150 to 170 sense a voltage change or a current amount of the bit lines BLe0 to BLek or BLo0 to BLok and store the sensing result as data stored in the memory cells.

If the interference phenomenon becomes severe during a program operation for storing data in memory cells, the threshold voltages of the peripheral memory cells in which the program operation is completed can be increased. As a result, a memory cell in which the threshold voltage is higher than the read voltage is generated. Such cells become defective cells (FC), and data read out from defective cells (FC) become error bits.

In step S303, the check circuit 180 determines whether the error bit of the data read by the operation circuits 134 and 150 to 170 is larger than the allowable value, and determines whether the read operation is pass / fail according to the result do. That is, the check circuit 180 determines whether error bits included in the read data can be corrected by an error detection correcting operation, and determines whether to pass or fail the read operation according to the result.

If it is determined by the check circuit 180 that the read operation is failed, the read voltage is changed from the first level R1 to the second level R2 in accordance with the read voltage change condition of the control circuit 120 in step S305 do.

The operation circuits 134 and 150 to 170 apply the read voltage Vread of the second level R2 to the first word line WL0 and store the data read from the memory cells do.

Then, in step S303, the check circuit 180 determines whether the error bit of the data read by the operation circuits 134, 150 to 170 is larger than the allowable value, and determines whether the read / .

Steps S301 to S305 are repeated until it is determined that the read operation is a pass.

1, 3, and 4B, if the number of error bits in the data read by the read voltage Vread at the fifth level R5 falls within the allowable range, the check circuit 180 determines that the read operation is a pass .

In this case, in step S307, the control circuit 120 stores the read path information in the second storage unit 123. [ At this time, the read path information may include the level of the read voltage applied to the word line when the read operation is passed. In addition, the read path information may include the number of times the read operation of the first word line is repeatedly performed until the read operation is passed.

In this way, the read path information is stored in the second storage unit 123 of the control circuit 120.

Hereinafter, the read operation of the remaining word lines will be described.

5 is a flowchart illustrating a method of operating a semiconductor device according to another embodiment of the present invention. 6A to 6C are views for explaining a method of operating a semiconductor device according to another embodiment of the present invention.

1, 5, and 6A, the read operation of the memory cells connected to the selected word line (e.g., WL1) is performed in step S501.

The operation circuits 134 and 150 to 170 are controlled by the read voltage Vread of the first level R1 to the selected word line WL1 according to the read voltage change condition stored in the first storage unit 121 of the control circuit 120, And stores the data read from the memory cells.

In step S503, the check circuit 180 determines whether the error bit of the data read from the memory cells of the selected word line WL1 is larger than the allowable value, and determines whether or not the read operation is pass / fail depending on the result . That is, the check circuit 180 determines whether or not the error bits read from the defective cells FC can be corrected by the error detection correcting operation, and determines whether to pass or fail the read operation according to the result.

Referring to FIGS. 1, 5 and 6B, if it is determined by the check circuit 180 that the read operation is a failure, in step S505 the read path condition stored in the second storage unit 123 of the control circuit 120 The read voltage is changed from the first level (R1) to the fifth level (R5). Since the read operation is judged to fail even by using the read voltages of the second level (R2) to the fourth level (R4) during the read operation of the first word line (WL0), the second level (R2) Lt; RTI ID = 0.0 > R4. &Lt; / RTI > Therefore, the number of times of the read operation can be reduced.

If the read operation is passed by the read voltage Vread of the second level in the read operation of the first word line WL0, the read voltage is changed from the first level R1 to the second level R2. In this case, the read voltage is changed to the same setting as the setting based on the read voltage change condition.

However, when the read operation is passed by the third level read voltage Vread in the read operation of the first word line WL0, the read voltage is changed from the first level R1 to the third level R3. In this case, the read voltage is changed by the setting based on the read voltage information and the setting based on the read path information.

In step S507, the operation circuits 134 and 150 to 170 apply the read voltage Vread of the fifth level R5 to the selected word line WL1 and store the data read from the memory cells.

In step S509, the check circuit 180 determines whether the error bit of the data read by the operation circuits 134 and 150 to 170 is larger than the allowable value, and determines whether the read operation is a pass / fail operation .

If it is determined that the read operation is a pass, the read operation is terminated. However, the feed path information may be re-stored in the second storage unit 123 of the control circuit 120 formally in step S513.

Although the read operation of the first word line WL0 is passed by the read voltage of the fifth level R5, the read operation of the selected word line WL1 may be failed by the read voltage of the fifth level R5 .

Referring to FIGS. 1, 5 and 6C, when the read operation of the selected word line WL1 using the read voltage of the fifth level R5 is failed, in step S511, The read voltage Vread is changed from the fifth level R5 to the next level R6 according to the read voltage change condition stored in the memory unit 121. [

The operation circuits 134 and 150 to 170 apply the read voltage Vread at the sixth level R6 to the selected word line WL1 and store the data read from the memory cells at step S507 .

If it is determined that the read operation is a pass, the control unit 120 may re-store the read path information in the second storage unit 123 in step S513. Since the read operation is performed by the read voltage of the sixth level (R6) other than the fifth level (R5), the read path information can be updated in accordance with the changed information.

When the read operation of the next word line WL2 using the read voltage Vread of the first level R1 is failed due to the update of the read path information, the read voltage is changed from the first level R1 to the sixth level R6). Thus, the change of the read voltage can be changed in accordance with the read path information generated in the read operation of the previous word line.

As described above, the reliability of the read operation can be improved by changing the read voltage, and the operation speed can be improved by changing the read voltage according to the read path information.

7 is a simplified block diagram of a memory system in accordance with an embodiment of the present invention.

Referring to FIG. 7, a memory system 700 according to an embodiment of the present invention includes a non-volatile memory device 720 and a memory controller 710.

The nonvolatile memory device 720 may be constituted by the above-described semiconductor memory device. The memory controller 710 will be configured to control the non-volatile memory device 720. May be provided as a memory card or a solid state disk (SSD) by the combination of the nonvolatile memory device 720 and the memory controller 710. [ The SRAM 711 is used as an operation memory of the processing unit 712. The host interface 713 has a data exchange protocol of the host connected to the memory system 700. The error correction block 714 detects and corrects errors included in data read from the nonvolatile memory device 720. The check circuit 170 described with reference to FIG. 1 may be an ECC circuit or an error correction block 714. The memory interface 715 interfaces with the nonvolatile memory device 720 of the present invention. The processing unit 712 performs all control operations for data exchange of the memory controller 710.

Although it is not shown in the drawing, the memory system 700 according to the present invention can be further provided with a ROM (not shown) or the like for storing code data for interfacing with a host, To those who have learned. The non-volatile memory device 720 may be provided in a multi-chip package comprising a plurality of flash memory chips. The memory system 700 of the present invention can be provided as a highly reliable storage medium with a low probability of occurrence of errors. In particular, the flash memory device of the present invention can be provided in a memory system such as a solid state disk (SSD) which has been actively studied recently. In this case, the memory controller 710 is configured to communicate with external (e.g., host) through one of various interface protocols such as USB, MMC, PCI-E, SATA, PATA, SCSI, ESDI, will be.

8 is a block diagram briefly showing a fusion memory device or a fusion memory system that performs program operation in accordance with various embodiments described above. For example, the technical features of the present invention can be applied to the one-nAND flash memory device 800 as a fusion memory device.

The NAND flash memory device 800 includes a host interface 810 for exchanging various information with devices using different protocols, a buffer RAM 820 for embedding codes for driving the memory devices or temporarily storing data, A control unit 830 for controlling read, program and all states in response to a control signal and an instruction given from the outside, a command and an address, and a configuration for defining a system operation environment in the memory device And a NAND flash cell array 850 configured with an operation circuit including a nonvolatile memory cell and a page buffer. The memory array of the NAND flash cell array 850 is applied to the memory array shown in FIG.

9, a computing system including a flash memory device 912 in accordance with the present invention is schematically illustrated.

The computing system 900 in accordance with the present invention includes a modem 950 electrically coupled to the system bus 960, a RAM 930, a user interface 940, a modem 950 such as a baseband chipset, Memory system 910. When the computing system 900 according to the present invention is a mobile device, a battery (not shown) for supplying the operating voltage of the computing system 900 will additionally be provided. Although it is not shown in the drawing, it is to be appreciated that the computing system 800 in accordance with the present invention may be further provided with application chipsets, camera image processors (CIS), mobile DRAMs, It is obvious to those who have acquired knowledge. The memory system 910 may constitute, for example, a solid state drive / disk (SSD) using nonvolatile memory for storing data. Alternatively, the memory system 910 may be provided as a fusion flash memory (e.g., a one-nAND flash memory).

110: memory array 110 MB: memory block
ST: String PAGE: Page
120: control circuit 134: voltage supply circuit
130: voltage generation circuit 140:
150: Page buffer group PB0 to PBk: Page buffer
160: column selection circuit 170: input / output circuit
180: Check circuit

Claims

Performing a first read operation of selected memory cells coupled to a selected word line using the first level of read voltages of a first level to an nth level of read voltages;
Determining a path / fail of the first read operation; And
And performing a second read operation of the selected memory cells using the selected one of the third to n-th level read voltages according to the read path information if the first read operation is a failure A method of operating a semiconductor device.

The semiconductor memory device according to claim 1, wherein before performing the first read operation,
And setting the read path information.

3. The method of claim 2, wherein the setting of the read path information comprises:
Repeating the third read operation of the first memory cells connected to the first word line while applying the first level to the n-th level of read voltages to the first word line of the memory block including the selected memory cells step;
Determining a pass / fail of the third read operation every time the third read operation is performed; And
And storing the read path information of the first memory cells when the third read operation is passed.

The method of claim 3,
When the third read operation is repeatedly performed, the first to n-th level read voltages are sequentially applied to the selected word line in accordance with a read voltage change condition.

The method of claim 3,
Wherein the read path information includes the number of times the third read operation is repeatedly performed.

The method of claim 3,
And the read path information includes a level of a read voltage applied to the selected word line when the third read operation is passed.

The method according to claim 1,
Wherein the read path information includes the number of times the read operation of the first word line is repeated until the read operation of the first word line of the memory block including the selected memory cells is passed.

The method according to claim 1,
Wherein the read path information includes the number of times the read operation of the previous word line is repeated until the read operation of the previous word line is passed.

The method according to claim 1,
Wherein the read path condition includes a level of a read voltage applied to the first word line when a read operation of a first word line of a memory block including the selected memory cells is passed.

The method according to claim 1,
Wherein the read path condition includes a level of a read voltage applied to the previous word line when the read operation of the previous word line is passed.

The method according to claim 1,
Determining a pass / fail of the second read operation; And
And re-executing the second read operation using the next level of the read voltage in accordance with the read voltage application condition if the second read operation is a failure.

12. The method of claim 11,
And changing the read path information if the second read operation is passed after re-execution of the second read operation.

The method according to claim 1,
And the read voltage of the first level is the read voltage of the highest level.

The method according to claim 1,
And the first-level read voltage is the lowest-level read voltage.

2. The method of claim 1, wherein the determining of the pass / fail of the first read operation comprises:
And determining that the first read operation is failed if the number of error bits of data read from the selected memory cells is larger than the allowable value.

A memory block including memory cells coupled to word lines;
An operation circuit configured to perform a read operation of selected memory cells connected to a selected word line using first to n-th level read voltages;
A check circuit for checking the pass / fail of the read operation; And
And a control circuit for controlling the read operation,
If the first read operation using the first level of the read voltage is a failure, the second lead of the selected memory cells, using the selected one of the third to n-th level read voltages, And the control circuit controls the operation circuit to perform an operation.

17. The method of claim 16,
The operation circuit repeatedly performs the read operation of the first memory cells connected to the first word line while sequentially applying the first level to the n-th level of read voltages to the first word line of the memory block,
When the read operation of the first memory cells is passed, the control circuit controls the number of times the read operation is performed until the read operation is passed, or the number of times of the read operation applied to the first word line Level as the read path information.

17. The method of claim 16, wherein if the second lead operation is a fail,
And the operation circuit is configured to re-execute the second read operation by using a read voltage of the next level in accordance with a read voltage change condition of the control circuit.

19. The method of claim 18,
And the control circuit is configured to change the read path information when the second read operation is passed after being re-executed.

17. The method of claim 16,
And the read voltage of the first level is set to a read voltage of the lowest level in accordance with a read voltage change condition of the control circuit.

17. The method of claim 16,
And the read voltage of the first level is set to the read voltage of the highest level in accordance with the read voltage change condition of the control circuit.

17. The method of claim 16,
Wherein the check circuit is configured to determine the read operation as fail if the number of error bits of data read by the read operation is larger than a tolerance value.

23. The method of claim 22,
Wherein the check circuit includes an error search correction circuit of a memory controller.