KR20140028718A - Semiconductor memory device and method of operating the same - Google Patents
Semiconductor memory device and method of operating the same Download PDFInfo
- Publication number
- KR20140028718A KR20140028718A KR1020120095651A KR20120095651A KR20140028718A KR 20140028718 A KR20140028718 A KR 20140028718A KR 1020120095651 A KR1020120095651 A KR 1020120095651A KR 20120095651 A KR20120095651 A KR 20120095651A KR 20140028718 A KR20140028718 A KR 20140028718A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
- G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
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Abstract
Description
The present invention relates to a semiconductor memory device and a method of operating the same, and more particularly, to a semiconductor memory device including a nonvolatile memory cell and a method of operating the same.
The NAND flash memory device is a typical nonvolatile memory device. The MLC stores two bits of data including least significant bit (LSB) data and most significant bit (MSB) data in one memory cell to increase data storage capacity. It works mainly by (Multi Level Cell) method.
Two bits of data stored in the memory cell are classified according to the threshold voltage level of the memory cell. In other words, according to two bits of data stored in the memory cell, the threshold voltage of the memory cell becomes one of an erase level and one of the first to third program levels.
In order to increase the degree of integration of the device, the size of the memory cells is reduced and the spacing of the memory cells is narrowed. As a result, while a program operation for storing data is performed, interference occurs between adjacent memory cells connected to the same word line, and interference occurs between adjacent memory cells connected to different word lines. Is generated. Due to such interference, an error may occur because a threshold voltage of a memory cell in which a program operation is completed is changed.
An embodiment of the present invention provides a semiconductor memory device and an operation method thereof that can improve the reliability of the operation.
A semiconductor memory device according to an embodiment of the present invention provides a memory array including memory cells and flag cells connected to word lines, and LSB data and MSB data, respectively, in memory cells connected to a selected word line among the word lines. Before performing the LSB program loop and the MSB program loop, and applying the first read voltage to the selected word line to read LSB data, and applying the second read voltage to the selected word line, the flag cell Peripheral circuitry configured to perform an operation of reading the flag data of the device.
A method of operating a semiconductor memory device according to an embodiment of the present invention includes performing an LSB program loop for storing LSB data in an LSB page of a selected word line, and applying LSD data to a selected word line by applying a first read voltage. Reading the flag data, reading the flag data of the flag cells connected to the selected word line by applying a second read voltage to the selected word line, and not storing the MSB data in the MSB page of the word line selected by the flag data. If not, then executing an MSB program loop to store the MSB data in the MSB page.
Embodiments of the present invention can improve the reliability of the operation.
1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention.
FIG. 2 is a circuit diagram illustrating the memory blocks shown in FIG. 1.
3 is a flowchart illustrating a method of operating a semiconductor memory device according to an embodiment of the present invention.
4 is a view for explaining a method of operating a semiconductor memory device according to an embodiment of the present invention.
5A and 5B are distribution diagrams illustrating a method of operating a semiconductor memory device according to an exemplary embodiment of the present invention.
6 is a simplified block diagram of a memory system in accordance with an embodiment of the present invention.
7 is a simplified block diagram illustrating a fusion memory device or a fusion memory system that performs program operations in accordance with various embodiments described above.
8 is a block diagram briefly illustrating a computing system including a flash memory device according to an embodiment of the present invention.
Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention.
Referring to FIG. 1, a semiconductor device includes a
The
FIG. 2 is a circuit diagram illustrating the memory blocks shown in FIG. 1.
Referring to FIG. 2, each memory block includes a plurality of memory strings ST connected between bit lines BLe0 to BLek, BLo0 to BLok, FBLe, and FBLo and a common source line SL. That is, the memory strings ST are connected to the corresponding bit lines BLe0 to BLek, BLo0 to BLok, FBLe, and FBLo, respectively, and are commonly connected to the common source line SL. Each memory string ST includes a source select transistor SST having a source connected to the common source line SL, a cell string having a plurality of memory cells Ce00 to Cen0 connected in series, and a drain connected to the bit line BLe0, And a drain select transistor (DST) connected to the gate of the transistor. The memory cells Ce00 to Cen0 included in the cell string are connected in series between the select transistors SST and DST. The gate of the source select transistor SST is connected to the source select line SSL and the gates of the memory cells Ce00 to Cen0 are connected to the word lines WL0 to WLn respectively. Is connected to a drain select line (DSL).
The source select transistor SST controls the connection between the cell strings Ce00 to Cen0 and the common source line SL, Or blocking.
The memory strings ST connected to the bit lines FBLe and FBLo among the memory strings ST include flag cells FCe0 and FCo0 instead of memory cells. The flag cells FCe0 and FCo0 operate by operating voltages applied to the word lines WL0 to WLn together with the memory cells. Such flag cells FCe0 and FCo0 may store information related to program states of memory cells. For example, information about whether 1 bit data or 2 bits data is stored in the memory cells Ce00 to Ce0k and Co00 to Co0k may be stored in the flag cells FCe0 and FCo0. That is, when only the LSB program operation is performed and only LSB data is stored in the memory cells Ce00 to Ce0k and Co00 to Co0k, '1' data is stored in the flag cells FCe0 and FCo0, and the LSB program operation and the MSB program operation are performed. When two bits of data including LSB data and MSB data are stored in the memory cells Ce00 to Ce0k and Co00 to Co0k, '0' data may be stored in the flag cells FCe0 and FCo0.
In the NAND flash memory device, memory cells included in a memory cell block may be divided into physical page units or logical page units. For example, memory cells Ce00 to Ce0k and Co00 to Co0k and flag cells FCe0 and FCo0 connected to one word line WL0 form one physical page PAGE. In addition, even-numbered memory cells Ce00 to Ce0k1 and the flag cell FCe0 connected to one word line (eg, WL0) constitute one even physical page, and odd-numbered memory cells Co00 to Co0k are flag cells. (FCo0) may constitute one odd physical page. These pages (or even pages and odd pages) are the basic unit of program operation or read operation.
Referring back to FIGS. 1 and 2, the
The
In response to the voltage control signal CMDv of the
To this end, the
As such, the output and change of the operating voltages Verase, Vpgm, Vread, Vpass, Vvfy, Vdsl, Vssl, and Vsl described below are controlled by the
The
The
The input /
The
3 is a flowchart illustrating a method of operating a semiconductor memory device according to an embodiment of the present invention. 4 is a view for explaining a method of operating a semiconductor memory device according to an embodiment of the present invention. 5A and 5B are distribution diagrams illustrating a method of operating a semiconductor memory device according to an exemplary embodiment of the present invention.
1, 3, 4, and 5A, an LSB program loop for storing LSB data in an LSB page of a word line (eg, WLm) selected in step S301 is performed. The LSB program loop includes an LSB program operation and an LSB program verify operation. If the LSB page is divided into an even LSB page and an odd LSB page, the LSB program loop is an even LSB program loop for storing even LSB data in the even LSB page, and an odd LSB for storing even odd LSB data in the odd LSB page. It can be implemented by being divided into program loops. Even LSB program loop and odd LSB program loop are implemented in the same way according to the stored data, except that only the stored data is different. Therefore, only one LSB program loop will be described.
To this end, the
Subsequently, the odd LSB program loop for storing odd LSB data in the odd LSB page of the selected word line WLm proceeds in the same manner as the even LSB program loop. Thus, the LSB program loop for storing LSB data in the LSB page of the selected word line WLm is completed.
Meanwhile, the LSB program loop of the selected word line WLm has completed storing LSB data in the LSB page of the word line WLm-1 adjacent to the selected word line WLm to one side (eg, to the source select line). This may be done before storing the MSB data in the MSB page of the word line WLm-1. After the LSB program loop of the selected word line WLm is completed, the MSB program loop for storing MSB data in the MSB page of the adjacent word line WLm-1 is completed. Subsequently, the LSB program loop for storing LSB data in the LSB page of the word
As the LSB program loop of the selected word line WLm is completed, the threshold voltages of the memory cells EMC and OMCell are divided into an erase level and a program level PV2. However, the threshold voltages of the flag cells EFCell and OFCell are distributed in the erase level.
Meanwhile, since the LSB program loop of the selected word line WLm is divided into an even LSB program loop and an odd LSB program loop, interference occurs in the even flag cell EFCell during the odd LSB program loop, and thus the even flag is performed. The threshold voltage of the cell FCell may change. In addition, while the MSB program loop and the LSB program loop of the adjacent word lines WLm-1 and WLm + 1 are implemented, interference occurs in the flag cells EFCell and OFCell, so that thresholds of the flag cells EFCell and OFCell are generated. The voltage can change. For example, the threshold voltages of the flag cells EFCell and OFCell increase to widen the threshold voltage distribution, and in some cases, the threshold voltage may be higher than the first read voltage R1 due to an interference phenomenon.
In step S303, MSB data for storing in the MSB page of the selected word line WLm is input to the
In step S305, an LSB read operation for reading LSB data (or even LSB data) stored in the LSB page (or even LSB page) of the selected word line WLm is performed. To this end, the
In step S307, a flag read operation for reading flag data (or even flag data) from the flag cell (or even flag cell) EFCell of the selected word line WLm is performed. To this end, the
Here, the LSB data and the flag data may be simultaneously read by applying the read voltage Vread of the first level R1. However, since the threshold voltage of the flag cell may be higher than the first level R1 due to the interference phenomenon, when some flag cells are read at the read voltage Vread of the first level R1, some flag cells are sensed in the program state. Error may occur. Therefore, the read operation of the flag data is preferably performed by using the read voltage of the second level R2 higher than the first level R1. Here, the first level R1 corresponds between the erase level PV0 and the first program level PV1, and the second level R2 corresponds to the first program level PV1 and the second program level PV2. It may correspond to between.
In step S309, when the flag data is '1', that is, when the threshold voltage of the flag cell is sensed to the erase level, it is determined that the MSB data is not stored in the MSB page of the selected word line WLm. In S311, the
Referring to FIG. 5B, after the even MSB data is stored in the even MSB page of the selected word line WLm, threshold voltages of the even memory cells EMC may be set according to the even LSB data and the even MSB data. The threshold voltages of the even flag cell EFCell are divided into the first to third program levels PV1 to PV3, and the threshold voltages of the even flag cell EFCell are divided into an erase level PV0 and a third program level PV3. That is, the threshold voltage of the even flag cell EFCell is raised to the third program level PV3 during the MSB program loop. When the MSB program loop is not implemented, the threshold voltage of the even flag cell EFCell maintains the erase level PV0.
If the even flag data is '0' in step S309, that is, if the threshold voltage of the even flag cell is sensed to be raised to the program level, the even MSB page of the selected word line WLm is determined. It is determined that the data is stored, and the
When the even MSB program loop is completed, as described above, the odd MSB data is input to the
Thus, even if the threshold voltages of the flag cells EFCell and OFCell are changed by an interference phenomenon during the program loop, the flag is read using the read voltage R2 different from the read voltage R1 for reading LSB data. By reading the data, it is possible to read the flag data accurately and improve the reliability of the operation.
6 is a simplified block diagram of a memory system in accordance with an embodiment of the present invention.
Referring to FIG. 6, a
The
May be provided as a memory card or a solid state disk (SSD) by the combination of the
Although it is not shown in the drawing, the
7 is a simplified block diagram illustrating a fusion memory device or a fusion memory system that performs program operations in accordance with various embodiments described above. For example, the technical features of the present invention can be applied to a one-nAND
The one NAND
8, a computing system including a
A
110:
ST: String PAGE: Page
120: control circuit 130: voltage supply circuit
131: voltage generation circuit 133: low decoder
140: page buffer group PB0 to PBk: page buffer
150: column selection circuit 160: input / output circuit
Claims (14)
Reading the LSB data by applying a first read voltage to the selected word line;
Reading flag data of flag cells connected to the selected word line by applying a second read voltage to the selected word line; And
And if it is determined that the MSB data is not stored in the MSB page of the selected word line by the flag data, performing an MSB program loop for storing the MSB data in the MSB page. .
Threshold voltages of the memory cells connected to the selected word line are divided into erase levels and first to third program levels according to the LSB data and the MSB data.
Threshold voltages of the flag cells are divided into the erase level and the third program level according to the MSB data.
And operating the second read voltage higher than the first read voltage.
The level of the first read voltage corresponds between an erase level and a first program level, and the level of the second read voltage corresponds between the first program level and a second program level higher than the first program level. How the memory device works.
And after the storage of the MSB data is completed in the MSB page of the word line adjacent to the selected word line, the LSB data and the flag data are read.
And after the storage of the LSB data is completed in the LSB page of the selected word line and the word line adjacent to the other side, the LSB data and the flag data are read.
And if the MSB data is stored in the MSB page of the selected word line by the flag data, the MSB program loop is stopped.
An LSB program loop and an MSB program loop for storing LSB data and MSB data, respectively, in memory cells connected to a selected word line among the word lines, and a first read to the selected word line before the MSB program loop is executed. And a peripheral circuit configured to apply the voltage to read the LSB data and to apply the second read voltage to the selected word line to read the flag data of the flag cells.
Threshold voltages of the memory cells are divided into erase levels and first to third program levels according to the LSB data and the MSB data.
Threshold voltages of the flag cells are divided into the erase level and the third program level according to the MSB data.
And the peripheral circuit applies the second read voltage higher than the first read voltage.
The peripheral circuit applies the first read voltage at a level between an erase level and a first program level, and applies the second read voltage to a level between the first program level and a second program level higher than the first program level. The semiconductor memory device is applied to.
And the peripheral circuit is configured to read the LSB data and the flag data after the storage of the MSB data is completed in the MSB page of the word line adjacent to the selected word line.
And the peripheral circuit is configured to read the LSB data and the flag data after the storage of LSB data is completed in the LSB page of the selected word line and the word line adjacent to the other side.
And the peripheral circuit is configured to stop the MSB program loop when it is determined by the flag data that MSB data is stored in the MSB page of the selected word line.
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KR1020120095651A KR20140028718A (en) | 2012-08-30 | 2012-08-30 | Semiconductor memory device and method of operating the same |
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KR1020120095651A KR20140028718A (en) | 2012-08-30 | 2012-08-30 | Semiconductor memory device and method of operating the same |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
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CN106205712A (en) * | 2015-01-20 | 2016-12-07 | 爱思开海力士有限公司 | Semiconductor storage unit and operational approach thereof |
CN107230496A (en) * | 2016-03-25 | 2017-10-03 | 三星电子株式会社 | Reading/the verification operation and control method of memory devices |
CN109935267A (en) * | 2017-12-19 | 2019-06-25 | 爱思开海力士有限公司 | Semiconductor memory system and its operating method |
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KR20100106761A (en) * | 2009-03-24 | 2010-10-04 | 주식회사 하이닉스반도체 | Program method of flash device |
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KR20080094246A (en) * | 2007-04-19 | 2008-10-23 | 삼성전자주식회사 | A nonvolatile memory device, memory sysem having its and method of lsb reading the same |
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CN106205712A (en) * | 2015-01-20 | 2016-12-07 | 爱思开海力士有限公司 | Semiconductor storage unit and operational approach thereof |
CN106205712B (en) * | 2015-01-20 | 2020-06-26 | 爱思开海力士有限公司 | Semiconductor memory device and method of operating the same |
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CN109935267B (en) * | 2017-12-19 | 2023-07-25 | 爱思开海力士有限公司 | Semiconductor memory device and method of operating the same |
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