KR20140028718A - Semiconductor memory device and method of operating the same - Google Patents

Semiconductor memory device and method of operating the same Download PDF

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Publication number
KR20140028718A
KR20140028718A KR1020120095651A KR20120095651A KR20140028718A KR 20140028718 A KR20140028718 A KR 20140028718A KR 1020120095651 A KR1020120095651 A KR 1020120095651A KR 20120095651 A KR20120095651 A KR 20120095651A KR 20140028718 A KR20140028718 A KR 20140028718A
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South Korea
Prior art keywords
data
msb
lsb
word line
program
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KR1020120095651A
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Korean (ko)
Inventor
임경훈
이근우
김태균
이혜령
안치욱
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에스케이하이닉스 주식회사
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Priority to KR1020120095651A priority Critical patent/KR20140028718A/en
Publication of KR20140028718A publication Critical patent/KR20140028718A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series

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Abstract

A method for operating a semiconductor memory device includes the steps of: performing an LSB program loop for storing LSB data in an LSB page of a selected word line; reading the LSB data by applying a first read voltage to the selected word line; reading flag data of flag cells connected to the selected word line by applying a second read voltage to the selected word line; and performing an MSB program loop to store MSB data in an MSB page if it is determined that the MSB data is not stored in the MSB page of the selected word line by the flag data. [Reference numerals] (AA) Start; (BB) No; (CC) Yes; (DD) End; (S301) LSB program of a memory cell; (S303) Input an MSB data; (S305) LSB read operation of the memory cell (Vread = R1); (S307) Read operation of a flag cell (Vread = R2); (S309) Flag cell data = 1?; (S311) Complete an MSB program loop of the memory cell

Description

Semiconductor memory device and method of operating same

The present invention relates to a semiconductor memory device and a method of operating the same, and more particularly, to a semiconductor memory device including a nonvolatile memory cell and a method of operating the same.

The NAND flash memory device is a typical nonvolatile memory device. The MLC stores two bits of data including least significant bit (LSB) data and most significant bit (MSB) data in one memory cell to increase data storage capacity. It works mainly by (Multi Level Cell) method.

Two bits of data stored in the memory cell are classified according to the threshold voltage level of the memory cell. In other words, according to two bits of data stored in the memory cell, the threshold voltage of the memory cell becomes one of an erase level and one of the first to third program levels.

In order to increase the degree of integration of the device, the size of the memory cells is reduced and the spacing of the memory cells is narrowed. As a result, while a program operation for storing data is performed, interference occurs between adjacent memory cells connected to the same word line, and interference occurs between adjacent memory cells connected to different word lines. Is generated. Due to such interference, an error may occur because a threshold voltage of a memory cell in which a program operation is completed is changed.

An embodiment of the present invention provides a semiconductor memory device and an operation method thereof that can improve the reliability of the operation.

A semiconductor memory device according to an embodiment of the present invention provides a memory array including memory cells and flag cells connected to word lines, and LSB data and MSB data, respectively, in memory cells connected to a selected word line among the word lines. Before performing the LSB program loop and the MSB program loop, and applying the first read voltage to the selected word line to read LSB data, and applying the second read voltage to the selected word line, the flag cell Peripheral circuitry configured to perform an operation of reading the flag data of the device.

A method of operating a semiconductor memory device according to an embodiment of the present invention includes performing an LSB program loop for storing LSB data in an LSB page of a selected word line, and applying LSD data to a selected word line by applying a first read voltage. Reading the flag data, reading the flag data of the flag cells connected to the selected word line by applying a second read voltage to the selected word line, and not storing the MSB data in the MSB page of the word line selected by the flag data. If not, then executing an MSB program loop to store the MSB data in the MSB page.

Embodiments of the present invention can improve the reliability of the operation.

1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention.
FIG. 2 is a circuit diagram illustrating the memory blocks shown in FIG. 1.
3 is a flowchart illustrating a method of operating a semiconductor memory device according to an embodiment of the present invention.
4 is a view for explaining a method of operating a semiconductor memory device according to an embodiment of the present invention.
5A and 5B are distribution diagrams illustrating a method of operating a semiconductor memory device according to an exemplary embodiment of the present invention.
6 is a simplified block diagram of a memory system in accordance with an embodiment of the present invention.
7 is a simplified block diagram illustrating a fusion memory device or a fusion memory system that performs program operations in accordance with various embodiments described above.
8 is a block diagram briefly illustrating a computing system including a flash memory device according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 1, a semiconductor device includes a memory array 110 and peripheral circuits 120 to 160. The peripheral circuit includes a control circuit 120 and operation circuits 130 to 160. In the case of a flash memory device, the operation circuit is configured to perform a read operation, a program loop (program operation and program verify operation) and an erase loop (erase operation and erase verify operation) of the memory cells, and the voltage supply circuit 130, page The buffer group 140, the column select circuit 150, and the input / output circuit 160 may be included. The control circuit 120 controls the program loop (program operation and program verify operation) and the erase loop (erase operation and erase verify operation) of the operation circuits 130 to 160.

The memory array 110 includes a plurality of memory blocks 110MB. Each memory block 110MB may include a plurality of memory strings ST. The structure of the memory block (110 MB) will be described below.

FIG. 2 is a circuit diagram illustrating the memory blocks shown in FIG. 1.

Referring to FIG. 2, each memory block includes a plurality of memory strings ST connected between bit lines BLe0 to BLek, BLo0 to BLok, FBLe, and FBLo and a common source line SL. That is, the memory strings ST are connected to the corresponding bit lines BLe0 to BLek, BLo0 to BLok, FBLe, and FBLo, respectively, and are commonly connected to the common source line SL. Each memory string ST includes a source select transistor SST having a source connected to the common source line SL, a cell string having a plurality of memory cells Ce00 to Cen0 connected in series, and a drain connected to the bit line BLe0, And a drain select transistor (DST) connected to the gate of the transistor. The memory cells Ce00 to Cen0 included in the cell string are connected in series between the select transistors SST and DST. The gate of the source select transistor SST is connected to the source select line SSL and the gates of the memory cells Ce00 to Cen0 are connected to the word lines WL0 to WLn respectively. Is connected to a drain select line (DSL).

The source select transistor SST controls the connection between the cell strings Ce00 to Cen0 and the common source line SL, Or blocking.

The memory strings ST connected to the bit lines FBLe and FBLo among the memory strings ST include flag cells FCe0 and FCo0 instead of memory cells. The flag cells FCe0 and FCo0 operate by operating voltages applied to the word lines WL0 to WLn together with the memory cells. Such flag cells FCe0 and FCo0 may store information related to program states of memory cells. For example, information about whether 1 bit data or 2 bits data is stored in the memory cells Ce00 to Ce0k and Co00 to Co0k may be stored in the flag cells FCe0 and FCo0. That is, when only the LSB program operation is performed and only LSB data is stored in the memory cells Ce00 to Ce0k and Co00 to Co0k, '1' data is stored in the flag cells FCe0 and FCo0, and the LSB program operation and the MSB program operation are performed. When two bits of data including LSB data and MSB data are stored in the memory cells Ce00 to Ce0k and Co00 to Co0k, '0' data may be stored in the flag cells FCe0 and FCo0.

In the NAND flash memory device, memory cells included in a memory cell block may be divided into physical page units or logical page units. For example, memory cells Ce00 to Ce0k and Co00 to Co0k and flag cells FCe0 and FCo0 connected to one word line WL0 form one physical page PAGE. In addition, even-numbered memory cells Ce00 to Ce0k1 and the flag cell FCe0 connected to one word line (eg, WL0) constitute one even physical page, and odd-numbered memory cells Co00 to Co0k are flag cells. (FCo0) may constitute one odd physical page. These pages (or even pages and odd pages) are the basic unit of program operation or read operation.

Referring back to FIGS. 1 and 2, the peripheral circuits 120 to 160 may include an erase loop, a program of memory cells (eg, Ce00 to Ce0k) and a flag cell (eg, FCe0) connected to a selected word line (eg, WL0). And perform a loop and read operation. These peripheral circuits are control circuits 120 for controlling program loops, read operations, and erase loops, and operation circuits 130 to 160 configured to perform program loops, read operations, and erase loops under control of the control circuit 120. It includes. In order to perform a program loop, a read operation, and an erase loop, the operation circuits 130 to 160 supply operating voltages Verase, Vpgm, Vread, Vpass, Vvfy, Vdsl, Vssl, and Vsl to local lines of the selected memory block. (SSL, WL0 to WLn, DSL) and the common source line SL, and selectively output and control the precharge / discharge of the bit lines BL0 to BLek, BLo0 to BLok, FBLe, and FBLo Are configured to sense the current flow of the fields BLe0 to BLek, BLo0 to BLok, FBLe, and FBLo. In particular, in the case of a NAND flash memory device, the operation circuit includes a voltage supply circuit 130, a page buffer group 140, a column select circuit 150, and an input / output circuit 160. Each component will be described in detail as follows.

The control circuit 120 performs operating voltages Verase, Vpgm, Vread, Vpass, and Vvfy for performing a program loop, a read operation, or an erase loop in response to a command signal CMD input through the input / output circuit 160 from the outside. Outputs a voltage control signal CMDv for controlling the voltage supply circuit 130 so that Vdsl, Vssl, and Vsl can be generated at a desired level. The control circuit 120 controls the control signals CMDpb for controlling the page buffers PB0 to PBk and FPB included in the page buffer group 140 to perform a program loop, a read operation, or an erase loop. Output When the address signal ADD is input, the control circuit 120 generates the column address signal CADD and the row address signal RADD by these signals, and outputs the same to the control circuit 120.

In response to the voltage control signal CMDv of the control circuit 120, the voltage supply circuit 130 requires operating voltages Verase, Vpgm, Vread, Vpass, Vvfy, and the like according to a program loop, a read operation, or an erase loop of the memory cells. Vdsl, Vssl, and Vsl) are generated and operated as the local lines SSL, WL0 to WLn, and DSL and the common source line SL of the selected memory block in response to the row address signal RADD of the control circuit 120. Output voltages.

To this end, the voltage supply circuit 130 may include a voltage generation circuit 131 and a row decoder 133. The voltage generation circuit 131 generates the operating voltages Verase, Vpgm, Vread, Vpass, Vvfy, Vdsl, Vssl, and Vsl in response to the voltage control signal CMDv of the control circuit 120 and the row decoder 140. In response to the row address signal RADD of the control circuit 120, the operating voltages are set to the local lines SSL, WL0 to WLn, and DSL of the selected memory block among the memory blocks 110MB and the common source line SL. To pass.

As such, the output and change of the operating voltages Verase, Vpgm, Vread, Vpass, Vvfy, Vdsl, Vssl, and Vsl described below are controlled by the voltage supply circuit 130 according to the voltage control signal CMDv of the control circuit 120. )

The page buffer groups 140 each include a plurality of page buffers PB0 to PBk and FPB connected to the memory array 110 through bit lines BLe0 to BLek, BLo0 to BLok, FBLe, and FBLo. . According to the operation control signal CMDpb of the control circuit 120 and the data DATA to be stored in the memory cells during the program operation, the page buffers PB0 to PBk and FPB are divided into the bit lines BLe0 to BLek and BLo0 to. BLok, FBLe, FBLo) are precharged selectively. In accordance with the operation control signal CMDpb of the control circuit 120 during the program verify operation or the read operation, the page buffers PB0 to PBk and FPB are connected to the bit lines BLe0 to BLek, BLo0 to BLok, FBLe, and FBLo. After precharging, the current flow of the bit lines BLe0 to BLek, BLo0 to BLok, FBLe, and FBLo is sensed to latch data read from the memory cell. The page buffers PB0 to PBk and FPB may be connected to bit lines, respectively, and for each pair of bit lines including even bit lines BLe0 to BLek and FBLe and odd bit lines BLo0 to BLok and FBLo. May be connected.

The column selection circuit 150 selects the page buffers PB0 to PBk included in the page buffer group 140 in response to the column address CADD output from the control circuit 120. That is, the column select circuit 150 sequentially transfers data to be stored in the memory cells to the page buffers PB0 to PBk and FBP in response to the column address CADD. In addition, the column selection circuit 150 sequentially stores the page buffers in response to the column address CADD so that data of the memory cells latched in the page buffers PB0 to PBk and FPB can be output to the outside by a read operation. Select (PB0 ~ PBk, FPB).

The input / output circuit 160 transmits the command signal CMD and the address signal ADD input from the outside to the control circuit 120. In addition, the input / output circuit 160 transmits data DATA input from the outside to the column select circuit 150 during the program operation or outputs data read from the memory cells to the outside during the read operation.

The peripheral circuits 120 to 160 including the above-described configurations complete the LSB program loop for storing LSB data in the LSB page of the selected word line, and then implement the MSB program loop for storing MSB data in the MSB page. Previously, an operation of reading LSB data by applying a first read voltage to a selected word line and an operation of reading flag data of the flag cells by applying a second read voltage to a selected word line is performed. That is, the peripheral circuits 120 ˜ 160 apply different read operations to selected word lines, respectively, to read LSB data and to read flag data. This will be described in detail as follows.

3 is a flowchart illustrating a method of operating a semiconductor memory device according to an embodiment of the present invention. 4 is a view for explaining a method of operating a semiconductor memory device according to an embodiment of the present invention. 5A and 5B are distribution diagrams illustrating a method of operating a semiconductor memory device according to an exemplary embodiment of the present invention.

1, 3, 4, and 5A, an LSB program loop for storing LSB data in an LSB page of a word line (eg, WLm) selected in step S301 is performed. The LSB program loop includes an LSB program operation and an LSB program verify operation. If the LSB page is divided into an even LSB page and an odd LSB page, the LSB program loop is an even LSB program loop for storing even LSB data in the even LSB page, and an odd LSB for storing even odd LSB data in the odd LSB page. It can be implemented by being divided into program loops. Even LSB program loop and odd LSB program loop are implemented in the same way according to the stored data, except that only the stored data is different. Therefore, only one LSB program loop will be described.

To this end, the peripheral circuits 120 to 160 selectively apply a program allowance voltage (eg, 0V) and a program prohibition voltage (eg, Vcc) to the even bit lines BLe0 to BLek and FBLe according to the even LSB data. The program voltage Vpgm is applied to the selected word line WLm. In this case, the peripheral circuits 120 to 160 apply a program inhibit voltage Vpgm to the odd bit lines BLo0 to BLok and FBLo. Subsequently, the peripheral circuits 120 to 160 perform an LSB program verification operation. If it is determined that even LSB data is normally stored in memory cells of the even LSB page, the LSB program loop is completed. Otherwise, after raising the program voltage Vpgm, the LSB program operation and the LSB program verification operation are performed again.

Subsequently, the odd LSB program loop for storing odd LSB data in the odd LSB page of the selected word line WLm proceeds in the same manner as the even LSB program loop. Thus, the LSB program loop for storing LSB data in the LSB page of the selected word line WLm is completed.

Meanwhile, the LSB program loop of the selected word line WLm has completed storing LSB data in the LSB page of the word line WLm-1 adjacent to the selected word line WLm to one side (eg, to the source select line). This may be done before storing the MSB data in the MSB page of the word line WLm-1. After the LSB program loop of the selected word line WLm is completed, the MSB program loop for storing MSB data in the MSB page of the adjacent word line WLm-1 is completed. Subsequently, the LSB program loop for storing LSB data in the LSB page of the word line WLm + 1 adjacent to the selected word line WLm to the other side (eg, to the drain select line) is completed.

As the LSB program loop of the selected word line WLm is completed, the threshold voltages of the memory cells EMC and OMCell are divided into an erase level and a program level PV2. However, the threshold voltages of the flag cells EFCell and OFCell are distributed in the erase level.

Meanwhile, since the LSB program loop of the selected word line WLm is divided into an even LSB program loop and an odd LSB program loop, interference occurs in the even flag cell EFCell during the odd LSB program loop, and thus the even flag is performed. The threshold voltage of the cell FCell may change. In addition, while the MSB program loop and the LSB program loop of the adjacent word lines WLm-1 and WLm + 1 are implemented, interference occurs in the flag cells EFCell and OFCell, so that thresholds of the flag cells EFCell and OFCell are generated. The voltage can change. For example, the threshold voltages of the flag cells EFCell and OFCell increase to widen the threshold voltage distribution, and in some cases, the threshold voltage may be higher than the first read voltage R1 due to an interference phenomenon.

In step S303, MSB data for storing in the MSB page of the selected word line WLm is input to the peripheral circuits 120 to 160. In detail, the MSB data is input to the page buffer group 150 through the input / output circuit 160 and the column select circuit 150. If the MSB page is divided into an even MSB page and an odd MSB page, the even MSB data is entered first.

In step S305, an LSB read operation for reading LSB data (or even LSB data) stored in the LSB page (or even LSB page) of the selected word line WLm is performed. To this end, the peripheral circuits 120 to 160 precharge the bit lines (eg, BLe0 to BLek), and then apply the read voltage Vread of the first level R1 to the selected word line WLm and the remaining word lines. The read pass voltage (Vpass) is applied. Subsequently, the peripheral circuits 120 to 160 sense voltage changes (or current changes) of the bit lines (eg, BLe0 to BLek) and latch the even LSB data according to the result. Thus, the peripheral circuits 120 to 160 store even LSB data read from the even LSB page of the selected word line WLm and even MSB data to be stored in the even MSB page of the selected word line WLm.

In step S307, a flag read operation for reading flag data (or even flag data) from the flag cell (or even flag cell) EFCell of the selected word line WLm is performed. To this end, the peripheral circuits 120 to 160 precharge the bit line (eg, EBLe), apply a read voltage Vread of the second level R2 to the selected word line WLm, and read the remaining word lines. The pass voltage Vpass is applied. Subsequently, the peripheral circuits 120 to 160 sense voltage changes (or current changes) of the bit lines (eg, FBLe) and latch the even flag data according to the result.

Here, the LSB data and the flag data may be simultaneously read by applying the read voltage Vread of the first level R1. However, since the threshold voltage of the flag cell may be higher than the first level R1 due to the interference phenomenon, when some flag cells are read at the read voltage Vread of the first level R1, some flag cells are sensed in the program state. Error may occur. Therefore, the read operation of the flag data is preferably performed by using the read voltage of the second level R2 higher than the first level R1. Here, the first level R1 corresponds between the erase level PV0 and the first program level PV1, and the second level R2 corresponds to the first program level PV1 and the second program level PV2. It may correspond to between.

In step S309, when the flag data is '1', that is, when the threshold voltage of the flag cell is sensed to the erase level, it is determined that the MSB data is not stored in the MSB page of the selected word line WLm. In S311, the peripheral circuits 120 to 160 execute an MSB program loop. The MSB program loop may be implemented in the same manner as the LSB program loop according to the MSB data. When the MSB page is divided into an even MSB page and an odd MSB page, the MSB program loop is divided into an even MSB program loop and an odd MSB program loop.

Referring to FIG. 5B, after the even MSB data is stored in the even MSB page of the selected word line WLm, threshold voltages of the even memory cells EMC may be set according to the even LSB data and the even MSB data. The threshold voltages of the even flag cell EFCell are divided into the first to third program levels PV1 to PV3, and the threshold voltages of the even flag cell EFCell are divided into an erase level PV0 and a third program level PV3. That is, the threshold voltage of the even flag cell EFCell is raised to the third program level PV3 during the MSB program loop. When the MSB program loop is not implemented, the threshold voltage of the even flag cell EFCell maintains the erase level PV0.

If the even flag data is '0' in step S309, that is, if the threshold voltage of the even flag cell is sensed to be raised to the program level, the even MSB page of the selected word line WLm is determined. It is determined that the data is stored, and the peripheral circuits 120 to 160 do not execute the even MSB program loop. The peripheral circuits 120 to 160 may select a different memory block to implement a program loop for storing data.

When the even MSB program loop is completed, as described above, the odd MSB data is input to the peripheral circuits 120 to 160 and the odd LSB data and the odd flag data are read by the peripheral circuits 120 to 160, and then these data are read. The odd MSB program loop may be implemented.

Thus, even if the threshold voltages of the flag cells EFCell and OFCell are changed by an interference phenomenon during the program loop, the flag is read using the read voltage R2 different from the read voltage R1 for reading LSB data. By reading the data, it is possible to read the flag data accurately and improve the reliability of the operation.

6 is a simplified block diagram of a memory system in accordance with an embodiment of the present invention.

Referring to FIG. 6, a memory system 600 according to an embodiment of the present invention includes a non-volatile memory device 620 and a memory controller 610.

The nonvolatile memory device 620 may be configured as the semiconductor memory device described above. The memory controller 610 is configured to control the nonvolatile memory device 620 in a general operation mode such as a program operation, a read operation, or an erase operation.

May be provided as a memory card or a solid state disk (SSD) by the combination of the nonvolatile memory device 620 and the memory controller 610. The SRAM 611 is used as an operation memory of the processing unit 612. [ The host interface 613 has a data exchange protocol of a host connected to the memory system 600. The error correction block 614 detects and corrects errors included in data read from the nonvolatile memory device 620. The memory interface 614 interfaces with the nonvolatile memory device 620 of the present invention. The processing unit 612 performs all the control operations for exchanging data of the memory controller 610.

Although it is not shown in the drawing, the memory system 600 according to the present invention may be further provided with a ROM (not shown) or the like for storing code data for interfacing with a host, To those who have learned. The non-volatile memory device 620 may be provided in a multi-chip package comprising a plurality of flash memory chips. The memory system 600 of the present invention can be provided as a highly reliable storage medium with a low probability of occurrence of errors. In particular, the flash memory device of the present invention can be provided in a memory system such as a solid state disk (SSD) which has been actively studied recently. In this case, the memory controller 610 is configured to communicate with an external (e.g., host) through one of various interface protocols such as USB, MMC, PCI-E, SATA, PATA, SCSI, ESDI, will be.

7 is a simplified block diagram illustrating a fusion memory device or a fusion memory system that performs program operations in accordance with various embodiments described above. For example, the technical features of the present invention can be applied to a one-nAND flash memory device 700 as a fusion memory device.

The one NAND flash memory device 700 may include a host interface 710 for exchanging various information with a device using different protocols, and a buffer RAM 720 that embeds codes for driving the memory device or temporarily stores data. And a controller 730 for controlling reads, programs, and all states in response to externally provided control signals and commands, data such as commands, addresses, and configurations for defining a system operating environment inside the memory device. And a NAND flash cell array 750 composed of a register 740 and an operating circuit including a nonvolatile memory cell and a page buffer. As the memory array of the NAND flash cell array 750, the memory array illustrated in FIG. 2 may be applied.

8, a computing system including a flash memory device 812 in accordance with the present invention is schematically illustrated.

A computing system 800 in accordance with the present invention includes a microprocessor 820 electrically coupled to a system bus 860, a RAM 830, a user interface 840, a modem 850 such as a baseband chipset, Memory system 810. When the computing system 800 according to the present invention is a mobile device, a battery (not shown) for supplying the operating voltage of the computing system 800 will additionally be provided. Although it is not shown in the drawing, it is to be appreciated that the computing system 800 in accordance with the present invention may be further provided with application chipsets, camera image processors (CIS), mobile DRAMs, It is obvious to those who have acquired knowledge. The memory system 810 may configure, for example, a solid state drive / disk (SSD) that uses a nonvolatile memory to store data. Alternatively, the memory system 810 may be provided as a fusion flash memory (e.g., a one-nAND flash memory).

110: memory array 110 MB: memory block
ST: String PAGE: Page
120: control circuit 130: voltage supply circuit
131: voltage generation circuit 133: low decoder
140: page buffer group PB0 to PBk: page buffer
150: column selection circuit 160: input / output circuit

Claims (14)

Executing an LSB program loop for storing LSB data in an LSB page of a selected word line;
Reading the LSB data by applying a first read voltage to the selected word line;
Reading flag data of flag cells connected to the selected word line by applying a second read voltage to the selected word line; And
And if it is determined that the MSB data is not stored in the MSB page of the selected word line by the flag data, performing an MSB program loop for storing the MSB data in the MSB page. .
The method of claim 1, wherein after the MSB data is stored,
Threshold voltages of the memory cells connected to the selected word line are divided into erase levels and first to third program levels according to the LSB data and the MSB data.
Threshold voltages of the flag cells are divided into the erase level and the third program level according to the MSB data.
The method of claim 1,
And operating the second read voltage higher than the first read voltage.
The method of claim 1,
The level of the first read voltage corresponds between an erase level and a first program level, and the level of the second read voltage corresponds between the first program level and a second program level higher than the first program level. How the memory device works.
The method of claim 1,
And after the storage of the MSB data is completed in the MSB page of the word line adjacent to the selected word line, the LSB data and the flag data are read.
The method of claim 5, wherein
And after the storage of the LSB data is completed in the LSB page of the selected word line and the word line adjacent to the other side, the LSB data and the flag data are read.
The method of claim 1,
And if the MSB data is stored in the MSB page of the selected word line by the flag data, the MSB program loop is stopped.
A memory array including memory cells and flag cells connected to word lines; And
An LSB program loop and an MSB program loop for storing LSB data and MSB data, respectively, in memory cells connected to a selected word line among the word lines, and a first read to the selected word line before the MSB program loop is executed. And a peripheral circuit configured to apply the voltage to read the LSB data and to apply the second read voltage to the selected word line to read the flag data of the flag cells.
The method of claim 8, wherein after the MSB data is stored,
Threshold voltages of the memory cells are divided into erase levels and first to third program levels according to the LSB data and the MSB data.
Threshold voltages of the flag cells are divided into the erase level and the third program level according to the MSB data.
The method of claim 8,
And the peripheral circuit applies the second read voltage higher than the first read voltage.
The method of claim 8,
The peripheral circuit applies the first read voltage at a level between an erase level and a first program level, and applies the second read voltage to a level between the first program level and a second program level higher than the first program level. The semiconductor memory device is applied to.
The method of claim 8,
And the peripheral circuit is configured to read the LSB data and the flag data after the storage of the MSB data is completed in the MSB page of the word line adjacent to the selected word line.
13. The method of claim 12,
And the peripheral circuit is configured to read the LSB data and the flag data after the storage of LSB data is completed in the LSB page of the selected word line and the word line adjacent to the other side.
The method of claim 8,
And the peripheral circuit is configured to stop the MSB program loop when it is determined by the flag data that MSB data is stored in the MSB page of the selected word line.
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