KR102039431B1

KR102039431B1 - Semiconductor memory device and method of operating the same

Info

Publication number: KR102039431B1
Application number: KR1020120095692A
Authority: KR
Inventors: 장채규; 왕종현; 차재용
Original assignee: 에스케이하이닉스 주식회사
Priority date: 2012-08-30
Filing date: 2012-08-30
Publication date: 2019-11-04
Also published as: KR20140028738A

Abstract

The semiconductor memory device may include bit lines included in the first bit line group and sequentially arranged, memory strings connected according to the first bit line connection signal, and bit lines included in the second bit line group and sequentially arranged. And a memory block including memory strings connected according to the second bit line connection signal, a read / write circuit connected to bit lines of the first bit line group, and bit lines and second of the first bit line group. Wires for connecting the bit lines of the bit line group, respectively.

Description

Semiconductor memory device and method of operation thereof {Semiconductor memory device and method of operating the same}

The present invention relates to a semiconductor memory device and a method of operating the same, and to a semiconductor memory device including a memory cell and a method of operating the same.

As the number of columns (eg, the number of bit lines) of the semiconductor memory device increases, the total size of the page buffer group including the page buffer connected to the bit lines and the memory cells performing read or write operations increases and the page buffer is increased. The area occupied by the group increases.

When the page buffer is connected to each pair of bit lines including the even bit line and the odd bit line, the threshold voltage of the memory cells connected to the even bit line may be increased due to interference during the write operation of the memory cells connected to the odd bit line. have.

For this reason, the ALB (All Bit Line) method, which simultaneously reads and writes memory cells connected to all bit lines, is applied. To this end, a page buffer must be connected to each bit line. The area occupied by the group will increase.

Embodiments of the present invention provide a semiconductor memory device and a method of operating the same, which can reduce an area occupied by circuits necessary for operating memory cells and improve operating characteristics thereof.

In an embodiment, a semiconductor memory device includes memory strings included in a first bit line group and sequentially connected to each other according to a plurality of bit lines and a first bit line connection signal, and a second bit line group. A memory block including memory strings connected according to sequentially arranged bit lines and a second bit line connection signal, a read / write circuit connected to bit lines of a first bit line group, and a first bit line group Wires for connecting the bit lines of the bit lines and the bit lines of the second bit line group.

In another embodiment, a semiconductor memory device includes a first bit line group including sequentially arranged bit lines, a second bit line group including sequentially arranged bit lines, and a first bit line group. Wiring lines connecting the bit lines and the bit lines of the second bit line group, memory cells connected to the bit lines of the first bit line group according to the first bit line connection signal, and the second bit line connection signal. The memory block may include a memory block including memory cells connected to bit lines of the second bit line group.

A method of operating a semiconductor memory device according to an embodiment of the present invention includes the steps of connecting some of the memory cells of the memory cells connected to the selected word line to the read / write circuit through the bit lines included in the first bit line group and sequentially arranged. Performing a read operation or a write operation of some memory cells, and through the bit lines of the first bit line group and the bit lines in which the remaining memory cells of the memory cells are included in the second bit line group and sequentially arranged; And connecting to a read / write circuit and performing a read operation or a write operation on the remaining memory cells.

According to another aspect of the present invention, there is provided a method of operating a semiconductor memory device, in which a read operation or a write operation of first to kth memory cells sequentially arranged among memory cells connected to a selected word line is performed, and sequentially among memory cells. A read operation or a write operation of the k + 1 th to the last memory cells arranged as is performed.

Embodiments of the present invention can reduce the area occupied by circuits required for the operation of memory cells and improve operating characteristics.

1 is a block diagram illustrating a semiconductor memory device in accordance with an embodiment of the present invention.
FIG. 2 is a circuit diagram illustrating the memory block shown in FIG. 1.
3 is a flowchart illustrating a method of operating a semiconductor memory device according to an embodiment of the present invention.
4 is a block diagram schematically illustrating a memory system according to an exemplary embodiment of the present invention.
5 is a block diagram schematically illustrating a fusion memory device or a fusion memory system performing a program operation according to various embodiments described above.
6 is a block diagram schematically illustrating a computing system including a flash memory device according to an exemplary embodiment of the present invention.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

1 is a block diagram illustrating a semiconductor memory device in accordance with an embodiment of the present invention.

Referring to FIG. 1, a semiconductor device includes a memory array 110 and peripheral circuits 120 to 160. The peripheral circuit includes a control circuit 120 and operation circuits 130 to 160. In the case of a flash memory device, an operation circuit is configured to perform a read operation, a program loop (a program operation and a program verify operation) and an erase loop (an erase operation and an erase verify operation) for memory cells, and a voltage supply circuit ( 130, the page buffer group 140, the column selection circuit 150, and the input / output circuit 160. The control circuit 120 controls the erase operation, the program loop, and the erase loop of the operation circuits 130 to 160.

The memory array 110 includes a plurality of memory blocks 110MB. Each memory block 110MB may include a plurality of memory strings. The structure of the memory block 110MB is as follows.

FIG. 2 is a circuit diagram illustrating the memory block shown in FIG. 1.

2, each memory block includes a plurality of memory strings STa and STb connected between bit lines BLa0 to BLak and BLb0 to BLbk and a common source line CSL. That is, the memory strings STa and STb are respectively connected to the corresponding bit lines BLa0 to BLak and BLb0 to BLbk and commonly connected to the common source line CSL. Each of the memory strings STa and STb includes a source select transistor SST having a source connected to a common source line CSL, a cell string having a plurality of memory cells C0 to Cn connected in series, and a bit line having a drain. And a drain select transistor DST connected to BLa0. Memory cells C0 to Cn included in the cell string are connected in series between the select transistors SST and DST. The gate of the source select transistor SST is connected to the source select line SSL, the gates of the memory cells C0 to Cn are respectively connected to the word lines WL0 to WLn, and the gate of the drain select transistor DST. Is connected to the drain select line DSL.

Here, the drain select transistors DST are connected to the memory strings STa and STa and the bit lines BLa0 to BLak and BLb0 to BLbk according to a drain select voltage (eg, Vdsl1) such as a bit line connection signal. The source select transistor SST connects or disconnects the cell strings C0 to Cn and the common source line CSL according to a source select voltage Vssl such as a source connection signal. It performs the function of the selection transistor to control.

In the NAND flash memory device, memory cells included in a memory cell block may be divided into physical page units or logical page units. For example, memory cells connected to one word line (eg, WL0) constitute one physical page PAGE. In particular, in the present invention, some of the memory cells connected to the word line WL0 may constitute one page PAGEa and the remaining memory cells may constitute another page PAGEb. For example, the first to k th memory cells of the memory cells connected to the word line WL0 may constitute the page PAGEa, and the k + 1 th to the last memory cells may constitute the page PAGEb. Therefore, the memory cells included in the pages PAGEa and PAGEb are each sequentially arranged. That is, the memory strings STa are sequentially arranged, and the memory strings STb are sequentially arranged after the memory strings STb. Here, the memory cells included in the page PAGEa are connected to the bit lines BLa0 to BLak included in the first bit line group and sequentially arranged, and the memory cells included in the page PAGEb are the second bit line. It may be connected to the bit lines BLb0 to BLbk included in the group and sequentially arranged. These pages become the basic unit of program loop or read operation.

In particular, the memory cells included in the page PAGEa are connected to the bit lines BLa0 to BLak according to the first bit line connection signal Vdsl1, and the memory cells included in the page PAGEb are connected to the second bit line. The bit lines BLb0 to BLbk may be connected to the signal Vdsl2. The number of memory cells included in the page PAGEa and the number of memory cells included in the page PAGEb may be the same. In other words, the memory strings STa are connected to the bit lines BLa0 to BLak according to the first bit line connection signal Vdsl1, and the memory strings STb are connected to the second bit line connection signal Vdsl2. Accordingly, the bit lines BLb0 to BLbk may be connected. In addition, the memory cells C0 to Cn and the source select transistors SST included in the pages PAGEa and PAGEb may be operated by the same signals or voltages.

Referring back to FIGS. 1 and 2, the peripheral circuits 120 to 160 are configured to perform an erase loop, a program loop, and a read operation of memory cells connected to the selected word line. The peripheral circuit may include an operation circuit 130 to 160 configured to perform a program loop, a read operation, and an erase loop under the control of the control circuit 120 and the control circuit 120 for controlling the program loop, the read operation, and the erase loop. It includes. In order to perform a program loop, a read operation, and an erase loop, the operation circuits 130 to 160 select operating voltages Verase, Vpgm, Vread, Vpass, Vvfy, Vdsl1, Vdsl2, Vssl, and Vsl of the selected memory block. Selectively output to the local lines SSL, WL0 to WLn, DSL1 and DSL2 and the common source line SL, and control precharge / discharge of the bit lines BLa0 to BLak and BLb0 to BLbk, or And a current flow of the fields BLa0 to BLak and BLb0 to BLbk. In particular, in the case of a NAND flash memory device, the operation circuit includes a voltage supply circuit 130, a read / write circuit 140, a column select circuit 150, and an input / output circuit 160. Here, the read / write circuit 140 may be a page buffer group including a plurality of page buffers. Each component will be described in detail as follows.

The control circuit 120 performs operating voltages Verase, Vpgm, Vread, Vpass, and Vvfy for performing a program loop, a read operation, or an erase loop in response to a command signal CMD input through the input / output circuit 160 from the outside. Outputs a voltage control signal CMDv for controlling the voltage supply circuit 130 so that Vdsl1, Vdsl2, Vssl, and Vsl can be generated at a desired level. The control circuit 120 controls the control signals CMDpb for controlling the page buffers PB0 to PBk and FPB included in the page buffer group 140 to perform a program loop, a read operation, or an erase loop. Output In addition, when the address signal ADD is input, the control circuit 120 generates a column address signal CADD and a row address signal RADD, and outputs them from the control circuit 120.

In response to the voltage control signal CMDv of the control circuit 120, the voltage supply circuit 130 requires operating voltages Verase, Vpgm, Vread, Vpass, Vvfy, and the like according to a program loop, a read operation, or an erase loop of memory cells. Vdsl1, Vdsl2, Vssl, and Vsl) are generated, and in response to the row address signal RADD of the control circuit 120, local lines SSL, WL0 to WLn, and DSL of the selected memory block and the common source line SL. Outputs operating voltages.

To this end, the voltage supply circuit 130 may include a voltage generation circuit 131 and a row decoder 133. The voltage generation circuit 131 generates the operating voltages Verase, Vpgm, Vread, Vpass, Vvfy, Vdsl1, Vdsl2, Vssl, and Vsl in response to the voltage control signal CMDv of the control circuit 120 and generates a row decoder. In response to the row address signal RADD of the control circuit 120, the operating voltages may be set to the local lines SSL, WL0 to WLn, and DSL of the selected memory block among the memory blocks 110MB and the common source line. CSL).

As such, the output and change of the operating voltages (Verase, Vpgm, Vread, Vpass, Vvfy, Vdsl1, Vdsl2, Vssl, Vsl) described below are controlled according to the voltage control signal (CMDv) of the control circuit 120. 130 is made.

The page buffer groups 140 each include a plurality of page buffers PB0 to PBk connected to the memory array 110 through bit lines BLa0 to BLak. During the program operation, the page buffers PB0 to PBk selectively free the bit lines BLa0 to BLak according to the operation control signal CMDpb of the control circuit 120 and the data DATA to be stored in the memory cells. Occupy. According to the operation control signal CMDpb of the control circuit 120 during the program verify operation or the read operation, the page buffers PB0 to PBk precharge the bit lines BLa0 to BLak and then the bit lines BLa0 to BLak. Current flow is sensed to latch data read from the memory cell. The page buffers PB0 to PBk may be connected to bit lines, respectively.

In particular, the page buffers PB0 to PBk are directly connected to some of the bit lines BLa0 to BLak of the bit lines BLa0 to BLak and BLb0 to BLbk, and are different from the remaining bit lines BLb0 to BLbk. It is connected through the wirings BLc0 to BLck. The wirings BLc0 to BLck may be formed (or disposed) on a layer different from the bit lines BLa0 to BLak and BLb0 to BLbk in the manufacturing process. In other words, the bit lines BLa0 to BLak of the first bit line group are directly connected to the page buffers PB0 to PBk, respectively, and the wirings BLc0 to BLck are connected to the bit lines of the first bit line group. BLa0 to BLak and the bit lines BLb0 to BLbk of the second bit line group are sequentially connected. Accordingly, the bit lines BLb0 to BLbk of the second bit line group are connected to the page buffers PB0 to PBk through the wirings BLc0 to BLck, respectively.

As such, since only the number of page buffers PB0 to PBk corresponding to half of the number of bit lines BLa0 to BLak and BLb0 to BLbk is installed, the area occupying the page buffers PB0 to PBk is reduced to half. Can be. The memory cells included in the page PAGEa and the memory cells included in the page PAGEb are sequentially arranged, and a program loop of the memory cells included in the page PAGEa or the memory cells included in the page PAGEb is provided. Since the processing is performed at the same time, it is possible to prevent interference between memory cells in the page.

The column selection circuit 150 selects the page buffers PB0 to PBk included in the page buffer group 140 in response to the column address CADD output from the control circuit 120. That is, the column select circuit 150 sequentially transfers data to be stored in the memory cells to the page buffers PB0 to PBk in response to the column address CADD. In addition, the column selection circuit 150 sequentially processes the page buffers PB0 in response to the column address CADD so that data of memory cells latched in the page buffers PB0 to PBk may be output to the outside by a read operation. ~ PBk).

The input / output circuit 160 transmits the command signal CMD and the address signal ADD input from the outside to the control circuit 120. In addition, the input / output circuit 160 transmits data DATA input from the outside to the column select circuit 150 during the program operation or outputs data read from the memory cells to the outside during the read operation.

Hereinafter, an operation of the semiconductor memory device including the above-described components will be described.

3 is a flowchart illustrating a method of operating a semiconductor memory device according to an embodiment of the present invention.

1 and 3, a read operation or a write operation of first to k th memory cells sequentially arranged among memory cells connected to a selected word line is performed. For example, a read operation or a write operation of memory cells included in the page PAGEa is performed. The write operation corresponds to a program loop. Hereinafter, the write operation will be described as an example.

For a write operation, in step S301, data to be stored in the memory cells of the page PAGEa is input to the read / write circuit 140 through the input / output circuit 160 and the column select circuit 150. In response to the first and second bit line connection signals Vdsl1 and Vdsl2 of the voltage supply circuit 130, the memory cells of the page PAGEa are connected to the bit lines BLa0 to BLak of the first bit line group. The memory cells of the page PAGEb are disconnected from the bit lines BLb0 to BLbk of the second bit line group. That is, the memory strings STa are connected to the bit lines BLa0 to BLak, and the memory strings STb are disconnected from the bit lines BLb0 to BLbk. Therefore, the memory cells included in the page PAGEb or the memory strings STb are in a floating state. As a result, the memory cells included in the page PAGEa or the memory strings STa are electrically connected to the bit lines BLa0 to BLak. The read / write circuit 140 selectively precharges or discharges the bit lines BLa0 to BLak according to the input data.

In operation S303, a write operation of memory cells connected to the read / write circuit 140 is performed through the bit lines BLa0 to BLak. To this end, the voltage supply circuit 140 applies a pass voltage Vpass to unselected word lines and a program voltage Vpgm to selected word lines. In this case, a source connection signal (or a source select voltage) Vssl is applied to the source select line SSL so that the source select transistor SST can be turned off, and a power source voltage is applied to the common source line CSL. (Vsl) can be applied. In this way, the program operation is performed.

Since the memory cells included in the page PAGEa share the same word line and are sequentially arranged, the phenomenon in which the threshold voltage is changed due to interference between the memory cells in the page PAGEa does not occur. Therefore, the electrical characteristics due to the interference phenomenon can be improved.

Subsequently, when a program is detected in an incomplete memory cell after performing the verify operation, the voltage supply circuit 130 raises the program voltage Vpgm according to the control signal CMDv of the control circuit 120, and then raises the elevated program. The program operation is executed again according to the voltage Vpgm.

When the data storage of the memory cells included in the page PAGEa is completed, a read operation is performed to store data in the k + 1st to the last remaining memory cells included in the page PAGEb.

In step S305, data to be stored in the memory cells of the page PAGEb is input to the read / write circuit 140 through the input / output circuit 160 and the column select circuit 150. In addition, in response to the first and second bit line connection signals Vdsl1 and Vdsl2 of the voltage supply circuit 130, the memory cells of the page PAGEa and the bit lines BLa0 to BLak of the first bitline group. Is disconnected, and the memory cells of the page PAGEb are connected to the bit lines BLb0 to BLbk of the second bit line group. Since the bit lines BLa0 to BLak are connected to the bit lines BLa0 to BLak by the bit lines BLb0 to BLbk and the wirings BLc0 to BLck, the memory cells of the page PAGEb are connected to the bit lines BLb0 to BLbk and the bit lines. It is connected to the read / write circuit 140 through BLa0 to BLak. That is, the memory strings STa are disconnected from the bit lines BLa0 to BLak, the memory strings STb are connected to the bit lines BLb0 to BLbk, and the bit lines BLb0 to BLbk. It is connected to the bit lines BLa0 to BLak through the channel. Therefore, memory cells included in the page PAGEa or the memory strings STa are in a floating state. As a result, the memory cells included in the page PAGEb or the memory strings STb are electrically connected to the bit lines BLa0 to BLak. The read / write circuit 140 selectively precharges or discharges the bit lines BLa0 to BLak according to the input data to be stored in the memory cells of the page PAGEb.

In operation S307, a write operation of the memory cells of the page PAGEb connected to the read / write circuit 140 through the bit lines BLa0 to BLak is performed. To this end, the voltage supply circuit 140 applies a pass voltage Vpass to unselected word lines and a program voltage Vpgm to selected word lines. In this case, a source connection signal (or a source select voltage) Vssl is applied to the source select line SSL so that the source select transistor SST can be turned off, and a power source voltage is applied to the common source line CSL. (Vsl) can be applied. In this way, the program operation is performed.

Since the memory cells included in the page PAGEb share the same word line and are sequentially arranged, the phenomenon in which the threshold voltage is changed due to interference between the memory cells in the page PAGEb does not occur. Therefore, the electrical characteristics due to the interference phenomenon can be improved. In addition, since the pages PAGEa and PAGEb are divided into both sides, it is possible to prevent the threshold voltages of the memory cells included in the page PAGEa from being changed by the interference phenomenon during the write operation of the page PAGEb.

The program loop described above may be applied to both the operation of storing LSB data and the operation of storing MSB data when storing two bits of data in one memory cell.

Similarly, in the read operation, when the read operation of the memory cells included in the page PAGEa or the memory strings STa is performed, the memory cells included in the page PAGEa or the memory strings STa may include bit lines (eg Memory cells connected to BLa0 to BLak and included in the page PAGEb or the memory strings STb may be disconnected from the bit lines BLb0 to BLbk. On the contrary, when performing a read operation of the memory cells included in the page PAGEb or the memory strings STb, the memory cells included in the page PAGEb or the memory strings STb are bit lines BLb0 to BLbk. ) Since the bit lines BLb0 to BLbk are connected to the bit lines BLa0 to BLak by the wirings BLc0 to BLck, the memory cells included in the page PAGEb or the memory strings STb are bit lines. It is connected to the bit lines BLa0 to BLak through BLb0 to BLbk. In this case, the memory cells included in the page PAGEa or the memory strings STa may be disconnected from the bit lines BLa0 to BLak. In the read operation, a ground voltage may be applied to the channel region of the memory cells not connected to the bit lines through the source select transistor from the common source line CSL.

In the erase operation, data stored in all memory cells included in the memory block 110BMB may be simultaneously erased without page division.

4 is a block diagram schematically illustrating a memory system according to an exemplary embodiment of the present invention.

Referring to FIG. 4, a memory system 400 according to an embodiment of the present invention includes a nonvolatile memory device 420 and a memory controller 410.

The nonvolatile memory device 420 may be configured as the semiconductor memory device described above. The memory controller 410 is configured to control the nonvolatile memory device 420 in a normal operation mode such as a program loop, a read operation, or an erase loop.

The combination of the nonvolatile memory device 420 and the memory controller 410 may be provided as a memory card or a solid state disk (SSD). SRAM 411 is used as the operating memory of the processing unit 412. The host interface 413 includes a data exchange protocol of a host that is connected to the memory system 400. The error correction block 414 detects and corrects an error included in data read from the nonvolatile memory device 420. The memory interface 414 interfaces with the nonvolatile memory device 420 of the present invention. The processing unit 412 performs various control operations for exchanging data of the memory controller 410.

Although not shown in the drawings, the memory system 400 according to the present invention may further be provided with a ROM (not shown) for storing code data for interfacing with a host. Self-explanatory to those who have learned. The nonvolatile memory device 420 may be provided in a multi-chip package composed of a plurality of flash memory chips. The memory system 400 of the present invention may be provided as a highly reliable storage medium having a low probability of error occurrence. In particular, the flash memory device of the present invention may be provided in a memory system such as a solid state disk (SSD), which is being actively studied recently. In this case, the memory controller 410 may be configured to communicate with an external (eg, host) via one of a variety of interface protocols such as USB, MMC, PCI-E, SATA, PATA, SCSI, ESDI, and IDE, and the like. will be.

5 is a block diagram schematically illustrating a fusion memory device or a fusion memory system performing a program operation according to various embodiments described above. For example, the technical features of the present invention may be applied to the one NAND flash memory device 500 as the fusion memory device.

The one NAND flash memory device 500 may include a host interface 510 for exchanging various information with devices using different protocols, and a buffer RAM 520 that embeds codes for driving the memory device or temporarily stores data. And a controller 530 for controlling reads, programs, and all states in response to externally provided control signals and commands, data such as commands, addresses, and configurations for defining a system operating environment inside the memory device. And a NAND flash cell array 550 composed of a register 540 and an operating circuit including a nonvolatile memory cell and a page buffer. The memory array shown in FIG. 2 may be applied to the memory array of the NAND flash cell array 550.

6 schematically illustrates a computing system including a flash memory device 612 in accordance with the present invention.

Computing system 600 according to the present invention includes a microprocessor 620, a RAM 630, a user interface 640, a modem 650, such as a baseband chipset, and electrically connected to a system bus 660; Memory system 610. When the computing system 600 according to the present invention is a mobile device, a battery (not shown) for supplying an operating voltage of the computing system 600 will be further provided. Although not shown in the drawings, the computing system 600 according to the present invention may further be provided with an application chipset, a camera image processor (CIS), a mobile DRAM, and the like. It is self-evident to those who have acquired knowledge. The memory system 610 may configure, for example, an SSD (Solid State Drive / Disk) that uses a nonvolatile memory to store data. Alternatively, the memory system 610 may be provided as a fusion flash memory (eg, one NAND flash memory).

110: memory array 110 MB: memory block
ST: string PAGE: page
120: control circuit 130: voltage supply circuit
131: voltage generation circuit 133: low decoder
140: page buffer group PB0 to PBk: page buffer
150: column selection circuit 160: input / output circuit

Claims

Memory strings included in the first bit line group and sequentially arranged, the memory strings connected according to the first bit line connection signal, and bit lines and the second bit included in the second bit line group and sequentially arranged. A memory block including memory strings connected according to a line connection signal;
A read / write circuit connected to bit lines of the first bit line group; And
Wires for connecting bit lines of the first bit line group and bit lines of the second bit line group, respectively;
And at least one of the bit lines of the first bit line group and the bit lines of the second bit line group.

Claim 2 has been abandoned upon payment of a set-up fee.

The method of claim 1,
Memory strings connected to bit lines of the first bit line group are sequentially arranged,
And memory strings connected to bit lines of the second bit line group sequentially.

Claim 3 has been abandoned upon payment of a set-up fee.

The memory string of claim 1, wherein each memory string connected to the bit lines of the first bit line group comprises:
A first select transistor connected to the bit lines of the first bit line group and operating according to the first bit line connection signal;
A third selection transistor connected to the common source line and operating according to the source connection signal; And
And memory cells connected in series between the first and third select transistors.

Claim 4 has been abandoned upon payment of a setup registration fee.

The memory string of claim 1, wherein each memory string connected to the bit lines of the second bit line group comprises:
A second selection transistor connected to the bit lines of the second bit line group and operating according to the second bit line connection signal;
A fourth selection transistor connected to the common source line and operating according to the source connection signal; And
And memory cells connected in series between the second and fourth select transistors.

A first bit line group including sequentially arranged bit lines;
A second bit line group including sequentially arranged bit lines;
Wirings connecting bit lines of the first bit line group and bit lines of the second bit line group, respectively; And
Memory cells connected to the bit lines of the first bit line group according to a first bit line connection signal, and memory cells connected to the bit lines of the second bit line group according to a second bit line connection signal. Memory block,
And a write or read operation of the memory cells connected to the bit lines of the second bit line group after the write or read operation of the memory cells connected to the bit lines of the first bit line group.

Claim 6 has been abandoned upon payment of a setup registration fee.

The method of claim 5,
Memory cells connected to the bit lines of the first bit line group are sequentially arranged;
And memory cells connected to the bit lines of the second bit line group sequentially.

Claim 7 was abandoned upon payment of a set-up fee.

The method of claim 5, wherein the memory block,
First select transistors connected to bit lines of the first bit line group and operated according to the first bit line connection signal;
Second select transistors connected to bit lines of the second bit line group and operated according to the second bit line connection signal;
Third select transistors commonly connected to a common source line and operating according to a source connection signal;
Second select transistors commonly connected to the common source line and operating according to a source connection signal;
Memory cells connected in series between the first and third select transistors; And
And memory cells connected in series between the second and fourth select transistors.

Claim 8 has been abandoned upon payment of a set-up fee.

The method according to claim 1 or 5,
The wiring lines are disposed on a layer different from the bit lines of the first and second bit line groups.

Claim 9 was abandoned upon payment of a set-up fee.

The method according to claim 1 or 5,
And the wirings sequentially connect bit lines of the first bit line group and bit lines of the second bit line group.

Claim 10 has been abandoned upon payment of a setup registration fee.

The method according to claim 1 or 5,
And memory cells connected to bit lines of the first bit line group and memory cells connected to bit lines of the second bit line group are connected to the same word lines.

Connecting some of the memory cells connected to the selected word line to the read / write circuit through the bit lines included in the first bit line group and sequentially arranged;
Performing a read operation or a write operation on the some memory cells;
After the read or write operation of the some memory cells is completed, the remaining memory cells of the memory cells are included in the second bit line group and sequentially arranged through the bit lines and the bit lines of the first bit line group. Connecting to the read / write circuit; And
And performing a read operation or a write operation on the remaining memory cells.

Claim 12 was abandoned upon payment of a set-up fee.

The method of claim 11,
And a plurality of bit lines of the first and second bit line groups are sequentially connected by wirings.

Claim 13 was abandoned upon payment of a set-up fee.

The method of claim 11,
While the read operation or the write operation of the some memory cells is performed, the connection between the remaining memory cells and the read / write circuit is cut off,
While the read operation or the write operation of the remaining memory cells is performed, the connection between the some memory cells and the read / write circuit is interrupted.

Claim 14 was abandoned upon payment of a set-up fee.

The method of claim 11,
And some of the memory cells are sequentially arranged, and the remaining memory cells are sequentially arranged after the some of the memory cells.

Performing a read operation or a write operation on the first to k th memory cells sequentially arranged among the memory cells connected to the selected word line; And
Performing a read operation or a write operation on the k + 1 th to the last memory cells sequentially arranged among the memory cells;
For the read operation or the write operation of the first to k th memory cells, the first to k th memory cells are connected to a read / write circuit through bit lines of a first bit line group sequentially arranged;
Bit lines and first bits of a second bit line group in which the k + 1st to last memory cells are sequentially arranged for the read operation or the write operation of the k + 1th to last memory cells A method of operating a semiconductor memory device connected to a read / write circuit through bit lines of a line group.

delete

Claim 17 was abandoned upon payment of a set-up fee.

The method of claim 15,
The k + 1st to the last memory cells are in a floating state while the read operation or the write operation of the first to kth memory cells is performed,
And the first to kth memory cells are in a floating state while the read or write operation of the k + 1th to last memory cells is performed.