KR20140085739A - Organic light emitting display device and method for driving thereof - Google Patents

Abstract

An organic light emitting display device according to the present invention, which solves a problem of visibility and brightness degradation of a sensing line due to the real-time sensing for external correction, includes a display panel which includes a plurality of pixels having a driving transistor for allowing an organic light emitting device to emit light; and a panel driving part which sets the display panel into a first display interval, a sensing interval, and a second display interval, displays pixel data on each pixel of the sensing line during the first display interval, senses characteristic changes of the driving transistor included in the pixels of the sensing line during the sensing interval, and displays brightness correction data, in which the brightness reduction of the sensing line during the second display interval is corrected, to each pixel of the sensing line.

Description

Technical Field [0001] The present invention relates to an organic light emitting diode (OLED) display device,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an organic light emitting diode (OLED) display, and more particularly, to an organic light emitting diode (OLED) display device and a driving method thereof that can solve luminance degradation and visibility problems of a sensing line by real time sensing for external compensation.

Recently, with the development of multimedia, the importance of flat panel display devices is increasing. In response to this, flat panel display devices such as liquid crystal display devices, plasma display devices, and organic light emitting display devices have been commercialized.

Of the flat panel display devices, the organic light emitting display device displays an image using an organic light emitting device that generates light by recombination of electrons and holes. The organic light emitting display device has a high response speed and self- Devices.

One pixel of a general organic light emitting display includes a pixel circuit including an organic light emitting element and a driving transistor for driving the organic light emitting element. However, since the threshold voltage / mobility characteristic of the driving transistor is different for each pixel in accordance with the non-uniformity of the manufacturing process of the thin film transistor and the driving time of a general organic light emitting display device, the amount of current flowing to the driving transistor of each pixel . The deviation of the amount of current flowing to the driving transistor of each of these pixels causes a luminance variation between the pixels, thereby lowering the uniformity of image quality. In order to solve such a problem, Korean Patent Laid-Open Publication No. 10-2010-0047505 (hereinafter referred to as "prior patent document") detects a threshold voltage of a driving switching element for each pixel, Discloses an organic light emitting diode display device capable of preventing the deterioration of image quality by preventing a luminance deviation between pixels by correcting a data voltage supplied to each pixel.

However, in the above-mentioned prior art documents, each pixel of each horizontal line is divided into a sensing period, a data programming period, and a light emission period, and no current flows through the pixels of one horizontal line during the sensing period. do. That is, the luminance of one horizontal line should have the luminance corresponding to the data for one frame, but the luminance is reduced by inserting the black luminance during the sensing period. For example, when the vertical synchronizing signal is 120 Hz, one frame is 8.33 ms. When the sensing interval is 200 to 250 us, the luminance of about 2.4 to 3% may be reduced. If the sensing period is 200 us to 250 us, Corresponds to a gray level value of about 7.5, which is a level recognized by the viewer's eyes.

Accordingly, the prior art document discloses that a luminance deviation, which is a horizontal line, is generated due to the black luminance due to real-time sensing sequentially one horizontal line by one horizontal line, as well as a sensing line SL is provided on the display panel 10, There is a problem that is perceived.

It is an object of the present invention to provide an organic light emitting display device and a method of driving the same that can solve the luminance degradation and visibility problem of a sensing line by real time sensing for external compensation.

Other features and advantages of the invention will be set forth in the description which follows, or may be obvious to those skilled in the art from the description and the claims.

According to an aspect of the present invention, there is provided an organic light emitting diode display comprising: a display panel including a plurality of pixels having a driving transistor for emitting an organic light emitting diode; And a display control circuit for setting the display panel as a first display period, a sensing period, and a second display period, displaying pixel data in each pixel of the sensing line during the first display period, And a panel driver for sensing a change in the characteristics of the driving transistor included therein and displaying luminance compensation data compensated for the luminance reduction of the sensing line during the second display period on each pixel of the sensing line. .

The panel driver may include a memory for storing a ratio of a first display interval, a sensing interval, and a second display interval for each of the sensing lines.

Wherein the panel driving unit stores pixel data of each pixel to be supplied to the sensing line in the first display period and calculates a luminance compensation based on a ratio of a first display interval and a second display interval corresponding to a sensing line stored in the memory, And generates the luminance compensation data by reflecting the calculated luminance compensation value on the pixel data of each of the stored pixels.

Wherein the luminance compensation value is a division value of a ratio of 1 to a subtraction value of the first display section ratio and a ratio of the second display section.

Wherein the memory stores a maximum input tone value for each position of each sensing line and the panel driver is configured to control the brightness compensation data to be generated when the pixel data reflected in the luminance compensation value exceeds the maximum input tone value And a maximum gradation value according to the number of bits of the pixel data is set as a gradation value of the pixel data.

According to another aspect of the present invention, there is provided a method of driving an organic light emitting display including a display panel including a plurality of pixels having a driving transistor for emitting an organic light emitting diode, Setting the display panel as a first display period, a sensing period, and a second display period; Displaying pixel data in each pixel of the sensing line during the first display period; And sensing the characteristic change of the driving transistor included in the pixels of the sensing line during the sensing period, and outputting the compensated luminance compensation data of the sensing line during the second display period to each pixel of the sensing line, On the display screen.

The driving method of the OLED display may further include storing a first display period ratio, a sensing period ratio, and a second display period ratio for each position of each sensing line in a memory.

The method of driving the organic light emitting display includes: storing pixel data of each pixel to be supplied to the sensing line during the first display period; Calculating a luminance compensation value based on a ratio of a first display section and a second display section corresponding to a sensing line stored in the memory, and reflecting the calculated luminance compensation value to pixel data of the stored pixels, The method of claim 1, further comprising the step of generating data.

Wherein the luminance compensation value is a division value of a ratio of 1 to a subtraction value of the first display section ratio and a ratio of the second display section.

Wherein the memory stores a maximum input gradation value for each position of each sensing line, and when the pixel data reflected in the luminance compensation value exceeds the maximum input gradation value at the time of generating the luminance compensation data, And the maximum gradation value according to the number of bits is set as the gradation value of the pixel data.

According to the solution of the above-mentioned problems, the organic light emitting display device and the driving method thereof according to the present invention have the following effects.

First, the luminance deviation between the horizontal lines due to the real-time compensation of the sensing line can be minimized.

Second, the visibility problem of the sensing line in which the sensing line is recognized by the black luminance of the sensing line can be solved.

1 is a diagram illustrating a problem that a sensing line is recognized on a screen by a conventional sensing method.
2 is a view for explaining an organic light emitting display according to an embodiment of the present invention.
3 is a diagram showing the structure of one pixel shown in Fig.
4 is a waveform diagram for explaining driving of the pixel shown in FIG.
5 is a block diagram for explaining the configuration of the timing control unit shown in FIG.
6A and 6B are views for explaining the ratio of the first display interval, the sensing interval, and the second display interval for each sensing line according to the present invention.
7 is a diagram for explaining maximum input tone values per sensing line according to the present invention.
8A and 8B are diagrams for explaining a method of generating luminance compensation data to be displayed in the second display period of the sensing line according to the present invention.
9 is a view for explaining a configuration of a column driver shown in FIG.
10 is a waveform diagram showing driving waveforms of first and second display periods according to the embodiment of the present invention.
11 is a waveform diagram showing a driving waveform of a sensing period according to an embodiment of the present invention.

The meaning of the terms described herein should be understood as follows.

The word " first, "" second," and the like, used to distinguish one element from another, are to be understood to include plural representations unless the context clearly dictates otherwise. The scope of the right should not be limited by these terms.

It should be understood that the terms "comprises" or "having" does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

It should be understood that the term "at least one" includes all possible combinations from one or more related items. For example, the meaning of "at least one of the first item, the second item and the third item" means not only the first item, the second item or the third item, but also the second item and the second item among the first item, Means any combination of items that can be presented from more than one.

The term "on" means not only when a configuration is formed directly on top of another configuration, but also when a third configuration is interposed between these configurations.

Hereinafter, preferred embodiments of an organic light emitting diode display and a driving method thereof according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a view for explaining an organic light emitting diode display according to an embodiment of the present invention, FIG. 3 is a diagram illustrating the structure of one pixel shown in FIG. 2, Fig.

Referring to FIGS. 2 to 4, the OLED display includes a display panel 100 and a panel driver 200.

The display panel 100 includes a plurality of pixels P. [ The plurality of pixels P includes a plurality of gate line groups GL1 to GLm, a plurality of data lines DL1 to DLn and a plurality of reference lines RL1 to RLn aligned with the plurality of data lines DL1 to DLn, RLn in the pixel region. A plurality of driving voltage lines PL are formed in the display panel 100 in parallel with the plurality of data lines DL1 to DLn and supplied with a driving voltage VDD from a voltage supply unit have.

Each of the plurality of pixels P includes a pixel circuit PC and an organic light emitting element OLED. In this case, each of the plurality of pixels P may be any one of a red pixel, a green pixel, a blue pixel, and a white pixel. One unit pixel for displaying one image may include an adjacent red pixel, a green pixel, and a blue pixel, or may include an adjacent red pixel, a green pixel, a blue pixel, and a white pixel.

In one embodiment, the pixel circuit PC may include a first switching transistor Tsw1, a second switching transistor Tsw2, a driving transistor Tdr, and a capacitor Cst. Here, the transistors Tsw1, Tsw2, and Tdr may be an a-Si TFT, a poly-Si TFT, an oxide TFT, an organic TFT, or the like as an N-type thin film transistor (TFT).

The first switching transistor Tsw1 includes a gate electrode connected to the first gate line GLa, a first electrode connected to the adjacent data line DL, and a first node n1, which is a gate electrode of the driving transistor Tdr, And a second electrode connected to the second electrode. The first switching transistor Tsw1 may supply the data voltage Vdata to the data line DL according to the first gate signal GSa of the gate-on voltage level supplied to the first gate line GLa. 1 node n1, that is, the gate electrode of the driving transistor Tdr.

The second switching transistor Tsw2 includes a gate electrode connected to the second gate line GLb, a first electrode connected to the adjacent reference line RL, and a second node n2, which is a source electrode of the driving transistor Tdr, And a second electrode connected to the second electrode. The second switching transistor Tsw2 is connected to the reference voltage Vref supplied to the reference line RL in accordance with the second gate signal GSb of the gate-on voltage level supplied to the second gate line GLb Voltage Vpre) to the second node n2, that is, the source electrode of the driving transistor Tdr.

The capacitor Cst includes first and second electrodes connected between the gate electrode and the source electrode of the driving transistor Tdr, that is, the first and second nodes n1 and n2. The capacitor Cst charges the difference voltage between the voltages supplied to the first and second nodes n1 and n2, and then switches the driving transistor Tdr according to the charged voltage.

The driving transistor Tdr includes a gate electrode commonly connected to the second electrode of the first switching transistor Tsw1 and the first electrode of the capacitor Cst, a first electrode of the second switching transistor Tsw2 and a capacitor Cst, A source electrode commonly connected to the organic light emitting device OLED, and a drain electrode connected to the driving voltage line PL. This driving transistor Tdr controls the amount of current flowing from the driving voltage line PL to the organic light emitting element OLED by being turned on by the voltage of the capacitor Cst.

In the above-described embodiment, the pixel circuit PC is composed of three transistors and one capacitor. However, the number of transistors and capacitors constituting the pixel circuit PC may be variously modified.

The organic light emitting diode OLED emits monochromatic light having a luminance corresponding to the data current Ioled by the data current Ioled supplied from the pixel circuit PC, that is, the driving transistor Tdr. The organic light emitting device OLED includes an anode electrode (not shown) connected to the second node n2 of the pixel circuit PC, an organic layer (not shown) formed on the anode electrode, and a cathode electrode . At this time, the organic layer may have a structure of a hole transporting layer / an organic light emitting layer / an electron transporting layer or a structure of a hole injecting layer / a hole transporting layer / an organic light emitting layer / an electron transporting layer / an electron injecting layer. Further, the organic layer may further include a functional layer for improving the luminous efficiency and / or lifetime of the organic light emitting layer. The cathode electrode may be formed individually in each of the plurality of pixels P or may be formed so as to be commonly connected to the plurality of pixels P. The cathode electrode may be provided with a constant voltage level from a voltage supply unit A cathode voltage VSS having a voltage level of zero is supplied.

Each of the plurality of gate line groups GL1 to GLm is formed to be parallel to the first direction of the display panel 100, for example, the lateral direction. At this time, each of the plurality of gate line groups GL1 to GLm consists of first and second gate lines GLa and GLb adjacent to each other. The first and second gate signals GSa and GSb are separately supplied from the panel driver 200 to the first and second gate lines GLa and GLb of the gate line groups GL1 to GLm .

Each of the plurality of data lines DL1 to DLn is formed to be parallel to the second direction of the display panel 100, for example, the longitudinal direction so as to intersect each of the plurality of gate line groups GL1 to GLm. A data voltage Vdata is supplied from the panel driver 200 to each of the data lines DL1 to DLn.

Each of the plurality of reference lines RL1 to RLn is formed in parallel with each of the plurality of data lines DL1 to DLn. The reference voltage Vref or the precharging voltage Vpre is selectively supplied from the panel driver 200 to the reference lines RL1 to RLn.

The panel driver 200 sequentially drives each pixel P formed on each horizontal line of the display panel 100 in units of one horizontal period to display an image in units of one frame, And the sensing line is driven by the first display period FDP, the sensing period SP and the second display period SDP. That is, in the case of each pixel P of the sensing line, the luminance corresponding to the data displayed in the first display period FDP due to the luminance drop due to the black luminance corresponding to the sensing period SP is supplied to the data of the next frame The panel driver 200 compensates the luminance reduction of the sensing line to the data of the first display period FDP and displays it on the sensing line in the second display period SDP after the sensing period SP Thereby compensating for the decrease in luminance due to the sensing period SP of the sensing line.

The first display period FDP is set as the data valid period of each frame Fn. That is, the first display period FDP is set to the effective data period of the vertical active period Vactive of the vertical synchronization signal Vsync or the data enable signal DE.

The sensing period SP is a period overlapping the vertical blanking period BP of the vertical synchronizing signal Vsync so that the last data valid signal of the last data enable signal DE in the current frame Fn and the last data valid signal of the last data enable signal DE Vsync may be set to the interval between the rising points of Vsync. That is, the sensing interval SP may be set to include the vertical blank interval BP and the back porch interval Vbp of the current frame Fn. Here, the back porch interval Vbp is a period between the last data valid signal and the polling time of the vertical synchronization signal Vsync.

The second display period SDP may be set as a period from the end of the sensing period SP to just before the data of the next frame Fn + 1 is displayed. The second display period SDP is a period for displaying the luminance compensation data to compensate for the luminance reduction of the sensing line according to the sensing period SP. The luminance compensation data may include a vertical synchronization signal (Vfp) between the rising point of the first data enable signal (Vsync) and the rising point of the first data enable signal (DE).

The first display period FDP, the sensing period SP, and the second display period SDP have the same one-frame period. In this case, the first display period FDP and the second display period SDP may vary depending on the driving time of the horizontal lines and the formation position on the display panel 100. [ That is, an image displayed on each horizontal line displayed in the first display period FDP of the current frame is held for one frame until data of the next frame is supplied.

The panel driver 200 includes a timing controller 210, a row driver 220, and a column driver 230.

The timing controller 210 controls the timing of the horizontal lines VSS based on the vertical synchronization signal Vsync and the data enable signal DE among the timing synchronization signals TSS supplied from the outside on the basis of the timing synchronization signal TSS supplied from the outside, The first to third gate control signals GCS1 and GCS2 corresponding to the first display period FDP, the sensing period SP and the second display period SDP, respectively, GCS2 and GCS3 and a data control signal DCS to control the driving timings of the row driving unit 220 and the column driving unit 230, respectively. In particular, the timing controller 210 generates an auxiliary data enable signal DE 'in the second display period SDP based on the vertical synchronizing signal Vsync, the horizontal synchronizing signal Hsync, and the main clock (not shown) So that the luminance compensation data in which the offset of the luminance reduction of the sensing line is compensated to the data of the first display period FDP during the second display period SDP is displayed on each pixel P of the sensing line.

The timing controller 210 arranges the input data Idata inputted from the outside into the pixel data DATA1 in accordance with the pixel arrangement structure and the driving method of the display panel 100 and supplies the pixel data DATA1 of each pixel The pixel data DATA1 to be supplied to the horizontal scanning line P is stored in the memory 240 together with the position information of the sensing line and the pixel data DATA1 to be supplied to each horizontal line during the first display period FDP is stored in the horizontal And supplies it to the column driver 230 in units of periods. The timing controller 210 generates sensing data DATA2 to be supplied to each pixel P of the sensing line during the sensing period SP and supplies the sensing data DATA2 to the column driver 230. [ The timing controller 210 compensates for the offset of the luminance reduction of the sensing line to the pixel data DATA1 of the sensing line stored in the memory 240 during the second display period SDP, And supplies the generated luminance compensation data DATA3 to the column driving unit 230. [

The timing controller 210 controls at least one of the threshold voltage and the mobility of the driving transistor included in each pixel P supplied from the column driver 230 during the sensing period SP Of the pixels P stored in the memory unit 240 during the first display period FDP in the memory unit 240 and stores sensing data Sdata corresponding to the sensing data Sdata And supplies the corrected input data Idata to the column driver 230. The column driver 230 receives the input data Idata. The sensing data Sdata sensed in the sensing period SP of the current frame Fn may be applied to the first display period FDP of the next frame Fn + P after the sensing data (Sdata) is acquired.

The row driver 220 is connected to the plurality of gate line groups GL1 to GLm and selectively outputs the first to third gate control signals GCS1, GCS2, and GCS3 selectively supplied from the timing controller 210. [ The first and second gate signals GSa and GSb corresponding to the first display period FDP, the sensing period SP and the second display period SDP are generated and applied to the plurality of gate line groups GL1 to GLm Supply. Here, each of the first to third gate control signals GCS1, GCS2, and GCS3 may be a gate start signal, a gate shift clock, or the like.

In detail, during the first display period FDP, the row driver 220 drives the pixels of each horizontal line according to the first gate control signal GCS1 to the data charging period and the light emitting period, And the second gate signals GSa and GSb to the plurality of gate line groups GL1 to GLm sequentially. During the sensing period SP, the row driver 220 drives the pixels of the sensing line in the initialization period, the voltage charging period, and the voltage sensing period according to the second gate control signal GCS2. 1 and the second gate signals GSa and GSb and supplies them to the gate line group of the sensing line. During the second display period (SDP), the row driver 220 drives the pixels of the sensing line according to the third gate control signal GCS3 in the data charging period and the light emitting period, 2 gate signals GSa and GSb and supplies them to the gate line group of the sensing line.

The column driver 230 is connected to each of the plurality of data lines DL1 to DLn and the plurality of reference lines RL1 to RLn and supplies the data control signal DCS selectively supplied from the timing controller 210 to the column driver 230. [ (DATA1, DATA2, and DATA3) supplied from the timing controller 210 to the data voltage Vdata so as to correspond to the first display period FDP, the sensing period SP, and the second display period SDP, And supplies the reference voltage Vref or the precharged voltage Vpre to the data lines DL1 to DLn and selectively supplies the reference voltages Vref and Vpre to the reference lines RL1 to RLn.

Specifically, during the first display period FDP, the column driver 230 drives the column driver 230 to output the pixel data DATA1 as the data voltage Vdata during the data charging period of each horizontal line according to the data control signal DCS And supplies the reference voltage Vref to the data lines DL1 to DLn while selectively supplying the reference voltage Vref to the reference lines RL1 to RLn. During the sensing period SP, the column driver 230 outputs the sensing data DATA2 as the data voltage Vdata during the initialization period and the voltage charging period of the sensing line according to the data control signal DCS And supply the precharge voltage Vpre to the reference lines RL1 to RLn in the initialization period and supply the reference lines RL1 to RLn and the floating The sensing data Sdata is generated by sensing the voltage of the reference lines RL1 to RLn, that is, the characteristic change of the driving transistor Tdr of the corresponding pixel, and supplies the sensing data Sdata to the timing control unit 210. [ During the second display period SDP, the column driver 230 converts the luminance compensation data DATA3 to the data voltage Vdata during the data charging period of the sensing line according to the data control signal DCS. And supplies the reference voltage Vref to the data lines DL1 to DLn and selectively supplies the reference voltage Vref to the reference lines RL1 to RLn.

5 is a block diagram for explaining the configuration of the timing control unit shown in FIG.

4 and 5, a timing controller 210 according to the present invention includes a section controller 211, a data processor 213, a luminance compensator 215, a control signal generator 217, (219).

The interval control unit 211 receives the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the data enable signal (Hsync) of the timing synchronization signal TSS input from an external system body (not shown) or a graphics card The sensing period SP and the second display period SDP are set based on the first display period DE, the second display period DE, and the second display period DE. In particular, the interval controller 211 controls the operation of the sensing interval SP by setting one of the horizontal lines as a sensing line on a frame-by-frame basis.

The data processing unit 213 stores the sensing data Sdata supplied from the column driver 230 in the memory unit 240. The data processing unit 213 receives input data Idata input from an external system body (not shown) or a graphics card (not shown) during the first display period FDP set by the interval control unit 211, (DATA1) according to the pixel arrangement structure and the driving method of the liquid crystal display panel 100 and supplies them to the data output unit 219. [ At this time, the data processing unit 213 reads the sensing data Sdata corresponding to the input data Idata in the memory unit 240, and outputs the input data Idata on the basis of the read sensing data Sdata The pixel data DATA1 can be generated.

The data processing unit 213 generates the sensing data DATA2 stored or set in the memory unit 240 during the sensing period SP set by the interval control unit 211 and supplies the sensing data DATA2 to the data output unit 219.

The luminance compensation unit 215 generates luminance compensation data DATA3 to be supplied to the sensing line during the second display period SDP set by the interval control unit 211 and supplies it to the data output unit 219. [ To this end, the luminance compensation unit 215 includes a line counter 215a, a line memory unit 215b, a lookup table (LUT), and a luminance compensation data generation unit 215c.

The line counter 215a generates counting information of each horizontal line according to the data enable signal DE based on the vertical synchronization signal Vsync. For example, the line counter 215a is enabled by the rising signal of the vertical synchronizing signal Vsync, counts every rising signal of the data enable signal DE to output counting information, and outputs the vertical synchronizing signal Vsync ) ≪ / RTI >

The line memory 215b is connected to each pixel P of the sensing line of the pixel data DATA1 output from the data processing unit 213 in the first display period FDP based on the interval control of the interval control unit 211 And stores pixel data DATA1 for one horizontal line to be supplied. 4, in the current frame Fn, when the first horizontal line is set as the sensing line, the line memory 215b outputs the pixel data of the first horizontal line outputted from the data processing unit 213 P of the pixel data DATA1 for one horizontal line to be supplied. In this line memory 215b, pixel data DATA1 of horizontal lines corresponding to the number of sensing lines set in the sensing period SP can be stored in units of horizontal lines.

The look-up table (LUT) includes a first display period occupied by the first display period FDP, a sensing period occupied by the sensing period SP, and a second display period occupied by the second display period SDP, And the second display interval ratio is stored for each horizontal line. That is, each pixel of each horizontal line sequentially displays the data of the current frame and holds it until immediately before the data of the next frame is supplied. Since the sensing period SP overlaps the blank interval of the vertical synchronization signal Vsync, the first display period FDT of each horizontal line gradually decreases from the first horizontal line to the last horizontal line. For example, as shown in FIGS. 6A and 6B, the first display intervals FDT of the first horizontal line and the n-1th horizontal line are different from each other, and the second display interval SDT is also different Accordingly, when the same compensation value is applied to all the sensing lines in the luminance compensation through the second display period SDT, uniform luminance compensation can not be performed. Therefore, accurate luminance compensation can be performed during the second display period SDT Information on the ratio of the first display period FDT of the sensing line to the horizontal line is required. Therefore, the ratio of the first display section, the sensing section, and the second display section of each horizontal line obtained through the preliminary experiment are stored in the look-up table (LUT) for each horizontal line.

The maximum input tone value for each horizontal line is further stored in the look-up table (LUT). At this time, as shown in FIG. 7, the maximum input tone value for each horizontal line is set to a different value for each position of each horizontal line through a preliminary experiment and is stored. That is, the luminance compensation data DATA3 displayed during the second display period SDP is set by the offset of the pixel data DATA1 of the horizontal line stored in the line memory 215b and the luminance reduction of the sensing line , And this occurs when the maximum gray level value according to the number of bits of data is exceeded. Accordingly, the maximum input tone value for each horizontal line becomes a reference value for clipping the tone value of the luminance compensation data (DATA3) to the maximum tone value according to the number of bits of data. 7, when the data is 8 bits and the maximum input gradation value of the k-th horizontal line is set to "200 ", the luminance compensation data DATA3 of the k- DATA1) exceeds "200 ", it is clipped to" 255 ".

4 and 5, the luminance compensation data generation unit 215c generates the luminance compensation data based on the ratio of the first display period of each horizontal line stored in the look-up table (LUT), the ratio of the sensing period The luminance compensation to be supplied to each pixel P of the sensing line based on the first display period ratio, the second display period ratio, and the maximum input gradation value and the pixel data (DATA1) of each pixel P of the sensing line stored in the line memory 215b And supplies the data DATA3 to the data output unit 219. [ At this time, the luminance compensation data generation unit 215c may generate the luminance compensation data (DATA3) before the second display period SDP.

Specifically, the luminance compensation data generation unit 215c determines whether the pixel data (DATA1) exceeds the maximum input gradation value, and when the pixel data (DATA1) exceeds the maximum input gradation value, the pixel data (DATA1) (1-FDT) / SDT based on the first display interval ratio FDT and the second display interval ratio SDT, as shown in the following equation (1): " (1) ), And generates luminance compensation data (DATA3) by multiplying the pixel data (DATA1) corrected to the maximum gradation value by the calculated luminance compensation value (1-FDT) / SDT). On the other hand, when the pixel data (DATA1) does not exceed the maximum input gradation value, the luminance compensation data generation section 215c does not correct the pixel data (DATA1) (1-FDT) / SDT) on the basis of the first display interval ratio FDT and the second display interval ratio SDT) and supplies the pixel data DATA1 (1-FDT) / SDT) to the calculated luminance compensation value (X) to generate the luminance compensation data (DATA3).

8A, a pixel P included in an i-th sensing line for displaying an image of pixel data DATA1 having a gray level value of "200" for one frame is taken as an example, (DATA3) is generated as follows.

First, the luminance compensation data generation unit 215c reads the maximum input tone value for the i-th sensing line in the look-up table (LUT) and compares it with the pixel data (DATA1). Hereinafter, it is assumed that the pixel data (DATA1) does not exceed the maximum input tone value.

Then, the luminance compensation data generation unit 215c generates the luminance compensation data for each of the first display period ratio FDT, the sensing period ratio ST, and the second display period ratio SDT for the i-th sensing line in the look-up table (LUT) And generates luminance compensation data DATA3 through the operation of Equation (1). Here, in the case of the pixel P included in the i-th sensing line, the luminance compensation data DATA3 is generated so as to have the gray level value of "220". At this time, the division operation (÷) in Equation (1) is preferably rounded up to three decimal places.

As another example, as shown in Fig. 8B, a pixel P included in a j-th sensing line displaying an image of pixel data (DATA1) having a grayscale value of "200" (DATA3) is generated as follows.

First, the luminance compensation data generation unit 215c reads the maximum input tone value for the jth sensing line in the look-up table (LUT) and compares it with the pixel data (DATA1). Hereinafter, it is assumed that the pixel data (DATA1) does not exceed the maximum input tone value.

Then, the luminance compensation data generating unit 215c generates a luminance compensation data generating unit 215c for generating a first display period ratio FDT, a sensing period ratio ST and a second display period ratio SDT for the jth sensing line in the look-up table (LUT) And generates luminance compensation data DATA3 through the operation of Equation (1). Here, in the case of the pixel P included in the jth sensing line, the luminance compensation data DATA3 is generated so as to have a gray level value of "210 ". At this time, the division operation (÷) in Equation (1) is preferably rounded up to three decimal places.

4 and 5, the control signal generating unit 217 generates a control signal for controlling the first display period FDP, the sensing period SP, and the second display period SDP, respectively, based on the interval control of the interval control unit 211 GCS2 and GCS3 and a data control signal DCS corresponding to the first and second gate control signals GCS1, GCS2 and GCS3 to the row driving unit 220 and the column driving unit 230, respectively.

Specifically, the control signal generation unit 217 generates a control signal based on the timing synchronization signal TSS based on the control of the first display period FDP according to the timing control unit 211, A first gate control signal GCS1 for sequentially supplying the gate signals GSa and GSb to the groups GL1 to GLm is generated and data And generates a data control signal DCS for supplying a voltage.

The control signal generation unit 217 generates a control signal for controlling the sensing period SP based on the timing synchronization signal TSS based on the control of the sensing period SP according to the period control unit 211 Generates a second gate control signal GCS2 for supplying the gate signals GSa and GSb and generates a data control signal DCS for supplying a data voltage to each pixel P of the sensing line so as to be synchronized with the second gate control signal GCS2 .

The control signal generating unit 217 generates a control signal for controlling the timing of the corresponding sensing line SDP during the second display period SDP according to the timing synchronization signal TSS based on the control of the second display period SDP according to the interval control unit 211. [ A third gate control signal GCS3 for supplying gate signals GSa and GSb to the gate line group and a data control signal DCS for supplying a data voltage to each pixel P of the sensing line, ). At this time, the control signal generator 217 decreases the counting value of the clock counter for generating the gate shift clock of the third gate control signal GCS3 at the start time of the second display period SDP, And a gate shift clock having a frequency that is faster than that of the clock signal FDP, and at the time point corresponding to the sensing line, the counting setting value of the clock counter is restored to a reference setting value, By generating the shift clock, the normal gate signals GSa and GSb are supplied to the gate line group of the sensing line.

The control signal generating unit 217 generates a control signal for controlling the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync and the main clock Mclk based on the control of the second display period SDP according to the interval control unit 211 Generates an auxiliary data enable signal DE 'for displaying the luminance compensation data DATA3 on each pixel P of the sensing line based on the generated auxiliary data enable signal DE' 219). That is, as shown in FIG. 4, the control signal generating unit 217 generates a control signal using the horizontal synchronization signal Hsync generated between the rising time of the vertical synchronization signal Vsync and the rising time of the first data enable signal And supplies the auxiliary data enable signal DE 'to the data output unit 219.

The data output unit 219 supplies the column driving unit 230 with the pixel data DATA1 or the sensing data DATA2 supplied from the data processing unit 213 based on the interval control of the interval control unit 211 And supplies the luminance compensation data (DATA3) supplied from the luminance compensation unit 215 to the column driving unit 230. [ The data output unit 219 outputs the pixel data DATA1 to the column driver 230 according to the control of the first display period FDP according to the interval controller 211 based on the data enable signal DE. And supplies the sensing data DATA2 to the column driver 230 under the control of the sensing interval SP according to the interval controller 211 based on the data enable signal DE, (DATA3) in accordance with the control of the second display period (SDP) according to the interval control unit 211 on the basis of the auxiliary data enable signal DE 'supplied from the control signal generating unit 217, To the driving unit 230.

The timing controller 210 may be configured to apply the generation algorithm of the above-described luminance compensation data based on the red, green, and blue RGB input data, and the RGBW input data converted from the RGB input data, The input data may be converted into a luminance component and a chrominance component, and the above-described generation algorithm of luminance compensation data may be applied based on the converted luminance component.

9 is a view for explaining a configuration of a column driver shown in FIG.

2 and 9, a column driver 230 according to an embodiment of the present invention includes a data driver 232 and a sensing unit 234.

The data driver 232 receives the data DATA1, DATA2 and DATA3 supplied from the timing controller 210 according to the first display interval FDP, the sensing interval SP and the second display interval SDP, To a voltage (Vdata) and supplies it to the data line DL. That is, during the first display period FDP, the data driver 232 converts the pixel data DATA1 to the data voltage Vdata in the data charging period of each horizontal line according to the data control signal DCS, DL1 to DLn. During the sensing period SP, the data driver 232 converts the sensing data DATA2 into the data voltage Vdata in the initialization period and the voltage charging period of the sensing line according to the data control signal DCS, (DL1 to DLn). During the second display period SDP, the data driver 232 converts the luminance compensation data DATA3 to the data voltage Vdata during the data charging period of the sensing line according to the data control signal DCS, DL1 to DLn.

The data driver 232 includes a shift register for generating a sampling signal based on a data start signal and a data shift signal supplied from the timing controller 210, a latch unit for latching data (DATA) according to a sampling signal, A digital-to-analog converter for selecting and outputting a gradation voltage corresponding to data latched in a plurality of gradation voltages as a data voltage (Vdata), and a data output circuit for outputting a gradation voltage corresponding to the data output And an output unit for outputting the data voltage Vdata to the data line DL according to a signal.

9, the data driver 232 is connected to one data line (DL), but is connected to a data line corresponding to the set number of channels.

The sensing unit 234 is connected to the reference line RL of each pixel P and includes a switching unit 234a and an analog-to-digital converter 234b.

The switching unit 234a includes a reference voltage supply line RVL to which a reference voltage Vref is supplied, a precharging voltage supply line PVL to which a precharging voltage Vpre is supplied, and an analog-to-digital converter 234b And selectively connects to the reference line RL. That is, the switching unit 234a connects the reference voltage supply line RVL to the reference line RL during the first display period FDP or the second display period SDP. The switching unit 234a connects the precharged voltage supply line PVL to the reference line RL during the initialization period of the sensing period SP and outputs the reference voltage Vref during the data charging period of the sensing period SP. Floating the line RL and connecting the reference line RL to the analog-to-digital converter 234b during the voltage sensing period of the sensing interval SP.

The reference voltage Vref may be any of the gradation voltages output from the gradation voltage generator of the data driver 232. In this case, the reference voltage supply line RVL is connected to the gradation voltage generator. Here, the reference voltage Vref may have a voltage level of 0 (Zero) or a voltage level lower than the conduction voltage of the organic light emitting diode OLED.

In addition, the precharging voltage Vpre may be any one of the gradation voltages output from the gradation voltage generator. In this case, the precharging voltage supply line PVL is connected to the gradation voltage generator.

When the analog-to-digital converter 234b is connected to the reference line RL by switching of the switching unit 234a, the analog-to-digital converter 234b senses a voltage charged in the reference line RL, digitizes the sensed voltage, (Sdata), and supplies the generated sensing data (Sdata) to the timing controller (210).

10 is a waveform diagram showing driving waveforms of first and second display periods according to the embodiment of the present invention.

Referring to FIG. 10 together with FIG. 2 and FIG. 3, a method of driving the first and second display periods FDP and SDP of the pixel shown in FIG. 3 will be described.

First, one pixel is driven during the initialization period t1, the data charging period t2, and the light emission period t3 during the first and second display periods FDP and SDP.

In the initialization period t1, the first gate signal GSa of the gate-off voltage level is supplied to the first gate line GLa by driving the row driver 220, The second gate signal GSb is supplied to the second gate line GLb and the reference voltage Vref is supplied to the reference line RL by driving the column driver 230. [ Accordingly, in the initialization period t1, the first switching transistor Tsw1 is turned off by the first gate signal GSa and the second switching transistor Tsw2 is turned off by the second gate signal GSb The reference voltage Vref supplied to the reference line RL is supplied to the second node n2 by turning on the voltage of the second node n2 and the voltage of the capacitor Cst, Vref).

In the data charge period t2, the first gate signal GSa of the gate-on voltage level is supplied to the first gate line GLa by driving the row driver 220, The second gate signal GSb supplied to the line GLb is maintained at the gate-on voltage level and the reference voltage Vref is continuously supplied to the reference line RL by driving the column driver 230 And the data voltage Vdata is supplied to the data line DL. At this time, the data voltage Vdata has a voltage level reflecting the voltage corresponding to the characteristic change of the driving transistor Tdr according to the sensing data Sdata or a voltage level converted from the luminance compensation data DATA3. Accordingly, in the data charging period t2, the first switching transistor Tsw1 is turned on by the first gate signal GSa, the second switching transistor Tsw2 is turned on by the second gate signal GSb, The data voltage Vdata is supplied to the first node n1 and the reference voltage Vref is supplied to the second node n2.

Therefore, in the data charging period t2, the capacitor Cst is charged with the difference voltage Vdata-Vref between the data voltage Vdata and the reference voltage Vref.

In the light emission period t3, the first and second gate signals GSa and GSb of the gate-off voltage level are applied to the first and second gate lines GLa , And GLb. Accordingly, in the light emission period t3, each of the first and second switching transistors Tsw1 and Tsw2 is turned off by the first and second gate signals GSa and GSb so that the driving transistor Tdr is turned on And is turned on by the voltage stored in the capacitor Cst.

Therefore, during the light emission period t3, the turn-on driving transistor Tdr is set to a voltage difference (Vdata-Vref) between the data voltage Vdata and the reference voltage Vref, The data current Ioled is supplied to the light emitting element OLED so that the light emitting element OLED emits light. That is, when the first and second switching transistors Tsw1 and Tsw2 are turned off in the light emission period t3, the driving transistor Tdr is driven by the driving voltage EVDD supplied to the driving voltage line VL The voltage of the second node n2 is increased while the light emitting device OLED starts to emit light in proportion to the current and the voltage of the first node n2 is increased by the voltage of the second node n2 by the capacitor Cst, The gate-source voltage Vgs of the driving transistor Tdr is continuously maintained by the voltage of the capacitor Cst as the voltage of the node n1 rises and the light emitting device OLED emits light until the next initialization period t1 It continues.

In Equation (2), "k" is a value determined by the structure and physical characteristics of the driving transistor DT as a proportional constant. The mobility of the driving transistor DT and the channel width Quot; W / L "which is the ratio of the channel length W to the channel length L, and the like.

The data current Ioled flowing through the light emitting device OLED during the light emission period t3 is controlled by the reference voltage Vref adjusted according to the current deviation described above, Is determined by the difference between the data voltage (Vdata) and the reference voltage (Vref), which is adjusted only in accordance with the above-described current deviation, without being influenced by the variation of the threshold voltage (Vth) / mobility.

On the other hand, in the above description, the initialization period t1 may be omitted. That is, since the reference voltage Vref is supplied to the second node n2 during the data charging period t2, the data voltage Vdata and the reference voltage Vdata are applied to the capacitor Cst without the initialization period t1, (Vdata-Vref) of the reference voltage Vref.

11 is a waveform diagram showing a driving waveform of a sensing period according to an embodiment of the present invention.

Referring to FIG. 11 with reference to FIG. 2 and FIG. 3, a driving method of the sensing period SP of the pixel shown in FIG. 3 will be described.

First, one pixel is driven during the initialization period t1, the voltage charging period t2, and the voltage sensing period t3 during the sensing interval SP.

The first and second gate signals GSa and GSb of the gate-on voltage level are applied to the first and second gate lines GLa and GLb by the row driver 220 in the initialization period t1. And the sensing data voltage Vdata is supplied from the column driver 230 to the data line DL and the precharging voltage Vpre is supplied to the sensing line SLi. Thus, each of the first and second switching transistors Tsw1 and Tsw2 of the sub-pixel P is turned on by the first and second gate signals GSa and GSb of the gate-on voltage level, The data voltage Vdata is supplied to the first node n1 and the voltage of the second node n2 is initialized to the precharging voltage Vpre so that the data voltage Vdata and the pre- The differential voltage Vdata-Vpre of the voltage Vpre is charged.

In the voltage charging period t2, the first and second gate signals GSa and GSb of the gate-on voltage level are applied to the first and second gate lines GLa and GLb according to the row driver 220, And the sensing data voltage Vdata is continuously supplied to the data line DL by driving the column driver 230 and the reference line RL is floated. Accordingly, in the voltage charging period t2, the driving transistor Tdr is turned on by the sensing data voltage Vdata, and the voltage corresponding to the current flowing in the driving transistor Tdr, which is turned on, The reference line RL of FIG. At this time, a voltage corresponding to the threshold voltage Vth of the driving transistor Tdr is charged in the reference line RL.

In the voltage sensing period t3, the first gate signal GSa of the gate-off voltage level is supplied to the first gate line GLa by the row driver 220 and the gate- And the floating reference line RL is connected again to the column driver 230. The second gate line GLb is connected to the second gate line GLb and the floating reference line RL is connected to the column driver 230 again. Accordingly, during the voltage sensing period t3, the column driver 230 detects the voltage charged in the connected reference line RL and outputs the detected voltage, that is, the threshold voltage of the driving transistor Tdr And supplies the generated sensing data to the timing controller 210. [

On the other hand, when the first switching transistor Tsw1 of the pixel P is turned on only during the initialization period t1 and the sensing data voltage Vdata is supplied only during the initialization period t1, The column driver 230 generates sensing data corresponding to the degree of mobility of the driving transistor Tdr through the reference line RL and provides the sensing data to the timing controller 210.

On the other hand, the pixel structure of the OLED display according to the present invention, and the driving waveforms of the display period and the sensing period of the pixel are not limited to the above description, The present invention can be applied to any pixel structure.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

100: display panel 200:
210: timing control unit 211:
213: Data processing unit 215:
217: luminance compensation data generation unit 219: data output unit
230: a row driver 240: a column driver

Claims (10)

A display panel including a plurality of pixels each having a driving transistor for emitting an organic light emitting element; And
Wherein the display panel is set as a first display period, a sensing period, and a second display period, pixel data is displayed on each pixel of the sensing line during the first display period, and the pixel data is included in the pixels of the sensing line during the sensing period And a panel driving unit for sensing a change in the characteristics of the driving transistor and for displaying luminance compensation data compensated for luminance reduction of the sensing line during the second display period on each pixel of the sensing line. To the organic light emitting display device. The method according to claim 1,
Wherein the panel driver includes a memory for storing a first display period ratio, a sensing period ratio, and a second display period ratio for each position of each sensing line. 3. The method of claim 2,
Wherein the panel-
Storing pixel data of each pixel to be supplied to the sensing line in the first display period,
Calculating a luminance compensation value based on a first display section ratio and a second display section ratio corresponding to a sensing line stored in the memory, and reflecting the calculated luminance compensation value to pixel data of the stored pixels, The organic light emitting display device comprising: The method of claim 3,
Wherein the luminance compensation value is a division value of a ratio of 1 to a subtraction ratio of the first display section ratio and a ratio of the second display section. The method of claim 3,
The maximum input tone value for each sensing line is stored in the memory,
When the pixel data reflected in the luminance compensation value exceeds the maximum input tone value at the time of generating the luminance compensation data, the panel driving unit sets the maximum tone value according to the number of bits of the pixel data as the tone value of the pixel data And the organic light emitting display device. A driving method of an organic light emitting display device including a display panel having a plurality of pixels each having a driving transistor for emitting an organic light emitting element,
Setting the display panel as a first display period, a sensing period, and a second display period;
Displaying pixel data in each pixel of the sensing line during the first display period; And
Sensing the characteristic change of the driving transistor included in the pixels of the sensing line during the sensing period, and outputting the compensated luminance compensation data to the pixels of the sensing line during the second display period Wherein the organic light emitting display device comprises a plurality of organic light emitting display devices. The method according to claim 6,
And storing the ratio of the first display period, the sensing period, and the second display period for each position of each sensing line in a memory. 8. The method of claim 7,
Further comprising storing pixel data of each pixel to be supplied to the sensing line during the first display period,
Calculating a luminance compensation value based on a first display section ratio and a second display section ratio corresponding to a sensing line stored in the memory, and reflecting the calculated luminance compensation value to pixel data of the stored pixels, The method of driving an organic light emitting display according to claim 1, further comprising the step of: 9. The method of claim 8,
Wherein the luminance compensation value is a division value of a ratio of 1 to a subtraction ratio of the first display section ratio and a ratio of the second display section. 10. The method of claim 9,
The maximum input tone value for each sensing line is stored in the memory,
When the pixel data reflected in the luminance compensation value exceeds the maximum input tone value at the time of generation of the luminance compensation data, the maximum tone value according to the number of bits of the pixel data is set as the tone value of the pixel data Wherein the organic light emitting display device comprises a plurality of pixels.

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