KR20140085708A - Method of manufacturing a semiconductor device - Google Patents

Method of manufacturing a semiconductor device Download PDF

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Publication number
KR20140085708A
KR20140085708A KR1020120154545A KR20120154545A KR20140085708A KR 20140085708 A KR20140085708 A KR 20140085708A KR 1020120154545 A KR1020120154545 A KR 1020120154545A KR 20120154545 A KR20120154545 A KR 20120154545A KR 20140085708 A KR20140085708 A KR 20140085708A
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KR
South Korea
Prior art keywords
growth substrate
layer
light emitting
substrate
emitting structure
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KR1020120154545A
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Korean (ko)
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최광용
이동건
이호준
이충현
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주식회사 엘지실트론
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Priority to KR1020120154545A priority Critical patent/KR20140085708A/en
Publication of KR20140085708A publication Critical patent/KR20140085708A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/7806—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Led Devices (AREA)

Abstract

A method of manufacturing a semiconductor device includes growing a light emitting structure on a growth substrate, bonding a carrier substrate to the growth substrate, and removing the growth substrate from the light emitting structure. In order to remove the growth substrate, the first CLO process is performed at the first etching temperature to remove the growth substrate, and the second CLO process is performed at the second etching temperature for the second period to remove the residual spot. The second etching temperature is at least 20 DEG C higher than the first etching temperature.

Description

[0001] The present invention relates to a method of manufacturing a semiconductor device,

An embodiment relates to a method of manufacturing a semiconductor device.

Since nitride based compound semiconductor materials have high breakdown voltage and mobility, they are used not only in various power electronic devices but also in semiconductor devices for generating light.

Semiconductor devices have advantages over conventional light sources such as fluorescent lamps and incandescent lamps in terms of low power consumption, semi-permanent lifetime, fast response speed, safety, and environmental friendliness. Therefore, much research is underway to replace existing light sources with semiconductor devices.

2. Description of the Related Art Semiconductor devices are increasingly used as light sources for various lamps used in indoor / outdoor applications, lighting devices such as liquid crystal display devices, electric sign boards, and street lamps.

Semiconductor devices are classified into horizontal semiconductor devices and vertical semiconductor devices.

In a vertical semiconductor device, a chemical lift-off (CLO) process is used to remove a growth substrate.

If the growth substrate is not completely removed by the CLO process, a residual spot remains. When a semiconductor device is manufactured in the state where such a residual spot is present, there is a problem that electrical characteristics and optical characteristics of the semiconductor device deteriorate due to such a residual spot.

The embodiment provides a method of manufacturing a semiconductor device capable of completely removing a residual spot.

The embodiment provides a method of manufacturing a semiconductor device capable of improving optical characteristics and electrical characteristics.

According to an embodiment, a method of manufacturing a semiconductor device includes the steps of: providing a growth substrate; Growing a light emitting structure on the growth substrate; Bonding a carrier substrate to the growth substrate; And removing the growth substrate from the light emitting structure. The removing the growth substrate may include removing a growth substrate by performing a first CLO process at a first etch temperature for a first time period; And performing a second CLO process at a second etch temperature for a second time period to remove the remaining spots. And the second etching temperature is at least 20 DEG C higher than the first etching temperature.

According to an embodiment, a method of manufacturing a semiconductor device includes the steps of: providing a growth substrate; Growing a light emitting structure on the growth substrate; Bonding a carrier substrate to the growth substrate; And removing the growth substrate from the light emitting structure, wherein the growth substrate is removed by an etchant containing at least one of H 2 SO 4 , HF, HNO 3, and NH 4 HF 2 .

The embodiment may further include removing the residual spot by adding a CLO process in a state where the temperature is raised after the growth substrate is removed.

In this embodiment, the optimum etching rate can be obtained by controlling the kind and the composition ratio of the etchant, and the growth substrate can be removed with the etch rate to completely remove the residual spots.

The embodiments can improve the optical and electrical properties by completely removing the residual spots.

1 to 10 are cross-sectional views showing a manufacturing process of a semiconductor device according to an embodiment.
11 is a view for explaining the CLO process according to the embodiment.
12A to 12D are diagrams showing the residual spots in the second CLO section.
13A to 13C are diagrams showing a residual spot according to an etching rate in a 2-inch growth substrate.
FIGS. 14A and 14B are diagrams showing a residual spot according to the etch rate in the growth substrate of 6 or more. FIG.

In describing an embodiment according to the invention, in the case of being described as being formed "above" or "below" each element, the upper (upper) or lower (lower) Directly contacted or formed such that one or more other components are disposed between the two components. Also, in the case of "upper (upper) or lower (lower)", it may include not only an upward direction but also a downward direction based on one component.

1 to 10 are cross-sectional views showing a manufacturing process of a semiconductor device according to an embodiment.

As shown in FIG. 1, a growth substrate 110 may be provided, and a buffer layer may be grown on the growth substrate 110.

The growth substrate 110 may be formed of at least one selected from the group consisting of sapphire (Al 2 O 3), SiC, Si, GaAs, GaN, ZnO, GaP, InP and Ge.

The buffer layer 120 may be formed to mitigate the lattice constant difference between the growth substrate 110 and the light emitting structure 130 grown on the buffer layer 120 by a post-process.

The buffer layer 120 may be formed of a II-VI or III-V compound semiconductor. The buffer layer 120 may be formed of at least one of AlN, AlGaN, and GaN, or a multi-layer structure composed of at least one of AlN, AlGaN, and GaN.

As shown in FIG. 2, the light emitting structure 130 may be grown on the buffer layer 120.

The light emitting structure 130 may function to generate light.

The light emitting structure 130 may include a first conductive semiconductor layer 132, an active layer 134, and a second conductive semiconductor layer 136.

The first conductivity type semiconductor layer 132, the active layer 134, and the second conductivity type semiconductor layer 136 may be sequentially grown on the buffer layer 120.

The first conductive semiconductor layer 132, the active layer 134 and the second conductive semiconductor layer 136 may be formed of a II-VI or III-V compound semiconductor.

Although not shown, another compound semiconductor layer may be grown under the first conductive semiconductor layer 132 and / or on the second conductive semiconductor layer 136, but the present invention is not limited thereto.

The first conductive semiconductor layer 132 may be, for example, an n-type semiconductor layer including an n-type dopant. The first conductive semiconductor layer 132 may be a semiconductor material having a composition formula of In x Al y Ga 1 -x- y N (0? X? 1, 0? Y? 1, 0? X + For example, at least one selected from the group consisting of InAlGaN, GaN, AlGaN, InGaN, AlN, InN and AlInN, and an n-type dopant such as Si, Ge, or Sn may be doped.

The active layer 134 may include a first carrier injected through the first conductive semiconductor layer 132 and a second carrier injected through the second conductive semiconductor layer 136, Light having a wavelength corresponding to an energy band gap according to the material of the active layer 134 may be generated.

The active layer 134 may include any one of a multiple quantum well structure (MQW), a quantum dot structure, and a quantum wire structure.

The active layer 134 may be repeatedly formed in the period of the well layer and the barrier layer. For example, the active layer 134 may be formed of a period of InGaN / GaN, a period of InGaN / AlGaN, a period of InGaN / InGaN, or the like. The energy band gap of the barrier layer may be greater than the energy band gap of the well layer.

The second conductive semiconductor layer 136 may be, for example, a p-type semiconductor layer including a p-type dopant. The second conductive semiconductor layer 136 may be a semiconductor material having a composition formula of In x Al y Ga 1 -x- y N (0? X? 1, 0? Y? 1, 0? X + For example, at least one selected from the group consisting of InAlGaN, GaN, AlGaN, InGaN, AlN, InN and AlInN and may be doped with a p-type dopant such as Mg, Zn, Ca, Sr and Ba.

As shown in FIG. 3, a first bonding layer 140a may be formed on the light emitting structure 130. FIG.

Although not shown, at least one or more of a transparent conductive layer, a reflective layer, and a current blocking layer may be formed before the first bonding layer 140a is formed, but the present invention is not limited thereto.

The transparent conductive layer and the reflective layer may be used as an electrode, but the present invention is not limited thereto.

The transparent conductive layer may form an ohmic contact with the light emitting structure 130, but the present invention is not limited thereto. The transparent conductive layer may be formed of, for example, a transparent oxide, but is not limited thereto. The transparent conductive layer may include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), and indium zinc tin oxide (IZTO), but the present invention is not limited thereto.

The reflective layer may reflect light of the light emitting structure 130, but the present invention is not limited thereto. The reflective layer may be formed of a reflective metallic material, but is not limited thereto. The reflective layer may include one or more of Al, Ag, and Au, but is not limited thereto.

The current blocking layer can prevent the current from being concentrated, but the present invention is not limited thereto. The current blocking layer may be an insulating layer, but the present invention is not limited thereto. The current blocking layer may be, for example, SiO 2 or SiN x , but is not limited thereto.

The current blocking layer may be formed of a material having a relatively lower electrical conductivity than the transparent conductive layer or the reflective layer, but the present invention is not limited thereto.

The first bonding layer 140a can be more easily adhered to another layer, for example, a second bonding layer described later.

The first bonding layer 140a may include at least one of Ni, Au and Sn, but the present invention is not limited thereto.

As shown in FIG. 4, a carrier substrate 210 may be prepared, and a second bonding layer 140b may be formed on the carrier substrate 210.

The carrier substrate 210 may employ a substrate having a thermal expansion coefficient that is less than or equal to the thermal expansion coefficient of the growth substrate.

The carrier substrate 210 may be formed of the same material as the growth substrate 110, but the present invention is not limited thereto.

The carrier substrate 210 may be formed of at least one selected from the group consisting of SiC, Si, GaAs, GaN, ZnO, GaP and InP.

Although not shown, a conductive supporting member may be used instead of the carrier substrate 210. [ The conductive support member may be formed of a metal material having excellent electrical conductivity, thermal conductivity, and strength, but the present invention is not limited thereto. The conductive base member may be made of, for example, Ti, Cr, Ni, Al, Pt, Au, W, But is not limited to, at least one selected from the group consisting of alloys (Cu Alloy), molybdenum (Mo), and copper-tungsten (Cu-W).

The second bonding layer 140b may be formed of the same material as the first bonding layer 140a, but the present invention is not limited thereto. The first bonding layer 140a may include at least one of Ni, Au and Sn, but the present invention is not limited thereto.

5, the first bonding layer 140a of the growth substrate 110 and the second bonding layer 140b of the carrier substrate 210 are arranged to face each other, and then heat and pressure are applied.

Accordingly, as shown in FIG. 6, the first and second bonding layers 140a and 140b may be bonded to each other to form a third bonding layer 140c.

For example, the bonding metal may be melted by increasing the temperature of the first bonding layer 140a and the second bonding layer 140B to about 300 deg. C, which is an eutectic temperature of the second bonding layer 140B, The carrier substrate 210 may be bonded to the growth substrate 110. Then, after cooling to a predetermined temperature, for example, about 250 ° C, the pressure applied may be removed to cool to room temperature.

As shown in FIG. 7, a protective film may be attached to the periphery of the carrier substrate 210. The protective film 150 may prevent the carrier substrate 210 from being etched by an etchant during a subsequent CLO process.

The protective film 150 may be formed of a material resistant to acid resistance and heat resistance. The protective film 150 may be an adhesive tape including an adhesive material on the inner surface, but the protective film 150 is not limited thereto.

The protective film 150 completely covers the carrier substrate 210 to prevent the carrier substrate 210 from being exposed to the outside.

The protective film 150 may be adhered not only to the carrier substrate 210 but also to a part of the side surface of the third bonding layer 140c.

As shown in FIG. 8, after the growth substrate 110 is oriented upward, the growth substrate 110 may be removed using a CLO (chemical lift off) process.

In the CLO process, a bath filled with an etchant is provided. When the growth substrate 110 is immersed in the container, the growth substrate 110 may be etched and eventually removed by an etchant.

In order to efficiently remove the growth substrate 110, appropriate process conditions may be required. Etching temperature, etchant flow, heater temperature, thickness of growth substrate 110, and etch rate can be used as process conditions.

1st Example

In the first embodiment, as shown in FIG. 11, the first and second CLO sections may be divided into the first and second CLO sections, and the first and second CLO sections may have different etching temperatures.

For example, the second etch temperature in the second CLO section may be at least 20 ° C greater than the first etch temperature in the first CLO section, and the maximum etch temperature may be 60 ° C in the second CLO section, It is not limited thereto.

In other words, the value between the second etching temperature and the first etching temperature may be at least 20 캜 and the second etching temperature may be at most 60 캜.

P1 is the start point of the first CLO process, and P3 is the end point of the second CLO process.

P2 may be a time point between the first and second CLO sections and may be a time point when the front surface of the buffer layer 120 under the growth substrate 110 is exposed.

If the growth substrate 110 is not completely removed even if the growth substrate 110 is removed at P3 and the entire surface of the buffer layer 120 is exposed, Residual spots may remain (Fig. 12A).

In the first embodiment, the first CLO process is performed at the first etching temperature for the first CLO period to remove the growth substrate 110. At this time, since the remaining spots remain as shown in FIG. 12A, The second CLO process may be performed at the second etch temperature to remove the residual spot (FIG. 12D).

Process conditions (first etching temperature / second etching temperature) P2 10 minutes after P2 20 minutes after P2 25 minutes after P2 Remarks Sample 1 40/60 Abundant presence decrease decrease Almost none 10 L (1 ea) Sample 2 43/60 Abundant presence decrease decrease Almost none 13L (2ea) Sample 3 50/65 Abundant presence Small amount reduction No change No change 13L (2ea) Sample 4 40/60 Abundant presence decrease decrease Almost none 18L (increase in volume) Sample 5 43/65 Abundant presence Small amount reduction No change No change 14L Sample 6 35/60 Abundant presence decrease decrease Almost none 13L, increase etching time Sample 7 40/55 Abundant presence decrease decrease Almost none 12L

Samples 1 and 2 have the same process conditions, but the etchant in the bath is 13 L for sample 2 and 10 L for sample 1, with more etchant for sample 2.

As in Sample 3 and Sample 5, when the second etching temperature is 65 degrees, the residual spot is slightly reduced until after 10 minutes from P2, but there is no change thereafter. That is, even if additional etching is performed by the second CLO section, the residual spot is not removed.

Accordingly, when the second etching temperature is 60 degrees or less and the difference between the second etching temperature and the first etching temperature is 20 degrees or more and the second etching period is 20 minutes or more, But the residual spot is almost removed.

Figure 12a shows the residual spots at P2, Figure 12b shows the residual spots after 10 minutes from P2, Figure 12c shows the remaining spots after 17 minutes from P2, Figure 12d shows the residual spots after 25 minutes from P2, Lt; / RTI >

12A, 12B and 12C, the residual spot is present, but the residual spot is not seen in FIG. 12D.

Thus, the second CLO section may be set to 20 minutes or more, but this is not limiting. This may mean that the second CLO process is performed for 20 minutes or more from the boundary point of the first and second CLO sections.

Preferably, the second CLO interval may be set to 25 minutes or more.

Second Example

As a second embodiment, it is possible to combine the etching etch materials contained in the etchant without removing the additional CLO process as in the first embodiment, and to remove the residual spots using the optimum etch rate.

The etching solution in the second embodiment may include at least one of sulfuric acid (H 2 SO 4 ), hydrofluoric acid (HF), nitric acid (HNO 3 ) and ammonium fluoride (NH 4 HF 2 ) .

It is possible to obtain an optimum etching rate capable of removing not only the growth substrate 110 but also the remaining spots by controlling the type of the etching material contained in the etching solution and the composition ratio of the etching material.

13A to 13C are diagrams showing a residual spot according to an etching rate in a 2-inch growth substrate.

13A shows an etching rate of 18 to 20 μm / min, FIG. 13B shows an etching rate of 12 to 17 μm / min, and FIG. 13C shows an etching rate of 25 to 29 μm / min.

As shown in FIG. 13B, when the growth substrate 110 is removed at an etching rate of 12 to 17 μm / min, the residual spot still remains.

However, it can be seen that when the growth substrate 110 is removed with an etching rate of 18 to 20 μm / min or an etching rate of 25 to 29 μm / min as shown in FIG. 13C, the residual spots are almost completely removed as shown in FIG. 13A .

Therefore, in removing the 2-inch growth substrate 110, the optimum etching rate may be 18 to 20 占 퐉 / min or 25 to 29 占 퐉 / min, but this is not limited thereto.

FIGS. 14A and 14B are diagrams showing a residual spot according to the etch rate in the growth substrate of 6 or more. FIG.

14A shows an etching rate of 12 to 17 μm / min, and FIG. 14B shows an etching rate of 25 to 29 μm / min.

As shown in FIG. 14A, when the growth substrate 110 is removed at an etching rate of 12 to 17 μm / min, the residual spot still remains.

However, as shown in FIG. 14B, when the growth substrate 110 is removed with an etching rate of 25 to 29 μm / min, the residual spots are almost completely removed.

Therefore, in removing the growth substrate 110 of 6 inches, the optimum etching rate may be 25 to 29 占 퐉 / min, but the present invention is not limited thereto.

As shown in FIG. 9, after the growth substrate 110 is removed, the protective film 150 may be removed. Foreign matter due to the adhesive material of the protective film 150 may remain on the carrier substrate 210, so that the adhesive material can be removed by performing a cleaning process.

The first electrode 160 may be formed on the buffer layer 120 and the second electrode layer 170 may be formed on the carrier substrate 210 as shown in FIG.

When the carrier substrate 210 is replaced with a conductive supporting substrate, the second electrode layer 170 may not be formed.

The first electrode 160 and the second electrode may be formed of a plurality of layers including different materials, but the present invention is not limited thereto.

The first electrode 160 and the second electrode layer 170 may be formed of the same material, but the present invention is not limited thereto.

The first electrode 160 and the second electrode layer 170 may be formed of a metal material having an excellent electrical conductivity, an excellent bonding property, or an excellent thermal conductivity. However, the present invention is not limited thereto.

The first electrode 160 may be formed of a metal material forming an ohmic contact with the buffer layer 120, but the present invention is not limited thereto.

The first electrode 160 and the second electrode layer 170 may be formed of a metal such as aluminum (Al), titanium (Ti), chromium (Cr), nickel (Ni), platinum (Pt), gold (Au), tungsten W), copper (Cu), and molybdenum (Mo). However, the present invention is not limited thereto.

If the first conductive semiconductor layer 132 is thick, the buffer layer 120 may be removed, but the present invention is not limited thereto.

The light extraction structure 180 may be formed on the buffer layer 120 by performing an etching process using the first electrode 160 as a mask. When the buffer layer 120 is removed, the light extracting structure 180 may be formed on the light emitting structure 130, that is, the second conductivity type semiconductor layer 136.

The light extracting structure 180 may include a plurality of protrusions.

The light extracting structure 180 may include a plurality of bars formed in a long direction in one direction or a plurality of dots spaced apart from each other.

The light extracting structure 180 may extract light generated in the light emitting structure 130 to improve light efficiency.

110: growth substrate
120: buffer layer
130: Light emitting structure
132: first conductivity type semiconductor layer
134: active layer
136: second conductive type semiconductor layer
140a, 140b, 140c: bonding layer
150: Protective film
160: first electrode
170: second electrode layer
180: Light extraction structure
210: carrier substrate

Claims (12)

Providing a growth substrate;
Growing a light emitting structure on the growth substrate;
Bonding a carrier substrate to the growth substrate; And
And removing the growth substrate from the light emitting structure,
Wherein the removing the growth substrate comprises:
Performing a first CLO process at a first etch temperature during a first interval to remove the growth substrate; And
Performing a second CLO process at a second etch temperature for a second time period to remove the remaining spot,
Wherein the second etching temperature is at least 20 DEG C higher than the first etching temperature. The method according to claim 1,
And the second etching temperature is 60 占 폚 or less. The method according to claim 1,
And a boundary point between the first and second sections is a time point when a front surface of the light emitting structure is exposed. The method of claim 3,
Wherein the second CLO process is performed at a time of 20 minutes or more from the boundary point
remind The method according to claim 1,
And the second section is 20 minutes or longer. Providing a growth substrate;
Growing a light emitting structure on the growth substrate;
Bonding a carrier substrate to the growth substrate; And
And removing the growth substrate from the light emitting structure,
Wherein the growth substrate is removed by an etchant containing at least one of sulfuric acid (H 2 SO 4 ), hydrofluoric acid (HF), nitric acid (HNO 3 ), and ammonium fluoride (NH 4 HF 2 ). The method according to claim 6,
Wherein the growth substrate has an etching rate of 18 to 20 占 퐉 / min. The method according to claim 6,
And the etching rate of the growth substrate is 25 to 29 占 퐉 / min. 7. The method according to claim 1 or 6,
Before growing the light emitting structure,
And growing a buffer layer on the growth substrate. 10. The method of claim 9,
Forming a first electrode on the buffer layer; And
And forming a second electrode layer below the carrier substrate. 7. The method according to claim 1 or 6,
Before removing the growth substrate,
Further comprising attaching a protective film around the carrier substrate,
Wherein the protective film is removed after the growth substrate is removed. 7. The method according to claim 1 or 6,
Wherein the growth substrate is formed of at least one selected from the group consisting of sapphire (Al 2 O 3), SiC, Si, GaAs, GaN, ZnO, GaP, InP and Ge.
KR1020120154545A 2012-12-27 2012-12-27 Method of manufacturing a semiconductor device KR20140085708A (en)

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