KR20140085222A - Fuse circuit and repair fuse circuit - Google Patents

Fuse circuit and repair fuse circuit Download PDF

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Publication number
KR20140085222A
KR20140085222A KR1020120155556A KR20120155556A KR20140085222A KR 20140085222 A KR20140085222 A KR 20140085222A KR 1020120155556 A KR1020120155556 A KR 1020120155556A KR 20120155556 A KR20120155556 A KR 20120155556A KR 20140085222 A KR20140085222 A KR 20140085222A
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KR
South Korea
Prior art keywords
fuse
latching
unit
activation
common
Prior art date
Application number
KR1020120155556A
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Korean (ko)
Inventor
이동근
Original Assignee
에스케이하이닉스 주식회사
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Priority to KR1020120155556A priority Critical patent/KR20140085222A/en
Publication of KR20140085222A publication Critical patent/KR20140085222A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G11C29/787—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using a fuse hierarchy
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/808—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme

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  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

A fuse circuit for storing various data, comprising: a fuse array having a plurality of fuses; a plurality of fuse information latching units for latching cutting information of the plurality of fuses output from the fuse array; And a common driver for performing a common operation of the fuse information latching unit.

Description

FUSE CIRCUIT AND REPAIR FUSE CIRCUIT BACKGROUND OF THE INVENTION 1. Field of the Invention [0001]

The present invention relates to semiconductor design techniques, and more particularly to a fuse circuit for storing various data and a repair fuse circuit for storing a repair target address.

Generally, semiconductor memory devices including DDR SDRAM (Double Data Rate Synchronous DRAM) have numerous memory cells. As the process technology is developed, the degree of integration increases and the number of memory cells is increasing. If any one of these memory cells is defective, the semiconductor memory device having the defective memory cell can not perform a desired operation and must be discarded. However, as the process technology of the semiconductor memory device is developed these days, only a small amount of defects occur in a small amount of memory cells. In order to dispose of the entire semiconductor memory device as a defective product due to a small amount of defects, It is very inefficient when viewed. Therefore, in order to compensate for this, the semiconductor memory device further includes a redundant memory cell in addition to a normal memory cell.

The redundancy memory cell is a circuit provided for the purpose of repairing a memory cell (hereinafter, referred to as " repair target memory cell ") in which a failure occurs in a normal memory cell. More specifically, for example, when a memory cell to be repaired is accessed during a read and a write operation, the normal memory cell is accessed internally instead of the memory cell to be repaired. At this time, the accessed memory cell is a redundancy memory cell. Therefore, when the address corresponding to the memory cell to be repaired is inputted, the semiconductor memory device performs an operation (hereinafter referred to as a repair operation) for accessing the redundancy memory cell other than the memory cell to be repaired (hereinafter referred to as a repair operation) The semiconductor memory device is guaranteed to operate normally.

On the other hand, the semiconductor memory device requires a circuit configuration other than the redundancy memory cell to perform the repair operation, and one of them is a repair fuse circuit. The repair fuse circuit is constituted by a plurality of fuses for storing an address corresponding to a memory cell to be repaired (hereinafter referred to as a "repair target address"), and a repair target address is programmed in a plurality of fuses. A semiconductor memory device performs a repair operation on a defective memory cell using a repair target address programmed into a plurality of fuses.

Here, programming means a series of operations for storing the scheduled data in the fuse. Typical programming methods are laser cutting and electric cutting. The laser cutting method is a method of blowing a blown fuse according to data to be stored by using a laser beam. In the electric cutting method, an overcurrent is applied to a fuse according to data to be stored, and the device is blown by melting. For reference, the laser cutting method has an advantage that it can be performed in a simpler manner than the electric cutting method, but it has a disadvantage that it must be performed in a wafer state before the semiconductor memory device is manufactured as a package.

Meanwhile, the semiconductor device includes a fuse circuit for various purposes in addition to a repair fuse circuit. The fuse circuit includes a tuning fuse circuit used for tuning a voltage in a constant voltage generation circuit sensitive to environment, , A test fuse circuit used for testing, and a control fuse circuit for controlling various mode selections.

1 is a circuit diagram for explaining a general fuse circuit.

Referring to FIG. 1, the fuse circuit includes a fuse driving unit 110 and a latching unit 120.

The fuse driving unit 110 includes a fuse F and outputs whether the fuse F is cut or not in response to a reset signal RST. The latching unit 120 latches the output signal of the fuse driving unit 110 and outputs the latched signal.

Hereinafter, a simple circuit operation of the fuse circuit will be described.

First, the reset signal RST is a signal that transitions from logic 'high' to logic 'low'. Therefore, in the period in which the reset signal RST is logic 'high', the NMOS transistor of the fuse driving unit 110 is turned on to pre-charge the output terminal of the fuse driving unit 110 to the ground power source voltage VSS, The PMOS transistor of the fuse driving unit 110 is turned on to output a signal corresponding to whether or not the fuse F is cut to the output terminal of the fuse driving unit 110 in a period in which the reset signal RST is logic low. More specifically, if the fuse F is cut in the period in which the reset signal RST is logic 'low', the output terminal of the fuse driving unit 110 maintains the ground power supply voltage VSS in the precharged state If the fuse F is not cut, the output terminal of the fuse driving unit 110 is driven to the supply voltage VDD. Accordingly, when the fuse F is cut, the latching unit 120 latches a logic 'low' corresponding to the ground power supply voltage VSS in a precharged state and outputs a logic 'high' that inverts the logic 'low'. If the fuse F is not cut, the latching unit 120 latches a logic high corresponding to the supply voltage VSS and outputs a logic low that inverts the logic high.

On the other hand, as mentioned above, as the process technology of the semiconductor memory device develops, the size of the circuit becomes smaller and smaller. However, although the fuse circuit occupies a relatively large area as compared with other circuits, there is a limit in reducing the size of the fuse circuit due to the physical characteristics of the circuit. Therefore, an improvement measure for reducing the size of the fuse circuit is required.

And to provide a fuse circuit capable of minimizing the area of a circuit for processing fuse information.

A fuse circuit according to an embodiment of the present invention includes: a fuse array having a plurality of fuses; A plurality of fuse information latching units for latching cutting information of the plurality of fuses output from the fuse array; And a common driver for performing a common operation of the plurality of fuse information latching units.

Preferably, the common driver includes a precharging unit for performing a precharging operation of the plurality of fuse information latching units.

A repair fuse circuit according to another embodiment of the present invention includes: a fuse array for storing a repair target address; An address latching unit including a plurality of latching units, for latching the repair target address to the plurality of latching units; And a common activation unit for commonly controlling an activation operation period of the plurality of latching units.

Preferably, a plurality of redundancy address latching sections each having the address latching section and the common activating section as one unit circuit are provided.

The fuse circuit according to the embodiment of the present invention can minimize the area of the circuit for processing the fuse information.

The area of the circuit for processing the fuse information can be minimized and the size of the chip using the fuse information can be minimized.

1 is a circuit diagram for explaining a general fuse circuit.
2 is a block diagram illustrating a fuse circuit according to an embodiment of the present invention.
3 is a circuit diagram for explaining a plurality of fuse information latching units 220 of FIG.
FIG. 4 is a circuit diagram for explaining a connection relationship between the common precharging unit 240 of FIG. 2 and a plurality of fuse information latching units 220.
5 is a block diagram illustrating a repair fuse circuit according to an embodiment of the present invention.
6 is a circuit diagram for explaining a plurality of redundancy address latching units 520 of FIG.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. .

2 is a block diagram illustrating a fuse circuit according to an embodiment of the present invention.

Referring to FIG. 2, the fuse circuit includes a fuse array 210, a plurality of fuse information latching units 220, an activation control unit 230, and a common precharging unit 240.

The fuse array 210 has a plurality of fuses and outputs a plurality of fuse information INF_FS <1: n>, where n is a natural number, whether or not a plurality of fuses are cut. Each of the plurality of fuse information latching units 220 latches each of a plurality of fuse information INF_FS <1: n> in response to each of a plurality of enable signals EN <1: n>. The activation control unit 230 generates a plurality of enable signals EN <1: n> for controlling activation of the plurality of fuse information latching units 220. The common precharging unit 240 is disposed in correspondence with the plurality of fuse information latching units 220 and performs a precharging operation of the plurality of fuse information latching units 220.

The fuse circuit according to the embodiment of the present invention includes one common precharging unit 240 corresponding to a plurality of fuse information latching units 220.

3 is a circuit diagram for explaining a plurality of fuse information latching units 220 of FIG. For convenience of explanation, one fuse information latching unit of the plurality of fuse information latching units 220 is shown as a representative and a common precharging unit 240 is additionally shown.

3 illustrates a first PMOS transistor PM1, first and second NMOS transistors NM1 and NM2 and a latching unit 221. The first PMOS transistor PM1 includes a common precharging unit 240 And the remaining first and second NMOS transistors NM1 and NM2 and the latching unit 221 are included in the fuse information latching unit.

Hereinafter, a simple circuit operation of the fuse circuit will be described.

First, the reset signal RST is a signal which transits from a logic low to a logic high. The first PMOS transistor PM1 is turned on and the supply voltage VDD stage which is the precharging voltage stage is connected to the input terminal ND of the latching unit 221 and the input terminal ND of the latching unit 221. [ . That is, the input terminal ND of the latching unit 221 is precharged to the supply voltage VDD. The first PMOS transistor PM1 is turned off and the supply voltage VDD and the input terminal ND of the latching unit 221 are connected to each other during a period in which the reset signal RST is at logic ' It breaks.

Next, when the enable signal EN becomes logic 'high', the second NMOS transistor NM2 is turned on. When the fuse information INF_FS is inputted, the first NMOS transistor NM1 is turned on according to the fuse information INF_FS. Is turned on or turned off. Then, the latching unit 221 latches a value corresponding to the turn-on or turn-off of the first NMOS transistor NM1. That is, when the fuse information INF_FS is logic 'low', the first NMOS transistor NM1 is turned off, and the latching unit 221 sets the logic 'high' corresponding to the supply power supply voltage VDD in the precharged state to And outputs a logic 'low' which is inverted. When the fuse information INF_FS is logic high, the first NMOS transistor NM1 is turned on and the latching unit 221 latches the logic low corresponding to the ground power supply voltage VSS, And outputs a logic high.

FIG. 4 is a circuit diagram for explaining a connection relationship between the common precharging unit 240 of FIG. 2 and a plurality of fuse information latching units 220.

4, the common precharging unit 240 includes a first PMOS transistor PM1 corresponding to a plurality of fuse information latching units 220 receiving a plurality of fuse information INF_FS <1: n> Respectively.

Accordingly, in the fuse circuit according to the embodiment of the present invention, a plurality of fuse information latching units 220 receives a plurality of fuse information INF_FS <1: n> corresponding to whether or not the fuse is cut, And it is possible that a plurality of fuse information latching units 220 commonly use the first PMOS transistor PM1 to minimize the area of the fuse circuit.

5 is a block diagram illustrating a repair fuse circuit according to an embodiment of the present invention.

Referring to FIG. 5, the repair fuse circuit includes a fuse array 510, a plurality of redundancy address latching units 520, and an activation control unit 530.

The fuse array 510 has a plurality of fuses and outputs a repair target address (INF_FS_ADD <1:13>) corresponding to whether the plurality of fuses are cut or not. For convenience of description, the repair target address (INF_FS_ADD <1:13>) is made up of 13 bits as an example.

The redundancy address latching unit 520 is for latching the repair target address INF_FS_ADD <1:13> in response to a plurality of enable signals EN <1: n>, and includes an address latching unit 521, And a common activation unit 522.

Here, the address latching unit 521 has thirteen latching units (not shown, see FIG. 6) for latching the repair target address INF_FS_ADD <1:13>, respectively. The common activation unit 522 is for controlling the activation operation period of the 13 latching units in common, and has one common activation unit 522 corresponding to 13 latching units.

Finally, the activation control unit 530 generates a plurality of enable signals EN <1: n> for controlling the activation operation of the common activation unit 522. Here, n is a natural number, and the plurality of redundancy address latching units 520 include n redundancy address latching units.

The repair fuse circuit according to the embodiment of the present invention includes one common activation unit 522 corresponding to a plurality of latching units for storing the repair target address INF_FS_ADD <1:13>.

6 is a circuit diagram for explaining a plurality of redundancy address latching units 520 of FIG. For convenience of explanation, one redundancy address latching unit of the plurality of redundancy address latching units 520 will be described as a representative.

Referring to FIG. 6, the redundancy address latching section includes an address latching section 521 and a common activation section 522.

The address latching unit 521 includes first to thirteenth address latching units 610, 620, ..., and 630 and first to thirteenth address latching units 610, 620, ..., and 630 (INF_FS_ADD < 1:13 >) are received and latched. The common activation unit 522 is responsive to the first enable signal EN <1> of the plurality of enable signals EN <1: n> output from the activation control unit 530 1 to thirteenth address latching units 610, 620, ..., 630.

The repair fuse circuit according to the embodiment of the present invention can receive the repair target address INF_FS_ADD <1:13>, latch it, and output it. It is possible to minimize the area of the repair fuse circuit by using the first to thirteenth address latching portions 610, 620, ..., and 630 in common with the second NMOS transistor NM2.

Hereinafter, a first address latching unit 610 among the first to thirteenth address latching units 610, 620, ..., and 630 will be described as a representative for convenience of explanation.

The first address latching unit 610 includes a first PMOS transistor PM1 receiving a reset signal RST, a first NMOS transistor NM1 receiving a first repair target address INF_FS_ADD <1> (611). The common activation unit 522 includes a second NMOS transistor NM2 receiving the first enable signal EN <1>.

The configuration of the first PMOS transistor PM1, the first and second NMOS transistors NM1 and NM2 and the latching unit 611 is different from that of the circuit configuration of FIG. 3 in that a repair target Receiving the address INF_FS_ADD is different, and the circuit operation is similar to each other. That is, the first address latching unit 610 activates in response to the first enable signal EN <1> after the reset operation and latches the input first repair target address INF_FS_ADD <1>.

Each of the first to thirteenth address latching units 610, 620, ..., 630 performs the above operation. That is, the first to thirteenth address latching units 610, 620, ..., 630 are activated in response to the first enable signal EN < 1 >, and the first to thirteenth repair target addresses INF_FS_ADD <1:13>).

Referring again to FIG. 5, each of the redundancy address latching units 520 has a configuration as shown in FIG. 6, and in response to a plurality of enable signals EN <1: n> output from the activation control unit 530 The activation interval is controlled.

Each of the redundancy address latching units 520 includes an address latching unit 521 and a common activation unit 522. Particularly, the common activation unit 522 includes an address latching unit 521, Only one of them is disposed in common to correspond to a plurality of latching units provided in the latching unit 521. [

The fuse circuit and the repair fuse circuit according to the above-described embodiments of the present invention can constitute a common circuit portion as one common circuit, so that the area of the circuit can be minimized.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention.

In addition, the logic gates and transistors exemplified in the above-described embodiments must be implemented in different positions and types according to the polarity of input signals.

210: Fuse array
220: a plurality of fuse information latching units
230:
240: Common precharging unit

Claims (10)

A fuse array having a plurality of fuses;
A plurality of fuse information latching units for latching cutting information of the plurality of fuses output from the fuse array; And
A common driver for performing a common operation of the plurality of fuse information latching units,
And a fuse circuit.
The method according to claim 1,
Wherein the common driver includes a precharging unit for performing a precharging operation of the plurality of fuse information latching units.
The method according to claim 1,
Wherein the common driver includes a switch for connecting each of the plurality of fuse information latching units and the precharge voltage stage during a precharging operation, the switch being disposed between each of the plurality of fuse information latching units and the precharge voltage stage, Fuse circuit.
The method according to claim 1,
And an activation control unit for controlling activation of the plurality of fuse information latching units.
5. The method of claim 4,
Wherein each of the plurality of fuse information latching units latches each of the cutting information in a corresponding fuse information latching unit in response to an output signal of the activation control unit.
A fuse array for storing a repair target address;
An address latching unit including a plurality of latching units, for latching the repair target address to the plurality of latching units; And
A common activation unit for commonly controlling the activation operation periods of the plurality of latching units;
And the repair fuse circuit.
The method according to claim 6,
And a redundancy address latching section that uses the address latching section and the common activation section as one unit circuit.
8. The method of claim 7,
And an activation control section for controlling activation of the common activation section.
9. The method of claim 8,
Wherein the plurality of latching units latch the repair target address in accordance with an activation operation of the common activation unit.
The method according to claim 6,
Wherein the plurality of latching units have a number corresponding to the repair target address.
KR1020120155556A 2012-12-27 2012-12-27 Fuse circuit and repair fuse circuit KR20140085222A (en)

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KR1020120155556A KR20140085222A (en) 2012-12-27 2012-12-27 Fuse circuit and repair fuse circuit

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9281082B1 (en) 2014-12-19 2016-03-08 SK Hynix Inc. Semiconductor memory device including redundancy circuit and fuse circuit
US9401219B2 (en) 2014-10-24 2016-07-26 SK Hynix Inc. Electronic fuse semiconductor device for selecting failed redundancy word lines
CN106158048A (en) * 2014-12-05 2016-11-23 爱思开海力士有限公司 Restoration information stores circuit and includes its semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9401219B2 (en) 2014-10-24 2016-07-26 SK Hynix Inc. Electronic fuse semiconductor device for selecting failed redundancy word lines
TWI638362B (en) * 2014-10-24 2018-10-11 愛思開海力士有限公司 Semiconductor devices
CN106158048A (en) * 2014-12-05 2016-11-23 爱思开海力士有限公司 Restoration information stores circuit and includes its semiconductor device
US9281082B1 (en) 2014-12-19 2016-03-08 SK Hynix Inc. Semiconductor memory device including redundancy circuit and fuse circuit

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