KR20130059180A

KR20130059180A - Fuse circuit and operating method thereof

Info

Publication number: KR20130059180A
Application number: KR1020110125360A
Authority: KR
Inventors: 김경태; 이한규
Original assignee: 에스케이하이닉스 주식회사
Priority date: 2011-11-28
Filing date: 2011-11-28
Publication date: 2013-06-05

Abstract

A fuse circuit for programming desired data, the fuse driving unit for driving an output node according to data programmed into a fuse in response to a fuse reset signal, and one end of the fuse in response to the programmed data. A voltage driver for driving with a driving force, an information latching unit having a driving force greater than the predetermined driving force, the latching the received data and outputting the programmed data as fuse information, and the program data in response to a control signal. A fuse circuit having an information transfer unit for receiving an input from a driver and transferring the information to the information latching unit is provided.

Description

Fuse circuit and its operation method {FUSE CIRCUIT AND OPERATING METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design techniques, and more particularly to a fuse circuit that can be programmed and used for desired data.

In general, semiconductor memory devices including DDR Double Data Rate Synchronous DRAM (DDR SDRAM) are provided with a myriad of memory cells, and as the process technology develops, the density increases and the number thereof increases. If any one of these memory cells is defective, the semiconductor memory device having the defective memory cell can not perform a desired operation and must be discarded. However, as the process technology of the semiconductor memory device develops these days, a defect occurs only in a small amount of memory cells, and due to such a small amount of defects, the yield of the product is considered in order to dispose of the entire semiconductor memory device as a defective product. Very inefficient in view. Therefore, in order to compensate for this, a redundancy memory cell is additionally provided in the semiconductor memory device as well as a normal memory cell.

The redundancy memory cell is a circuit provided for the purpose of repairing a memory cell (hereinafter, referred to as " repair target memory cell ") in which a failure occurs in a normal memory cell. More specifically, for example, when a memory cell to be repaired is accessed during a read and a write operation, the normal memory cell is accessed internally instead of the memory cell to be repaired. At this time, the accessed memory cell is a redundancy memory cell. Therefore, when the address corresponding to the repair target memory cell is input, the semiconductor memory device performs an operation (hereinafter, referred to as a repair operation) to access a redundant memory cell instead of the repair target memory cell, and performs the repair operation. Through this, the semiconductor memory device is guaranteed to operate normally.

Meanwhile, the semiconductor memory device requires not only a redundant memory cell but also other circuit configurations in order to perform a repair operation, one of which is a repair fuse circuit. The repair fuse circuit stores an address corresponding to a repair target memory cell (hereinafter referred to as a repair target address), and a repair target address is programmed into each fuse provided in the repair fuse circuit. The semiconductor memory device performs a repair operation using the repair target address programmed as described above.

Here, programming means a series of operations for storing the scheduled data in the fuse. Typical programming methods include laser cutting and electric cutting. The laser cutting method is a method of blowing a blown fuse according to data to be stored by using a laser beam. In the electric cutting method, an overcurrent is applied to a fuse according to data to be stored, and the device is blown by melting. For reference, the laser cutting method has an advantage of being able to be performed in a simpler manner than the electric cutting method, but has a disadvantage that the semiconductor device must be performed in a wafer state before the semiconductor device is manufactured into a package.

On the other hand, the semiconductor memory device includes a fuse circuit for various purposes in addition to the repair fuse circuit, and such a fuse circuit is a tuning fuse circuit used to tune a voltage in a constant voltage generation circuit that operates sensitively according to an environment. Or a test fuse circuit used for testing, or a control fuse circuit for controlling various mode selections.

1 is a circuit diagram for explaining a general fuse circuit.

Referring to FIG. 1, a fuse circuit includes a fuse driver 110 and a fuse information output unit 120.

The fuse driver 110 drives the second node BB, which is an output node of the fuse driver 110, in response to data programmed into the fuse F in response to the fuse reset signal FSE. A first PMOS transistor P1 connected in series between the VDD terminal and the ground power supply voltage VSS terminal, a fuse F, and a first NMOS transistor N1 are provided.

The fuse information output unit 120 outputs the fuse information INF_FS according to the voltage level of the second node B. The fuse information output unit 120 outputs the signal received through the second node B as the fuse information INF_FS. The inverter IV1 includes a second NMOS transistor N2 for connecting the second node BB to the ground power supply voltage terminal VSS by receiving feedback from the fuse information INF_FS.

2 and 3 are timing diagrams for describing an operation of the fuse circuit of FIG. 1. For reference, the fuse reset signal FSE may be viewed as a signal activated in response to a power up signal (not shown) that is activated during a power up operation of the semiconductor memory device.

FIG. 2 is a circuit operation in which the fuse F of FIG. 1 is not cut.

First, the supply power supply voltage VDD is a power source applied from the outside of the semiconductor device and rises to a voltage level of a constant slope when the semiconductor device is initially driven. At this time, when the power supply voltage VDD rises above the predetermined voltage level, the power-up signal is activated, and the fuse reset signal FSE is activated in a pulse form in response to the power-up signal.

1 and 2, in a section in which the fuse reset signal FSE is logic 'low', the first PMOS transistor P1 is turned on and one side of the fuse F is turned on. The supply power supply voltage VDD is applied to the first node AA. At this time, the second node BB, which is the other end of the fuse F, also becomes a voltage level corresponding to the supply power supply voltage VDD. Subsequently, when the fuse reset signal FSE transitions from logic 'low' to logic 'high', the first PMOS transistor P1 is turned off and the first NMOS transistor N1 is turned on. Therefore, the second node BB is discharged to the ground power supply voltage VSS. At this time, the fuse information INF_FS becomes logic 'high', and the second NMOS transistor N2 fed back with the fuse information INF_FS latches the second node BB turned on and initialized to logic 'low'. . Next, when the fuse reset signal FSE transitions from logic 'high' to logic 'low', the first PMOS transistor P1 is turned on and the first NMOS transistor N1 is turned off. Here, since the fuse F is not cut, the second node BB rises to a voltage level corresponding to the supply power supply voltage VDD, and the fuse information INF_FS becomes logic 'low'.

3 is a circuit operation in a state in which the fuse F of FIG. 1 is cut.

1 and 3, in a period where the fuse reset signal FSE is logic 'high', the first PMOS transistor P1 is turned off and the first NMOS transistor N1 is turned on. Therefore, the second node BB is discharged to the ground power supply voltage VSS. At this time, the first node AA is in a floating state (wave pattern). Next, when the fuse reset signal FSE transitions from logic 'high' to logic 'low', the first PMOS transistor P1 is turned on and the first NMOS transistor N1 is turned off. Here, since the fuse F is in the cut state, the second node BB maintains a voltage level corresponding to the ground power supply voltage VSS, and the fuse information INF_FS becomes logic 'high'.

As shown in FIGS. 2 and 3, the fuse circuit has a logic level value of the fuse information INF_FS depending on a state programmed in the fuse F, that is, whether the fuse F is cut. In other words, when the fuse F is not cut, the fuse information INF_FS is logic 'low', and when the fuse F is cut, the fuse information INF_FS is logic 'high'.

On the other hand, as the process technology of the semiconductor device is developed, the size of the circuit provided in the semiconductor device is designed to be smaller and smaller, and so is the fuse circuit. The smaller size of the fuse circuit means that the cutting area of the fuse is also smaller, which means that even if the fuse is cut, there is a high possibility of changing to an uncut state, that is, a short state, for various reasons. The most representative cause of such a fuse failure is an electric field generated by the voltage difference across the fuse.

The occurrence of an electric field causing a fuse failure can be most correlated with the polarity of the voltage applied across the fuse. In general, the fuse is designed of copper (Cu), the ionization and reduction of the copper (Cu) constituting the fuse occurs according to the polarity of the voltage applied across the fuse. In other words, if the positive electrode (+) and the negative electrode (-) are applied to both ends of the cut fuse, the ionization phenomenon occurs at the positive electrode (+) of the fuse, and the reducing action occurs at the negative electrode (-). Therefore, copper ions move from the positive electrode (+) of the fuse to the negative electrode (-) of the fuse, and eventually, due to this chemical phenomenon, copper is adsorbed to the negative electrode (-) and the cut fuse is gradually cut into the uncut fuse. Is deformed.

Referring to FIG. 3 again, after the fuse information INF_FS is determined according to whether the fuse F is cut, different voltages are applied to the first node AA and the second node BB across the fuse F. Referring to FIG. . That is, the first node AA is applied with the supply power supply voltage VDD, and the second node BB is applied with the ground power supply voltage VSS. Therefore, there is a high possibility that a fuse failure phenomenon occurs in the fuse F.

Such a fuse failure phenomenon causes the data value to be changed to another data value even though the intended data value is programmed into the fuse, which causes a decrease in the performance and reliability of the circuit. In particular, when a defective fuse shape occurs in the repair fuse circuit, the semiconductor memory device may not secure an accurate repair operation, thereby causing a malfunction.

An embodiment of the present invention provides a fuse circuit that can prevent the fuse failure by controlling the voltage applied to the fuse.

A fuse circuit according to an embodiment of the present invention includes a fuse driver for driving an output node according to data programmed into a fuse in response to a fuse reset signal; A voltage driver for driving one end of the fuse with a predetermined driving force in response to the programmed data; An information latching unit having a driving force greater than the predetermined driving force, for receiving and latching the programmed data and outputting the same as fuse information; And an information transfer unit for receiving the programmed data from the fuse driver in response to a control signal and transferring the programmed data to the information latching unit.

Preferably, the information latching portion is configured with a MOS transistor having a predetermined loading, and the voltage driver is characterized in that the loading having a larger than the predetermined loading.

A fuse circuit according to another embodiment of the present invention includes a fuse having one end connected to a first power supply voltage; A first MOS transistor connecting between the other end of the fuse and an output node in response to a control signal; A second MOS transistor for initializing the output node to a second power supply voltage in response to a fuse reset signal; A third MOS transistor coupled to the first power supply voltage and configured to drive the other end of the fuse with a predetermined driving force in response to a voltage level of the output node; And a plurality of MOS transistors having a driving force greater than the predetermined driving force, for receiving and latching data programmed into the fuse and outputting the data as fuse information.

Preferably, a fourth MOS transistor is further connected between the first power supply voltage and one end of the fuse, and applies a same voltage corresponding to the first power supply voltage to both ends of the fuse.

According to still another aspect of the present invention, there is provided a method of operating a fuse circuit, the method comprising: generating fuse information by driving an output node with a driving force in which one of first and second loadings is reflected according to programmed data of a fuse; And after generating the fuse information, separating the fuse and the output node, and driving one end of the fuse with a driving force reflecting the second loading.

Preferably, the generating of the fuse information further includes driving the output node with a third driving force that is greater than the driving force in which the second loading is reflected and is less than or equal to the driving force in which the first loading is reflected.

In the fuse circuit according to the exemplary embodiment of the present invention, the voltage at both ends of the fuse is controlled to be the same voltage, thereby preventing a defect phenomenon occurring in the fuse circuit.

By preventing the defective phenomenon which arises in a fuse, the effect which can raise the reliability of the semiconductor device provided with this fuse circuit can be acquired.

1 is a circuit diagram for explaining a general fuse circuit.
2 is a circuit diagram illustrating a fuse circuit according to an exemplary embodiment of the present invention.
FIG. 3 is a timing diagram for describing an operation of the fuse circuit of FIG. 2.
4 is a circuit diagram illustrating a fuse circuit according to an exemplary embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. .

4 is a circuit diagram illustrating a fuse circuit according to an exemplary embodiment of the present invention.

Referring to FIG. 4, the fuse circuit includes a fuse driver 410, an information transfer unit 420, an information latching unit 430, and a voltage driver 440.

The fuse driver 410 drives the third node CC, which is an output node, in response to the data programmed into the fuse F in response to the fuse reset signal FSE. The fuse driver 410 supplies the supply power voltage VDD and the first node. A first PMOS transistor P1 connected between the first and second nodes AA, a fuse F connected between the first node AA, and the second node BB; A first NMOS transistor N1 is connected between the three node CC and the ground power supply voltage VSS, and receives the fuse reset signal FSE as a gate. Here, the first NMOS transistor N1 performs an operation of initializing the third node CC during an initial operation of the fuse circuit.

The information transmitter 420 transmits the programmed data transmitted through the second node BB to the degree latching unit 430 through the third node CC in response to the control signal FSEBP. A second PMOS transistor P2 is connected between the second node BB and the third node CC and receives a control signal FSEBP as a gate.

The information latching unit 430 receives and latches data programmed in the fuse F through the third node CC and outputs the data to the fuse information INF_FS. It is connected between the first inverter IV1 outputting the information INF_FS, the input terminal of the first inverter IV1 and the ground power supply voltage VSS terminal, and the output signal INF_FS of the first inverter IV1 is gated. A third PMOS transistor connected between an input second NMOS transistor N2 and an input terminal of the first inverter IV1 and a supply power voltage VDD terminal and receiving an output signal INF_FS of the inverter IV1 as a gate; (P3) is provided. Here, the second NMOS transistor N2 has a loading smaller than that of the fourth PMOS transistor P4 which will be described later. Small loading means that the resistance value reflected in the current flowing through the transmission path is small, and inversely, the driving force is large. For example, the loading of the MOS transistor may be defined as the length of the MOS transistor or the width of the MOS transistor.

The voltage driver 440 is for driving the second node BB, which is one end of the fuse F, with a predetermined driving force in response to the programmed data transmitted through the third node CC, and supplies a supply power voltage VDD. And a fourth PMOS transistor P4 connected between the terminal and the second node BB and receiving the third node CC as a gate. Here, the loading of the fourth PMOS transistor P4 is larger than the loading of the second NMOS transistor N2. That is, the driving force of the fourth PMOS transistor P4 is smaller than the driving force of the second NMOS transistor N2.

FIG. 5 is a waveform diagram illustrating the fuse reset signal FSE and the control signal FSEBP of FIG. 4.

Referring to FIG. 5, the fuse reset signal FSE and the control signal FSEBP transition from logic 'low' to logic 'high' during the initial power-up operation, and the fuse reset signal FSE and the control signal FSEBP are The third node CC is initialized to the ground power supply voltage VSS in a period in which all are logic 'high'. Thereafter, when the fuse reset signal FSE is deactivated to logic 'low', the first NMOS transistor N1 is turned off, and when the control signal FSEBP is activated to logic 'low', data programmed in the fuse F is stored. The fuse information INF_FS is output through the second node BB and the third node CC. Subsequently, after the data programmed in the fuse F is transferred to the fuse information INF_FS, the control signal FSEBP transitions from logic 'low' to logic 'high' and is deactivated. The first node AA and the second node BB are supplied with a supply power supply voltage VDD. In other words, the fuse circuit according to the embodiment of the present invention can apply the same power supply voltage to both ends of the fuse F.

Hereinafter, the operation of the fuse circuit according to the embodiment of the present invention will be described with reference to FIGS. 4 and 5.

First, a case in which the fuse F is not cut will be described.

The third node CC is initialized to the ground power supply voltage VSS in the initialization operation period, that is, in the period in which the fuse reset signal FSE and the control signal FSEBP are both logic 'high'. Thereafter, when the fuse reset signal FSE becomes logic 'low' and the control signal FSEBP becomes logic 'low', the second node BB and the third node CC correspond to the supply power supply voltage VSS. To become 'high'. At this time, since the driving force of the second NMOS transistor N2 is less than or equal to the driving force of the first PMOS transistor P1, the second and third nodes BB and CC are driven by the supply power supply voltage VDD. Accordingly, the fuse information INF_FS becomes logic 'low', and the third PMOS transistor P3 operating in response to the fuse information INF_FS is turned on to latch the fuse information INF_FS of the logic 'low'. Thereafter, the control signal FSEBP transitions from logic 'low' to logic 'high' and is deactivated. The supply power voltage VDD is applied to the first node AA and the second node BB of the fuse F. do.

Next, a case in which the fuse F is cut will be described.

After the reset operation period, when the fuse reset signal FSE becomes logic 'low' and the control signal FSEBP becomes logic 'low', the fourth node is reset by the third node CC initialized to the ground power supply voltage VSS. The PMOS transistor P4 is turned on. Therefore, the second and third nodes BB and CC are driven by the driving force through the fourth PMOS transistor P4. At this time, since the driving force of the second NMOS transistor N2 is greater than that of the fourth PMOS transistor P4, the second and third nodes BB and CC are not the supply power voltage VDD but the ground power voltage VSS. Driven by). Accordingly, the fuse information INF_FS becomes logic 'high', and the second NMOS transistor N2 operating in response to the fuse information INF_FS is turned on to latch the fuse information INF_FS of the logic 'high'. Thereafter, when the control signal FSEBP transitions from logic 'low' to logic 'high', the first node AA of the fuse F is driven by the driving force through the first PMOS transistor P1 to supply the supply power voltage ( VDD is applied, and the second node BB is driven by the driving force through the fourth PMOS transistor P4 to apply the supply power supply voltage VDD. That is, a supply power supply voltage VDD is applied to the first node AA and the second node BB of the fuse F.

Here, the first PMOS transistor P1 is configured such that the same supply power supply voltage VDD can be applied to both ends of the fuse F. The first PMOS transistor P1 has the same configuration as the dummy transistor corresponding to the fourth PMOS transistor P4. That is, since the first node AA has a voltage level corresponding to the loading of the first PMOS transistor P1, and the second node BB has a voltage level corresponding to the loading of the fourth PMOS transistor P4. The first and second nodes AA and BB have the same voltage level.

As a result, in the fuse circuit according to the embodiment of the present invention, the driving force reflected by the third node CC is different according to the case where the fuse F is cut and the case where the fuse F is not cut. It is possible to output the fuse information (INF_FS) programmed in the fuse (F) by using. In addition, after generating the fuse information INF_FS, it is possible to remove the fuse F and apply the same voltage to both ends of the fuse F. FIG.

As described above, the fuse circuit according to the embodiment of the present invention can prevent the fuse failure by applying the same power supply voltage to both ends of the fuse.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention.

In addition, the logic gates and transistors exemplified in the above-described embodiments must be implemented in different positions and types according to the polarity of input signals.

410: fuse driving unit 420: information transmission unit
430: information latching unit 440: voltage driver

Claims

A fuse driver for driving an output node according to data programmed into the fuse in response to the fuse reset signal;
A voltage driver for driving one end of the fuse with a predetermined driving force in response to the programmed data;
An information latching unit having a driving force greater than the predetermined driving force, for receiving and latching the programmed data and outputting the same as fuse information; And
An information transfer unit for receiving the programmed data from the fuse driver in response to a control signal and transferring the programmed data to the information latching unit
A fuse circuit comprising a.

The method of claim 1,
The information latching portion is composed of a MOS transistor having a predetermined loading,
And the voltage driver has a larger loading than the predetermined loading.

The method of claim 1,
And the voltage driver includes a MOS transistor for connecting a predetermined voltage with one end of the fuse in response to the programmed data.

The method of claim 2,
And a dummy transistor connected between the predetermined voltage and the other end of the fuse and configured to apply the same voltage corresponding to the predetermined voltage to both ends of the fuse.

The method of claim 1,
And the control signal is inactivated after the fuse reset signal is inactivated and the programmed data is transferred to the information latching unit.

A fuse having one end connected to the first power supply voltage;
A first MOS transistor connecting between the other end of the fuse and an output node in response to a control signal;
A second MOS transistor for initializing the output node to a second power supply voltage in response to a fuse reset signal;
A third MOS transistor coupled to the first power supply voltage and configured to drive the other end of the fuse with a predetermined driving force in response to a voltage level of the output node; And
A plurality of MOS transistors having a driving force larger than the predetermined driving force, for receiving and latching data programmed into the fuse and outputting the data as fuse information.
A fuse circuit comprising a.

The method according to claim 6,
And a fourth MOS transistor connected between the first power supply voltage and one end of the fuse and configured to apply the same voltage corresponding to the first power supply voltage to both ends of the fuse.

The method according to claim 6,
The plurality of MOS transducers have a predetermined loading,
And the third MOS transistor has a loading greater than the predetermined loading.

The method according to claim 6,
And the control signal is inactivated after the fuse reset signal is inactivated and the programmed data is transferred to the information latching unit.

Generating fuse information by driving an output node with a driving force in which one of the first and second loadings is reflected according to the programmed data of the fuses; And
After generating the fuse information, separating the fuse from the output node and driving one end of the fuse with a driving force reflecting the second loading;
Method of operation of the fuse circuit comprising a.

The method of claim 10,
The generating of the fuse information may further include driving the output node with a third driving force that is greater than the driving force in which the second loading is reflected and is less than or equal to the driving force in which the first loading is reflected.

The method of claim 11,
And the third driving force corresponds to the first power supply voltage, and the driving force in which the first and second loadings are reflected corresponds to the same second power supply voltage.