KR20140083745A - Semiconductor device with buried bitline and method for manufacturing the same - Google Patents

Abstract

Present technique relates to a semiconductor device having buried bit lines and a method for fabricating the same. The method of fabricating the semiconductor device according to the present invention includes the steps of burring a plurality of first punch preventing layers spaced apart from each other in a preliminary substrate; forming body lines on the first punch preventing layers, respectively, by etching the preliminary substrate; forming second punch preventing layers between the first punch preventing layers; and forming bit lines buried in the body lines. According to the present technology, after the first punch preventing layer is buried in the first trench, the body line is grown by growing an epitaxial layer to form a single crystalline body line having high quality. In addition, according to the present technology, the first punch preventing layer is formed under the buried bit line, and the second punch preventing layer is formed between the buried bit lines, so that the punch can be prevented between the neighboring buried bit lines.

Description

TECHNICAL FIELD [0001] The present invention relates to a semiconductor device having a buried bit line and a manufacturing method thereof. [0002]

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having buried bit lines and a manufacturing method thereof.

Most of the semiconductor devices include transistors. For example, in a memory device such as a DRAM, a memory cell includes a cell transistor such as a MOSFET. In general, a MOSFET forms a source / drain region in a semiconductor substrate, thereby forming a planar channel between the source region and the drain region. Such a general MOSFET is abbreviated as a 'horizontal channel transistor'.

As the integration and performance of the memory device are continuously required, the fabrication technology of the MOSFET is physically limited. For example, as the size of the memory cell decreases, the size of the MOSFET decreases and the channel length of the MOSFET also decreases. If the channel length of the MOSFET is reduced, the characteristics of the memory device are deteriorated due to various problems such as a decrease in data retention characteristics.

A vertical channel transistor has been proposed to increase the channel length. A vertical channel transistor (VCT) includes a pillar in which a vertical channel is formed. A source region and a drain region are formed at the top and bottom of the pillar. Either the source region or the drain region is connected to the bit line.

1 is a view showing a semiconductor device according to a conventional technique.

Referring to FIG. 1, a plurality of bodies 12 separated from each other are formed on a semiconductor substrate 11. A pillar 13 is formed perpendicularly to the surface of the body 12. The buried bit line 14 is buried in the body 12. The pillar 13 includes first and second source / drain regions 16 and 18 and a channel region 17. A word line 15 extending in a direction intersecting the buried bit line 14 is formed on the sidewall of the pillar 13. Since the word line 15 has a vertical structure, a vertical channel is formed.

1, the pre-body line is formed by etching the semiconductor substrate 11 in consideration of the height of the pillar 13 including the channel region 17. In this case, Thereafter, the upper portion of the spare body line is etched to form the pillars 13. The lower portion of the pillar 13 becomes the body 12.

The prior art must secure a certain height (refer to 'P1') below the buried bit line 14 in order to prevent a punch (refer to 'P') between neighboring buried bit lines 14. The height P1 for preventing punching is required to be about 80 to 90 nm including the depth of the first source / drain region 16 under the buried bit line 14. Therefore, the total height (H ') of the body 12 and the pillars 13 becomes very high, and high aspect ratio etching is required when forming the spare body lines.

As a result, since the height of the pillars 13 and the body 12 must be taken into consideration in the prior art, not only high aspect ratio etching is required but also aspect ratios are increased to prevent punching between the buried bit lines 14, Lt; / RTI >

Further, the prior art has a limitation in reducing the parasitic capacitance between the buried bit lines 14, although the interval between the adjacent buried bit lines 14 is widened. That is, the area of the first source / drain region 16 connected to the buried bit line 14 affects the parasitic capacitance. Therefore, the parasitic capacitance increases because the opposite area (P2 ') between the adjacent buried bit lines 14 includes the first source / drain region 16.

Embodiments of the present invention provide a semiconductor device capable of preventing punching between neighboring buried bit lines and reducing parasitic capacitance and a method of manufacturing the same.

A method for fabricating a semiconductor device according to an embodiment of the present invention includes embedding a plurality of first punch preventing layers spaced apart from each other in a preliminary substrate, etching each preliminary substrate to form body lines on the first punch preventing layer, Forming a second punch preventing layer between each of the plurality of first punch preventing layers, and forming a bit line buried in the body line. The first punch preventing layer and the second punch preventing layer may include silicon oxide. Forming the plurality of first punch barrier layers comprises etching a semiconductor substrate to form a plurality of sacrificial body lines separated by a plurality of first trenches, forming the first punch barrier layer recessed in the first trenches And forming a spare body line to respectively capture the first trench on the first anti-punch layer. The spare body line may comprise a silicon epitaxial layer, a silicon germanium epitaxial layer or a silicon carbide epitaxial layer.

A method for manufacturing a semiconductor device according to an embodiment of the present invention includes a step of forming a plurality of first punch preventing layers on a semiconductor substrate, a plurality of body lines formed on the first punch preventing layer, Forming a spacer covering the semiconductor structure while exposing the second punch blocking layer; selectively removing the second punch blocking layer to open the lower side wall of the body line; Forming a buried bit line in the body line exposed by the open portion, and forming a buried bit line in the body line exposed by the open portion. Wherein forming the semiconductor structure comprises etching a semiconductor substrate to form a plurality of sacrificial body lines separated by a plurality of first trenches; Forming the first punch barrier layer recessed in the first trench; Forming a body line to glue the first trench on the first anti-punch layer; Removing the sacrificial body line; And forming the second punch preventing layer that is recessed between the body lines.

A semiconductor device according to an embodiment of the present invention includes a plurality of active regions including a body formed on a semiconductor substrate and a pillar on the body, a first punch preventing layer buried under the body, 2 punch barrier layer, and a bit line embedded in the body on the first punch blocking layer.

The present technology has the effect of forming a body line having a high quality single crystal by growing a body line through epitaxial growth after embedding the first punch preventing layer in the first trench.

The present invention also has the effect of suppressing punching between neighboring buried bit lines by forming a first punch preventing layer below the buried bit lines and forming a second punch preventing layer between the buried bit lines.

In addition, since the source / drain junctions are not formed under the buried bit lines, the present invention can reduce the parasitic capacitance by reducing the area of the opposing buried bit lines.

In addition, since the junction of the source / drain and the like is not formed under the buried bit line in the present technology, the height of the body line is reduced, thereby reducing the aspect ratio and preventing pattern lining.

1 is a view showing a semiconductor device according to a conventional technique.
2A is a diagram showing a semiconductor device having a buried bit line according to the first embodiment.
2B is a diagram showing a semiconductor device having buried bit lines according to the second embodiment.
3A to 3I are views showing an example for forming buried bit lines of the semiconductor device according to the first embodiment.
4A to 4D are views showing an example for forming pillars and word lines of the semiconductor device according to the first embodiment.
5A to 5K are views showing an example for forming buried bit lines of the semiconductor device according to the second embodiment.
6 is a schematic view showing a memory card;
7 is a block diagram showing an electronic system.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. .

2A is a diagram showing a semiconductor device having a buried bit line according to the first embodiment. 2B is a diagram showing a semiconductor device having buried bit lines according to the second embodiment.

2A, a semiconductor device includes a buried bit line 104, a pillar 103, and a word line 107. [ A plurality of active regions having a vertical structure including the body 102 and the pillars 103 are formed on the semiconductor substrate 101. [ The buried bit line 104 is embedded in the body 102.

The semiconductor substrate 101 may comprise a silicon-containing material. The semiconductor substrate 101 may include a single crystal silicon substrate. The body 102, the pillar 103 and the semiconductor substrate 101 may comprise the same material. Thus, the body 102 and the pillar 103 comprise a silicon-containing material. The body 102 and the pillars 103 comprise monocrystalline silicon.

The active region has a line-like structure and includes a body 102 and a pillar 103 formed on the body 102. [ A plurality of pillars 103 may be formed on one body 102. The plurality of bodies 102 may be a linear structure formed on the semiconductor substrate 101. The body 102 is formed on the semiconductor substrate 101 vertically. The pillar 103 may be formed to extend vertically on the body 102. For example, the body 102 and the pillars 103 may be orthogonal. The plurality of pillars (103) are formed separately from each other on the body (102). The plurality of pillars 103 may have an array arrangement of a matrix structure. The pillar 103 may include a channel region of a vertical channel transistor. In addition, the pillar 103 may include the first and second source / drain regions 108 and 109 and the channel region of the vertical channel transistor. The first source / drain region 108 of the first and second source / drain regions 108 and 109 may be coupled to the buried bit line 104. And the other one of the second source / drain regions 109 may be connected to the capacitor. The first source / drain region 108, the channel region, and the second source / drain region 109 may be vertically connected. The first source / drain region 108, the channel region, and the second source / drain region 109 may form an NPN junction or a PNP junction. For example, when the first and second source / drain regions 108 and 109 are doped with impurities of the first conductivity type, the channel region may be doped with impurities of the second conductivity type that are opposite to the first conductivity type . As is well known, when the impurities of the first conductivity type are N-type impurities, the impurities of the second conductivity type include P-type impurities. Conversely, when the impurities of the first conductivity type are P-type impurities, the impurities of the second conductivity type include N-type impurities. If the vertical channel transistor is an NMOSFET, the first and second source / drain regions and the channel region may form an NPN junction.

The body 102 is formed on the semiconductor substrate 102 vertically. The body 102 may extend in a first direction. The buried bit line 104 and the body 102 may extend in the same first direction. The body 102 and the pillars 103 may be formed by epitaxial growth and then patterned. The body 102 and the pillar 103 may comprise a silicon epitaxial layer, a silicon germanium epitaxial layer or a silicon carbide epitaxial layer. In addition, the body 102 and the pillars 103 may be doped with boron, phosphorus, arsenic, or the like in situ.

A first punch preventing layer 105 is formed below the buried bit line 104 and a second punch preventing layer 106 is formed on the semiconductor substrate 101 between the buried bit lines 104. When the first and second anti-punch layers 105 and 106 include an insulating material such as silicon oxide, the body 102 has a structure formed on the SOI structure. The first punch barrier layer 105 may extend parallel to the buried bit line 104. The second punch barrier layer 106 may also be formed in parallel with the buried bit line 104. The first punch preventing layer 105 may have a deeper depth than the second punch preventing layer 106. The lower portion of the first punch preventing layer 105 may be extended to the second punch preventing layer 106.

The buried bit line 104 is formed buried in the body 102. A full suicide process may be applied to fill the buried bit line 104 in the body 102. [ The buried bit line 104 may extend in a first direction. The buried bit line 104 includes a metallic material. The buried bit line 104 may comprise a metal silicide. Whereby the buried bit line 104 has a low resistance. The metal silicide includes any one selected from the group consisting of cobalt silicide, titanium silicide, nickel silicide, and platinum silicide. The metal silicide may include a three-component system such as cobalt titanium silicide (CoTiSi _x ), cobalt nickel silicide (CoNiSi _x ), and cobalt platinum silicide (CoPtSi _x ).

The word line 107 is formed on the sidewall of the pillar 103 and is formed perpendicular to the sidewall of the pillar 103. Therefore, it is also referred to as a vertical word line. The word lines 107 are formed on both side walls of the pillars 103 and can have a double wordline structure. Even at the double word line structure, the ends of each word line can be connected to each other. Since the pillar 103 is a region where the channel of the vertical channel transistor is formed, a vertical channel is formed by the word line 107. [ Thereby, a vertical channel transistor including a word line 107, a first source / drain region 108, a channel region, and a second source / drain region 109 is formed. The word line 107 may extend in a second direction orthogonal to the first direction. The word line 107 and the buried bit line 104 may be formed in directions intersecting with each other. The word line 107 includes a metallic material. The word line 107 may include titanium nitride (TiN), a stack of tungsten nitride and tungsten (WN / W), and the like. The word line 105 and the buried bit line 104 may be spaced apart. For this purpose, an insulating layer (not shown) may be further formed between the word line 107 and the buried bit line 104. Here, the insulating layer includes silicon oxide or the like. In another embodiment, the wordline 107 may extend in a second direction while surrounding the sidewall of the pillar 103. In addition, a word line 107 connected to the gate electrode may be formed after a gate electrode surrounding the side wall of the pillar 103 is formed.

Referring to FIG. 2B, the semiconductor device includes a buried bit line 204, a pillar 203, and a word line 207. A plurality of active regions having a vertical structure including a body 202 and a pillar 203 are formed on a semiconductor substrate 201. [ The buried bit line 204 is buried in the body 202.

The semiconductor substrate 201 may comprise a silicon-containing material. The semiconductor substrate 201 may include a single crystal silicon substrate. The body 202, the pillar 203, and the semiconductor substrate 201 may comprise the same material. Thus, the body 202 and the pillar 203 comprise a silicon-containing material. The body 202 and the pillars 203 comprise monocrystalline silicon. Body 202 and pillar 203 may comprise a silicon epitaxial layer, a silicon germanium epitaxial layer, or a silicon carbide epitaxial layer. In addition, the body 202 and the pillars 203 may be doped with boron, phosphorus, arsenic, or the like in situ.

The active region has a line-like structure and includes a body 202 and a pillar 203 formed on the body 202. A plurality of pillars 203 may be formed on one body 202. The plurality of bodies 202 may be a line structure formed on the semiconductor substrate 201. The body 202 is formed on the semiconductor substrate 201 vertically. The pillar 203 may extend vertically on the body 202. For example, the body 202 and the pillars 203 may be orthogonal. The plurality of pillars (203) are formed separately from each other on the body (202). The plurality of pillars 203 may have an array arrangement of a matrix structure. The pillar 203 may include a channel region of a vertical channel transistor. In addition, the pillar 203 may include first and second source / drain regions 208 and 209 and a channel region of a vertical channel transistor. The first source / drain region 208 of the first and second source / drain regions 208 and 209 may be coupled to the buried bit line 204. And the other one of the second source / drain regions 209 may be connected to the capacitor. The first source / drain region 208, the channel region, and the second source / drain region 209 may be vertically connected. The first source / drain region 208, the channel region, and the second source / drain region 209 may form an NPN junction or a PNP junction.

The body 202 is formed vertically on the semiconductor substrate 201. The body 202 may extend in a first direction. The buried bit line 204 and the body 202 may extend in the same direction in the first direction. The body 202 and the pillars 203 may be formed by epitaxial growth and then patterned.

The buried bit line 204 is formed buried in the body 202. A full suicide process may be applied to fill the buried bit line 204 in the body 202. [ The buried bit line 204 may extend in a first direction. The buried bit line 204 includes a metallic material. The buried bit line 204 may comprise a metal silicide. Whereby the buried bit line 204 has a low resistance. The metal silicide includes any one selected from the group consisting of cobalt silicide, titanium silicide, nickel silicide, and platinum silicide. The metal silicide may include a three-component system such as cobalt titanium silicide (CoTiSi _x ), cobalt nickel silicide (CoNiSi _x ), and cobalt platinum silicide (CoPtSi _x ).

The word line 207 is formed on the sidewall of the pillar 103 and is formed perpendicular to the sidewall of the pillar 203. Therefore, it is also referred to as a vertical word line. The word lines 207 are formed on both sidewalls of the pillars 203, and can have a double word line structure. Even with the double word line structure, the ends of each word line 207 can be connected to each other. The vertical channel is formed by the word line 207 since the pillar 203 is the region where the channel of the vertical channel transistor is formed. Thereby, a vertical channel transistor including a word line 207, a first source / drain region 208, a channel region, and a second source / drain region 209 is formed. The word line 207 may extend in a second direction orthogonal to the first direction. The word line 207 and the buried bit line 204 may be formed in directions intersecting with each other. The word line 207 includes a metallic material. The word line 207 may include titanium nitride (TiN), a stack of tungsten nitride and tungsten (WN / W), and the like. The word line 207 and the buried bit line 204 may be spaced apart. For this, an insulating film (not shown) may be further formed between the word line 207 and the buried bit line 204. Here, the insulating film includes silicon oxide or the like. In another embodiment, the word line 207 may extend in a second direction (Y direction) surrounding the sidewall of the pillar 203. In addition, a word line 207 connected to the gate electrode may be formed after a gate electrode surrounding the side wall of the pillar 203 is formed.

A first punch preventing layer 205 for preventing punching is formed below the buried bit line 204. The second punch preventing layer 206 is formed between the first punch preventing layers 205. The first punch preventing layer 205 and the second punch preventing layer 206 may include an insulating material. When the first and second anti-punch layers 205 and 206 comprise an insulating layer, the body 202 is formed on the SOI structure. The first punch preventing layer 205 does not extend to the lower portion of the second punch preventing layer 206. That is, the widths of the first punch preventing layer 205 and the second punch preventing layer 206 may be the same.

According to the embodiments described above, a vertical structure is formed in which the buried bit lines 104, 204 are located under the pillars 103, 203. Thus, the buried bit lines 104 and 204 need not be formed between the pillars 103 and 203, thereby enabling high integration.

Then, the buried bit lines 104 and 204 are buried in the bodies 102 and 202, respectively. Thus, the adjacent buried bit lines 104 and 204 are sufficiently spaced, and the parasitic capacitance C _B between the adjacent bit lines 104 and 204 is reduced. In addition, since the first source / drain regions 108 and 208 are not formed below the buried bit lines 104 and 204, the opposing area between the adjacent buried bit lines 104 and 204, which affect the parasitic capacitance, is reduced . This further reduces the parasitic capacitance.

Embodiments can also prevent punching between adjacent buried bit lines 104, 204 by forming first punch barrier 105, 205 under buried bit lines 104, In addition, by further forming the second punch preventing layers 205 and 206 between the buried bit lines 104 and 204, the punch preventing effect can be further increased.

3A to 3I are views showing an example for forming buried bit lines of the semiconductor device according to the first embodiment.

A first mask pattern 22 is formed on the semiconductor substrate 21, as shown in Fig. The semiconductor substrate 21 includes a single crystalline material. The semiconductor substrate 21 includes a silicon-containing substrate, and may include, for example, single crystalline silicon. The first mask pattern 22 comprises silicon nitride. The first mask pattern 22 may be a multi-layered structure including silicon oxide and silicon nitride. For example, the first mask pattern 22 may be stacked in the order of silicon nitride and silicon oxide. Further, the first mask pattern 22 may be laminated in the order of silicon nitride, silicon oxide, silicon oxynitride, and amorphous carbon. A pad oxide layer (not shown) may be further formed between the semiconductor substrate 21 and the first mask pattern 22 when silicon nitride is included. The first mask pattern 22 may be formed using a photoresist pattern not shown. The first mask pattern 22 is formed extending in the first direction. The first mask pattern 22 may include a line pattern extending in a first direction.

Next, the semiconductor substrate 21 is etched using the first mask pattern 22 as an etching mask. Thus, a plurality of first trenches 23 having a predetermined depth from the upper surface of the semiconductor substrate 21 are formed. The first trench 23 may extend in a first direction. A plurality of sacrificial body lines 24 separated by the plurality of first trenches 23 are formed. The sacrificial body line 24 has two sidewalls. The etch process for forming the first trenches 23 may include anisotropic etch. In plan view, sacrificial body line 24 is separated by first trench 23 and has a line shape extending in a first direction.

As described above, the plurality of sacrificial body lines 24 are separated from each other by the first trenches 23.

As shown in FIG. 3B, a first insulating layer 25A recessed in the first trench 23 is formed. The first insulating layer 25A may include silicon oxide. An etch-back process may be performed after silicon oxide is formed on the entire surface so as to cover the first trench 23 in order to recess the first insulating layer 25A. Planarization can be performed using a CMP process before the etch-back process.

As shown in FIG. 3C, a pre-body line 26A is formed to capture the first trench 24. The spare body line 26A can be formed through epitaxial growth. The spare body line 26A may be formed through selective epitaxial growth (SEG). The spare body line 26A is laterally grown from the side wall of the sacrificial body line 24 to fill the first trench 23. The spare body line 26A may have a line shape. Because the sacrificial body line 24 is a silicon-containing material, the spare body line 26A may be a silicon-containing material. For example, the spare body line 26A may comprise a silicon epitaxial layer. When growing the spare body line 26A, the dopant can be grown to undoped undoped, and in other embodiments, the dopant can be in-situ doped. Here, the dopant may include an N-type dopant and a P-type dopant. The dopant may include Boron, Phosphorus, Arsenic. The spare body line 26A may include a silicon germanium epitaxial layer or a silicon carbide epitaxial layer in addition to the silicon epitaxial layer.

Thus, when the spare body line 26A is grown, the sacrificial body line 24 and the spare body line 26A are alternately formed. Since the semiconductor substrate 21, the sacrificial body line 24 and the spare body line 26A are silicon-containing materials, the first insulating layer 25A may be buried in the preliminary substrate 27. [ The preliminary substrate 27 includes a single crystal material. The preliminary substrate 27 includes a silicon-containing substrate, which may include, for example, monocrystalline silicon.

As shown in Fig. 3D, a second mask pattern 28A is formed. The second mask pattern 28A may be formed on the spare body line 26A between the first mask patterns 22. [ The second mask pattern 28A may comprise silicon nitride. In order to form the second mask pattern 28A between the first mask patterns 22, a planarization process may be performed after forming silicon nitride on the entire surface.

Next, a third mask pattern 29 is formed on the second mask pattern 28A. The third mask pattern 29 may have a smaller line width than the second mask pattern 28A. The third mask pattern 29 may include a photosensitive film. The third mask pattern 29 may have the form of a line / space. The first mask pattern 22 is all exposed by the third mask pattern 29 and the second mask pattern 28A is partially exposed.

The second mask pattern 28 and the first mask pattern 22 are etched using the third mask pattern 29 as an etching mask, as shown in FIG. 3E. Subsequently, the spare body line 26A and the sacrificial body line 24 of the spare substrate 27 are etched and a part of the first insulating layer 25A is etched. Body line 26 is formed by etching the spare body line 26A. All sacrificial body lines 24 are removed. The first punch preventing layer 25 is formed by etching the first insulating layer 25A. The body lines 26 can be separated from each other by the second trenches 30. The line widths of the body lines 26 are all the same, and the line widths of the second trenches 30 may all be the same. The line widths of the body line 26 and the second trench 30 may be the same.

The first mask pattern 22 and the sacrificial body line 24 are all removed and the first insulating layer 25A is partially etched to form the body line 26 and the first punch preventing layer 25 do. A first anti-pinning layer 25 is formed under the body line 26. The line width of the first punch preventing layer 25 may be larger than that of the body line 26. [ As a result, the effect of preventing punching between neighboring body lines 26 is increased.

As shown in FIG. 3F, a second insulating layer 31A is formed to fill the second trench 30. The second insulating layer 31A can be subjected to a certain depth first order recession. Thus, a recessed second insulating layer 31A that partially captures the second trench 30 can be formed. The recessed second insulating layer 31A supports the lower sidewall of the body line 26.

Next, a protective layer 32A is formed on the entire surface including the recessed second insulating layer 31A. The protective layer 32A may be formed of silicon oxide or silicon nitride, or may be formed by laminating silicon oxide and silicon nitride.

As shown in FIG. 3G, the protective layer 32A is selectively etched to form the spacer 32. Then, as shown in FIG. An etch-back process may be applied to form the spacers 32. [ By forming the spacer 32, the second insulating layer 31A is exposed.

Next, the second insulating layer 31A is subjected to second-order recessing. Thus, the second punch preventing layer 31 is formed, and the lower side wall of the body line 26 is exposed by the second punch preventing layer 31. [ At this time, the lower sidewalls on both sides of the body line 26 are exposed at the same time, thereby forming the open portions 33A and 33B. The open portions 33A and 33B expose both side walls of the body line 26 between the spacer 32 and the second punch preventing layer 31. [ The second punch preventing layer 31 is formed on the substrate 21 between the body lines 26 and can be connected to the first punch preventing layer 25. The first punch preventing layer 25 may have a shape extending to a lower portion of the second punch preventing layer 31.

As a result, a first punch preventing layer 25 is formed under the body line 26 and a second punch preventing layer 31 is formed on the substrate 21 between the body lines 26. Such a punch preventive structure prevents punching between adjacent body lines 26, and the punch preventive effect is further enhanced by the second punch preventing layer 31. [ The height of the body line 26 can be reduced by the height of the first punch preventing layer 25, thereby reducing the aspect ratio, thereby preventing pattern lining.

The open portions 33A and 33B can be opened in the form of a line extending along the side wall of the body line 26. In particular, the openings 33A and 33B are formed simultaneously on the lower sidewalls of the neighboring body lines 26. [ This is called BSC (Both side contact). The body line 26 is covered by an insulating material such as a spacer 32, a second mask pattern 28 and a second punch preventing layer 31 and is formed by openings 33A and 33B formed by these insulating materials Both lower side walls are exposed.

Since the first punch preventing layer 25 and the second punch preventing layer 31 include silicon oxide, the body line 26 is formed on the SOI (Silicon On Insulator) structure.

A metal layer 34 is formed on the entire surface including the open portions 33A and 33B, as shown in FIG. 3H. Here, the metal layer 34 includes a metal such as a precious metal or a refractory metal. The metal layer 34 includes a metal capable of silicidation. For example, the metal layer 34 includes any one selected from cobalt (Co), titanium (Ti), nickel (Ni), and platinum (Pt). The metal layer 34 is formed using chemical vapor deposition (CVD) or atomic layer deposition (ALD).

Next, annealing is performed. Silicidation is thus performed in which the metal layer 34 reacts with the lower sidewall of the body line 26. The metal silicide 35 is formed by the reaction between the metal layer 34 and the body line 26 because the metal layer 34 contains a metal and the material of the body line 26 contains silicon. The metal silicide 35 includes any one selected from the group consisting of cobalt silicide, titanium silicide, nickel silicide, and platinum silicide. The metal silicide 35 may include a ternary system such as cobalt titanium silicide (CoTiSi _x ), cobalt nickel silicide (CoNiSi _x ), and cobalt platinum silicide (CoPtSi _x ). The anneal includes Rapid Thermal Anneal. Rapid annealing (RTA) may be performed at different temperatures depending on the type of the body line 26 and the metal layer 34. For example, when cobalt (Co) is used for the metal layer 34, the annealing temperature range is preferably 400 to 800 ° C. The metal silicide 35 may be partially silicided or fully silicided (FUSI). Hereinafter, the embodiment includes a fully suicided metal silicide 35. The silicidation can sufficiently proceed from one side wall of the body line 26 to fully silicide the exposed portion of the body line 26 exposed by the open portions 33A and 33B. The metal silicide 35 is embedded in the body line 26 by complete silicidation. After the formation of the metal silicide 35, the unreacted metal layer remains.

The metal silicide 35 formed by such a silicidation process becomes the buried bit line BBL. Hereinafter, the metal silicide is referred to as a buried bit line 35. The metal silicide does not extend downward by the first and second punch preventing layers 25 and 31 when the metal silicide to be the buried bit line 35 is formed.

As shown in Figure 3i, the unreacted metal layer is removed. At this time, the unreacted metal layer can be removed by wet etching.

On the other hand, if the metal layer 34 is cobalt, rapid thermal annealing (RTA) is performed at least twice to form cobalt silicide. For example, primary annealing and secondary annealing are performed. The primary annealing proceeds at a temperature of 400 to 600 ° C, and the secondary annealing proceeds at a temperature of 600 to 800 ° C. Cobalt suicide with a 'CoSi _x (x = 0.1 to 1.5)' phase is formed by primary annealing. Converted to cobalt silicide of 'CoSi ₂ phase' by secondary annealing. Among cobalt silicides, cobalt silicide having a 'CoSi ₂ ' phase has the lowest resistivity. The unreacted cobalt is removed between the primary annealing and the secondary annealing. Unreacted cobalt can be removed by using a mixed chemical of sulfuric acid (H ₂ SO ₄ ) and peroxide (H ₂ O ₂ ).

Next, a first interlayer insulating layer 36 is formed on the entire surface of the body line 26 to fill the gap therebetween. The first interlayer insulating layer 36 may include an oxide such as BPSG. The first interlayer insulating layer 36 may be planarized so that the surface of the second mask pattern 28 is exposed. The adjacent buried bit lines 35 and the body lines 26 are insulated from each other by the first interlayer insulating layer 36. [

According to the first embodiment described above, a buried bit line 35 buried in the body line 26 is formed. Thus, adjacent buried bit lines 35 are sufficiently separated by the first punch preventing layer 25 and the second punch preventing layer 31, and punching between the adjacent buried bit lines 35 is prevented. In addition, since the source / drain is not formed by the first punch preventing layer 25 under the buried bit line 34, the facing area is reduced accordingly. This further reduces the parasitic capacitance between the adjacent buried bit lines 35.

A vertical channel transistor including a pillar may be formed on the body line 26. [ In this embodiment, a part of the body line 26 may be etched to form a pillar.

4A to 4D are views showing an example for forming pillars and word lines of the semiconductor device according to the first embodiment. Hereinafter, the method of forming the pillar is a view taken along the line A-A 'in Fig. 3I.

As shown in FIG. 4A, the top of the body line 26 is etched using a fourth mask pattern 37. The fourth mask pattern 37 may include a line pattern in a direction intersecting the body line 26. The second mask pattern 28 is etched using the third mask pattern 37 as an etching mask and the body line 26 and the first interlayer insulating layer 36 are etched to a certain depth. A plurality of pillars 260 are formed. The pillar 260 may be formed by etching the body line 26.

The pillar 260 is formed by etching the body line 26 and the body 261 is formed below the pillar 260. [ The body 261 is in the form of a line extending in either direction and a plurality of pillars 260 are formed on one body 261.

A buried bit line 35 is formed in the body 261. A first punch barrier layer 25 is formed below the buried bit line 35. The body 261 is in the form of a line extending in the same direction as the buried bit line 40. The pillar 260 extends in the vertical direction on the body 261. The pillars 260 are formed on a cell-by-cell basis. Accordingly, a plurality of pillars 260 are formed on one body 261. The pillar 260 is a structure in which a channel region of a vertical channel transistor is formed. The plurality of pillars 260 may have an array arrangement of a matrix structure on the body 261. Since the material of the body line 26 includes silicon, the pillar 260 may include a silicon pillar. The pillar 260 may include a single crystal silicon pillar.

In the pillar 260, a vertical structure of the first source / drain region, the channel region, and the second source / drain region may be formed. For example, the pillar 260 may include an NPN junction. The NPN junction can be formed through ion implantation after the pillars 260 are formed. A portion of the first source / drain region N may be formed in the body 261. [ The top surface of the first source / drain region N may extend to the bottom of the pillar 260.

4B, after the fourth mask pattern 37 is removed, a conductive layer 39A is formed to partially fill the spaces between the pillars 260. As shown in FIG. The gate insulating layer 38 can be formed before forming the conductive layer 39A. The gate insulating layer 38 may be formed by oxidizing the sidewalls of the pillars 260 and the upper surface of the body 261. The conductive layer 39A uses a low-resistance material. For example, a metal layer can be used. The metal layer may include a titanium film, a titanium nitride film, a tungsten film, and the like. The conductive layer 39A can be recessed by sequentially performing planarization and etchback.

As shown in Fig. 4C, the conductive layer 39A is etched. Thus, the word line 39 is formed on the sidewall of the pillar 260. After a spacer (not shown) using silicon nitride or the like is formed to etch the conductive layer 39A, the spacer may be used as an etching mask.

The word line 39 may be formed in a second direction that intersects the buried bit line 35. The word line 39 also serves as a vertical gate electrode. In another embodiment, the word line 39 may be formed to surround the pillar 260. [ In another embodiment, the annular vertical gate electrode surrounding the pillars 260 may be formed and then the word lines 39 connecting the neighboring vertical gate electrodes to each other may be formed. In yet another embodiment, the word line 39 may be formed on top of the pillar 260 through the gate contact after formation of the vertical gate electrode.

As shown in FIG. 4D, a second interlayer insulating layer 40 is formed to isolate the word lines 39 from each other.

Then, the second mask pattern 28 is selectively etched to form a contact hole on the pillar 260. Next, a storage node contact plug 41 for embedding the contact hole is formed. In another embodiment, a portion of the second mask pattern 28 may be etched to form a contact hole.

The storage node 42 of the capacitor can be formed on the storage node contact plug 41. [ The storage node 42 may be in the form of a pillar. In another embodiment, the storage node 42 may be in the form of a cylinder. Although not shown, a dielectric film and an upper electrode are formed on the storage node 42 subsequently.

The NPN junction is formed after the pillar 260 is formed. However, in another embodiment, the first source / drain region may be formed using plasma doping before forming the buried bit line 35, And a second source / drain region may be formed through ion implantation after formation. The channel region may be formed by in-situ doping when selective epitaxial growth is performed, or may be formed by tilt ion implantation after filer formation. A first source / drain region is not formed under the buried bit line 35 by the first punch preventing layer 25 when the first source / drain region is formed before the buried bit line 35 is formed. Thus, the area of the opposing buried bit lines 35 facing each other can be reduced.

5A to 5K are views showing an example for forming buried bit lines of the semiconductor device according to the second embodiment.

As shown in FIG. 5A, a first mask pattern 52 is formed on the semiconductor substrate 51. The semiconductor substrate 51 includes a single crystalline material. The semiconductor substrate 51 includes a silicon-containing substrate, and may include, for example, single crystalline silicon. The first mask pattern 52 comprises silicon nitride. The first mask pattern 52 may comprise silicon nitride. The first mask pattern 52 is formed extending in the first direction. The first mask pattern 52 may include a line pattern extending in a first direction.

Next, the semiconductor substrate 51 is etched using the first mask pattern 52 as an etching mask. Thus, a plurality of first trenches 54 having a certain depth from the upper surface of the semiconductor substrate 51 are formed. The first trench 54 may extend in a first direction. A plurality of sacrificial body lines 53 separated by the plurality of first trenches 54 are formed. The sacrificial body line 53 has two sidewalls. The etch process for forming the first trenches 54 may include anisotropic etch. In plan view, the sacrificial body line 53 is separated by a first trench 54 and has a line shape extending in a first direction.

As described above, the plurality of sacrificial body lines 53 are separated from each other by the first trenches 54.

As shown in FIG. 5B, a first punch preventing layer 55 recessed in the first trench 54 is formed. The first anti-pinning layer 55 may include silicon oxide. An etch-back process may be performed after silicon oxide is formed on the entire surface so as to cover the first trenches 53 in order to recess the first punch preventing layer 55. Planarization can be performed using a CMP process before the etch-back process.

As shown in FIG. 5C, a body line 56 is formed to fill the first trench 54. The body line 56 may be formed through epitaxial growth. The body line 56 may be formed through selective epitaxial growth (SEG). The body line 56 is laterally grown from the sidewalls of the sacrificial body line 53 to fill the first trench 54. The body line 56 may have a line shape. Because the sacrificial body line 53 is a silicon-containing material, the body line 56 may be a silicon-containing material. For example, the body line 56 may comprise a silicon epitaxial layer. As the body line 56 is grown, the dopant can grow into undoped undoped, and in other embodiments the dopant can be in-situ doped. Here, the dopant may include an N-type dopant and a P-type dopant. The dopant may include Boron, Phosphorus, Arsenic. The body line 56 may comprise a silicon germanium epitaxial layer or a silicon carbide epitaxial layer in addition to the silicon epitaxial layer.

Thus, when the body line 56 is grown, the sacrificial body line 53 and the body line 56 are alternately formed. Since the semiconductor substrate 51, the sacrificial body line 53 and the body line 56 are the silicon-containing material 57, the first punch preventing layer 55 may be buried in the preliminary substrate 57. [

The body line 56 can be grown such that a groove 58 having a predetermined depth is formed between the first mask patterns 52. [

A second mask pattern 59 is formed, as shown in Fig. 5D. A second mask pattern 59 may be formed on the body line 56 between the first mask patterns 52. The second mask pattern 59 may be formed using silicon oxide. The second mask pattern 59 may have the form of a line / space. In order to form the second mask pattern 59 between the first mask patterns 52, a planarization process may be performed after forming the silicon oxide on the entire surface.

Next, the first mask pattern 52 is selectively removed. Thus, a groove 60 is formed between the body lines 56. That is, grooves 60 are formed on the sacrificial body line 53 between the second mask patterns 69. Since the second mask pattern 59 includes silicon oxide, the first mask pattern 52 can be selectively removed.

As shown in FIG. 5E, the sacrificial body line 53 is etched using the second mask pattern 59 as an etching mask. Accordingly, the body lines 56 can be separated from each other by the second trenches 61. [ The line widths of the body lines 56 are all the same, and the line widths of the second trenches 61 can all be the same. The line widths of the body line 56 and the second trench 61 may be the same.

As described above, the body line 56 is formed by removing all the sacrificial body lines 53. A first punch preventing layer 55 is formed under the body line 56. The line width of the first punch preventing layer 55 may be the same as that of the body line 56. Punching between the neighboring body lines 56 is prevented by the first punch preventing layer 55. [

As shown in FIG. 5F, a second insulating layer 62A is formed to fill the second trenches 61. As shown in FIG. The second insulating layer 62A may include silicon oxide. The second insulating layer 62A may be planarized until the surface of the second mask pattern 59 is exposed.

As shown in Fig. 5G, the first insulating layer 62A is first deeply recessed. Thus, a recessed second insulating layer pattern 62B partially filling the second trenches 61 can be formed. The recessed second insulating layer pattern 62B supports the lower sidewall of the body line 56. When the second insulating layer pattern 62B is recessed, the second mask pattern 59 can be simultaneously removed.

As described above, by forming the second insulating layer pattern 6B, the semiconductor substrate 51 is protected with the semiconductor substrate 51 including the first punch preventing layer 55, the body line 56 and the recessed second insulating layer pattern 62B. A structure can be formed.

As shown in FIG. 5H, a protective layer 63A is formed on the entire surface including the recessed second insulating layer pattern 62B. The protective layer 63A may be formed of silicon oxide or silicon nitride, or may be formed by laminating silicon oxide and silicon nitride. The protective layer 63A may be formed thicker at the top of the body line 56. [ That is, the thickness formed at the upper portion of the body line 56 may be thicker than the thickness formed at both side walls of the body line 56. For this purpose, the protective layer 63A may be formed by plasma CVD.

As shown in Fig. 5I, the protective layer 63A is selectively etched to form the spacer 63. Then, as shown in Fig. An etch-back process may be applied to form the spacers 63. [ By forming the spacer 63, the second insulating layer pattern 62B is exposed. The spacers 63 may be shaped to cover the top and both sidewalls of the body line 56.

Next, the second insulating layer 62B is subjected to second-order recessing. Thus, the second punch preventing layer 62 is formed, and the lower side wall of the body line 56 is exposed by the second punch preventing layer 62. At this time, the lower side walls on both sides of the body line 56 are exposed at the same time, thereby forming the open portions 64A and 64B. The open portions 64A and 64B expose both sidewalls of the body line 56 between the spacer 63 and the second punch preventing layer 62. [ The second punch preventing layer 62 is formed on the substrate 51 between the body lines 56 and may be connected to the first punch preventing layer 55.

As a result, a first punch preventing layer 55 is formed under the body line 56 and a second punch preventing layer 62 is formed on the substrate 51 between the body lines 56. Such a punch preventive structure prevents punching between adjacent body lines 56, and the second punch preventing layer 62 further enhances the punch preventing effect.

The open portions 64A and 64B may be opened in a line form extending along the side wall of the body line 56. [ In particular, the openings 64A, 64B are formed at the bottom sidewalls of the adjacent body lines 56 at the same time. This is called BSC (Both side contact). The body line 56 is covered with an insulating material such as a spacer 63 and a second punch preventing layer 62 and both lower sidewalls are exposed by the open portions 64A and 64B formed by these insulating materials.

Since the first punch preventing layer 55 and the second punch preventing layer 62 include silicon oxide, the body line 56 is formed on the SOI (Silicon On Insulator) structure.

As shown in FIG. 5J, a metal layer (not shown) is formed on the entire surface including the open portions 64A and 64B. Here, the metal layer includes a metal such as a precious metal or a refractory metal. The metal layer includes a metal capable of silicidation. For example, the metal layer includes any one selected from the group consisting of Co, Ti, Ta, Ni, W, Pt, and Pd. The metal layer is formed using chemical vapor deposition (CVD) or atomic layer deposition (ALD).

Next, annealing is performed. Thereby, silicidation is performed in which the metal layer and the lower sidewall of the body line 56 react with each other. Since the metal layer contains the metal and the material of the body line 56 contains silicon, the metal silicide 65 is formed by the reaction of the metal layer and the body line 56. The metal silicide 65 includes any one selected from the group consisting of cobalt silicide, titanium silicide, tantalum silicide, nickel silicide, tungsten silicide, platinum silicide, and palladium silicide. The metal silicide 65 may include a three-component system such as cobalt titanium silicide (CoTiSi _x ), cobalt nickel silicide (CoNiSi _x ), and cobalt platinum silicide (CoPtSi _x ). The anneal includes Rapid Thermal Anneal. Rapid annealing (RTA) may be performed at different temperatures depending on the type of the metal lines and the body lines 56. For example, when cobalt (Co) is used as the metal layer, the annealing temperature range is preferably 400 ° C to 800 ° C. The metal silicide 65 may be partially silicided or fully silicided (FUSI). Hereinafter, the embodiment includes a fully suicided metal silicide 65. The silicidation can be sufficiently advanced from one side wall of the body line 56 to completely silicide the exposed portion of the body line 56 exposed by the open portions 64A and 64B. The metal silicide 65 is buried in the body line 56 by complete silicidation. After the formation of the metal silicide 65, the unreacted metal layer remains.

The metal silicide 65 formed by such a silicidation process becomes the buried bit line BBL. Hereinafter, the metal silicide is referred to as a buried bit line 65.

As shown in FIG. 5K, the unreacted metal layer is removed. At this time, the unreacted metal layer can be removed by wet etching.

On the other hand, if the metal layer is cobalt, rapid thermal annealing (RTA) is performed at least twice to form cobalt silicide. For example, primary annealing and secondary annealing are performed. The primary annealing proceeds at a temperature of 400 to 600 ° C, and the secondary annealing proceeds at a temperature of 600 to 800 ° C. Cobalt suicide with a 'CoSi _x (x = 0.1 to 1.5)' phase is formed by primary annealing. Converted to cobalt silicide of 'CoSi ₂ phase' by secondary annealing. Among cobalt silicides, cobalt silicide having a 'CoSi ₂ ' phase has the lowest resistivity. The unreacted cobalt is removed between the primary annealing and the secondary annealing. Unreacted cobalt can be removed by using a mixed chemical of sulfuric acid (H ₂ SO ₄ ) and peroxide (H ₂ O ₂ ).

Next, a first interlayer insulating layer 66 is formed on the entire surface to fill the space between the body lines 56. The first interlayer insulating layer 66 may include an oxide such as BPSG. The first interlayer insulating layer 66 may be planarized so that the surface of the spacer 63 is exposed. The adjacent buried bit lines 65 and body lines 56 are insulated from each other by the first interlayer insulating layer 66. [

Subsequently, a vertical channel transistor including a pillar may be formed on top of the body line 56. In this embodiment, a part of the body line 56 may be etched to form a pillar. This will be referred to the first embodiment.

The embedded bit line and the vertical channel transistor according to the above embodiments may be applied to a dynamic random access memory (DRAM), and the present invention is not limited thereto. For example, a static random access memory (SRAM), a flash memory, a ferroelectric random Access Memory), MRAM (Magnetic Random Access Memory), and PRAM (Phase Change Random Access Memory).

6 is a schematic view showing a memory card; Referring to FIG. 6, the memory card 300 may include a controller 310 and a memory 320. Controller 310 and memory 320 may exchange electrical signals. For example, the memory 320 and the controller 310 can exchange data according to a command of the controller 310. [ Accordingly, the memory card 300 can store data in the memory 320 or output data from the memory 320 to the outside. The memory 320 may include buried bit lines and vertical channel transistors as described above. The memory card 300 may be used as a data storage medium for various portable apparatuses. For example, the memory card 300 may be a memory stick card, a smart media card (SM), a secure digital (SD) card, a mini secure digital card, mini SD), or a multi media card (MMC).

7 is a block diagram showing an electronic system. 7, the electronic system 400 may include a processor 410, an input / output device 430, and a chip 420, which may communicate with each other using a bus 440 . The processor 410 may be responsible for executing the program and controlling the electronic system 400. The input / output device 430 may be used to input or output data of the electronic system 400. The electronic system 400 may be connected to an external device, e.g., a personal computer or network, using the input / output device 430 to exchange data with the external device. The chip 420 may store code and data for operation of the processor 410 and may process some of the operations provided in the process 410. For example, chip 420 may include the buried bit line and vertical channel transistors described above. The electronic system 400 may comprise various electronic control devices that require the chip 420 and may include a mobile phone, an MP3 player, navigation, a solid state disk (SSD) ), Household appliances, and the like.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined by the appended claims. Will be clear to those who have knowledge of.

101: semiconductor substrate 102: body
103: Pillar 104: Embedded bit line
105: first punch preventing layer 106: second punch preventing layer
107: word line 108: first source / drain region
109: second source / drain region

Claims (24)

Embedding a plurality of first punch preventing layers spaced apart from each other in a preliminary substrate;
Etching the preliminary substrate to form body lines on the first punch preventing layer, respectively;
Forming a second punch preventing layer between each of the plurality of first punch preventing layers; And
Forming a buried bit line within the body line;
≪ / RTI >
The method according to claim 1,
After forming the bit line,
Etching a top portion of the body line to form a plurality of pillars including a channel region of the vertical channel transistor;
Forming a gate electrode on a sidewall of the pillar; And
Forming a capacitor connected to the top of the pillar
≪ / RTI >
The method according to claim 1,
Wherein the first punch preventing layer and the second punch preventing layer comprise an insulating material.
The method according to claim 1,
Wherein the first punch preventing layer and the second punch preventing layer comprise silicon oxide.
The method according to claim 1,
The step of embedding the plurality of first anti-
Etching the semiconductor substrate to form a plurality of sacrificial body lines separated by a plurality of first trenches;
Forming the first punch barrier layer recessed in the first trench; And
Forming a spare body line that grips the first trenches on the first punch preventing layer, respectively
≪ / RTI >
6. The method of claim 5,
Wherein forming the spare body line comprises:
Performing selective epitaxial growth from the sidewalls of the sacrificial body line
≪ / RTI >
6. The method of claim 5,
Wherein the semiconductor substrate comprises a silicon containing substrate and the spare body line comprises an epitaxial layer containing silicon.
6. The method of claim 5,
Wherein the spare body line comprises a silicon epitaxial layer, a silicon germanium epitaxial layer, or a silicon carbide epitaxial layer.
The method according to claim 1,
Wherein forming the second punch barrier layer and the bit line comprises:
Forming a recessed insulating layer between the body lines;
Forming spacers covering both side walls of the body line exposed by the recessed insulating layer;
Forming the second punch barrier layer having an opening to selectively open the lower sidewall of the body line by selectively removing the insulating layer;
Forming a metal layer on the entire surface including the open portion; And
Annealing the metal layer to induce a silicidation reaction between the metal layer and the body line
≪ / RTI >
10. The method of claim 9,
Wherein the anneal proceeds to completely silicide the lower sidewall of the body line.
Forming a semiconductor structure including a plurality of first punch preventing layers on a semiconductor substrate, a plurality of body lines formed on the first punch preventing layer, and a second punch preventing layer recessed between the plurality of body lines;
Forming a spacer covering the semiconductor structure while exposing the second punch blocking layer;
Forming an open portion that selectively recesses the second punch blocking layer to open a lower sidewall of the body line; And
Forming a buried bit line in the body line exposed by the open portion
≪ / RTI >
12. The method of claim 11,
After forming the bit line,
Etching a top portion of the body line to form a plurality of pillars including a channel region of the vertical channel transistor;
Forming a gate electrode on a sidewall of the pillar; And
Forming a capacitor connected to the top of the pillar
≪ / RTI >
12. The method of claim 11,
Wherein the first punch preventing layer and the second punch preventing layer comprise silicon oxide.
12. The method of claim 11,
Wherein forming the semiconductor structure comprises:
Etching the semiconductor substrate to form a plurality of sacrificial body lines separated by the plurality of first trenches;
Forming the first punch barrier layer recessed in the first trench;
Forming a body line to glue the first trench on the first anti-punch layer;
Removing the sacrificial body line; And
Forming a second punch preventing layer that is recessed between the body lines
≪ / RTI >
15. The method of claim 14,
Wherein forming the body line comprises:
Performing selective epitaxial growth from the sidewalls of the sacrificial body line
≪ / RTI >
15. The method of claim 14,
Wherein the semiconductor substrate comprises a silicon containing substrate and the body line comprises an epitaxial layer containing silicon.
15. The method of claim 14,
Wherein the body line comprises a silicon epitaxial layer, a silicon germanium epitaxial layer, or a silicon carbide epitaxial layer.
12. The method of claim 11,
Wherein forming the bit line comprises:
Forming a metal layer including the open portion; And
Annealing the metal layer to induce a silicidation reaction between the metal layer and the body line
≪ / RTI >
19. The method of claim 18,
Wherein the anneal proceeds to completely silicide the lower sidewall of the body line.
A plurality of active regions including a body formed on a semiconductor substrate and a pillar on said body;
A first punch barrier layer embedded beneath the body;
A second punch preventing layer formed on the semiconductor substrate between the bodies; And
The bit line embedded in the body on the first anti-
≪ / RTI >
21. The method of claim 20,
A vertical channel transistor including a gate electrode formed on a sidewall of the pillar; And
The capacitor formed on the pillars
.
21. The method of claim 20,
Wherein the first punch preventing layer and the second punch preventing layer comprise an insulating material.
21. The method of claim 20,
Wherein the first punch preventing layer and the second punch preventing layer comprise silicon oxide. 21. The method of claim 20,
Wherein the body and the pillars comprise a silicon epitaxial layer, a silicon germanium epitaxial layer, or a silicon carbide epitaxial layer.

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