CN108461496B - Integrated circuit memory, forming method thereof and semiconductor integrated circuit device - Google Patents

Integrated circuit memory, forming method thereof and semiconductor integrated circuit device Download PDF

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CN108461496B
CN108461496B CN201810439588.9A CN201810439588A CN108461496B CN 108461496 B CN108461496 B CN 108461496B CN 201810439588 A CN201810439588 A CN 201810439588A CN 108461496 B CN108461496 B CN 108461496B
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CN108461496A (en
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请求不公布姓名
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Changxin Memory Technologies Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells

Abstract

The invention provides an integrated circuit memory, a method for forming the same and a semiconductor integrated circuit device. The active pillars vertically disposed on the substrate are used to form vertical memory transistors, thereby facilitating a reduction in the cell layout size of the vertical memory transistors on the substrate, and further enabling a further reduction in the size of the integrated circuit memory. In addition, the vertical memory transistors with the vertical structure have better arrangement flexibility, for example, a plurality of vertical memory transistors can be arranged in a hexagonal dense mode, so that the arrangement density of memory cells in the integrated circuit memory is improved.

Description

Integrated circuit memory, forming method thereof and semiconductor integrated circuit device
Technical Field
The present invention relates to the field of semiconductor technology, and more particularly, to an integrated circuit memory, a method of forming the same, and a semiconductor integrated circuit device.
Background
The smaller the semiconductor device is, so that the semiconductor device is suitable for mobile computing application, and the less energy can be consumed, so that the service time of a battery between charging is prolonged. And, as the size of the semiconductor device is reduced, the circuit density can be correspondingly increased, so that the semiconductor device can have more powerful computing power.
However, current technological developments have been limited by the resolution of the lithographic apparatus available at the time. In particular, the minimum dimensions of the semiconductor device, such as the line width CD (Critical Dimension) and the line spacing S (spaces), depend on the resolution capability of the lithographic apparatus, and thus, patterns smaller than the minimum feature size cannot be stably obtained under the limitation of the minimum feature size available to the lithographic apparatus. This will limit further reduction in the size of the semiconductor device and cannot again increase the arrangement density of the unit elements in the semiconductor device.
For a memory (e.g., a dynamic random access memory DRAM), its memory cells include a memory transistor and a memory element connected thereto. The source region, the channel region and the drain region of the memory transistor are horizontally distributed along a direction parallel to the surface of the substrate, and when the memory transistor of the memory cell is normally turned on, a channel current thereof generally flows between the source region and the drain region along the horizontal direction. Then, when the memory transistor is reduced to a predetermined size, a short channel effect of the memory transistor is extremely likely to occur. It can be seen that the size of the conventional memory is limited by the resolution of the lithographic apparatus, and the short channel effect caused by the reduced size is also considered.
Disclosure of Invention
The invention aims to provide an integrated circuit memory, which is used for reducing the size of the integrated circuit memory and improving the arrangement density of memory cells in the integrated circuit memory.
In order to solve the above technical problems, the present invention provides an integrated circuit memory, comprising:
a substrate;
a plurality of bit lines formed on the substrate and extending along a first direction;
a plurality of active pillars formed on the bit lines such that bottom ends of the active pillars are connected to the bit lines;
and the plurality of word lines are formed on the substrate and extend along the second direction, the word lines are connected with gate tubes in the extending direction, the gate tubes encircle the outer side walls of the corresponding active columns, the top ends of the active columns are exposed out of the gate tubes, and the active columns and the gate tubes jointly form the vertical storage transistor of the integrated circuit memory.
Optionally, a cell configuration size of the vertical memory transistor of the integrated circuit memory on the substrate is 4 times or more a square of a minimum feature size.
Optionally, the integrated circuit memory further includes a storage element, and the integrated circuit memory further includes: and a plurality of memory elements formed above the vertical memory transistors and electrically connected to the top ends of the active pillars.
Optionally, a first doped region is formed in the bottom portion of the active pillar and connected to the bit line, and a second doped region is formed in the top portion of the active pillar and connected to a memory element, where the first doped region and the second doped region respectively form a drain region and a source region of the vertical memory transistor.
Optionally, the integrated circuit memory further includes: and the insulating dielectric layer is formed on the substrate, fills gaps between adjacent bit lines and covers the bit lines, and the word lines are formed on the insulating dielectric layer.
Optionally, the insulating medium layer also surrounds a part of bottom end of the active column; and, a top surface of the insulating dielectric layer is higher than a top surface of the bit line and lower than a top boundary of the first doped region of the active pillar.
Optionally, a top surface of the gate tube is lower than a top surface of the active pillar and higher than a bottom boundary of the second doped region of the active pillar.
Optionally, the integrated circuit memory further includes: and a spacer dielectric layer formed on the substrate and filling the gaps between the adjacent word lines.
Optionally, the word line includes a gate tube surrounding a sidewall of the active pillar, and a connection line portion for connecting the gate tube on an adjacent active pillar, and a top surface of the connection line portion is lower than a top surface of the gate tube; the spacer dielectric layer further covers the connecting wire portion and extends to cover the side wall of the grid tube.
Optionally, the shape of the active column comprises a cylinder.
Optionally, the word lines and the bit lines spatially intersect and have a plurality of overlapping areas, one overlapping area corresponds to one active column, and six active columns of the active columns, which are equidistantly adjacent to the same active column, are arranged in a hexagonal array.
Optionally, the integrated circuit memory further includes: and a spacer dielectric layer formed on the substrate and filling the gap between the adjacent gate tubes.
Optionally, the word line includes a plurality of connection line parts connecting the gate transistors, the connection line parts regularly and linearly connecting the gate transistors on the adjacent active pillars, and a top surface of the connection line part is lower than a top surface of the gate transistor; the spacer dielectric layer further covers the connecting wire portion and extends to cover the side wall of the grid tube.
Optionally, the projection image of the extending direction of the connecting line portion of the word line on the substrate intersects the bit line and has an included angle, and the included angle is between 50 ° and 70 °.
Still another object of the present invention is to provide a method for forming an integrated circuit memory, comprising:
providing a substrate, and forming a plurality of bit lines on the substrate, wherein the bit lines extend along a first direction;
forming a plurality of active pillars on the bit lines, bottom ends of the active pillars being connected to the bit lines; the method comprises the steps of,
and forming a plurality of word lines on the substrate, wherein the word lines extend along a second direction, the word lines are connected with gate tubes in the extending direction, the gate tubes encircle the outer side walls of the corresponding active columns, and the active columns and the gate tubes jointly form the vertical storage transistor of the integrated circuit memory.
Optionally, a cell configuration size of the vertical memory transistor on the substrate is 4 times or more of a square of a minimum feature size.
Optionally, after forming the word line, the method further includes:
a memory element is formed over the vertical memory transistor, the memory element being electrically connected to the top end of the active pillar.
Optionally, the method for forming the active column includes:
forming a sacrificial layer on the substrate, wherein a plurality of through holes are formed in the sacrificial layer, and the through holes expose the bit lines; the method comprises the steps of,
active material is filled in the through holes to form the active pillars, and the sacrificial layer is removed.
Optionally, the shape of the through hole includes a cylindrical shape.
Optionally, after forming the active pillars and before forming the word lines, the method further includes:
and forming an insulating dielectric layer on the substrate, wherein the insulating dielectric layer fills gaps between adjacent bit lines and covers the bit lines.
Optionally, the forming method of the word line and the gate tube includes:
forming a conductive material layer on the substrate, the conductive material layer covering the top surface and the sidewalls of the active pillars and covering the film surface between adjacent active pillars 300; the method comprises the steps of,
providing a mask, wherein a plurality of lines extending along a second direction are defined in the mask, and performing an etching back process on the conductive material layer by using the mask to form conductive lines corresponding to the lines; the part of the conducting wire surrounding the outer side wall of the active column body forms the grid tube, and the part of the conducting wire connected with the adjacent grid tube forms a connecting wire part of the word line.
Optionally, after performing the etching back process on the conductive material layer, the method further includes:
forming a dielectric material layer on the substrate, wherein the dielectric material layer fills gaps between adjacent gate tubes and covers the conductive material layer on the top surface of the active pillars 300;
performing a planarization process on the dielectric material layer to remove a portion of the dielectric material layer covering the top surface of the active pillars until the conductive material layer is exposed; the method comprises the steps of,
a planarization process is continued on the dielectric material layer and the conductive material layer to remove the conductive material layer at the top surface of the active pillars (300) until the top surface of the active pillars 300 is exposed.
Optionally, after exposing the top end portion of the active pillar, the method further includes:
an ion implantation process is performed to form a second doped region in the top end portion of the active column.
Optionally, the projection image of the extending direction of the word line on the substrate intersects the bit line and has an included angle, and the included angle is between 50 ° and 70 °.
Optionally, the word lines and the bit lines spatially intersect and have a plurality of overlapping areas, one overlapping area corresponds to one active column, and six active columns of the active columns, which are equidistantly adjacent to the same active column, are arranged in a hexagonal array.
Based on the integrated circuit memory as described above, the present invention also provides a semiconductor device comprising:
a substrate;
a plurality of first conductive lines formed on the substrate and extending along a first direction;
a plurality of active pillars formed on the first conductive lines such that bottom ends of the active pillars are connected to the first conductive lines; the method comprises the steps of,
and a plurality of second conductive lines formed on the substrate and extending along a second direction, the second conductive lines surrounding sidewalls of the corresponding active pillars in an extending direction thereof to extend and connect the plurality of corresponding active pillars.
In the integrated circuit memory provided by the invention, the active column vertically arranged on the substrate is adopted to form the active region of the vertical memory transistor, the bottom end part of the active column can be led out from the bottom of the active column by utilizing the bit line positioned below the active column, and the vertical memory transistor (namely, the source region, the channel region and the drain region are vertically arranged along the height direction) with a vertical structure can be formed by combining the grid tube surrounding the outer side wall of the active column. Vertical memory transistor of vertical structure having a larger cell layout size on a substrate Small (e.g. cell configuration size can reach 4F 2 ) The size of the integrated circuit memory can thus be correspondingly further reduced. In addition, the active area is formed by adopting the active column, so that the risk of short channel effect of the memory transistor can be further reduced, and the problem that the transistor with a horizontal structure is easy to generate short channel effect due to the reduction of the size of the transistor is avoided. Meanwhile, the storage transistors with the vertical structures have better arrangement flexibility, so that dense arrangement of a plurality of vertical storage transistors is facilitated. For example, the vertical memory transistors may be arranged in a hexagonal dense manner, and the memory cells in the integrated circuit memory may be arranged in a hexagonal dense manner.
Drawings
FIG. 1 is a schematic diagram of an integrated circuit memory;
FIG. 2a is a top view of an integrated circuit memory according to a first embodiment of the invention;
FIG. 2b is a schematic diagram of an integrated circuit memory with memory elements omitted;
FIG. 3a is a schematic cross-sectional view of the integrated circuit memory along aa' in the first embodiment of the present invention shown in FIG. 2 a;
FIG. 3b is a schematic cross-sectional view of the integrated circuit memory along the bb' direction of FIG. 2a according to one embodiment of the present invention;
FIG. 3c is a partial enlarged view of two adjacent vertical memory transistors of the integrated circuit memory according to the first embodiment of the present invention;
FIG. 4 is a flow chart illustrating a method for forming an integrated circuit memory according to a second embodiment of the invention;
fig. 5a is a top view of a forming method of an integrated circuit memory in a second embodiment of the invention when the forming method performs step S100;
FIG. 5b is a schematic cross-sectional view illustrating a method for forming an integrated circuit memory according to a second embodiment of the invention when the method is performed in step S100;
fig. 6a is a top view of a forming method of an integrated circuit memory in a second embodiment of the invention when the forming method performs step S200;
fig. 6b to 6d are schematic cross-sectional views of the forming method of the integrated circuit memory in the second embodiment of the invention when executing the step S200;
fig. 7a is a top view of a forming method of an integrated circuit memory in a second embodiment of the invention when the forming method performs step S201;
fig. 7b is a schematic cross-sectional view illustrating a method for forming an integrated circuit memory according to a second embodiment of the invention when the method is executed in step S201;
fig. 8a to 9a are plan views illustrating a method for forming an integrated circuit memory according to a second embodiment of the invention when the method performs step S300;
fig. 8b to 8c and fig. 9b are schematic cross-sectional views of the forming method of the integrated circuit memory in the second embodiment of the invention when the forming method is executed in step S300.
Wherein, the reference numerals are as follows:
10-active region; 20-word lines;
30-bit lines;
100-a substrate; 200-bit lines;
300-active pillars;
300D-a first doped region; 300S-a second doped region;
301-bottom end; 302-a tip portion;
300M-sacrificial layer;
400-word lines; 400 a-a layer of conductive material;
410-a gate work function layer; 410 a-a work function material layer;
420-a gate conductive layer; 420 a-a layer of conductive material;
400G-gate tube; 400L-connecting line part;
400M-mask; 400E-etchant;
500-gate dielectric layer; 600-insulating dielectric layers;
700-a spacer dielectric layer; 800-isolating layer;
900-node contact layer;
h-through holes;
theta-angle;
a U-memory unit;
a C-memory element;
a T-vertical memory transistor;
the width dimension of the D1-memory transistor in the direction perpendicular to the bit line;
the width dimension of the D2-memory transistor in the direction perpendicular to the word line.
Detailed Description
As described in the background art, in the conventional memory (for example, in the DRAM), the memory transistors are in a horizontal structure, so that the reduction of the size of the memory transistors is limited, and the arrangement density of the memory transistors cannot be further improved.
FIG. 1 is a schematic diagram of a memory, as shown in FIG. 1, comprising:
A substrate, in which a plurality of active regions 10 are defined, the active regions 10 having a first doped region and two second doped regions located at two sides of the first doped region;
a plurality of word lines 20 formed on the substrate and intersecting the respective active regions 10, portions of the word lines 20 intersecting the active regions 10 being used to form gate transistors of the memory transistors;
a plurality of bit lines 30 formed on the substrate and electrically connected with the first doped regions of the corresponding active regions 10 to induce the first doped regions; the method comprises the steps of,
it can be seen that in the conventional memory, the active region 10 of the memory transistor is formed by horizontal diffusion, i.e., the first doped region and the second doped region are horizontally distributed in a direction parallel to the substrate surface, so as to form a memory transistor with a horizontal structure.
For the memory transistor shown in fig. 1, when the size of the memory transistor is reduced, that is, the size of the active region 10 is correspondingly reduced, the risk of short channel effect is increased. Furthermore, even though the short channel effect of the memory transistor is not considered, the size of the memory transistor cannot be further reduced under the limitation of the resolution of the lithographic apparatus.
Referring specifically to FIG. 1, a memory transistor is shown in the vertical directionA width dimension D2 in a direction perpendicular to the word line 20 is 3F; and, the width dimension D1 of one memory transistor in the direction perpendicular to the bit line 30 is 2F, so that the area of one memory transistor on the substrate to be configured for it is 6F 2 (3F x 2F), where F is the minimum feature size. That is, based on the resolution of the existing lithographic apparatus, the cell configuration size of the memory transistor can only reach 6F 2 And cannot continue the downscaling.
It should be noted that, the "minimum feature size F" described herein is: based on the resolution of the current lithographic apparatus, a minimum limit linewidth dimension and a minimum limit linewidth dimension can be obtained. Wherein the minimum limit line width dimension and the minimum limit line spacing dimension are equal.
In addition, in the memory shown in fig. 1, a contact window is additionally formed above the active region thereof, so as to expose the second doped region of the active region 10 by using the contact window. In this way, in a subsequent process, a memory element (e.g., a storage capacitor) can be formed on the substrate, the memory element being electrically connected to the second doped region of the active region through the contact window. Therefore, when the second doped region is led out to be electrically connected with a memory element formed later, an additional contact window needs to be prepared, so that the preparation process is more complicated.
To this end, the present invention provides an integrated circuit memory in which an active pillar vertically disposed on a substrate is used instead of a conventional horizontally diffused active region, and a bit line is disposed under the active pillar, thereby realizing that a bottom end portion of the active pillar is connected to the bit line; and the storage element can be electrically connected with the top end part of the active column body, so that a storage unit with a vertical structure is further formed.
That is, the integrated circuit memory provided by the invention not only can further reduce the cell configuration size of the memory transistor, but also can effectively reduce the risk of short channel effect of the memory transistor after reduction; and the storage transistor with the vertical structure also has the characteristic of more flexible arrangement.
The integrated circuit memory, the method of forming the same, and the semiconductor device according to the present invention are described in further detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
Fig. 2a is a top view of an integrated circuit memory according to a first embodiment of the present invention, fig. 2b is a schematic diagram of a structure of the integrated circuit memory according to the first embodiment of the present invention with its memory element omitted, fig. 3a is a schematic diagram of a cross section of the integrated circuit memory according to the first embodiment of the present invention along aa 'direction shown in fig. 2a, fig. 3b is a schematic diagram of a cross section of the integrated circuit memory according to the first embodiment of the present invention along bb' direction shown in fig. 2a, and fig. 3c is a partial enlarged view of two adjacent vertical memory transistors of the integrated circuit memory according to the first embodiment of the present invention.
As shown in fig. 2a to 2b and fig. 3a to 3b, the integrated circuit memory includes a substrate 100, a plurality of bit lines 200, a plurality of active pillars 300, and a plurality of word lines 400, wherein the word lines 400 are connected with gate transistors 400G in an extending direction thereof. The active pillars 300 and the gate transistors 400G together form a vertical memory transistor T of an integrated circuit memory.
The substrate 100 may be, for example, a Silicon substrate or a Silicon On Insulator (SOI).
A plurality of the bit lines 200 are formed on the substrate 100 and extend along a first direction. The bit line 200 may have a stacked structure, for example, the bit line 200 includes a bit line isolation layer (not shown), a bit line conductive layer (not shown), a bit line work function layer (not shown), and a bit line contact layer (not shown) stacked on the substrate 100 in this order. Specifically, the material of the bit line isolation layer includes, for example, silicon nitride (SiN), the material of the bit line conductive layer includes, for example, tungsten (W), the material of the bit line work function layer includes, for example, titanium nitride (TiN), and the material of the bit line contact layer includes, for example, doped polysilicon (Poly).
It should be noted that, the conductivity type of the doped polysilicon layer of the bit line contact layer may be adjusted according to the conductivity type of the vertical memory transistor T, for example, the conductivity type of the vertical memory transistor T is N-type, and the doped polysilicon layer in the bit line contact layer may be N-type doped accordingly.
With continued reference to fig. 3a and 3b, a plurality of active pillars 300 are formed on the bit lines 200 such that bottom ends 301 of the active pillars 300 are connected to the bit lines 200. The active pillars 300 are, for example, cylindrical. In this embodiment, the bottom 301 of the active pillar 300 is connected to the bit line contact layer of the bit line 200, and the bit line contact layer may be a film doped with conductive ions, so that the contact resistance between the bit line 200 and the active pillar 300 can be effectively reduced, thereby being beneficial to reducing the leakage current phenomenon of the device.
Referring specifically to fig. 3c, the active pillars 300 may be used to form conductive channels of the vertical memory transistor T, and thus the active pillars 300 may be formed using channel materials, for example, the material of the active pillars 300 may include one or a combination of indium gallium arsenide (InGaAs) and gallium arsenide (GaAs). In addition, both end portions of the active pillar 300 are also used to form source and drain regions of the vertical memory transistor T, and thus a first doped region 300D may be further formed in the bottom end portion 301 of the active pillar 300, and a second doped region 300S may be further formed in the top end portion 302 of the active pillar 300, and the first doped region 300D and the second doped region 300S may respectively constitute the drain and source regions of the vertical memory transistor T. The first doped region 300D and the second doped region 300S of the corresponding conductivity type may be disposed according to the conductivity type of the vertical memory transistor T.
In this embodiment, the vertical memory transistor T is an N-type transistor, and the first doped region 300D and the second doped region 300D may be doped regions implanted with arsenic (As) ions or phosphorus (P) ions, respectively.
A plurality of word lines 400 are formed on the substrate 100 and extend along the second direction. In this embodiment, the word line 400 extends obliquely with respect to the bit line 200, so that the extending direction of the word line 400 forms an angle θ between the projected image on the substrate and the bit line 200, for example, 50 ° to 70 °. In this way, a dense arrangement of memory cells in the integrated circuit memory is achieved.
As further shown in fig. 3a, 3b and 3c, the word line 400 is connected with a gate tube 400G in the extending direction thereof, and the gate tube 400G surrounds the outer sidewall of the corresponding active pillars 300, so that the word line 400 is extended to connect a plurality of the corresponding active pillars 300. Wherein, for the word line 400 and the gate tube 400G, one is understood as: the word line 400 is connected to a plurality of the gate transistors 400G on the same extension line; the other can also be understood as: the portion of the word line 400 surrounding the active pillar 300 constitutes the gate tube 400G.
Further, the word line 400 includes a plurality of connection line parts 400L connecting the gate transistors 400G, and the connection line parts 400L are regularly and linearly connected to the gate transistors 400G on the adjacent active pillars 300. In an alternative, the top surface of the connection line portion 400L may be further lower than the top surface of the gate tube 400G, and at this time, the gate tube 400G and the connection line portion 400L may define a gap between adjacent active pillars 300. Therefore, in this embodiment, the angle θ formed when the projection image on the substrate and the bit line 200 intersect in the extending direction of the connecting line portion 400L of the word line 400 is, for example, 50 ° to 70 °.
The word line 400 is also a stacked structure, and includes a gate work function layer 410 and a gate conductive layer 420 stacked in sequence. The material of the gate work function layer 410 includes, for example, one of titanium (Ti) or titanium nitride (TiN) or a combination thereof, and the material of the gate conductive layer 420 includes, for example, one of polysilicon (Poly) and tungsten (W) or a combination thereof.
In addition, the integrated circuit memory further includes a gate dielectric layer 500, the gate dielectric layer 500 being formed on the substrate 100 and covering sidewalls of the active pillars 300, and the word line 400 being formed on the gate dielectric layer 500 such that the gate tube 400G is spaced apart from the gate dielectric layer 500 to cover sidewalls of the active pillars 300. The material of the gate dielectric layer 410 includes, for example, silicon oxide (SiO).
With continued reference to fig. 3a, 3b and 3c, the top end 302 of the active pillar 300 is exposed to the gate tube 400G. Specifically, the bottom end 301 and the top end 302 of the active pillar 300 may be used to form a drain region (first doped region 300D) and a source region (second doped region 300S), respectively, wherein the drain region of the active pillar 300 is connected to the bit line 200 and the source region is exposed from the gate tube 400G for connection to a memory element C (e.g., a storage capacitor, etc.).
The source region, the channel region and the drain region of the memory transistor T are formed by adopting the active layer with a columnar structure, and the source region and the drain region of the memory transistor T are vertically distributed along the height direction, so that the memory transistor T with a vertical structure is formed. Compared with a conventional memory transistor of a horizontal structure in which the source region and the drain region are horizontally distributed in a direction perpendicular to the height direction, the memory transistor of a vertical structure occupies a smaller area on the substrate 100, which is advantageous in achieving a reduction in the size of the memory transistor T. In addition, the vertical memory transistor can effectively utilize the space region above the substrate 100, for example, the channel length of the memory transistor T can be adjusted by changing the height of the active pillars 300, so as to reduce the risk of short channel effect of the memory transistor T.
Specifically, in the integrated circuit memory of the present embodiment, the cell configuration size of one vertical memory transistor T on the substrate 100 can be 4 times (2f=4f) the square of the minimum feature size 2 Where F is the minimum feature size). It should be noted that "cell configuration size" as referred to herein means: the cell configuration size for which a memory cell needs to be configured on a substrate specifically includes: the size that one memory cell actually needs to occupy on a substrate, and the size of the space that needs to be reserved between that memory cell and an adjacent memory cell. For example, the size occupied by N memory transistors on the substrateM, then the cell configuration size of one memory transistor on the substrate 100 is N/M.
Referring to fig. 2b with emphasis, for the vertical memory transistor T based on the vertical structure, a plurality of word lines 400 and a plurality of bit lines 200 spatially intersect and have a plurality of overlapping regions, wherein one overlapping region corresponds to one vertical memory transistor T (corresponding to one active pillar 300). According to the conventional manufacturing process, the bit line 200 and the word line 400 with the minimum feature size F can be formed, and the line spacing between the adjacent bit line and the adjacent word line is also equal to or greater than the minimum feature size F, so that the width dimension D1 of one vertical memory transistor T in the direction perpendicular to the bit line is 2F, and the width dimension D2 in the direction perpendicular to the word line is 2F, so that the cell configuration size of the vertical memory transistor T can be correspondingly made to reach 4F 2 (2 f x 2 f). That is, the cell layout size of the vertical memory transistor T is 4 times or more the square of the minimum feature size.
In addition, as the vertical storage transistors T adopt a vertical structure, the arrangement mode of the plurality of vertical storage transistors T is more flexible, and the realization of denser arrangement of the vertical storage transistor array is facilitated. For example, the vertical memory transistor array may be arranged in a hexagonal array (correspondingly, the plurality of active pillars 300 are also arranged in a hexagonal array). Specifically, the hexagonal arrangement manner of the memory transistor array is, for example: six vertical memory transistors of the plurality of vertical memory transistors, which are equidistantly adjacent to the same vertical memory transistor, are arranged in a hexagonal array. Correspondingly, six active columns of the active columns which are equidistantly adjacent to the same active column can be arranged in a hexagonal array.
With continued reference to fig. 3a and 3b, the integrated circuit memory further includes: a plurality of memory elements C formed above the vertical memory transistors T and electrically connected to the top end 302 of the active pillars 300. It will be appreciated that one of the vertical memory transistors T and one of the memory elements C constitute one memory cell U of the integrated circuit memory. As described above, since the second doped region 300S of the active pillar 300 is directly exposed from the gate tube 400G, the second doped region 300S can be electrically connected to the memory device C without passing through a contact window.
Wherein the storage element C comprises, for example, a storage capacitor. The storage capacitor may be formed using a semiconductor process. The storage capacitor further includes a lower electrode plate (not shown), which is electrically connected to the top end 302 of the active column 300, a capacitive medium layer (not shown), and an upper electrode plate (not shown), which are sequentially formed on the lower electrode plate. Preferably, the storage capacitor is a double-sided capacitor, that is, the capacitor dielectric layer and the upper electrode plate are sequentially formed on two opposite surfaces of the lower electrode plate, so that two capacitors can be formed on two sides of the lower electrode plate by using one lower electrode plate, thereby being beneficial to improving the capacitance value of the storage capacitor. Alternatively, the capacitor dielectric layer may be formed of a high K dielectric material, such as aluminum oxide (Al 2 O 3 ) Or zirconia (ZrO), etc.
It can be seen that the memory element C is also formed above the memory transistor T by fully utilizing a space region above the memory transistor T, and the memory element C and the memory transistor T can be in a one-to-one correspondence (for example, a position of the memory element C corresponds to a position of the memory transistor T), so that the memory cell U formed by the vertical memory transistor T and the memory element C is also in a vertical structure (or an up-down structure). It is thus considered that the cell arrangement size of one memory cell U on the substrate 100 depends on the cell arrangement size of one vertical memory transistor T on the substrate 100, and accordingly, when the size of the vertical memory transistor T on the substrate 100 is reduced, it is advantageous to achieve the reduction of the cell arrangement size of the entire memory cell U.
Therefore, in the present embodiment, the cell configuration size of the vertical memory transistor T on the substrate can reach 4F 2 The cell layout size of the memory cell U on the substrate can also reach 4F 2 The method comprises the steps of carrying out a first treatment on the surface of the And, when the plurality of vertical memory transistors T are arranged in a hexagonal dense manner,the memory units U are correspondingly arranged in a hexagonal dense manner. The memory cells of the vertical structure in this embodiment can be arranged with extremely high density, and are particularly suitable for miniaturized, densely arranged and high-speed operation memory integrated circuit memories. In particular, for the dynamic random access integrated circuit memory (Dynamic Random Access Memory, DRAM), since the DRAM integrated circuit memory has a simple structure (i.e., one memory cell usually requires only one storage capacitor and one storage transistor), the memory cell adopting the above structure is more remarkable in size reduction and increased arrangement density for the DRAM integrated circuit memory.
Referring next to fig. 3 a-3 c, the integrated circuit memory further includes an insulating dielectric layer 600 formed on the substrate 100, the insulating dielectric layer 600 filling gaps between adjacent bit lines 200 and covering the bit lines 200. That is, the adjacent bit lines 200 are isolated by the insulating dielectric layer 600, and the bit lines 200 and the word lines 400 are isolated from each other, thereby improving parasitic capacitance between the bit lines 200 and the word lines 400.
In this embodiment, the top surface of the insulating dielectric layer 600 is higher than the top surface of the bit line 200, so that the insulating dielectric layer 600 can cover the bit line 200. At this time, the insulating dielectric layer 600 can also surround a portion of the bottom end 301 of the active pillars 300. The insulating dielectric layer 600 can have a direct or indirect effect on the bottom position of the formed word line 400 due to its presence. Based on this, in this embodiment, the top surface of the insulating dielectric layer 600 is further made lower than the top boundary of the first doped region 300D of the active pillar 300, on the basis that the top surface of the insulating dielectric layer 600 is made higher than the top surface of the bit line 200. In this way, the bottom of the word line 400 is lower than the top boundary of the first doped region 300D, so as to ensure that the gate transistor 400G can at least partially cover the first doped region 300D, so as to ensure the performance of the vertical memory transistor T.
Similarly, the top surface of the gate tube 400G is higher than the bottom boundary of the second doped region 300S of the active pillar 300, and the gate tube 400G can at least partially cover the second doped region 300S, so that current conduction between the first doped region 300D and the second doped region 300S can be controlled by using the gate tube 400G. Further, the top surface of the gate tube 400G may be further lower than the top surface of the active pillar 300, that is, the gate tube 400G does not completely cover the second doped region 300S extending to the sidewall of the active pillar, but partially covers the second doped region 300S, so that the leakage current phenomenon of the vertical memory transistor can be effectively improved.
With continued reference to fig. 3 a-3 c, the integrated circuit memory further includes: a spacer dielectric layer 700. The spacer dielectric layer 700 is formed on the substrate 100 and fills the gap between adjacent gate tubes 400G. In addition, in the present embodiment, a gap is defined between adjacent active pillars 300 corresponding to the gate tube 400G and the connection line portion 400L on the same word line 400, so that the spacer medium layer 700 further fills the gap defined by the gate tube 400G and the connection line portion 400L (i.e., the spacer medium layer 700 covers the connection line portion 400L and extends to cover the sidewall of the gate tube 400G). It will be appreciated that the spacing dielectric layer 700 is used to fill the gaps between adjacent vertical memory transistors T to separate the adjacent vertical memory transistors T from each other. The material of the spacer dielectric layer 700 includes silicon oxide (SiO), for example.
Alternatively, the top surface of the spacer dielectric layer 700 is not higher than the top surface of the active pillars 300, and in this embodiment, the top surface of the spacer dielectric layer 700 is flush with the top surface of the active pillars 300.
Further, an isolation layer 800 is further disposed between the vertical memory transistor T and the memory element C, so that the isolation layer 800 is used to isolate the portion between the vertical memory transistor T and the memory element C, which is not required to be connected. In this embodiment, the isolation layer 800 covers the spacer dielectric layer 700 and covers the gate tube 400G and a portion of the top end 302 of the active pillar 300. The material of the isolation layer 800 includes, for example, silicon nitride (SiN).
In addition, in the present embodiment, a node contact layer 900 is further formed on the top end portion 302 of the active pillar 300, and the node contact layer 900 penetrates the isolation layer 800 to be connected to the second doped region 300S of the active pillar 300 and is used for connection to the memory element C. That is, the second doped region 300S of the active pillar 300 is connected to the memory element C through the node contact layer 900, and thus, it is advantageous to reduce the contact resistance between the memory element C and the active pillar 300, so as to further improve the performance of the entire integrated circuit memory. The material of the node contact layer 900 includes tungsten (W), for example.
Example two
Fig. 4 is a flow chart of a forming method of an integrated circuit memory according to a second embodiment of the present invention, and referring to fig. 4, the forming method of the integrated circuit memory in this embodiment includes:
step S100, providing a substrate, and forming a plurality of bit lines on the substrate, wherein the bit lines extend along a first direction;
step S200, forming a plurality of active pillars on the bit lines, wherein the bottom ends of the active pillars are connected to the bit lines;
and step S300, forming a plurality of word lines on the substrate, wherein the word lines extend along a second direction, the word lines are connected with gate tubes in the extending direction, the gate tubes encircle the outer side walls of the corresponding active columns, and the active columns and the gate tubes jointly form the vertical storage transistor of the integrated circuit memory.
Based on the forming method of the integrated circuit memory, namely, the vertical memory transistor with a vertical structure can be formed. The vertical memory transistor with vertical structure is beneficial to the reduction of the size of single vertical memory transistor, for example, the unit configuration size of the formed vertical memory transistor on the substrate is larger than or equal to 4 times of the square of the minimum feature size (4F 2 ) Thereby effectively reducing the size of the whole integrated circuit memory; on the other hand, the arrangement flexibility of a plurality of vertical memory transistors is improved, so that the vertical memory transistors can be liftedThe arrangement density of the memory cells in the high-integrated circuit memory can be realized, for example, in a hexagonal arrangement mode of a plurality of vertical memory transistors.
The steps of the forming method in this embodiment will be described in detail below with reference to the drawings.
Fig. 5a is a top view of the forming method of the integrated circuit memory in the second embodiment of the invention when the forming method of the integrated circuit memory in the second embodiment of the invention is executed in step S100, and fig. 5b is a schematic cross-sectional view of the forming method of the integrated circuit memory in the second embodiment of the invention when the forming method of the integrated circuit memory in the second embodiment of the invention is executed in step S100.
In step S100, referring specifically to fig. 5a and 5b, a substrate 100 is provided, and a plurality of bit lines 200 are formed on the substrate 100, the bit lines 200 extending along a first direction.
In one embodiment, the bit line 200 may have a stacked structure including a bit line isolation layer, a bit line conductive layer, and a bit line contact layer sequentially formed on the substrate 100. The bit line contact layer is used for being connected with the bottom end of an active column formed later.
Fig. 6a is a top view of the forming method of the integrated circuit memory in the second embodiment of the present invention when the forming method of the integrated circuit memory in the second embodiment of the present invention is executed in step S200, and fig. 6b to 6d are schematic cross-sectional views of the forming method of the integrated circuit memory in the second embodiment of the present invention when the forming method of the integrated circuit memory in the second embodiment of the present invention is executed in step S200.
In step S200, referring specifically to fig. 6a and 6d, a plurality of active pillars 300 are formed on the bit lines 200, and bottom ends 301 of the active pillars 300 are connected to the bit lines 200.
The active pillars 300 are used to form a source region, a channel region and a drain region of a vertical memory transistor, and the formed source region, channel region and drain region can be vertically arranged along a height direction, so as to form a memory transistor with a vertical structure, so that an arrangement manner of the active pillars 300 directly affects an arrangement manner of an entire memory cell formed subsequently.
In this embodiment, the plurality of active pillars 300 are arranged in a hexagonal manner, that is, six active pillars of the same active pillar 300 that are equidistant from each other are arranged in a hexagonal array. Therefore, the vertical memory transistors (memory cells) formed later can be arranged in a hexagonal mode, so that the arrangement density of the memory cells is improved.
Referring further to fig. 6b to 6d, the method for forming the active pillars 300 includes:
referring to fig. 6b, a sacrificial layer 300M is formed on the substrate 100, wherein a plurality of through holes H are formed in the sacrificial layer 300M, and the through holes H expose the bit lines 200;
next, as shown with reference to fig. 6c and 6d, an active material is filled in the through hole H to form the active column 300, and the sacrificial layer 300M is removed.
Further, since the active pillars 300 are used to form the source, channel and drain regions of the vertical memory transistor, the via H may be filled with an active material doped with conductive ions, accordingly. Specifically, when filling the bottom of the via H, an in-situ doping process may be used, for example, to form the first doped region 300D in the bottom end 301 of the active pillar 300.
In a preferred embodiment, after forming the active pillars 300, the method further includes step S201: an insulating dielectric layer is formed on the substrate 100.
Fig. 7a is a top view of the forming method of the integrated circuit memory in the second embodiment of the invention when the forming method of the integrated circuit memory in the second embodiment of the invention is executed in step S201, and fig. 7b is a schematic cross-sectional view of the forming method of the integrated circuit memory in the second embodiment of the invention when the forming method of the integrated circuit memory in the second embodiment of the invention is executed in step S201.
In step S201, referring specifically to fig. 7a and 7b, an insulating dielectric layer 600 is formed on the substrate 100, and the insulating dielectric layer 600 fills the gaps between adjacent bit lines 200 and covers the bit lines 200.
The bit line 200 is isolated from subsequently formed word lines by forming the insulating dielectric layer 600. In addition, the parasitic capacitance between the bit line 200 and the subsequently formed word line can be further improved by adjusting the thickness of the insulating dielectric layer 600. As shown in fig. 7b, the top surface of the insulating dielectric layer 600 is higher than the top surface of the bit line 200 and lower than the bottom boundary of the first doped region 300S of the active pillar 300.
Fig. 8a to fig. 9a are plan views of the forming method of the integrated circuit memory in the second embodiment of the present invention when the forming method of the integrated circuit memory in the second embodiment of the present invention is executed in step S300, and fig. 8b to fig. 8c and fig. 9b are schematic cross-sectional views of the forming method of the integrated circuit memory in the second embodiment of the present invention when the forming method of the integrated circuit memory in the second embodiment of the present invention is executed in step S300.
In step S300, referring specifically to fig. 8a to 8c and fig. 9a to 9b, a plurality of word lines 400 are formed on the substrate 100, the word lines 400 extend along the second direction, the word lines 400 are connected with gate tubes 400G in the extending direction thereof, and the gate tubes 400G surround the sidewalls of the corresponding active pillars 300. And the active pillars 300 and the gate transistors 400G together form vertical memory transistors of the integrated circuit memory. Further, the top surface of the active pillar 300 is exposed to the gate tube 400G.
Wherein the word line 400 and the gate tube 400G may be formed in the same process step, it may be considered that a portion of the word line 400 surrounding the sidewall of the active pillar 300 is used to form the gate tube 400G. Alternatively, the gate transistors 400G and the word lines 400 may be formed in two process steps, respectively, in which case the word lines 400 are used to interconnect the plurality of gate transistors 400G on the same extension line. In this embodiment, the word lines 400 and the bit lines 200 spatially intersect to have a plurality of overlapping regions, and one overlapping region corresponds to one of the active pillars 300, and corresponds to one of the vertical memory transistors.
Further, before forming the word line 400, it further includes: a gate dielectric layer 500 is formed on the substrate 100, and the gate dielectric layer 500 can be conformally formed on the active pillars 300 and cover portions of the insulating dielectric layer 600 corresponding between adjacent active pillars 300.
In an alternative embodiment, the method for forming the word line 400 and the gate tube 400G may include the following steps.
In a first step, referring specifically to fig. 8a and 8b, a conductive material layer 400a is formed on the substrate 100, wherein the conductive material layer 400a covers the top surface and the sidewalls of the active pillars 300 and covers the surface of the film between adjacent active pillars 300. In this embodiment, the conductive material layer 400a is formed on the gate dielectric layer 500. Wherein the conductive material layer 400a sequentially includes a work function material layer 410a and a conductive material layer 420a.
And a second step, as shown in fig. 8a to 8c, of combining a mask 400M and performing an etching back process, wherein a plurality of lines extending along the second direction are defined in the mask 400M, and the conductive material layer 400a is etched back through the mask 400M to form a plurality of conductive lines corresponding to the lines.
As shown in fig. 8a, in this embodiment, the extending direction of the line in the mask 400M corresponds to the extending direction of the word line 400. Therefore, when the back etching process is performed on the conductive material layer 400a using the reticle 400M, the etchant 400E can remove portions of the conductive material layer 400a not corresponding to the lines (e.g., portions of the conductive material layer 400a corresponding to between adjacent lines) and leave the conductive material layer corresponding to the lines to form conductive lines and serve to constitute the word lines 400 and the gate transistors 400G. At this time, a portion of the conductive line surrounding the outer sidewall of the active pillar 300 constitutes the gate tube 400G, and a portion of the conductive line connecting adjacent gate tubes constitutes a connection line portion of the word line 400.
It should be noted that, in this embodiment, even if the line of the mask 400M does not completely cover the conductive material layer on the active pillar 300 (including the conductive material layer on the sidewall of the active pillar), since the etching process is an etching back process, the conductive material layer formed on the gate dielectric layer 500 can be removed after the etching process, and the conductive material layer formed on the sidewall of the active pillar 300 cannot be completely removed.
In addition, after performing the etching back process on the conductive material layer, the method further includes: removing a portion of the conductive line covering the top surface of the active pillars 300; and, the top end portion of the active column 300 may be further exposed. Wherein the removal of the portion of the conductive line covering the top surface of the active pillars 300 may be performed simultaneously in conjunction with a subsequent isolation process.
Referring specifically to fig. 9a and 9b, in a subsequent process, the method may further include: filling the gap between adjacent active pillars 300 with a spacer dielectric layer 700. In this embodiment, the spacer dielectric layer 700 fills the gaps between adjacent word lines 400. In addition, the gate tube 400G and the connection line portion corresponding to the same word line 400 define a gap between the adjacent active pillars 300, so that the spacer dielectric layer 700 further fills the gap defined by the gate tube 400G and the connection line portion.
Wherein, the spacer dielectric layer 700 may be formed by using a planarization process, specifically:
first, a dielectric material layer is formed on the substrate 100, the dielectric material layer fills the gaps between the adjacent gate tubes 400G and covers the conductive material layer on the top surface of the active pillars 300;
then, a planarization process is performed on the dielectric material layer to remove a portion of the dielectric material layer covering the top surface of the active pillars 300 until the conductive material layer covering the top surface of the active pillars 300 is exposed;
and then, a planarization process is continuously performed on the dielectric material layer and the conductive material layer to remove the conductive material layer and remove the dielectric material layer at the corresponding height position until the top surface of the active pillars 300 is exposed. In this embodiment, after removing the conductive material layer on the top surface of the active pillars 300, the portion of the gate dielectric layer 500 on the top surface of the active pillars 300 is further removed, thereby exposing the top surface of the active pillars 300.
Thus, the spacer dielectric layer 700 may be formed by a planarization process, and the conductive material on the top of the active pillars 300 may be further removed, and the top ends of the active pillars 300 may be exposed. And, the top surface of the spacer dielectric layer 700 may be made flush with the top surface of the active pillars 300, thereby facilitating the formation of subsequent memory elements.
Further, after exposing the top surface of the active pillars 300, it further includes: an ion implantation process is performed to form a second doped region 300S in the top end portion of the active column 300.
In a preferred embodiment, after the conductive material layer on the top surface of the active pillar 300 is removed (i.e., after the active pillar 300 is exposed in this embodiment), the gate tube 400G may be further etched, and the exposed gate tube is etched to reduce the height of the gate tube, so that the portion of the second doped region 300S diffused into the sidewall of the active pillar is not completely covered by the gate tube, which is beneficial to reducing the leakage current phenomenon of the vertical memory transistor formed. Meanwhile, the height of the gate tube can be correspondingly controlled, so that the top surface of the gate tube is higher than the bottom boundary of the second doped region 300S, and therefore a space overlapping region exists between the gate tube and the second doped region 300S, and the function of the vertical memory transistor is guaranteed. In addition, by continuing to etch the gate tube, the problem of shorting the gate tube to the top end 302 of the active pillars 300 due to the conductive material extending to the top surface of the active pillars 300 during the grinding of the conductive material layer can be avoided.
It is considered that the vertical memory transistor fabrication process is substantially completed so far. In a subsequent process, a memory element may be formed over the vertical memory transistor.
In a preferred embodiment, after removing the conductive material layer on the top surface of the active pillars 300 (i.e., after exposing the active pillars 300 in the present embodiment), the method may further include: an isolation layer is formed on the substrate 100, the isolation layer covering the spacer dielectric layer 700 and covering the gate tube 400G and a portion of the top end portion of the active pillars 300. That is, the gate tube is prevented from being exposed by the isolation layer, so that the gate tube can be prevented from being electrically connected with a memory element formed later.
Further, a node contact layer may be formed on the top end 302 of the active pillar 300, and the node contact layer is embedded in the isolation layer to be connected to the second doped region 300S of the active pillar 300 and is used for electrically connecting to a memory element formed later.
Thus, step S400 may be performed to form a memory device above the vertical memory transistor, where the memory device is electrically connected to the top end 302 of the active pillar 300. Wherein the storage element is, for example, a storage capacitor, and the storage capacitor can be prepared using a semiconductor process.
In addition, there are various semiconductor devices in the semiconductor field, and there is also a need to draw out an active region in the various semiconductor devices. The active area to be led out can also be replaced by the active column provided by the invention, so that the active area in the semiconductor device can be vertically arranged and led out.
Specifically, the present invention also provides a semiconductor device, including:
a substrate;
a plurality of first conductive lines formed on the substrate and extending along a first direction;
a plurality of active pillars formed on the first conductive lines such that bottom ends of the active pillars are connected to the first conductive lines; the method comprises the steps of,
and a plurality of second conductive lines formed on the substrate and extending along a second direction, the second conductive lines surrounding sidewalls of the corresponding active pillars in an extending direction thereof to extend and connect the plurality of corresponding active pillars.
That is, in the semiconductor device, the bottom end portion of the active column may be drawn out from below with the first conductive line located therebelow; the top end of the active column can be used for connecting with other elements; and, a portion of the second conductive line surrounds a sidewall of the active pillar, so that in one embodiment, a portion of the active pillar near the middle may be routed using the second conductive line; alternatively, in another embodiment, a control signal may be delivered through the second conductive line to control the conduction of current between the two ends of the active column.
In summary, in the integrated circuit memory provided by the present invention, the active pillars vertically disposed on the substrate are adopted, so that the vertical memory transistor with a vertical structure can be formed, which is not only beneficial to the reduction of the cell configuration size of the memory transistor (for example, 4F or more) 2 ) And also further improves the arrangement density (e.g., hexagonal dense arrangement) of vertical memory transistors. Thus, the size of the integrated circuit memory can be correspondingly reduced.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.

Claims (22)

1. A method of forming an integrated circuit memory, comprising:
providing a substrate, and forming a plurality of bit lines on the substrate, wherein the bit lines extend along a first direction;
Forming a plurality of active pillars on the bit lines, bottom ends of the active pillars being connected to the bit lines; the method for forming the active column comprises the following steps: forming a sacrificial layer on the substrate, wherein a plurality of through holes are formed in the sacrificial layer, and the through holes expose the bit lines; and filling an active material in the through hole to form the active column, and removing the sacrificial layer; the method comprises the steps of,
and forming a plurality of word lines on the substrate, wherein the word lines extend along a second direction, the word lines are connected with gate tubes in the extending direction, the gate tubes encircle the outer side walls of the corresponding active columns, and the active columns and the gate tubes jointly form the vertical storage transistor of the integrated circuit memory.
2. The method of forming an integrated circuit memory of claim 1, wherein a cell layout size of said vertical memory transistor on said substrate is 4 times or more square of a minimum feature size.
3. The method of forming an integrated circuit memory of claim 1, further comprising, after forming the word line:
and forming a storage element above the vertical storage transistor, wherein the storage element is electrically connected with the top end part of the active column.
4. The method of forming an integrated circuit memory of claim 1, wherein the shape of the via comprises a cylindrical shape.
5. The method of forming an integrated circuit memory of claim 1, further comprising, after forming the active pillars, and before forming the word lines:
and forming an insulating dielectric layer on the substrate, wherein the insulating dielectric layer fills gaps between adjacent bit lines and covers the bit lines.
6. The method of forming an integrated circuit memory of claim 1, wherein the method of forming the word line and the gate tube comprises:
forming a conductive material layer on the substrate, wherein the conductive material layer covers the top surface and the side wall of the active column and covers the surface of the film layer between the adjacent active columns; the method comprises the steps of,
providing a mask, wherein a plurality of lines extending along a second direction are defined in the mask, and performing an etching back process on the conductive material layer by using the mask to form conductive lines corresponding to the lines; the part of the conducting wire surrounding the outer side wall of the active column body forms the grid tube, and the part of the conducting wire connected with the adjacent grid tube forms a connecting wire part of the word line.
7. The method of forming an integrated circuit memory of claim 6, further comprising, after performing an etch back process on the conductive material layer:
forming a dielectric material layer on the substrate, wherein the dielectric material layer fills gaps between adjacent gate tubes and covers the conductive material layer on the top surface of the active column;
performing a planarization process on the dielectric material layer to remove a portion of the dielectric material layer covering the top surface of the active pillars until the conductive material layer is exposed; the method comprises the steps of,
and continuously performing a planarization process on the dielectric material layer and the conductive material layer to remove the conductive material layer positioned on the top surface of the active column until the top surface of the active column is exposed.
8. The method of forming an integrated circuit memory of claim 7, further comprising, after exposing the top end of the active pillars:
an ion implantation process is performed to form a second doped region in a top portion of the active column.
9. The method of claim 1, wherein the projected image of the word line extending direction on the substrate intersects the bit line and has an included angle between 50 ° and 70 °.
10. The method of forming an integrated circuit memory as claimed in any one of claims 1 to 9, wherein a plurality of said word lines and a plurality of said bit lines spatially intersect and have a plurality of overlapping regions, one overlapping region corresponding to each of said active pillars, six active pillars of a plurality of said active pillars being equally spaced apart adjacent to one active pillar in a hexagonal array arrangement.
11. An integrated circuit memory formed by the method of forming of any one of claims 1-10, comprising:
a substrate;
a plurality of bit lines formed on the substrate and extending along a first direction;
a plurality of active pillars formed on the bit lines such that bottom ends of the active pillars are connected to the bit lines; the method comprises the steps of,
and the plurality of word lines are formed on the substrate and extend along the second direction, the word lines are connected with gate tubes in the extending direction, the gate tubes encircle the outer side walls of the corresponding active columns, the top ends of the active columns are exposed out of the gate tubes, and the active columns and the gate tubes jointly form the vertical storage transistor of the integrated circuit memory.
12. The integrated circuit memory of claim 11, wherein a cell layout size of the vertical memory transistor of the integrated circuit memory on the substrate is 4 times or more a square of a minimum feature size.
13. The integrated circuit memory of claim 11, wherein the integrated circuit memory further comprises: and a plurality of memory elements formed above the vertical memory transistors and electrically connected to the top ends of the active pillars.
14. The integrated circuit memory of claim 11, wherein a first doped region is formed in the bottom portion of the active pillar connected to the bit line, and a second doped region is formed in the top portion of the active pillar for connecting to a memory element, the first doped region and the second doped region forming a drain region and a source region of the vertical memory transistor, respectively.
15. The integrated circuit memory of claim 14, further comprising:
and the insulating dielectric layer is formed on the substrate, fills gaps between adjacent bit lines and covers the bit lines, and the word lines are formed on the insulating dielectric layer.
16. The integrated circuit memory of claim 15, wherein the insulating dielectric layer further surrounds a portion of a bottom end of the active pillars; and, a top surface of the insulating dielectric layer is higher than a top surface of the bit line and lower than a top boundary of the first doped region of the active pillar.
17. The integrated circuit memory of claim 11, wherein the active pillars comprise a cylinder in shape.
18. The integrated circuit memory of claim 11, wherein a plurality of said word lines and a plurality of said bit lines spatially intersect and have a plurality of overlap regions, one overlap region corresponding to each of said active pillars, six of said plurality of active pillars equally adjacent to the same active pillar being in a hexagonal array arrangement.
19. The integrated circuit memory of claim 11, further comprising:
and a spacer dielectric layer formed on the substrate and filling the gap between the adjacent gate tubes.
20. The integrated circuit memory of claim 19, wherein the word line includes a plurality of connection line portions connecting the gate tubes, the connection line portions regularly linearly connecting the gate tubes on adjacent ones of the active pillars, and a top surface of the connection line portions is lower than a top surface of the gate tubes; the spacer dielectric layer further covers the connecting wire portion and extends to cover the side wall of the grid tube.
21. The integrated circuit memory of claim 20, wherein the direction of extension of the connection line portion of the word line intersects the bit line at an angle between 50 ° and 70 °.
22. A semiconductor integrated circuit device manufactured by the forming method according to any one of claims 1 to 10, comprising:
a substrate;
a plurality of first conductive lines formed on the substrate and extending along a first direction;
a plurality of active pillars formed on the first conductive lines such that bottom ends of the active pillars are connected to the first conductive lines; the method comprises the steps of,
and a plurality of second conductive lines formed on the substrate and extending along a second direction, the second conductive lines surrounding sidewalls of the corresponding active pillars in an extending direction thereof to extend and connect the plurality of corresponding active pillars.
CN201810439588.9A 2018-05-09 2018-05-09 Integrated circuit memory, forming method thereof and semiconductor integrated circuit device Active CN108461496B (en)

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