KR20140080741A - Asymmetric two-terminal biristor and fabrication method - Google Patents

Abstract

An embodiment of the present invention relates to an asymmetric two-terminal biristor and a fabrication method thereof. An asymmetric two-terminal biristor according to an embodiment includes a substrate; a first semiconductor layer which is formed on the substrate; a second substrate layer which is formed on the first semiconductor layer; a third semiconductor layer which is formed on the second semiconductor layer; a first conduction layer which is electrically connected to the first semiconductor layer; and a second conduction layer which is electrically connected to the third semiconductor layer. The second semiconductor layer has a first impurity region and a second impurity region. The concentration of the first impurity region is greater than that of the second impurity region.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an asymmetric two-terminal bi-

An embodiment relates to an asymmetric two-terminal bister device and a manufacturing method thereof.

A conventional DRAM memory unit cell is composed of one transistor (Transistor T) and one capacitor (capacitor C), that is, 1T / 1C DRAM (DRAM). In the case of semiconductor devices, especially memory, the memory capacity per unit area may become larger as the device size is reduced. In general, it is technically possible to reduce the size of a transistor in the case of a general DRAM which is widely used, but it faces a technical limitation in reducing the size of a capacitor to a transistor while maintaining a constant capacitance. As an alternative to the above-mentioned problem, a capacitor-less DRAM (DRAM) device capable of performing a role of a DRAM without using a capacitor, which is pointed out as a problem in reducing the size of a DRAM cell, has been proposed. Since capacitorless DRAM is composed of only one transistor, it is advantageous for miniaturization of a unit memory cell and can have a high integration density through a simple memory cell structure, and a manufacturing process is also simple, which is advantageous for commercialization. However, in the case of a capacitorless DRAM, deterioration of a gate insulating film occurs due to a high driving voltage required in a process of writing and reading a memory state, which causes fatal problems in terms of reliability and durability among memory operating characteristics.

The embodiment provides an asymmetric two-terminal bi-lister device operating in only one direction.

In addition, the embodiment provides an asymmetric two-terminal bister device with small area and high reliability.

In addition, the embodiment provides an asymmetric two-terminal bi-lister device capable of a crossbar arrangement without adding a diode or a transistor.

In addition, the embodiment provides an asymmetric two-terminal bi-lister device capable of arranging a two-terminal memory element without a leakage current problem.

An asymmetric two-terminal bister device according to an embodiment includes a substrate; A first semiconductor layer formed on the substrate; A second semiconductor layer formed on the first semiconductor layer; A third semiconductor layer formed on the second semiconductor layer; A first conductive layer electrically connected to the first semiconductor layer; And a second conductive layer electrically connected to the third semiconductor layer, wherein the second semiconductor layer has a first impurity region and a second impurity region, and the concentration of the first impurity region is less than the concentration of the second impurity region ≪ / RTI >

The semiconductor layer may further include an insulating layer for electrically isolating the first to third semiconductor layers from the first and second conductive layers.

The substrate may be a silicon wafer, a strained silicon wafer, a germanium wafer, a strained germanium wafer, a silicon germanium wafer, an insulating layer buried silicon wafer, an insulating layer buried strained silicon wafer, an insulating layer buried germanium wafer, A germanium wafer, and an insulating layer buried silicon germanium.

The contact landing pad may further include a contact landing pad formed between the third semiconductor layer and the second conductive layer, and the contact landing pad may be one of a metal layer, an amorphous silicon layer, and an epitaxial growth layer .

If the first and third semiconductor layers are N-type semiconductor layers, the second semiconductor layer may be a P ⁺ -P ⁰ -type semiconductor layer or a P ⁰ -P ⁺ -type semiconductor layer.

If the first and third semiconductor layers are P-type semiconductor layers, the second semiconductor layer may be an N ⁺ -N ⁰ -type semiconductor layer or a N ⁰ -N ⁺ -type semiconductor layer.

Here, the first and third semiconductor layers are N-type semiconductor layers, and the second semiconductor layer is a P-type semiconductor layer, and the balance band energy of the materials of the first and third semiconductor layers is lower than that of the second semiconductor layer And wherein the conduction band energy of the material of the first and third semiconductor layers is lower than the conduction band energy of the material of the second semiconductor layer and the conduction band energy of the material of the first and third semiconductor layers The energy gap may be greater than the energy gap of the material of the second semiconductor layer.

Here, the first and third semiconductor layers are P-type semiconductor layers, the second semiconductor layer is an N-type semiconductor layer, and the balance band energy of the materials of the first and third semiconductor layers is And the conduction band energies of the materials of the first and third semiconductor layers are higher than the conduction band energies of the materials of the second semiconductor layer and the energy of the material of the first and third semiconductor layers The energy gap may be greater than the energy gap of the material of the second semiconductor layer.

On the other hand, as another category in the embodiment, a manufacturing method includes: forming a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer on a substrate in this order; Forming an etching hard mask on the third semiconductor layer; Performing an etching process to a portion of the first semiconductor layer, and removing the etching hard mask; Forming an insulating layer on the first to third semiconductor layers; And forming a first conductive layer connected to the first semiconductor layer and a second conductive layer connected to the third semiconductor layer on the insulating layer.

Here, the method may further include a step of heat-treating the first to third semiconductor layers.

The step of forming the first semiconductor layer, the second semiconductor layer and the third semiconductor layer in this order may include at least one of ion implantation, epitaxial growth and selective epitaxial growth, The selective epitaxial growth material may be at least one of silicon, strained silicon, germanium, strained germanium, silicon germanium, and silicon carbide.

Here, the hard mask for etching may be at least one of a light-blocking film having an etch selectivity, an oxide film, and a nitride film.

Also, an asymmetric two-terminal bi-ristor device according to an embodiment includes a substrate; A first semiconductor layer formed on the substrate; A third semiconductor layer formed on the substrate and spaced apart from the first semiconductor layer; A second semiconductor layer formed on the substrate and disposed between the first semiconductor layer and the third semiconductor layer; A first conductive layer electrically connected to the first semiconductor layer; And a second conductive layer electrically connected to the third semiconductor layer, wherein the second semiconductor layer has a first impurity region and a second impurity region, and the concentration of the first impurity region is less than the concentration of the second impurity region ≪ / RTI >

The semiconductor light emitting device further includes an insulating layer for electrically separating the first to third semiconductor layers and the first and second conductive layers.

Here, the substrate may be at least one of an insulating layer buried silicon wafer, an insulating layer buried strained silicon wafer, an insulating layer buried germanium wafer, an insulating layer buried strained germanium wafer, and an insulating buried silicon germanium wafer.

If the first and third semiconductor layers are N-type semiconductor layers, the second semiconductor layer may be a P ⁺ -P ⁰ -type semiconductor layer or a P ⁰ -P ⁺ -type semiconductor layer.

If the first and third semiconductor layers are P-type semiconductor layers, the second semiconductor layer may be an N ⁺ -N ⁰ -type semiconductor layer or a N ⁰ -N ⁺ -type semiconductor layer.

Here, the first and third semiconductor layers are an N-type semiconductor layer, the second semiconductor layer is a P-type semiconductor layer,

Wherein the balance band energy of the material of the first and third semiconductor layers is lower than the balance band energy of the material of the second semiconductor layer,

Wherein the conduction band energy of the material of the first and third semiconductor layers is lower than the conduction band energy of the material of the second semiconductor layer,

 The energy gap of the material of the first and third semiconductor layers may be greater than the energy gap of the material of the second semiconductor layer.

Here, the first and third semiconductor layers are P-type semiconductor layers, the second semiconductor layer is an N-type semiconductor layer, and the balance band energy of the materials of the first and third semiconductor layers is And the conduction band energies of the materials of the first and third semiconductor layers are higher than the conduction band energies of the materials of the second semiconductor layer and the energy of the material of the first and third semiconductor layers The energy gap may be greater than the energy gap of the material of the second semiconductor layer.

On the other hand, as a category according to an embodiment, a manufacturing method includes: forming a second semiconductor layer on a substrate; Forming a hard mask for ion implantation on the second semiconductor layer, and forming first and third semiconductor layers; Forming an insulating layer on the first to third semiconductor layers; And forming the first conductive layer connected to the first semiconductor layer and the second conductive layer connected to the second semiconductor layer on the insulating layer.

The forming of the first and third semiconductor layers may further include a step of heat-treating the first to third semiconductor layers.

Here, the step of forming the second semiconductor layer and the step of forming the first and third semiconductor layers include at least one of ion implantation, epitaxial growth and selective epitaxial growth, and the epitaxial growth and the epitaxial growth The selective epitaxial growth material may be at least one of silicon, strained silicon, germanium, strained germanium, silicon germanium, and silicon carbide.

The asymmetric two-terminal bi-lister device according to the present invention has an advantage of being unidirectionally driven only when a forward voltage is applied and is not driven when a backward voltage is applied.

In addition, there is an advantage that the deterioration of the device is originally cut off through the structure having no gate and gate insulating film, thereby providing high reliability and durability.

In addition, there is an advantage that a crossbar arrangement can be formed without adding a diode or a transistor through the asymmetric operation characteristics of the device itself.

In addition, there is an advantage of solving the problem of leakage current through the adjacent cells occurring in the arrangement of the two-terminal memory elements.

Fig. 1 shows an asymmetric two-terminal bister element according to the first embodiment.
2A to 2E illustrate a process for manufacturing an asymmetric two-terminal bister device according to the first embodiment.
3 is an arrangement view of an asymmetric two-terminal bi-splicer device according to the first embodiment.
Fig. 4 shows an asymmetric two-terminal bister element according to the second embodiment.
5A to 5D illustrate a process for manufacturing an asymmetric two-terminal bister device according to the second embodiment.
6 is a three-dimensional view of an asymmetric two-terminal biistor device according to the second embodiment.
FIG. 7 is a current-voltage graph of an asymmetric two-terminal biistor device according to the first and second embodiments.
8 is a current-time graph showing the memory operation of the asymmetric 2-terminal bi-raster device according to the first and second embodiments.
9 is a graph of a current-memory operation repetition characteristic showing the reliability and durability of the asymmetric two-terminal bi-splice device according to the first and second embodiments.

The thickness and size of each layer in the drawings are exaggerated, omitted, or schematically shown for convenience and clarity of explanation. Also, the size of each component does not entirely reflect the actual size.

In the description of embodiments according to the present invention, it is to be understood that where an element is described as being formed "on or under" another element, On or under includes both the two elements being directly in direct contact with each other or one or more other elements being indirectly formed between the two elements. Also, when expressed as "on or under", it may include not only an upward direction but also a downward direction with respect to one element.

Hereinafter, an asymmetric two-terminal bister device according to an embodiment of the present invention will be described with reference to the accompanying drawings.

≪ Embodiment 1 >

1 is an asymmetric two-terminal bi-ristor device according to the first embodiment. Referring to FIG. 1, an asymmetric 2-terminal bister device according to a first embodiment includes a substrate 100, first to third semiconductor layers 101, 102 and 103, an insulating layer 200, 2 conductive layers 301 and 302, respectively.

Specifically, the substrate 100 may be a silicon wafer, a strained silicon wafer, a germanium wafer, a strained germanium wafer, a silicon germanium wafer, , Silicon on Insulator (SOI) wafers, Strained Silicon on Insulator (SSOI) wafers, Germanium on Insulator (GOI) wafers, Insulating layer embedded strained germanium A strained Germanium on Insulator (SGOI) wafer, and a Silicon Germanium on Insulator.

The first to third semiconductor layers 101, 102, and 103 may be stacked on the substrate. In detail, a first semiconductor layer 101 having a laterally elongated first portion and a vertically protruded second portion is disposed on a substrate, and a first semiconductor layer 101 is formed on the protruding portion of the second portion of the first semiconductor layer 101 A second semiconductor layer 102 may be disposed on the second semiconductor layer 102, and a third semiconductor layer 103 may be disposed on the second semiconductor layer 102. The first semiconductor layer 101 and the second semiconductor layer 102 may be electrically connected to each other. In addition, the second semiconductor layer 102 and the third semiconductor layer 103 may be electrically connected to each other. Here, the first to third semiconductor layers 101, 102, and 103 are active semiconductor regions.

The first and third semiconductor layers 101 and 103 may be an N-type semiconductor layer. The second semiconductor layer 102 may be a P-type semiconductor layer. Here, the second semiconductor layer 102 is ion-implanted in the acceleration energy and the first impurity region which is the amount (dose), otherwise a distinct generated by the impurities P ⁺ type semiconductor region and a second impurity region of the P ⁰ type semiconductor Region. ≪ / RTI > Here, the impurity concentration of the P ⁺ type semiconductor region is larger than the impurity concentration of the P ⁰ type semiconductor region. Although the first and third semiconductor layers 101 and 103 are shown as the N-type semiconductor layer in the first embodiment, the first and third semiconductor layers 101 and 103 are not P-type semiconductor layers have. At this time, the second semiconductor layer 102 may include an N ⁺ type semiconductor region of the first impurity region and an N ⁰ type semiconductor region of the second impurity region. Although the P ⁺ type semiconductor region in the second semiconductor layer 102 is shown on the P ⁰ type semiconductor region in the first embodiment, the second semiconductor layer 102 is not limited to the P ⁰ type semiconductor region, And may be formed on the P ⁺ type semiconductor region.

The first and second conductive layers 301 and 302 are layers for transmitting external electrical signals. The first conductive layer 301 is electrically connected to one surface of the first portion of the first semiconductor layer 101 and the second conductive layer 302 is electrically connected to the third semiconductor layer 103. In addition, the second semiconductor layer 102 may not be electrically connected to the first and second conductive layers 301 and 302 and may be electrically flotated.

The insulating layer 200 includes first to third semiconductor layers 101, 102, 103 and first and second conductive layers 101, 102, 103 for protecting the first to third semiconductor layers 101, 102, (301, 302). Here, the insulating layer 200 may be an oxide, a nitride, a solid, or a liquid or a gas.

2A to 2E illustrate a process for manufacturing an asymmetric two-terminal bister device according to the first embodiment. Hereinafter, a method of fabricating the asymmetric 2-terminal bister device according to the first embodiment will be sequentially described with reference to FIGS. 2A to 2E. FIG.

On a substrate 100, as shown in Figure 2a of the first to third semiconductor layers (101, 102, 103), the N-type - (P ⁺ -P ⁰⁾ ion for forming the mold type semiconductor layer -N An injection 400 is performed. The ion implantation 400 is a method of introducing impurity atoms into a semiconductor crystal to obtain necessary resistivity. The ion implantation 400 ionizes impurity atoms and injects the impurities into the semiconductor crystal surface at a high speed by a high-speed accelerator. First, a first semiconductor layer 101 is formed through an ion implantation 400, and then a second semiconductor layer 102 is formed on a first semiconductor layer 101. At this time, the (P ⁺ -P ⁰ ) -type semiconductor layer can be formed by controlling the acceleration energy of the ion implantation and the amount of the impurity. Specifically, when the ion implantation is performed at a specific position, the specific position becomes P ⁺ and the periphery thereof becomes P ⁰ . In addition, P ⁺ and P ⁰ can be formed by ion implantation at a concentration of two or more different impurities. Subsequently, the third semiconductor layer 103 is formed on the second semiconductor layer 102. Further, by adding a step of thermal annealing the first to third semiconductor layers 101, 102, and 103 after the ion implantation, the implanted impurities can be activated and the distribution of the implanted impurities can be controlled to a desired shape . Here, another method of forming the first to third semiconductor layers 101, 102, and 103 may be a method such as epitaxial growth or selective epitaxial growth. Here, epitaxial growth is a technology for growing crystals oriented on a surface of a substrate 100 as one of semiconductor manufacturing techniques. In addition, the epitaxial growth or selective epitaxial growth material may be at least one of silicon, strained silicon, germanium, strained germanium, silicon germanium and silicon carbide.

The materials forming the first to third semiconductor layers 101, 102 and 103 may be silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC) The first to third semiconductor layers 101, 102, and 103 have a valance band of the material of the first and third semiconductor layers 101 and 103 when the N type-P type N type junction, Energy is advantageous if it is lower than the balance band energy of the material of the second semiconductor layer 102 and the conduction band energy of the material of the first and second semiconductor layers 101 and 103 is lower than that of the second semiconductor layer 102) is lower than the conduction band energy of the material of the second electrode (102). In addition, since the energy gap, which is the difference between the conduction band energy and the balance band energy, is larger as the first and third semiconductor layers 101 and 103 are larger than the second semiconductor layer 102, The energy gap of the material of the semiconductor layers 101 and 103 may be larger than the energy gap of the material of the second semiconductor layer 102. [ Here, the valence band is the energy band occupied by the electrons bound to a specific nucleus. It is also the energy band in which the electrons can move freely in the energy spectrum of the conduction band solids. Generally, the energy level of the balance band is lower than the energy level of the conduction band.

Thus, when the first and third semiconductor layers are the N-type semiconductor layer and the second semiconductor layer is the P-type semiconductor layer, the first and third semiconductor layers 101 and 103 are more balanced than the second semiconductor layer 102 Band energy is lower and the first and third semiconductor layers 101 and 103 are lower in conduction band energy than the second semiconductor layer 102 and the first and third semiconductor layers 101 and 103 are lower in energy than the second semiconductor layer 102. [ Terminal bi-lister device according to the first embodiment using a material having a larger energy gap than that of the asymmetric two-terminal bister device 102 improves its function as a memory. That is, a high current value can be obtained because the injection efficiency of electrons can be increased, and the extra holes stored in the second semiconductor layer 102 are electrically charged by the high hole barrier of the first and third semiconductor layers 101 and 103 The data retention time can be extended by extending the retention time. In addition, since a voltage required for impact ionization forming extra majors is lowered and a current gain for extra holes is increased, a voltage required for memory driving is reduced and low-power driving can be possible. Here, impact ionization is one in which atoms or molecules of a gas or vapor strike against other particles and turn into an electrically charged atom or atomic group.

As shown in FIG. 2B, an etching process is performed to form a vertical device structure. At this time, in order to protect the active semiconductor region from being etched, an etching hard mask 500 is formed and an etching process is performed as shown in FIG. 2C. The etching process is performed until a portion of the first semiconductor layer 101 is etched. A part of the first semiconductor layer 101 may extend to the first portion of the first semiconductor layer 101 described in FIG. Further, when the visual processing is performed, the portion where the hard mask 500 for etching is formed is not etched. After the etching process, the etching hard mask 500 is removed. Here, the hard mask 500 for etching may be a material having an etch selectivity to silicon, such as a photoresist, an oxide, or a nitride.

As shown in FIG. 2D, an insulating layer 200 for protecting the first to third semiconductor layers 101, 102, and 103 is formed after an etching step for forming a vertical structure. Specifically, it may be a shape which surrounds the upper surface and side surfaces of the first to third semiconductor layers 101, 102 and 103. Here, the insulating layer 200 may be any one of solid, liquid, and gas that electrically isolates the conductive layers 301 and 302 from the first, second, and third semiconductor layers 101, 102, and 103.

As shown in FIG. 2E, after the insulating layer 200 is formed, conductive layers 301 and 302 for transmitting an external electric signal are formed. The first semiconductor layer 101, which is the bottom region of the active semiconductor region of the vertical structure, is connected to the first conductive layer 301 to form one terminal. Specifically, it is connected to the first portion of the first semiconductor layer 101 described in Fig. In addition, the third semiconductor layer 103, which is the upper region of the active semiconductor region in the vertical structure, is connected to the second conductive layer 302 to form another terminal. In addition, the second semiconductor layer 102 is not electrically connected to the first and second conductive layers 301 and 302, and is electrically floating. Here, a contact landing pad (not shown) may be formed between the third semiconductor layer 103 and the second conductive layer 302. The contact landing pad may be a metal layer, an amorphous silicon layer, or an epitaxially grown layer.

In the steps of FIGS. 2A to 2E, a method of manufacturing an asymmetric 2-terminal bister device having an N-type (P ⁺ -P ⁰ ) -type semiconductor junction structure has been described. However, according to the ion implantation energy of impurities, The second semiconductor layer 102 may be formed of a P (P ⁰ -P ⁺ ) -type semiconductor layer as well as a P (P ⁺ -P ⁰ ) -type semiconductor layer.

Further, in accordance with the manufacturing sequence of the first to third semiconductor layers 101, 102 and 103 are P-type -N (N ⁺ -N ⁰⁾ -P-type semiconductor junction structure and a P-type -N (N ⁰ -N ⁺ ) -Type semiconductor junction structure. Here, when the first to third semiconductor layers 101, 102, and 103 are asymmetric 2-terminal bisters having a P-type-N-type semiconductor junction structure, the balance band of the material of the two P- Energy is higher than the balance band energy of the material of the N-type semiconductor layer, and the conduction band energy of the material of the two P-type semiconductor layers is higher than the conduction band energy of the material of the N-type semiconductor layer, The energy gap of the material may be greater than the energy gap of the material of the N-type semiconductor layer.

3 is an arrangement view of an asymmetric two-terminal bi-splicer device according to the first embodiment.

Referring to FIG. 3, a plurality of first to third semiconductor layers 101, 102 and 103 are electrically connected to one conductive layer 301 in the asymmetric two-terminal bister element according to the first embodiment.

≪ Embodiment 2 >

Fig. 4 shows an asymmetric two-terminal bister element according to the second embodiment.

Among the constituent elements constituting the asymmetric two-terminal bi-ristor element according to the second embodiment, the same constituent elements as those of the first embodiment use the same reference numerals. Hereinafter, differences from the first embodiment will be mainly described.

Referring to FIG. 4, the asymmetric 2-terminal bi-ristor device according to the second embodiment includes a substrate 100 ', first to third semiconductor layers 101, 102 and 103, an insulating layer 200, And may include a second conductive layer 301, 302.

Specifically, the substrate 100 'may be a silicon on insulator (SOI) wafer, a strained silicon on insulator (SSOI) wafer, a germanium on insulator (GOI) wafer, A strained germanium on insulator (SGOI) wafer, and a silicon germanium on insulator.

The first to third semiconductor layers 101, 102, and 103 may be arranged side by side on the substrate 100 '. More specifically, the first semiconductor layer 101 is disposed on the substrate 100 ', the third semiconductor layer 103 is disposed so as to be spaced apart from the first semiconductor layer 101, and the first semiconductor layer 101 and the third semiconductor layer 101 The second semiconductor layer 102 may be disposed between the semiconductor layers 103. [ The first semiconductor layer 101 and the second semiconductor layer 102 may be electrically connected. Also, the second semiconductor layer 102 and the third semiconductor layer 103 may be electrically connected.

The first and second conductive layers 301 and 302 are layers for transmitting external electrical signals. The first conductive layer 301 is disposed on and electrically connected to the first semiconductor layer 101. And the second conductive layer 302 is disposed on and electrically connected to the third semiconductor layer 103. In addition, the second semiconductor layer 102 may not be electrically connected to the first and second conductive layers 301 and 302 and may be in an electrically floating state.

5A to 5E illustrate a process for manufacturing an asymmetric two-terminal bister device according to the second embodiment. Hereinafter, a method of fabricating the asymmetric 2-terminal bister device according to the second embodiment will be sequentially described with reference to FIGS. 5A to 5E.

As shown in FIG. 5A, a second semiconductor layer 102 is formed on a substrate 100 '. At this time, the (P ⁺ -P ⁰ ) -type semiconductor layer can be formed by controlling the acceleration energy of the ion implantation and the amount of the impurity. Then, as shown in FIG. 5B, the first and third semiconductor layers 101 and 103 are formed. Further, by adding a step of thermal annealing the first to third semiconductor layers 101, 102, and 103 after the ion implantation, the implanted impurities can be activated and the distribution of the implanted impurities can be controlled to a desired shape . In the fabrication of the asymmetric 2-terminal bisterstore device according to the second embodiment, the semiconductor layer which does not require ion implantation is shielded from ion implantation by using the hard mask 700 for ion implantation in the ion implantation 400 (P ⁺ -P ⁰ ) -type N-type semiconductor layer may be formed by epitaxial growth or selective epitaxial growth.

The materials forming the first to third semiconductor layers 101, 102 and 103 may be silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC) The first to third semiconductor layers 101, 102, and 103 have a valance band of the material of the first and third semiconductor layers 101 and 103 when the N type-P type N type junction, Energy is advantageous if it is lower than the balance band energy of the material of the second semiconductor layer 102 and the conduction band energy of the material of the first and second semiconductor layers 101 and 103 is lower than that of the second semiconductor layer 102) is lower than the conduction band energy of the material of the second electrode (102). In addition, since the energy gap, which is the difference between the conduction band energy and the balance band energy, is larger as the first and third semiconductor layers 101 and 103 are larger than the second semiconductor layer 102, The energy gap of the material of the semiconductor layers 101 and 103 may be larger than the energy gap of the material of the second semiconductor layer 102. [

As shown in FIG. 5C, an insulating layer 200 for protecting the first to third semiconductor layers 101, 102, and 103 is formed. Here, the insulating layer 200 may be any one of solid, liquid, and gas that electrically isolates the conductive layers 301 and 302 from the first, second, and third semiconductor layers 101, 102, and 103.

5D, after the formation of the insulating layer 200, the conductive layers 301 and 302 for transmitting an external electric signal are formed. The first semiconductor layer 101 is connected to the first conductive layer 301 to form one terminal and the third semiconductor layer 103 is connected to the second conductive layer 302 to form another terminal do. In addition, the second semiconductor layer 102 is not electrically connected to the first and second conductive layers 301 and 302, and is electrically floating.

5A to 5D, a method of fabricating an asymmetric 2-terminal bister device having an N-type (P ⁺ -P ⁰ ) -type semiconductor junction structure has been described. However, the asymmetric structure The second semiconductor layer 102 may be made of a P ⁰ -P ⁺ type semiconductor layer. In addition, it can be manufactured in a p-type semiconductor junction structure of a p-type -N (N ⁺ -N ⁰ ) type and a p-type semiconductor junction structure of a p-type -N (N ⁰ -N ⁺ ) type. Here, when the first to third semiconductor layers 102 are asymmetric two-terminal bisters having a p-type-N-type-P-type semiconductor junction structure,

The balance band energy of the material of the two P-type semiconductor layers is higher than the balance band energy of the material of the N-type semiconductor layers, and the conduction band energy of the materials of the two P- Energy, and the energy gap of the material of the two P-type semiconductor layers may be larger than the energy gap of the material of the N-type semiconductor layer.

6 is a three-dimensional view of an asymmetric two-terminal biistor device according to the second embodiment.

Referring to FIG. 6, the second semiconductor layer 102 of the asymmetric two-terminal bister element according to the second embodiment is not connected to the first and second conductive layers 301 and 302.

FIG. 7 is a current-voltage graph of an asymmetric 2-terminal biistor device according to the first and second embodiments; FIG. Specifically, the horizontal axis in FIG. 7 is the voltage and the vertical axis is the current.

Referring to FIG. 7, when a proper voltage is applied between two terminals, the current rapidly changes from off-state (0) to on-state (1). Here, the abrupt increase of the current occurs when the condition (M-1) *?? 1 is satisfied. Also, M is a multiplication factor and? Is a current gain.

Terminal biistor element according to the first and second embodiments applies a voltage to the second conductive layer and grounds the first conductive layer to generate a hysteresis voltage-current graph necessary for driving the memory Show. Here, the hysteresis is a phenomenon in which a certain physical quantity is not determined solely by the physical condition at that time but depends on the change process of the state before the material is determined.

On the other hand, in the reverse direction in which the voltage is applied to the first conductive layer and the second conductive layer is grounded, a low-level current (off-state, 0) flows regardless of the applied voltage. No hysteresis voltage-current graphs are shown. In the forward direction, the values of M and β are higher in the same voltage condition than in the reverse direction due to the asymmetric P ⁺ -P ⁰ structure, and therefore, the minimum voltage required for the memory driving is lower than the reverse voltage in the forward direction. Using this difference in forward and reverse operating voltages, selective memory operation in one direction is possible through the asymmetric P ⁺ -P ⁰ structure.

As described above, it is possible to implement an asymmetric two-terminal bi-lister which is driven only by applying a forward voltage through the asymmetric two-terminal bi-ristor device according to the embodiment, that is, operates only in one direction.

8 is a current-time graph showing the memory operation of the asymmetric two-terminal bi-splice device according to the first and second embodiments. Specifically, the horizontal axis represents time and the vertical axis represents current.

Referring to FIG. 8, it can be seen that the asymmetric 2-terminal biistor element according to the first and second embodiments changes the state of the asymmetric 2-terminal biistor element to the ON state through the write '1' operation. In addition, it can be seen that the state of the asymmetric 2-terminal bi-raster device changes to the OFF state through the write '0' operation. This is because the electrons injected from the first semiconductor layer by the electric field move to the third semiconductor layer through the second semiconductor layer, and the high electric field formed between the second semiconductor layer and the third semiconductor layer causes collisional ionization (impact ionization), thereby generating electron and hole pairs. Here, the generated electrons are directly transferred to the third semiconductor layer, but in the case of holes, they accumulate in the electrically isolated second semiconductor layer. This lowers the high potential barrier between the first semiconductor layer and the second semiconductor layer so that a large number of electrons can pass from the first semiconductor layer to the second semiconductor layer. Further, the electrons flowing into the second semiconductor layer move again to the third semiconductor layer to which the high voltage is applied. Electrons moving to the third semiconductor layer to which a high voltage is applied cause impact ionization again by an electric field formed between the second semiconductor layer and the third semiconductor layer to generate electrons and electron pairs. At this time, holes are accumulated again in the second semiconductor layer. Due to the feedback phenomenon, the potential barrier between the first semiconductor layer and the second semiconductor layer is sufficiently lowered by the holes generated continuously, so that the electrons flow from the first semiconductor layer to the second semiconductor layer becomes easy, After 1 'operation, much current flows even at the voltage of low read' 1 'operation.

Thus, the asymmetric 2-terminal bi-lister device according to the first and second embodiments not only can change the state of the asymmetric 2-terminal bi-lister device through the write '1' or write '0' , It is possible to maintain the ON state temporarily even when the applied voltage is removed. This is determined depending on the presence or absence of holes existing in the electrically floating second semiconductor layer, and if a voltage higher than a specific value is applied again within a predetermined time, the previous current state can be shown through feedback. Here, the ON state of the memory can be continuously maintained through the process of compensating the holes decreasing with time, and the process of replenishing the holes is the same as the reading operation. That is, the on-state asymmetric two-terminal bi-lister device generates a collision ionization phenomenon by the read operation, and holes are continuously generated and accumulated through the feedback process. On the other hand, in the case of the off-state device, the collision ionization phenomenon does not occur only by the read operation, and therefore, the off state is maintained. Write '1', the on state of the changed memory can be changed to the memory off state through the write '0' operation. A write '0' operation is possible by reducing the applied voltage to a high level to eliminate the formation of additional electrons and holes pairs or by applying a negative voltage to the third semiconductor layer region to remove the extra holes present in the second semiconductor layer . If the voltage applied between the two terminals is lowered below a certain value, the original small value current flows. Separately, for fast memory operation, it is possible to apply a negative voltage to the third semiconductor layer.

FIG. 9 is a graph of current-memory operation repetition characteristics showing the reliability and durability of the asymmetric two-terminal bi-ristor device according to the first and second embodiments. Specifically, the horizontal axis represents the number of repetitions of the memory operation and the vertical axis represents the current.

 Referring to FIG. 9, in the case of a three-terminal capacitorless DRAM, as the number of memory operations increases due to a deterioration phenomenon of a gate insulating film that occurs during a memory operation, different current states of on and off states Decrease gradually. As a result, the deterioration of the gate insulating film is intensified, and the difference in the memory-state current rapidly decreases, resulting in a failure in the memory operation.

On the other hand, in the asymmetric two-terminal bi-lister device having no gate and gate insulating film according to the first and second embodiments, stable characteristics and high reliability and durability can be obtained even in repetitive memory operation have. Table 1 below shows the results of comparing characteristics of various DRAM devices.

1T / 1C DRAM 1T-DRAM Thyristor Asymmetric two-terminal bi-lister element rescue 1T + 1C 1T 1T 1R Manufacturing process Very complex usually complicacy Simple area 8 to 6 F ² 8 to 6 F ² 8 to 6 F ² 4 F ² responsibility Very good Poor usually Very good

The asymmetric two-terminal bi-lister device according to the first and second embodiments advantageously has a very simple device structure and manufacturing process compared to the conventional DRAM technology. The asymmetric device structure allows the memory array to be configured without additional selection switch elements, thereby providing a high degree of integration. High speed memory operation is possible through write and read operation through collision ionization and large memory state sensing current can be secured. In addition, it has a high reliability and durability by blocking the deterioration of the device from the source through the structure having no gate and gate insulating film.

The asymmetric 2-terminal bi-splitter device according to the embodiments of the present invention shown in FIGS. 1 to 9 may be driven only when a forward voltage is applied, and may have one direction that is not driven when a backward voltage is applied.

In addition, deterioration of the device is originally cut through the structure having no gate and gate insulating film, so that high reliability and durability can be obtained.

In addition, the asymmetric operation characteristic of the device itself allows a crossbar array configuration without adding a diode or a transistor, thereby simplifying the manufacturing process of the memory array and improving the integration degree.

In addition, the asymmetric two-terminal bi-lister device according to the first embodiment originally blocks operation deterioration of the device related to the gate insulating film of the capacitorless DRAM device of the conventional MOSFET structure, and has excellent memory reliability and durability. In addition, since the first to third semiconductor layers 101, 102, and 103 are vertical structures, the size of the DRAM memory unit cell can also be reduced from 8F ² to 4F ² . In addition, a problem of leakage current through adjacent cells occurring in an array configuration of a two-terminal memory element can be solved by using the second semiconductor layer 102.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be understood that various modifications and applications are possible. For example, each component specifically shown in the embodiments can be modified and implemented. It is to be understood that all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

100, 100 ': substrate 101: first semiconductor layer
102: second semiconductor layer 103: third semiconductor layer
200: insulating layer 301, 302: conductive layer

Claims (22)

Board;
A first semiconductor layer formed on the substrate;
A second semiconductor layer formed on the first semiconductor layer;
A third semiconductor layer formed on the second semiconductor layer;
A first conductive layer electrically connected to the first semiconductor layer; And
And a second conductive layer electrically connected to the third semiconductor layer,
Wherein the second semiconductor layer has a first impurity region and a second impurity region, and the concentration of the first impurity region is larger than the concentration of the second impurity region. The method according to claim 1,
Further comprising an insulating layer for electrically separating said first to third semiconductor layers and said first and second conductive layers. The method according to claim 1,
The substrate may be a silicon wafer, a strained silicon wafer, a germanium wafer, a strained germanium wafer, a silicon germanium wafer, an insulating layer buried silicon wafer, an insulating layer buried strained silicon wafer, an insulating layer buried germanium wafer, an insulating layer buried strained germanium wafer And an insulating layer buried silicon germanium. The method according to claim 1,
And a contact landing pad formed between the third semiconductor layer and the second conductive layer,
Wherein the contact landing pad is one of a metal layer, an amorphous silicon layer, and an epitaxially grown layer. The method according to claim 1,
If the first and third semiconductor layers are N-type semiconductor layers,
Wherein the second semiconductor layer is a P ⁺ -P ⁰ -type semiconductor layer or a P ⁰ -P ⁺ -type semiconductor layer. The method according to claim 1,
If the first and third semiconductor layers are P-type semiconductor layers,
Wherein the second semiconductor layer is an N ⁺ N ⁰ type semiconductor layer or a N ⁰ - N ⁺ type semiconductor layer. The method according to claim 1,
The first and third semiconductor layers are an N-type semiconductor layer, the second semiconductor layer is a P-type semiconductor layer,
Wherein the balance band energy of the material of the first and third semiconductor layers is lower than the balance band energy of the material of the second semiconductor layer,
Wherein the conduction band energy of the material of the first and third semiconductor layers is lower than the conduction band energy of the material of the second semiconductor layer,
Wherein the energy gap of the material of the first and third semiconductor layers is greater than the energy gap of the material of the second semiconductor layer. The method according to claim 1,
The first and third semiconductor layers are P-type semiconductor layers, the second semiconductor layer is an N-type semiconductor layer,
Wherein the balance band energy of the material of the first and third semiconductor layers is higher than the balance band energy of the material of the second semiconductor layer,
Wherein the conduction band energy of the material of the first and third semiconductor layers is higher than the conduction band energy of the material of the second semiconductor layer,
Wherein the energy gap of the material of the first and third semiconductor layers is greater than the energy gap of the material of the second semiconductor layer. Forming a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer on a substrate in this order;
Forming an etching hard mask on the third semiconductor layer;
Performing an etching process to a portion of the first semiconductor layer, and removing the etching hard mask;
Forming an insulating layer on the first to third semiconductor layers; And
And forming a first conductive layer connected to the first semiconductor layer and a second conductive layer connected to the third semiconductor layer on the insulating layer. 10. The method of claim 9,
Further comprising the step of heat treating the first to third semiconductor layers. 10. The method of claim 9,
Wherein the step of forming the first semiconductor layer, the second semiconductor layer and the third semiconductor layer in order includes at least one of ion implantation, epitaxial growth and selective epitaxial growth,
Wherein the epitaxial growth or the selective epitaxial growth material is at least one of silicon, strained silicon, germanium, strained germanium, silicon germanium, and silicon carbide. 10. The method of claim 9,
Wherein the hard mask for etching is at least one of a light-shielding film having an etch selectivity, an oxide film, and a nitride film. Board;
A first semiconductor layer formed on the substrate;
A third semiconductor layer formed on the substrate and spaced apart from the first semiconductor layer;
A second semiconductor layer formed on the substrate and disposed between the first semiconductor layer and the third semiconductor layer;
A first conductive layer electrically connected to the first semiconductor layer; And
And a second conductive layer electrically connected to the third semiconductor layer,
Wherein the second semiconductor layer has a first impurity region and a second impurity region, and the concentration of the first impurity region is larger than the concentration of the second impurity region. 14. The method of claim 13,
Further comprising an insulating layer for electrically separating the first to third semiconductor layers from the first and second conductive layers. 14. The method of claim 13,
Wherein the substrate is at least one of an insulating layer buried silicon wafer, an insulating layer buried strained silicon wafer, an insulating layer buried germanium wafer, an insulating layer buried strained germanium wafer, and an insulating layer buried silicon germanium wafer. 14. The method of claim 13,
If the first and third semiconductor layers are N-type semiconductor layers,
And the second semiconductor layer is a P ⁺ -P ⁰ -type semiconductor layer or a P ⁰ -P ⁺ -type semiconductor layer. 14. The method of claim 13,
If the first and third semiconductor layers are P-type semiconductor layers,
Wherein the second semiconductor layer is an N ⁺ N ⁰ type semiconductor layer or a N ⁰ - N ⁺ type semiconductor layer. 14. The method of claim 13,
The first and third semiconductor layers are an N-type semiconductor layer, the second semiconductor layer is a P-type semiconductor layer,
Wherein the balance band energy of the material of the first and third semiconductor layers is lower than the balance band energy of the material of the second semiconductor layer,
Wherein the conduction band energy of the material of the first and third semiconductor layers is lower than the conduction band energy of the material of the second semiconductor layer,
Wherein the energy gap of the material of the first and third semiconductor layers is greater than the energy gap of the material of the second semiconductor layer. 14. The method of claim 13,
The first and third semiconductor layers are P-type semiconductor layers, the second semiconductor layer is an N-type semiconductor layer,
Wherein the balance band energy of the material of the first and third semiconductor layers is higher than the balance band energy of the material of the second semiconductor layer,
Wherein the conduction band energy of the material of the first and third semiconductor layers is higher than the conduction band energy of the material of the second semiconductor layer,
Wherein the energy gap of the material of the first and third semiconductor layers is greater than the energy gap of the material of the second semiconductor layer. Forming a second semiconductor layer on the substrate;
Forming a hard mask for ion implantation on the second semiconductor layer, and forming first and third semiconductor layers;
Forming an insulating layer on the first to third semiconductor layers; And
And forming the first conductive layer connected to the first semiconductor layer and the second conductive layer connected to the second semiconductor layer on the insulating layer. 21. The method of claim 20,
Wherein forming the first and third semiconductor layers comprises:
Further comprising the step of heat treating the first to third semiconductor layers. 21. The method of claim 20,
Wherein forming the second semiconductor layer and forming the first and third semiconductor layers include at least one of ion implantation, epitaxial growth, and selective epitaxial growth,
Wherein the epitaxial growth and the selective epitaxial growth material are at least one of silicon, strained silicon, germanium, strained germanium, silicon germanium, and silicon carbide.

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