KR20140078503A - The field effect element equipped with the current sensing function - Google Patents

Abstract

The present invention provides a semiconductor device with improved reliability in operation, and more specifically, provides a sense FET device with improved reliability with respect to operation-assisted breakdown. The present invention provides a semiconductor device comprising: a main cell including a field effect transistor having a gate end, a source end and a drain end; A field effect transistor having a current capability smaller than that of the main cell to sense a current flowing through the drain terminal, and a terminal connected to the gate terminal and the drain terminal and the terminal connected to the gate terminal and the drain terminal, Wherein the sensing cell comprises a plurality of gate patterns arranged to implement a field effect transistor of the sensing cell and an electric field having a well pattern disposed at a lower end thereof across the plurality of gate patterns, Thereby providing an effect element.

Description

FIELD EFFECT ELEMENT EQUIPPED WITH THE CURRENT SENSING FUNCTION Field of the Invention [0001]

Field of the Invention [0002] The present invention relates to a semiconductor device, and more particularly, to a field effect device, particularly to a current sensing-field effect transistor (S-FET device).

BACKGROUND ART [0002] Semiconductor devices used for storing and processing information in computer systems, electronic communication fields, and the like are becoming increasingly inexpensive, compact, and large-capacity. Semiconductor devices will have a large number of integrated devices, the most common being field effect transistor (FET) devices. The FET device has two electrode regions and a channel region distributed therebetween, and forms a conductive channel in the channel region, thereby allowing a current to flow between the two electrodes.

A MOSFET device is a device in which a metal / conductor is stacked on top of a channel to form a conductive channel in the channel, and the MOSFET is activated by activating the channel region. Due to the high integration, MOSFETs are designed with decreasing channel lengths, which can result in higher operating speeds. However, when the channel length of the MOSFET is reduced to a certain length or less, a short channel effect occurs due to the material of the semiconductor substrate surrounding the channel region. This performance degradation occurs due to the interaction of the source region and the drain region.

In addition, MOSFET devices may have a well-known avalanche breakdown phenomenon as they implement the structure, thereby failing to perform the intended operation. The avalanche breakdown is accompanied by an increase in the electric field at both ends, accelerating electrons, causing collision ionization by accelerated electrons, and resulting in a high current, resulting in a high avalanche current undesirably. This destroys the MOSFET device. MOSFET devices are becoming more vulnerable to avalanche breakdown as the channel length becomes smaller.

The present invention provides a semiconductor device with improved reliability in operation, and more specifically, provides an S-FET device with improved reliability regarding operation avalanche breakdown.

The present invention provides a semiconductor device comprising: a main cell including a field effect transistor having a gate end, a source end and a drain end; A field effect transistor having a current capability smaller than that of the main cell to sense a current flowing through the drain terminal, and a terminal connected to the gate terminal and the drain terminal and the terminal connected to the gate terminal and the drain terminal, Wherein the sensing cell comprises a plurality of gate patterns arranged to implement a field effect transistor of the sensing cell and an electric field having a well pattern disposed at a lower end thereof across the plurality of gate patterns, Thereby providing an effect element.

Also, the well pattern may include a first well pattern and a second well pattern arranged to cross each other with respect to both ends of the plurality of gate patterns.

Further, the gate pattern includes polysilicon.

The well pattern is a P-type well.

The S-FET device provided according to the present invention has the same operational reliability as the main cell and the sensing cell that constitute the S-FET device, so that the semiconductor device can be realized more stably.

The S-FET device according to the present invention can prevent the concentration of the unbalance current in the sensing cell, and the semiconductor device having the S-FET device according to the present invention can be expected to improve reliability in operation.

1 is a circuit diagram showing an S-FET device according to an embodiment of the present invention;
Fig. 2 is a layout diagram of the S-FET device shown in Fig. 1. Fig.
Fig. 3 is a layout diagram of the S-FET device shown in Fig. 2
4 shows a package of the S-FET device shown in Fig. 2; Fig.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. do.

1 is a circuit diagram showing an S-FET device according to an embodiment of the present invention.

Referring to FIG. 1, the S-FET device includes a main cell and a sense cell. The main cell includes a field effect transistor connected to a gate terminal, a source terminal and a drain terminal. The sense cell includes a gate terminal, , A selection stage (CS), and a field effect transistor connected to a drain stage (Drain).

A sense cell is a device having an area less than 0.1% of the main cell to sense the drain current. The sense cell detects the current flowing in the selected end (CS) A resistance of about 100 ohms is connected. In general, S-FET devices and resistors can be implemented in a single IC form. A certain portion of the current flowing in the drain stage flows into the selected stage CS and the drain current flowing in the drain stage can be calculated by sensing the current flowing in the selected stage CS.

A main cell and a sense cell each having a main-cell and a sense-cell, which constitute the S-FET device, are different from each other in the amount of current that can be driven, And has a layout area.

Therefore, in the case of the S-FET device, the sense-cell characteristics of the sense-cell may be lower than that of the main-cell. If an Avalanche breakdown occurs, the Avalanche breakdown current in the Sense-Cell is concentrated and becomes weak. In order to improve this, the structure of the sense cell must be designed to be the same as the structure of the main cell to have a high withstand voltage structure.

2 is a layout view of the S-FET device shown in FIG.

The S-FET device according to the present embodiment realizes the layout of the polysilicon pattern 10 and the P-type well 20 as shown in FIG. The left side is a main cell region, and the right side region is a sense-cell region.

The S-FET device according to the present embodiment includes a P-type well pattern 30 disposed in a polysilicon pattern 10 in a region where a sense-cell is laid out, (Sense-Cell) is reduced, so that a stable breakdown voltage can be obtained during operation.

In this way, the S-FET device can maintain the operational reliability of the main cell and the sensing cell constituting the device substantially similar. Therefore, the semiconductor device provided with the S-FET device provided according to the present invention can be stably operated.

3 is a cross-sectional view of the S-FET device of FIG. 1 according to a temporal example.

The upper diagram of FIG. 3 shows a method of performing the layout of the sense cell in FIG. 2, and the lower diagram shows a method of laying out the sense cell proposed by the present invention Respectively.

The S-FET device according to the present embodiment includes a P-type well (P-well) disposed at the lower end of a place where a plurality of polysilicon patterns (poly) are arranged in parallel in a sense- As shown in FIG. 3, a P-type well is disposed so as to cross a polysilicon pattern at one end of a plurality of polysilicon patterns. A polysilicon pattern (poly) constitutes the gate pattern of the field effect transistor of the sense cell. In this way, a region where a voltage difference is generated between the main cell and the sense cell is reduced, and a stable breakdown voltage can be obtained during operation.

When a sensing cell is operated, a high electric field can be concentrated in the P-type well. If the P-type well is arranged as shown in the lower part of FIG. 3, the distribution concentration of the electric field is relaxed , The internal pressure of the entire sensing cell structure can be maintained in a balanced manner.

4 is a view showing a package of the S-FET device shown in Fig.

4 is a view showing a package state of an IC chip in which the S-FET device shown in Figs. 1 to 3 is implemented. When the S-FET device is implemented as described with reference to FIGS. 1 to 3, it can be expected that the S-FET is more stable and reliable in operation in the region where the sensing cell is disposed (current sensing) It is expected that the operation reliability of the device can be improved.

As described above, in the S-FET device according to the present invention, when a sensing cell constituting the S-FET device is laid out, a P-type well (P-well) It is possible to prevent concentration of avalanche current in the sensing cell. Therefore, the semiconductor device having the S-FET device according to the present invention can be expected to improve reliability in operation.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, I will understand. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined by the scope of the appended claims, as well as the appended claims.

10: Polysilicon pattern
20: P-type well
30: P-type well pattern

Claims (4)

A main cell including a field effect transistor having a gate end, a source end, and a drain end;
A field effect transistor having a current capability smaller than that of the main cell to sense a current flowing through the drain terminal, and a terminal connected to the gate terminal and the drain terminal and the terminal connected to the gate terminal and the drain terminal, And a sensing cell,
Wherein the sensing cell includes a plurality of gate patterns arranged to implement a field effect transistor of the sensing cell, and a well pattern disposed at a lower end of the sensing pattern across the plurality of gate patterns.
The method according to claim 1,
The well pattern
And a first well pattern and a second well pattern arranged to cross each other with respect to both ends of the plurality of gate patterns.
3. The method of claim 2,
Wherein the gate pattern comprises polysilicon.
The method of claim 3,
Wherein the well pattern is a P-type well.

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