KR20140076054A - Display device having touch sensors and control method of gate driving circuit thereof - Google Patents

Display device having touch sensors and control method of gate driving circuit thereof Download PDF

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KR20140076054A
KR20140076054A KR1020120144156A KR20120144156A KR20140076054A KR 20140076054 A KR20140076054 A KR 20140076054A KR 1020120144156 A KR1020120144156 A KR 1020120144156A KR 20120144156 A KR20120144156 A KR 20120144156A KR 20140076054 A KR20140076054 A KR 20140076054A
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gate
touch sensor
clock
touch
display
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KR1020120144156A
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Korean (ko)
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KR102020935B1 (en
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박인래
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엘지디스플레이 주식회사
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Human Computer Interaction (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

The present invention relates to a display device having touch sensors and a method for controlling a gate driving circuit thereof. The display device comprises: a display panel including a pixel array and touch sensors; a gate driving circuit including a shift resistor in which stages are dependently connected; and a timing controller which controls the gate driving circuit by supplying a gate start pulse and a gate shift clock to the gate driving circuit. The timing controller maintains a first clock of the gate shift clock supplied to a pull-up transistor of a first stage connected to a first gate line, in which a display interval is started, at a high logic level during the touch sensor interval.

Description

TECHNICAL FIELD [0001] The present invention relates to a display device having touch sensors and a method of controlling the gate driver circuit,

The present invention relates to a display device having touch sensors and a gate drive circuit control method therefor.

A user interface (UI) enables a user (a user) to communicate with various electric or electronic devices, allowing the user to easily control the device as desired. Representative examples of the user interface include a keypad, a keyboard, a mouse, an on-screen display (OSD), a remote controller having infrared communication or radio frequency (RF) communication functions. User interface technology has been developed to enhance the user's sensibility and ease of operation. Recently, the user interface has evolved into a touch UI, a voice recognition UI, a 3D UI, and the like.

Touch UI is becoming a necessity for portable information devices and is being applied to household appliances. The touch sensing system of the capacitive touch screen has the advantage that the structure of the touch screen is higher in durability and sharpness than that of the conventional resistive film type, and can be applied to various applications. In recent years, most touch screens have been implemented in a capacitive type.

The touch sensors of the touch screen may be placed on a display device or embedded in a display device. The driving circuit of the display device includes a data driving circuit for generating a data voltage and a gate driving circuit for generating a gate pulse (or a scanning pulse) in synchronization with the data voltage. When the touch sensors of the touch screen are embedded in the display device, since the pixels of the display device are arranged close to each other, noise is introduced into the touch sensors due to driving signals of the display device when data is written to the pixels of the display device It is easy to become. When the touch sensors are incorporated in the display device, the period for writing data in the display device and the period for driving the touch screen are time-divided. For example, one frame period is divided into two, data is written to pixels during one of the periods, and the touch sensors are driven for the remaining period.

1, a screen of a display device is divided into a plurality of pixel blocks B 1 to B N , a touch screen is divided into a plurality of sensor blocks S 1 to S M , A method of alternately driving the blocks B 1 to B N and the touch sensor blocks S 1 to S M has been proposed. For example, the first pixel blocks (B 1), the first touch sensor block (S 1), a second pixel block (B 2), the second touch sensor block (S 2) in order of pixel blocks (B 1 ~ B N and the touch sensor blocks S 1 to S M are alternately driven. In Fig. 1, Vsync is a vertical synchronization signal defining one frame period. In this driving method, the gate driving circuit outputs the gate pulse while the pixel blocks are driven, and does not output the gate pulse during the driving time of the touch sensor block. Therefore, a control method capable of temporarily stopping and resuming the output of the gate drive circuit is needed.

The present invention provides a display device having touch sensors capable of temporarily stopping the output of a gate drive circuit during a touch sensor interval and then resuming the output thereof to resume the display interval without changing the brightness, and a gate drive circuit control method thereof.

According to an embodiment of the present invention, a display device having touch sensors includes a display panel including a pixel array and touch sensors; A gate drive circuit including shift registers to which stages are connected in a dependent manner; And a timing controller for supplying a gate start pulse and a gate shift clock to the gate driving circuit to control the gate driving circuit.

During one frame period, the pixel arrays and the touch sensors of the display panel are divided into a plurality of blocks, and a touch sensor section in which a touch sensor block is driven is allocated between display periods in which pixel blocks are driven.

The timing controller supplies the I-th clock of the gate shift clock supplied to the pull-up transistor of the I-stage connected to the I-th gate line (I is a positive integer of 2 or more) Level.

A method of controlling a gate driving circuit of a display device includes driving a plurality of blocks by driving pixel arrays and touch sensors of the display panel in one frame period, Assigning a touch sensor section in which a sensor block is driven; And holding the I-th clock of the gate shift clock supplied to the pull-up transistor of the I-stage connected to the I-th gate line (I is a positive integer equal to or greater than two) .

The present invention maintains the clock supplied to the pull-up transistor of the stage of the gate driving circuit outputting the first gate pulse at a specific logic level during the touch sensor interval when the display interval is resumed. As a result, the display apparatus of the present invention can resume the display period without line noise when the touch sensor block is temporarily stopped while the touch sensor block is being driven, and then the output is resumed.

1 is a diagram illustrating an example in which pixel blocks and touch sensor blocks are alternately driven within one frame period.
2 is a diagram illustrating a touch sensing system according to an embodiment of the present invention.
3 is an equivalent circuit diagram of the touch screen shown in FIG.
4 to 6 are views showing various combinations of the display panel and the touch screen.
7 is a view showing an example in which GIP circuits are arranged on both sides of the display panel.
8 is a block diagram showing an example of a shift register configuration of the GIP circuit shown in FIG.
9 is a diagram showing the circuit configuration of the stage shown in FIG.
10 is a timing chart showing an example of maintaining gate shift clocks at a low logic level in a touch sensor interval.
11 is a waveform diagram showing noise appearing at a timing at which the gate shift clocks are inverted to a high logic level immediately after the gate shift clocks are held at a low logic level as shown in FIG.
12 is a waveform diagram illustrating a method of controlling a gate driving circuit according to an embodiment of the present invention.

The touch sensing system of the present invention can be implemented as a capacitive touch screen that senses a touch input through a plurality of capacitive sensors. The capacitive touch screen includes a plurality of touch sensors. Each of the touch sensors includes a capacitance in terms of an equivalent circuit. The capacitance type touch screen can be divided into self capacitance and mutual capacitance. The self-capacitance is formed along a conductor wiring of a single layer formed in one direction. The mutual capacitance is formed between two orthogonal conductor wirings. In the following embodiments, mutual capacitance type touch screens are exemplified, but are not limited thereto.

The display device of the present invention can be applied to a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), an organic light emitting display , OLED), and electrophoresis (EPD) display devices. In the following embodiments, a liquid crystal display element is described as an example of a flat panel display device, but the present invention is not limited thereto.

 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

1 to 5, the display device of the present invention includes a display panel (PNL), a display driving circuit, a touch screen (TSP), a touch screen driving circuit, and the like.

The display panel (PNL) includes a liquid crystal layer formed between two substrates. The pixel array of the display panel PNL is formed by m (m is a positive integer) data lines D1 to Dm and n (n is a positive integer) gate lines G1 to Gn And includes m x n pixels formed in the defined pixel region. Each of the pixels is connected to TFTs (Thin Film Transistors) formed at intersections of the data lines D1 to Dm and the gate lines G1 to Gn, a pixel electrode for charging a data voltage, A storage capacitor (Cst) for maintaining the voltage, and the like.

A black matrix, a color filter and the like are formed on the upper substrate of the display panel PNL. The lower substrate of the display panel (PNL) may be implemented as a COT (Color Filter On TFT) structure. In this case, the black matrix and the color filter may be formed on the lower substrate of the display panel (PNL). The common electrode to which the common voltage is supplied may be formed on the upper substrate or the lower substrate of the display panel (PNL). On the upper substrate and the lower substrate of the display panel (PNL), a polarizing plate is attached, and an alignment film for forming a pretilt angle of liquid crystal on the inner surface in contact with the liquid crystal is formed. A column spacer for maintaining a cell gap of the liquid crystal cell is formed between the upper substrate and the lower substrate of the display panel PNL.

A backlight unit may be disposed below the rear surface of the display panel PNL. The backlight unit is implemented as an edge type or direct type backlight unit, and irradiates light to the display panel (PNL). The display panel PNL may be implemented in any known liquid crystal mode such as TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In Plane Switching) mode and FFS (Fringe Field Switching) mode.

The display driving circuit includes a data driving circuit 12, a gate driving circuit 14 and a timing controller 20, and writes the video data voltage of the input image to the pixels of the display panel PNL.

The data driving circuit 12 converts the digital video data RGB input from the timing controller 20 into an analog positive / negative gamma compensation voltage to output a data voltage. The data voltage output from the data driving circuit 12 is supplied to the data lines D1 to Dm.

The gate drive circuit 14 sequentially supplies a gate pulse (or a scan pulse) synchronized with the data voltage to the gate lines G1 to Gn to select a line of the display panel PNL into which the data voltage is written. The gate drive circuit 14 may be disposed at one edge of the display panel PNL or may be disposed at both edges of the display panel PNL as shown in FIG. The gate drive circuit 14 may be implemented as a GIP (Gate In Panel) circuit (GIP_L, GIP_R) formed together with the pixel array on the lower substrate of the display panel PNL as shown in FIG. The GIP circuit includes a shift register for sequentially shifting gate pulses under the control of the timing controller 20. [

The timing controller 20 inputs a timing signal such as a vertical synchronizing signal Vsync, a horizontal synchronizing signal Hsync, a data enable signal DE and a main clock MCLK input from the host system 50 And outputs a data timing control signal for controlling the operation timing of the data driving circuit 12 and a gate timing control signal for controlling the operation timing of the gate driving circuit 14 to control the operation timing. The data timing control signal includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (POL), and a source output enable signal (SOE) . The source start pulse SSP controls the sampling start start timing of the data driving circuit 12. The source sampling clock SSC is a clock for shifting the data sampling timing. The polarity control signal POL controls the polarity of the data voltage output from the data driving circuit 12. [ The source start pulse SSP and the source sampling clock SSC may be omitted if the signal transfer interface between the timing controller 20 and the data driving circuit 12 is a mini LVDS (Low Voltage Differential Signaling) interface.

The gate timing control signal includes a gate start pulse (GSP), a gate shift clock, a gate output enable signal (GOE), and the like. The gate timing control signal includes a gate start pulse (GSP), a gate shift clock (GSC), and the like. The gate start pulse GSP is input to the shift register to control the start timing of the shift resister. The gate shift clock GSC is input to the shift register to control the output shift timing of the shift resister. The shift register of the gate driving circuit 14 is connected to a plurality of stages in a dependent manner as shown in FIG. 8 to start outputting gate pulses in response to the gate start pulse GSP, and the gate shift clock GSC In synchronization with the rising edge, the gate pulse is shifted to the next stage.

The host system 50 may be implemented as any one of a television system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, and a phone system. The host system 50 converts a digital video data RGB of an input image into a format suitable for display on a display panel PNL including a system on chip (SoC) with a built-in scaler. The host system 50 transmits the timing signals Vsync, Hsync, DE, and MCLK to the timing controller 20 together with the digital video data RGB of the input image. Further, the host system 50 executes an application program associated with coordinates (XY) received from the touch screen drive circuit.

The display device of the present invention sequentially drives pixel blocks and touch sensor blocks within one frame period as shown in FIG. 1, and alternately drives a pixel block and a touch sensor block. For example, the diagram of a first block of pixels as shown in 1 (B 1), the first touch sensor block (S 1), a second pixel block (B 2), the second touch sensor block (S 2) in order of blocks of pixels (B 1 to B N ) and the touch sensor blocks (S 1 to S M ) are alternately driven. A method of alternately driving the pixel block and the touch sensor block within one frame period can be applied by the proposed method through the Korean patent application 10-2012-0078146 (2012.07.18), which is filed by the present applicant. This time division method is controlled by the timing controller 20. The timing controller 20 holds the logic level of the gate shift clock GSC to a specific logic in order to temporarily stop the output of the gate driving circuit 14 during the period in which the touch sensor block is driven, The gate shift clock GSC is generated in a normal one horizontal period (1H) period when the next pixel block starts to be driven after the output is stopped. One horizontal period (1H) is equal to the pixel data charging time of one line in the display panel (PNL).

 The touch screen TSP may be bonded onto the upper polarizer POL1 of the display panel PNL as shown in FIG. 3 or may be formed between the upper polarizer POL1 of the display panel PNL and the upper substrate GLS1 as shown in FIG. . In addition, the touch sensors Cts of the touch screen TSP may be embedded in the lower substrate in an in-cell type together with the pixel array in the display panel PNL as shown in FIG. In Fig. 3 to Fig. 5, "PIX" means a pixel electrode of a liquid crystal cell, "GLS2" means a lower substrate, and "POL2" means a lower polarizer.

The touch screen TSP includes Tx lines (Tx1 to Txj, j is a positive integer smaller than n), Rx lines Rx1 to Rxi, i, which intersect with Tx lines Tx1 to Txj, And ix j number of touch sensors Cts formed at intersections of the Tx lines Tx1 to Txj and the Rx lines Rx1 to Rxi. Each of the touch sensors Cts includes mutual capacities.

The touch screen driving circuit includes a touch sensing circuit 30, an algorithm executing unit 36, and the like. The touch screen driving circuit supplies a driving signal to the touch sensors to sense a charge change amount of the touch sensor, compares the charge change amount with a predetermined threshold value, and detects a touch input position. The touch screen driving circuit executes a touch coordinate algorithm to calculate coordinates (XY) of the touch input position and transmits it to the host system 50.

The touch sensing circuit 30 includes a Tx driver 32, an Rx sensing unit 34, a timing generator 38, and the like. The touch sensing circuit 30 applies a driving signal to the touch sensors Cts through the Tx lines Tx1 to Txj using the Tx driving unit 32 and applies the driving signals to the Rx lines Rx1 to Rxi And the Rx sensing unit 34 to output touch raw data by sensing the amount of charge change of the touch sensors Cts. The touch sensing circuit 30 may be integrated into one ROIC (read-out integrated circuit).

The Tx driver 32 selects a Tx channel to output a driving signal in response to a Tx setup signal from the timing generator 38 and drives the Tx lines Tx1 to Txj connected to the selected Tx channel Signal. The Tx lines Tx1 to Txj are charged during the high potential interval of the driving signal to supply charges to the touch sensors Cts. The driving signal can be generated in various forms such as a pulse, a sinusoidal wave, and a triangular wave. The driving signal is generated by accumulating N (N is a positive integer equal to or greater than 2) times the voltage of the touch sensors Cts through the Rx lines Rx1 to Rxi to the capacitors of the integrator built in the Rx sensing unit 34 And may be continuously supplied to each of the touch sensors Cst N times.

The Rx sensing unit 34 selects Rx lines to receive the voltage of the touch sensor in response to the Rx setup signal from the timing generator 38. [ The Rx sensing unit 34 receives the charge of the touch sensor Cts through the selected Rx lines in synchronization with the driving signal. The Rx sensing unit 34 samples the received charge and accumulates the accumulated charge in the capacitor of the integrator and converts the voltage of the capacitor to digital data using an analog to digital converter do. The Rx sensing unit 34 outputs touch raw data converted into digital data.

The timing generator 38 controls the Tx channel and the Rx channel setting in response to the Tx setup signal and the Rx setup signal from the algorithm executing unit 36 and synchronizes the Tx driver 32 and the Rx sensing unit 34. Also, the touch source data outputted from the Rx sensing unit 34 is stored in a buffer memory (not shown), and the touch source data is read from the memory and transmitted to the algorithm executing unit 36.

The algorithm executing section 36 supplies the Tx setup signal and the Rx setup signal to the timing generating section 38 and supplies the ADC clock signal for operating the ADC of the Rx sensing section 34 to the Rx sensing section 34. [ The algorithm executing unit 36 executes a predetermined touch coordinate algorithm to compare the touch raw data received from the touch sensing circuit 30 with a preset threshold value. The touch coordinate algorithm determines the touch primitive data equal to or larger than the threshold value as the data of the touch input area and calculates the coordinates (XY) of each of the touch input areas. The algorithm executing unit 36 may be implemented as an MCU (Micro Controller Unit).

7 is a diagram showing an example in which GIP circuits GIP_L and GIP_R are arranged on both sides of the display panel PNL. 8 is a block diagram showing an example of a shift register configuration of the GIP circuit shown in FIG. 9 is a diagram showing the circuit configuration of the stage shown in FIG.

7 to 9, each of the GIP circuits GIP_L and GIP_R disposed on both sides of the pixel array includes a gate start pulse GSP and gate shift clocks GCLK1-L to GCLK4-L, GCLK1-R to GCLK4 -R), and sequentially outputs gate pulses. Although the gate shift clocks (GCLK1-L to GCLK4-L, GCLK1-R to GCLK4-R) illustrate a four-phase clock, a two-phase clock or a six-phase clock is also possible.

The first GIP circuit GIP_L is disposed outside the left side of the pixel array. The first first GIP circuit GIP_L is connected to the odd-numbered gate lines G1, G3, ..., Gn-1 of the pixel array and is connected to the gate lines G1, G3, And sequentially outputs gate pulses. The second GIP circuit GIP_R is disposed outside the right side of the pixel array. The shift register of the second GIP circuit GIP_R is connected to the even-numbered gate lines G2, G4, ... Gn of the pixel array to apply a gate pulse to the gate lines G2, G4, ..., Sequentially. In FIG. 7, GCLK1-L to GCLK4-L are four-phase gate shift clocks applied to the first GIP circuit GIP_L and GCLK1-R to GCLK4-R are four-phase gate shifts applied to the second GIP circuit GIP_R. It is a clock. The clocks of the gate shift clocks GCLK1-L to GCLK4-L and GCLK1-R to GCLK4-R are partially overlapped. The GIP circuits GIP_L and GIP_R generate outputs in synchronization with the rising edges of the gate shift clocks GCLK1-L to GCLK4-L and GCLK1-R to GCLK4-R. Therefore, the Nth (N is a positive integer of 2 or more) gate pulses outputted from the GIP circuits GIP_L and GIP_R are superimposed on the gate shift clocks GCLK1-L to GCLK4-L and GCLK1-R to GCLK4-R And overlaps the rear portion of the (N-l) -th gate pulse by the width.

Each of the GIP circuits GIP_L and GIP_R includes a plurality of stages S (N-1) to S (R)) to which the gate shift clocks GCLK1-L to GCLK4-L, GCLK1-R to GCLK4- S (N + 4)).

Each of the stages S (N-1) to S (N + 1) includes a first transistor T1, a second transistor T2, a third transistor T3, To T3 may be implemented as an n-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

The Nth stage S (N) receives the first, second and fourth clocks GCLK1, GCLK2 and GCLK4 and also receives the output Vout of the (N-1) th stage S 1) and an output Vout (N + 1) of the (N + 1) th stage S (N + 1). The output Vout (N-1) of the (N-1) th stage S (N-1) is supplied as a gate pulse to the (N-1) th gate line, Terminal.

1) of the (N-1) th stage S (N-1) in response to the first clock GCLK1 in the Nth stage S (N) (Q (N)) with the voltage of the node Q (N). When the second clock signal GCLK2 generated subsequent to the first clock signal GCLK1 is supplied when the Q node Q (N) is charged, the second transistor T2 supplies the voltage of the second clock signal GCLK2 Up transistor that supplies the voltage Vout (N) of the output node to the output node. The third transistor T3 is a pull-down transistor for discharging the voltage of the output node in response to the fourth clock GCLK4.

Hereinafter, a period during which the pixel blocks are driven is referred to as a display period, and a period during which the touch sensor blocks are driven is referred to as a touch sensor period. 10, the timing controller 20 supplies the gate shift clocks GCLK1-L to GCLK4-L and GCLK1-R to GCLK4-R during the touch sensor periods Tt1, Tt2 and Tt3 to the low logic level (Low logic level). However, when the display interval is resumed immediately after the gate shift clocks GCLK1-L to GCLK4-L, GCLK1-R to GCLK4-R are maintained at a low logic level, the clocks GCLK1- -R ~ GCLK4-R) to the high logic level, the noise 102 may be applied to the gate lines as shown in FIG. In Fig. 10, the number in the pulse is the number of the gate lines (G1 to Gn) to which the pulse is applied. In FIG. 11, reference numeral 101 denotes a normal gate pulse generated in the display periods Td1, Td3, and Td3.

Referring to FIG. 10, the display periods Td1, Td2, and Td3 and the touch sensor periods Tt1, Tt2, and Tt3 are time-divided within one frame period. Assume that the pixel blocks B 1 to B N each include pixels arranged in 19 lines. In this example, one pixel block includes 19 gate lines. During the first display period Td1, the gate shift clocks GCLK1-L to GCLK4-L and GCLK1-R to GCLK4-R are normally generated in one horizontal period to form the first to nineteenth gate lines G1 to G19, The gate pulse is sequentially supplied. Then, during the first touch sensor period Tt1, the gate shift clocks (GCLK1-L to GCLK4-L, GCLK1-R to GCLK4-R) are held at a low logic level. Then, the clocks GCLK2-R and GCLK3-L are inverted to a high logic level to start the second display period Td2. The clock GCLK2-R is applied to the second transistor T2 of the Nth stage S (N) of the right GIP circuit GIP_R in Fig. 9 so that the gate pulse is output from the Nth stage S (N) And is applied to the gate of the first transistor T1 of the (N + 1) th stage S (N + 1) to change the voltage of the Q node Q (N + 1) The voltage between the gate and the source of the transistor T2 rises and an undesired output is generated from the (N + 1) th stage S (N + 1). Likewise, the clock GCLK3-L is applied to the second transistor T2 of the N + 1 stage S (N + 1) of the left GIP circuit GIP_L in FIG. 9, (N + 2) th stage, and is applied to the gate of the first transistor T1 of the (N + 2) th stage S (N + 2) ) Of the second transistor T2 so that the gate-source voltage of the second transistor T2 rises and an undesired output is generated from the (N + 2) th stage S (N + 2). Accordingly, when the second display period Td2 is started, gate pulses are sequentially supplied to the 20th and 21st gate lines G20 and G21 so that the data is normally addressed, and at the same time, the 22nd and 23rd gate lines G22, G23 are applied to the TFTs connected to the gate lines G22 and G23 to change the luminance of the pixels of the 22nd and 23rd lines of the display panel PNL . The luminance variation of the second line appears every time the display periods Td1, Td2, and Td3 are resumed, and thus appears as one pixel block period.

In order to prevent the luminance fluctuation of the two lines generated when the display period is resumed, the timing controller 20 sets the clock applied to the second transistor of the stages in which the gate pulse is first output when the display period is resumed And holds it at a high logic level during the touch sensor interval. During this touch sensor interval, the other clocks maintain a low logic level. 12, the number in the pulse is the number of the gate lines (G1 to Gn) to which the pulse is applied.

Referring to FIG. 12, the display periods Td1, Td2, and Td3 and the touch sensor periods Tt1, Tt2, and Tt3 are time-divided within one frame period. Assume that the pixel blocks B 1 to B N each include pixels arranged in 19 lines. In this example, one pixel block includes 19 gate lines. During the first display period Td1, the gate shift clocks GCLK1-L to GCLK4-L and GCLK1-R to GCLK4-R are normally generated in one horizontal period to form the first to nineteenth gate lines G1 to G19, The gate pulse is sequentially supplied. During the first touch sensor period Tt1, the gate shift clocks GCLK1-L to GCLK4-L and GCLK1-R to GCLK4-R are maintained at a logic level. During the first touch sensor period Tt1, the right second clock GCLK2-R and the left third clock GCLK3-L are maintained at the high logic level and the other clocks GCLK1-L, GCLK2-L, GCLK4- L, GCLK1-R, GCLK3-R, GCLK4-R) are kept at a logic level. The second clock GCLK2-R on the right side and the third clock GCLK3-L on the left side are supplied to the second transistor T2 of the stages in which the first display period Td1 generates an output at the start thereof, Timing clock.

When the second clock GCLK2-R maintains the high logic level during the first touch sensor period Tt1, the drain of the second transistor T2 of the Nth stage S (N) of the right GIP circuit GIP_R The voltage is held at a high logic voltage so that the gate pulse is maintained at a high voltage. When the second clock GCLK2-R maintains the high logic level during the first touch sensor period Tt1, the Q node Q (N + 1) of the (N + 1) th stage of the right GIP circuit GIP_R (N + 1)) voltage is maintained at a high logic level so that the output of the (N + 1) th stage S (N + 1) does not fluctuate. When the third clock GCLK3-L maintains a high logic level during the first touch sensor period Tt1, the second transistor (N + 1) of the N + 1th stage S (N + 1) of the left GIP circuit GIP_L The gate pulse is maintained at the high voltage from the (N + 1) th stage S (N + 1) since the drain voltage of the node Q2 is maintained at the high logic voltage and the voltage of the Q node Q . When the third clock GCLK3-L maintains a high logic level during the first touch sensor period Tt1, the Q node Q of the N + 2th stage S (N + 2) of the left GIP circuit GIP_L (N + 2)) voltage is maintained at a high logic level so that the output of the (N + 1) th stage S (N + 1) does not fluctuate.

When the second display period Td2 is resumed, the gate shift clocks GCLK1-L to GCLK4-L and GCLK1-R to GCLK4-R are normally generated in one horizontal period and the 20th to 38th gate lines G20, 38 sequentially output gate pulses. Therefore, the I-th clock supplied to the second transistor (T2) of the I-stage connected to the I-th gate line (I is a positive integer equal to or greater than two) Maintaining the logic level can prevent abnormal output of the (I + 1) th stage when the display interval is resumed.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

DIS: Display panel TSP: Touch screen
12: Data driving circuit 14: Gate driving circuit
20: timing controller 30: touch sensing circuit
32: Tx driving unit 34: Rx sensing unit
36: algorithm executing section 38: timing generating section

Claims (5)

A display panel including a pixel array and touch sensors;
A gate drive circuit including shift registers to which stages are connected in a dependent manner; And
And a timing controller for supplying a gate start pulse and a gate shift clock to the gate driving circuit to control the gate driving circuit,
During one frame period, the pixel arrays and the touch sensors of the display panel are divided into a plurality of blocks, and a touch sensor section in which a touch sensor block is driven is allocated between display periods in which pixel blocks are driven,
The timing controller includes:
The I-th clock of the gate shift clock supplied to the pull-up transistor of the I-stage connected to the I-th gate line (I is a positive integer equal to or greater than 2) gate line in which the display period starts is maintained at the high logic level during the touch sensor interval Wherein the touch sensor is a touch sensor. The method according to claim 1,
The timing controller includes:
And maintains the clocks other than the I-th clock at a low logic level in the gate shift clock during the touch sensor interval. The method according to claim 1,
The timing controller includes:
And the gate shift clock is generated in one horizontal period period during the display period. A gate drive circuit including a shift register to which stages are connected in a connected manner, and a timing control circuit for supplying a gate start pulse and a gate shift clock to the gate drive circuit to control the gate drive circuit A method of controlling a gate drive circuit of a display device having touch sensors including a controller,
In one frame period, the pixel arrays and the touch sensors of the display panel are divided into a plurality of blocks and driven, and a touch sensor section in which a touch sensor block is driven is allocated between display periods in which pixel blocks are driven ; And
The I-th clock of the gate shift clock supplied to the pull-up transistor of the I-stage connected to the I-th gate line (I is a positive integer equal to or greater than 2) gate line in which the display period starts is maintained at the high logic level during the touch sensor interval The method of claim 1, further comprising the steps of: 5. The method of claim 4,
Maintaining the I-th clock of the gate shift clock at the high logic level during the touch sensor interval comprises:
And maintaining the clocks other than the I-th clock at a low logic level in the gate shift clock during the touch sensor interval.
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