KR20140072358A - Method of manufacturing semiconductor devices - Google Patents

Method of manufacturing semiconductor devices Download PDF

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Publication number
KR20140072358A
KR20140072358A KR1020120138888A KR20120138888A KR20140072358A KR 20140072358 A KR20140072358 A KR 20140072358A KR 1020120138888 A KR1020120138888 A KR 1020120138888A KR 20120138888 A KR20120138888 A KR 20120138888A KR 20140072358 A KR20140072358 A KR 20140072358A
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South Korea
Prior art keywords
film
holes
forming
mold film
trenches
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KR1020120138888A
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Korean (ko)
Inventor
송주학
김지용
박우현
신효진
정영진
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삼성전자주식회사
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Priority to KR1020120138888A priority Critical patent/KR20140072358A/en
Publication of KR20140072358A publication Critical patent/KR20140072358A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method of manufacturing a semiconductor device is provided. A contact mold film is formed on the substrate, and first holes are formed through the contact mold film. A wiring mold film is formed on the contact mold film so that a first air gap is formed in the first holes. Thereby forming trenches exposing the first holes in the wiring mold film. After forming the trenches, the wiring mold film which is interposed in the first holes and defines the first air gap is continuously etched to form second holes. Within the trenches and the second holes, wirings and contacts connected to the respective wirings are formed.

Description

[0001] METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES [0002]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device including wiring structures.

Due to their small size, versatility and / or low manufacturing cost, semiconductor devices are becoming an important element in the electronics industry. Semiconductor devices can be classified into a semiconductor memory element for storing logic data, a semiconductor logic element for processing logic data, and a hybrid semiconductor element including a memory element and a logic element.

BACKGROUND ART [0002] With the recent trend toward higher speed and lower power consumption of electronic devices, semiconductor devices embedded therein require fast operation speed and / or low operating voltage. Semiconductor devices are becoming more highly integrated to meet these requirements. As the degree of integration of semiconductor devices increases, the reliability of semiconductor devices may deteriorate. However, as the electronics industry is highly developed, the demand for high reliability of semiconductor devices is increasing. Therefore, much research has been conducted to improve the reliability of semiconductor devices.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device having excellent reliability and a manufacturing method thereof.

It is another object of the present invention to provide a semiconductor device optimized for high integration and a manufacturing method thereof.

A method of manufacturing a semiconductor device according to the present invention includes: forming a contact mold film on a substrate; forming first holes passing through the contact mold film; forming a first air gap in the first holes; Forming a wiring mold film on the contact mold film so as to form the trenches exposing the first holes in the wiring mold film; forming trenches in the wiring mold film after the trenches are formed; And forming second holes by successively etching the wiring mold film defining the first air gap, and forming wirings and contacts connected to the wirings within the trenches and the second holes ≪ / RTI >

According to one embodiment, forming the contact mold film comprises sequentially depositing a first film and a second film on the substrate, the second film comprising a material having an etch selectivity relative to the first film .

According to one embodiment, the wiring mold film may comprise a material having an etch selectivity relative to the second film.

According to one embodiment, the trenches may be formed to expose the second film.

According to one embodiment, forming the trenches comprises forming mask patterns extending in the first direction on the wiring mold film and spaced apart in the second direction, and forming the mask patterns using the mask patterns as an etch mask And etching the wiring mold film until the second film is exposed, wherein the etching process may be performed under conditions having an etch selectivity with respect to the second film.

According to one embodiment, forming the second holes may comprise performing an etch process having an etch selectivity to the second film.

According to one embodiment, forming the wires and the contacts includes forming a conductive film on the substrate to fill the trenches and the second holes, and planarizing the conductive film until the wiring mold film is exposed, Lt; / RTI >

According to one embodiment, the conductive film may include tungsten.

The method of manufacturing a semiconductor device according to the present invention further includes forming an upper interlayer dielectric film on the wirings so as to selectively remove an upper portion of the wiring mold film and to form a second air gap between the wirings .

According to one embodiment, the second air gap may extend parallel to the wires.

According to the concept of the present invention, by forming an air gap inside the holes including the region in which the contacts are to be formed, the contacts can be easily formed in a subsequent process. Further, as the interconnects and the contacts connected thereto are formed at the same time, defects due to misalignment of interconnects and contacts can be minimized. Therefore, a semiconductor device having excellent reliability and optimized for high integration can be provided.

1A is a plan view of a semiconductor device according to an embodiment of the present invention.
1B is a cross-sectional view taken along line I-I 'of FIG. 1A.
1C is a cross-sectional view taken along line II-II 'in FIG. 1A.
2A to 8A are plan views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
Figs. 2B to 8B are sectional views taken along the line I-I 'in Figs. 2A to 8A, respectively.
Figs. 2C to 8C are cross-sectional views along II-II 'of Figs. 2A to 8A, respectively.
9 is a schematic block diagram showing an example of an electronic device including a semiconductor device according to the concept of the present invention.
10 is a schematic block diagram showing an example of a memory card having a semiconductor device according to the concept of the present invention.

In order to fully understand the structure and effects of the present invention, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described below, but may be embodied in various forms and various modifications may be made. It will be apparent to those skilled in the art that the present invention may be embodied in many other specific forms without departing from the spirit or essential characteristics thereof.

In this specification, when an element is referred to as being on another element, it may be directly formed on another element, or a third element may be interposed therebetween. Further, in the drawings, the thickness of the components is exaggerated for an effective description of the technical content. The same reference numerals denote the same elements throughout the specification.

Embodiments described herein will be described with reference to cross-sectional views and / or plan views that are ideal illustrations of the present invention. In the drawings, the thicknesses of the films and regions are exaggerated for an effective description of the technical content. Thus, the regions illustrated in the figures have schematic attributes, and the shapes of the regions illustrated in the figures are intended to illustrate specific types of regions of the elements and are not intended to limit the scope of the invention. Although the terms first, second, third, etc. in the various embodiments of the present disclosure are used to describe various components, these components should not be limited by these terms. These terms have only been used to distinguish one component from another. The embodiments described and exemplified herein also include their complementary embodiments.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. The terms "comprises" and / or "comprising" used in the specification do not exclude the presence or addition of one or more other elements.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1A is a plan view of a semiconductor device according to an embodiment of the present invention, and FIGS. 1B and 1C are cross-sectional views taken along the line I-I 'and II-II' of FIG. 1A, respectively.

1A to 1C, a lower interlayer dielectric layer 103 may be disposed on a substrate 100, and a contact mold layer 110 may be disposed on the lower interlayer dielectric layer 103. Referring to FIG. The substrate 100 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The lower interlayer dielectric layer 103 may be a single layer or a multi-layer, and may include an oxide, a nitride, and / or an oxynitride. The contact mold film 110 may include a first film 105 on the lower interlayer dielectric film 103 and a second film 107 on the first film 105. The second film 107 may include a material having an etch selectivity to the first film 105. The first film 105 may comprise an oxide and the second film 107 may comprise nitride. For example, the first film 105 may include PE-TEOS (Plasma Enhanced-Tetraethylorthosilicate), and the second film 107 may include SiN. The second film 107 may have a relatively thinner thickness than the first film 105.

Wires 150 spaced in a second direction (e.g., the Y direction) that intersect the first direction and extend in a first direction (e.g., the X direction) are arranged on the contact mold film 110 . 1B and 1C show Z-Y cross-section and Z-X cross-section, respectively, in a third direction (for example, the Z direction) perpendicular to both the first and second directions. In the contact mold film 110, the contacts 160 connected to the wirings 150 may be disposed. Each of the contacts 160 may extend from the portion of the lower surface of each of the wirings 150 toward the substrate 100 and penetrate the contact mold film 110. The contacts 160 and the wires 150 connected to each other can form a single body. That is, the contacts 160 and the wirings 150 may be in contact with each other without an interface.

According to one embodiment, the conductive pillars 104 may be disposed in the lower interlayer dielectric film 103. Each of the contacts 160 may be connected to the conductive pillar 104. The conductive pillars 104 may be connected to the substrate 100 through the lower interlayer dielectric layer 103. Although not shown, the substrate 100 may include transistors, and the conductive pillars 104 may be connected to source / drain regions or gate patterns of the transistors. According to another embodiment, the lower interconnection lines may be disposed in the lower interlayer dielectric film 103, unlike those shown in Figs. 1A to 1C. Each of the lower wirings may be disposed between each of the conductive pillar 104 and each of the contacts 160.

According to one embodiment, as shown in FIG. 1A, the contacts 160 connected to the interconnections 150 adjacent to each other may be spaced apart in the first direction (e.g., the X direction). Each of the contacts 160 may include a first sidewall S1 and a second sidewall S2 extending from a portion of the sidewalls of the respective wirings 150. [ The first sidewall S1 may form one plane with one side wall S3 of each of the wirings 150 in a direction perpendicular to the substrate 100. [ The second side wall S2 may have a round shape. However, the shapes of the first sidewall S1 and the second sidewall S2 are not limited thereto, and may have various shapes.

The conductive pillars 104 may include a conductive material. For example, the conductive material may be a doped semiconductor (ex, doped silicon, etc.), a metal (ex, tungsten, etc.), a conductive metal nitride (ex, titanium nitride or tantalum nitride), a transition metal (ex, And the like), and a conductive metal-semiconductor compound (ex, metal silicide, etc.). 1A to 1C, when the lower interconnection lines are disposed in the lower interlayer dielectric film 103, the lower interconnection lines may include a conductive material as described above.

The contacts 160 may include the same conductive material as the wires 150. For example, the contacts 160 and the wires 150 may include a metal such as tungsten (W).

The upper interlayer dielectric layer 130 may be disposed on the wirings 150. A first air gap 200 formed between a pair of adjacent wirings 150 may be disposed in the upper interlayer dielectric film 130. The first air gap 200 may extend parallel to the wirings 150. The upper ILD layer 130 may be a single layer or a multilayer and may include an oxide. For example, the upper interlayer dielectric layer 130 may include PE-TEOS.

According to one embodiment, a wiring mold film 120 may be disposed between the upper interlayer dielectric film 130 and the contact mold film 110. The wirings 150 may be connected to the contacts 160 through the wiring mold film 120. The wiring mold film 120 may be disposed between the contact mold film 110 and the contacts 160. However, according to another embodiment, the wiring mold film 120 is not interposed between the upper interlayer dielectric film 130 and the contact mold film 110, unlike the one shown in FIGS. 1A to 1C, And may be interposed only between the mold film 110 and the contacts 160. The wiring mold film 120 may include an oxide, for example, the oxide may be PE-TEOS.

2A to 8A are plan views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. Figs. 2B to 8B are cross-sectional views taken along the line I-I 'in Figs. 2A to 8A, and Figs. 2C to 8C are cross-sectional views according to II-II' in Figs. 2A to 8A, respectively.

2A through 2C, a lower interlayer dielectric layer 103 may be formed on a substrate 100, and a contact mold layer 110 may be formed on the lower interlayer dielectric layer 103. Referring to FIG. The substrate 100 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The lower interlayer dielectric layer 103 may be formed as a single layer or a multilayer, and may include an oxide, a nitride, and / or an oxynitride. The conductive pillars 104 may be formed in the lower interlayer dielectric layer 103. The conductive pillars 104 may be connected to the substrate 100 through the lower interlayer dielectric layer 103. The conductive pillars 104 may include a conductive material. For example, the conductive material may be a doped semiconductor (ex, doped silicon, etc.), a metal (ex, tungsten, etc.), a conductive metal nitride (ex, titanium nitride or tantalum nitride), a transition metal (ex, And the like), and a conductive metal-semiconductor compound (ex, metal silicide, etc.).

The contact mold film 110 may include a first film 105 on the lower interlayer dielectric film 103 and a second film 107 on the first film 105. The second film 107 may be formed of a material having an etch selectivity with respect to the first film 105. The first film 105 may comprise an oxide and the second film 107 may comprise nitride. For example, the first film 105 may include PE-TEOS (Plasma Enhanced-Tetraethylorthosilicate), and the second film 107 may include SiN. The first and second films 105 and 107 may be formed by a chemical vapor deposition (CVD) method.

Referring to FIGS. 3A to 3C, the first holes 111 may be formed in the contact mold film 110. Specifically, first mask patterns (not shown) may be formed on the second film 107. The first mask patterns may define a region where the first holes 111 are to be formed. In one example, the first mask patterns may comprise a photoresist. The first holes 111 may be formed by successively etching the second film 107 and the first film 105 using the first mask patterns as an etching mask. The first holes 111 may be formed to expose upper surfaces of the conductive pillars 104. Thereafter, the first mask patterns may be removed using an ashing process or the like.

4A to 4C, a wiring mold film 120 may be formed on the contact mold film 110 such that a second air gap 113 is formed in each of the first holes 111 have. The wiring mold film 120 may fill a part of the first holes 111. The second air gap 113 may be defined by the wiring mold film 120 filling a part of the first holes 111. The second air gap 113 may be surrounded by the wiring mold film 120. The wiring mold film 120 may include a material having an etch selectivity with respect to the second film 107. The wiring mold film 120 may include an oxide, for example, PETEOS. The wiring mold film 120 may be formed under a condition with low step coverage. The wiring mold film 120 may be formed by a chemical vapor deposition (CVD) method, for example.

5A to 5C, trenches 125 (for example, Y direction) extending in the first direction (e.g., the X direction) and spaced apart from the wiring mold film 120 in the second direction May be formed. The trenches 125 may define an area where wirings are to be formed. Specifically, second mask patterns (not shown) may be formed on the wiring mold film 120 to define regions where the trenches 125 are to be formed. For example, the second mask patterns may be a photoresist pattern or a hard mask pattern. The trenches 125 may be formed by etching the wiring mold film 120 using the second mask patterns as an etching mask. During the etching process, the second film 107 may be used as an etch stop layer. The trenches 125 may be formed to expose the second film 107 and the first holes 111.

After the trenches 125 are formed, second trenches 115 may be formed in the contact mold film 110 to extend downward from a portion of the lower surface 125L of each trench 125. The second holes 115 may define an area where the contacts are to be formed. Specifically, after the trenches 125 are formed, a portion of the first holes 111 may be filled and the wiring mold film 120 defining the second air gap 113 may be continuously etched . During the etching process, a part of the wiring mold film 120 may remain in the first holes 111. [ The etch process may be performed under conditions having etch selectivity with respect to the second film 107. The second holes 115 may be formed to expose the upper surface of the conductive pillars 104. The second holes 115 that expose the upper surface of the conductive pillars 104 can be easily formed by the second air gap 113 formed in the first holes 111. [ Accordingly, in the subsequent process, the contacts formed in the second holes 115 are easily connected to the lower conductive pillars 104, so that a semiconductor device having excellent reliability can be realized. The second holes 115 extending downward from a portion of the lower surface 125L of the trenches 125 are formed simultaneously with the trenches 125 so that the trenches 125 And the misalignment of the wirings and contacts formed in the second holes 115 can be minimized. Thus, a semiconductor device optimized for high integration can be realized.

Referring to FIGS. 6A to 6C, a conductive film 140 may be formed on the substrate 100. The conductive layer 140 may be formed to fill the second holes 115 and the trenches 125. The conductive layer 140 may be formed by a chemical vapor deposition (CVD) method. The conductive layer 140 may include a conductive material. For example, the conductive layer 140 may include a metal such as tungsten (W).

Referring to FIGS. 7A to 7C, contacts 160 may be formed in the second holes 115, and wirings 150 may be formed in the trenches 125 at the same time. Specifically, the conductive film 140 may be planarized by performing a chemical mechanical polishing (CMP) process on the conductive film 140. The polishing process may be performed until the wiring mold film 120 is exposed. Accordingly, the wirings 150 and the contacts 160 connected to the wirings 150 can be simultaneously formed. Each of the contacts 160 extends downward from a portion of the lower surface of each of the wirings 150 and can be connected to the respective conductive pillars 104 through the contact mold film 110. The contacts 160 and the wires 150 connected to each other can form a single body. That is, the contacts 160 and the wirings 150 may be in contact with each other without an interface.

 8A to 8C, the upper portion of the wiring mold film 120 may be selectively removed. For example, the wiring mold film 120 may be removed by a dry etching process. The etch process may be performed under conditions having etch selectivity with respect to the second film 107. According to one embodiment, the etching process may be performed until a part of the wiring mold film 120 remains on the contact mold film 110. However, according to another embodiment, unlike the one shown in FIG. 8B, the etching process can be performed until the second film 107 is exposed. In this case, the wiring mold film 120 may remain in the first hole 111 only.

1A to 1C, an upper interlayer dielectric film 130 may be formed on the wirings 150 such that a first air gap 200 is formed between the wirings 150 adjacent to each other. have. The first air gap 200 may be surrounded by the upper ILD layer 130. The first air gap 200 may extend parallel to the wirings 150. The upper interlayer dielectric layer 130 may include an oxide, for example, PETEOS. The upper ILD layer 130 may be formed under a condition with low step coverage. The upper interlayer dielectric layer 130 may be formed by a chemical vapor deposition (CVD) method, for example. As the first air gap 200 is formed between the wirings 150 adjacent to each other, the parasitic capacitance between the wirings 150 adjacent to each other can be minimized. Accordingly, a signal delay due to the parasitic capacitance of the wirings 150 can be minimized, and a semiconductor device having excellent reliability can be realized. In addition, since the parasitic capacitance is minimized by the first air gap 200, the interval between the wirings 150 can be minimized. Thus, a semiconductor device optimized for high integration can be realized.

According to the concept of the present invention, the second holes 115 formed by the second air gap 113 formed inside the first holes 111 can be easily formed. Accordingly, the contacts formed in the second holes 115 in the subsequent process can be easily connected to the lower conductive pillars 104, thereby realizing a semiconductor device having excellent reliability. In addition, as the second holes 115 are formed at the same time as the trenches 125, misalignment (misalignment) of wirings and contacts formed in the trenches 125 and the second holes 115 in a subsequent process ) Can be minimized. Thus, a semiconductor device optimized for high integration can be realized.

9 is a schematic block diagram showing an example of an electronic device including a semiconductor device according to the concept of the present invention.

9, an electronic device 1100 according to the inventive concept includes a controller 1110, an input / output device 1120, a memory device 1130, an interface 1140, and a bus 1150 , bus). The controller 1110, the input / output device 1120, the storage device 1130, and / or the interface 1140 may be coupled to each other via the bus 1150. The bus 1150 corresponds to a path through which data is moved.

The controller 1110 may include at least one of a microprocessor, a digital signal process, a microcontroller, and logic elements capable of performing similar functions. The input / output device 1120 may include a keypad, a keyboard, a display device, and the like. The storage device 1130 may store data and / or instructions and the like. The storage device 1130 may include a semiconductor device according to the concept of the present invention. Further, the storage device 1130 may further include other types of semiconductor memory devices (ex, a DRAM device and / or an SRAM device, etc.). The interface 1140 may perform functions to transmit data to or receive data from the communication network.

The electronic device 1100 can be a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a digital A music player, a digital music player, a memory card, or other electronic product.

10 is a schematic block diagram showing an example of a memory card having a semiconductor device according to the concept of the present invention.

Referring to FIG. 10, the memory card 1200 includes a storage device 1210. The storage device 1210 may include a semiconductor device according to the concept of the present invention. Further, the storage device 1210 may further include other types of semiconductor memory devices (ex, a DRAM device and / or an SRAM device, etc.). The memory card 1200 may include a memory controller 1220 that controls exchange of data between a host 1230 and the storage device 1210.

The foregoing description of embodiments of the present invention provides illustrative examples for the description of the present invention. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention as defined by the appended claims. It is clear.

100: substrate 111: first contact holes
103: lower interlayer dielectric film 113: second air gap
104: Challenge Pillars 125: Trenches
105: first film 125L: bottom surface of the trenches
107: Second film 140: Conductive film
110: contact mold film
120: wiring mold film
130: upper interlevel dielectric layer
150: Wiring
160: contacts
200: first air gap

Claims (10)

Forming a contact mold film on the substrate;
Forming first holes through the contact mold film;
Forming a wiring mold film on the contact mold film so that a first air gap is formed in the first holes;
Forming trenches exposing the first holes in the wiring mold film;
After forming the trenches, successively etching the wiring mold film which is interposed in the first holes and defines the first air gap to form second holes; And
And forming wirings and contacts connected to the respective wirings within the trenches and the second holes. The method according to claim 1,
Forming the contact mold film comprises depositing a first film and a second film in sequence on the substrate,
Wherein the second film comprises a material having an etch selectivity relative to the first film. The method of claim 2,
Wherein the wiring mold film includes a material having an etch selectivity with respect to the second film. The method of claim 2,
Wherein the trenches are formed to expose the second film. The method of claim 2,
Forming the trenches comprises:
Forming mask patterns extending in the first direction on the wiring mold film and spaced apart in the second direction; And
And etching the wiring mold film using the mask patterns as an etching mask until the second film is exposed,
Wherein the etching process is performed under the condition that the etch selectivity is selected for the second film. The method of claim 2,
Wherein forming the second holes comprises performing an etching process with an etch selectivity ratio to the second film. The method according to claim 1,
Forming the wires and the contacts comprises:
Forming a conductive film on the substrate to fill the trenches and the second holes; And
And planarizing the conductive film until the wiring mold film is exposed. The method of claim 7,
Wherein the conductive film comprises tungsten. The method according to claim 1,
Selectively removing an upper portion of the wiring mold film; And
Further comprising forming an upper interlayer dielectric film on the wirings so that a second air gap is formed between the wirings. The method of claim 9,
And the second air gap extends in parallel with the wirings.
KR1020120138888A 2012-12-03 2012-12-03 Method of manufacturing semiconductor devices KR20140072358A (en)

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