KR20140066397A - Light emitting diode having a plurality of light emitting units - Google Patents

Abstract

Disclosed is a light emitting diode (LED) having a plurality of unit light emitting elements. The LED comprises a substrate; the unit light emitting elements disposed on the substrate; and multiple wiring connecting the unit light emitting elements, wherein the unit light emitting elements include unit light emitting elements of a parallelogram shape with two acute angles and two obtuse angles. The present invention can reduce the loss of the light generated from the side of the unit light emitting elements by mounting the unit light emitting elements of a parallelogram shape. Furthermore, disclosed is a technique for improving light extraction efficiency by forming an uneven pattern having fine irregularities on the substrate.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a light emitting diode (LED) having a plurality of unit light emitting elements

The present invention relates to a light emitting diode, and more particularly, to a light emitting diode having a plurality of unit light emitting elements in a parallelogram shape.

The light emitting diode is widely used as a display element and a backlight, and consumes less power and has a longer life than a conventional bulb or a fluorescent lamp. Thus, the light emitting diode is used as a general illumination application instead of an incandescent lamp and a fluorescent lamp.

Generally, since the light emitting diode is driven when the forward current flows, it is repeatedly turned on / off according to the direction of the current under the alternating current power supply. Therefore, when the light emitting diode is directly connected to the AC power source, the light emitting diode does not emit light continuously, and is easily damaged by the reverse current. Furthermore, since a single light emitting diode is driven under a constant forward voltage, it can not be driven under a high voltage.

In recent years, light emitting diodes for solving the problems of such light emitting diodes and driving them under a high voltage AC power supply have been developed. Such a light emitting diode generally includes a plurality of unit light emitting elements having a substantially square or rectangular shape, and these unit light emitting elements can be driven at a high voltage by being connected in series by wiring. Also, it is possible to provide a light emitting diode which can be driven under AC power by connecting a series array of unit light emitting elements to a rectifying circuit such as a bridge rectifier.

However, conventional light emitting diodes having a plurality of unit light emitting elements are not relatively high in light efficiency, and efforts to improve light efficiency are continuously required.

On the other hand, in order to increase the light extraction efficiency, a method of forming a concavo-convex pattern on a substrate, such as a patterned sapphire substrate (PSS), and growing a semiconductor layer on the concavo- Open Patent Publication No. 2011-0024762). However, the formation of such concave-convex patterns alone has a limitation in increasing the light extraction efficiency.

It is an object of the present invention to provide a light emitting diode having improved light extraction efficiency.

Another object of the present invention is to provide a light emitting diode capable of increasing light efficiency in a light emitting diode including a plurality of unit light emitting elements.

Another object of the present invention is to provide a light emitting diode capable of reducing light loss caused by components of a light emitting diode.

A light emitting diode according to embodiments of the present invention includes: a substrate; A plurality of unit light emitting elements positioned on the substrate; And wires connecting the plurality of unit light emitting elements, wherein the plurality of unit light emitting elements include unit light emitting elements having a parallelogram shape and having two acute angles and two obtuse angles.

In the present specification, "parallelogram shape" is a shape having an acute angle and an obtuse angle, unlike a rectangle, and the angular portion and the obtuse angle are rounded. In particular, the acute angle portion can be rounded to have a larger curvature than the dull corner portion.

Since the unit light emitting elements have a rectangular shape and a parallelogram shape other than that of the unit light emitting elements, it is possible to reduce the light loss generated from the side of the unit light emitting element, further reduce the optical interference between the unit light emitting elements, .

The plurality of unit light emitting elements may further include a unit light emitting element having a triangular shape. The unit light emitting device having a triangular shape can also reduce light loss generated from the side surface of the unit light emitting device.

In a specific embodiment, the plurality of unit light emitting elements may comprise six parallelogram unit light emitting elements and one triangle unit light emitting element. Further, the six parallelogram unit light emitting elements are arranged in two rows, and the unit light emitting elements of the first column and the unit light emitting elements of the second column may be arranged to have a mirror surface symmetry structure with each other. In addition, the triangular unit light emitting device may be disposed over the first row and the second row near one edge of the substrate.

The light emitting diode includes: a first electrode pad disposed in a first column; And a second electrode pad disposed in the second column. The first and second electrode pads may be disposed near the other edge opposite to one edge of the substrate on which the triangular unit light emitting device is disposed.

Meanwhile, the unit light emitting elements of the first row and the unit light emitting elements of the second column may be arranged parallel to each other.

One side of the triangular unit light emitting element is parallel to one side of the unit light emitting element in the first row and the other side of the triangle unit light emitting element is parallel to one side of the unit light emitting element in the second row And the remaining sides of the triangular-shaped unit light-emitting device may be parallel to one edge of the substrate.

In some embodiments, the substrate has a concavo-convex pattern having a convex portion on the upper surface and a concave portion defined by the convex portion, and the concavo-convex pattern in a part of the concavo-convex pattern may have fine concavities and convexities on its surface . The fine concavities and convexities may be irregularly formed, but the present invention is not limited thereto and may be formed regularly. The light extraction efficiency can be increased by the concavo-convex pattern provided with the fine irregularities.

The concavo-convex pattern having fine irregularities on the surface can be disposed in the separation groove separating the unit light emitting elements. The concavo-convex pattern disposed in the separation groove helps extract light within the substrate and also diffuses the light emitted from the unit light emitting elements and directed to the substrate, thereby improving light extraction efficiency.

Further, the unit light emitting devices may include a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer, and the unit light emitting devices may be formed by etching the second conductivity type semiconductor layer and the active layer, And a mesa etching region for exposing the semiconductor layer, and the concave-convex pattern located under the mesa etching region may have fine concavities and convexities on its surface. The concavo-convex pattern located under the mesa etching region has micro-irregularities on the surface thereof, thereby improving the light extraction efficiency of the light emitting diode by further irregularly reflecting light traveling toward the substrate side.

In some embodiments, the convex portion of the concavo-convex pattern may have a side surface including a plurality of crystal planes and a top corner vertex in which at least a part of the side surfaces meet. Further, the side surfaces may have lower side surfaces which are first crystal faces and upper side faces which are second crystal faces, and the upper vertex may be made to meet with the second crystal faces. The inclined angle formed by the second crystal face with the substrate surface is smaller than the inclined angle formed by the first crystal face with the substrate surface.

On the other hand, the convex portion may have the form of a stripe or an island. In particular, the convex portion has the shape of an island, the bottom surface of the convex portion has a pseudo-triangular shape, and each line segment may be a curved surface protruding outward.

In some embodiments, the convex portion of the concave-convex pattern may have side faces that are crystal faces and a flat upper face. The convex portion of the concavo-convex pattern may have a lower side and an upper side having different inclination angles. Further, the convex portion of the concavo-convex pattern may have a lower side, an intermediate side, and an upper side, and the adjacent sides may have different inclination angles.

The plurality of unit light emitting elements may be connected in series by wires.

The light emitting diode may further include a first electrode and a second electrode disposed on the unit light emitting devices. Each unit light emitting device includes a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer. The first electrode is electrically connected to the first conductivity type semiconductor layer, And may be electrically connected to the second conductivity type semiconductor layer. The wiring may connect a first electrode of one unit light emitting device and a second electrode of another unit light emitting device adjacent to the first electrode.

The second electrode may have a curved shape. One end of the second electrode may be located close to the corner portion, and the other end may be located near the dull corner. At this time, the second electrode may be arranged in a curved shape, and the other end closer to the obtuse angle may be farther away from the edge than the one end near the obtuse angle. By forming the second electrode in a curved shape, it is possible to improve the current dispersion characteristic in the unit light emitting device and improve the light emitting efficiency.

At least one of the first conductivity type semiconductor layer, the active layer, and the second conductivity type semiconductor layer may be inclined at an angle of less than 90 degrees with respect to the substrate surface. Accordingly, optical interference or light absorption between the unit light emitting elements can be further reduced.

A method of manufacturing a light emitting diode according to embodiments of the present invention includes providing a substrate, forming a laminate including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer on the substrate, To form a plurality of unit light emitting elements. Here, the unit light emitting devices include unit light emitting devices having a parallelogram shape with two acute angles and two obtuse angles.

Furthermore, providing the substrate may include forming a concavo-convex pattern on the upper surface of the substrate, the concavo-convex pattern including a convex portion and concave defined by the convex portion, And forming fine irregularities. The fine concavities and convexities may be irregularly formed, but the present invention is not limited thereto and may be formed regularly.

The formation of the fine irregularities may be performed after patterning the laminate. Alternatively, the fine irregularities may be performed before patterning the laminate.

According to still another embodiment of the present invention, there is provided a light emitting diode comprising: a substrate; And a plurality of unit light emitting elements positioned on the substrate. Here, the plurality of unit light emitting elements include unit light emitting elements having parallel acute angular shapes having two acute angles and two obtuse angles, and the substrate has a concavo-convex pattern having a convex portion on the upper surface and a concave portion defined by the convex portion And the concavo-convex pattern in a part of the concavo-convex pattern may have fine irregularities on its surface.

The light emitting diode may further include an insulating film covering the plurality of light emitting devices and the concavo-convex pattern on the substrate.

On the other hand, the concavo-convex pattern having the fine irregularities may be located in a limited region of the substrate in contact with the insulating film. Alternatively, the concavo-convex pattern having the fine concavities and convexities may be additionally disposed below a partial region of the unit light emitting devices in addition to the substrate region to which the insulating film is in contact. Particularly, the partial region may be the mesa etching region.

According to the present invention, the light extraction efficiency of the light emitting diode can be improved by reducing the light loss generated from the sides of the unit light emitting elements by adopting the unit light emitting elements having the parallelogram shape. Furthermore, the light extraction efficiency can be improved by disposing the concavo-convex pattern having fine irregularities in the substrate region between the unit light emitting elements.

1 is a schematic plan view illustrating a light emitting diode according to an embodiment of the present invention.
2 is a schematic cross-sectional view illustrating a light emitting diode according to an embodiment of the present invention.
3 is a schematic plan view for explaining a unit light emitting device having a parallelogram shape.
4A to 4J are cross-sectional views illustrating a method of manufacturing a light emitting diode according to an embodiment of the present invention.
5 to 7 are plan views schematically showing the shapes of the etching mask pattern
to be.
8 is a plan view showing a concavo-convex pattern.
9 is a perspective view showing one convex portion.
FIGS. 10A and 10B are schematic views showing that the light emitted from the active layer is reflected in various directions by the concave-convex pattern in the lower part of the light emitting diode and the concave-convex pattern in the separation area.
11A to 11E are cross-sectional views illustrating a method of fabricating a light emitting diode according to another embodiment of the present invention.
12A to 12D are cross-sectional views illustrating a method for fabricating a light emitting diode according to another embodiment of the present invention.
13A to 13D are cross-sectional views illustrating a method of manufacturing a light emitting diode according to another embodiment of the present invention.
15A to 15D are cross-sectional views illustrating a method for fabricating a light emitting diode according to another embodiment of the present invention.
16A to 16D are cross-sectional views illustrating a method of manufacturing a light emitting diode according to another embodiment of the present invention.
Figs. 17 and 18 are SEM cross-sectional photographs after the epitaxial layer was grown on the concavo-convex pattern produced according to the concavo-convex pattern production example 1 and the production example 2, respectively.
Figs. 19A to 19C are SEM photographs showing a substrate having a concavo-convex pattern manufactured according to the concavo-convex pattern production example 4. Fig.
Fig. 20 is a schematic view showing a light emitting device according to a second embodiment of the present invention,
FIG. 2 is a graph illustrating the output of the light emitting diodes of FIG.
Figs. 21A to 21B are SEM photographs showing a substrate having a concavo-convex pattern manufactured according to the concavo-convex pattern production example 5. Fig.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the length, thickness, etc. of layers and regions may be exaggerated for convenience. Like reference numerals designate like elements throughout the specification.

When a layer is referred to herein as being "on" another layer or substrate, it may be located directly on the other layer or substrate, or a third layer between the layer and the other layer or substrate It can be intervened. Also, in this specification, the expression of a spatial direction should be understood in a relative direction, and should not be construed as limiting in the sense of an absolute direction. In addition, the term " first "or" second "in the present specification is not intended to imply any limitation on the components, but should be understood as terms for distinguishing components.

FIGS. 1 and 2 are a schematic plan view and a sectional view for explaining a light emitting diode according to an embodiment of the present invention, and FIG. 3 is a schematic plan view for explaining the unit light emitting device of FIG.

1 to 3, the light emitting diode according to the present embodiment includes a substrate 10, a plurality of unit light emitting devices 100 and 200 (UD), and wirings 46. In addition, the light emitting diode may include first and second electrode pads 300a and 300b. The current spreading conductive layer 44, the first electrodes 100a and 200a, and the second electrodes 100b and 200b may be disposed on the unit light emitting devices 100 and 200, respectively. In addition, the light emitting diode may include a passivation film 43 and a separation insulating film 40.

The substrate 10 is not particularly limited and may be formed of a material such as sapphire (Al 2 O 3), silicon carbide (SiC), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), aluminum nitride Ga2O3), or a silicon substrate. In particular, the substrate 10 may be an insulating substrate such as a sapphire substrate or a conductive substrate having an insulating layer on the upper surface thereof.

The substrate 10 has a generally rectangular shape and may have a rectangular shape as shown. In this specification, the shape of the substrate and the unit light emitting elements, that is, the shapes such as a rectangle, a parallelogram, and a triangle, refers to a shape seen from a plan view. However, as will be appreciated by those skilled in the art, the polygonal shape, such as a triangle, square, or parallelogram, referred to herein, should not be understood to mean only a geometrically perfect polygonal shape, have. For example, each corner of the polygonal shape can be rounded.

The substrate 10 may have a concavo-convex pattern 10a including a concave 10ac and a convex 10av on the upper surface thereof and may have a concavo-convex pattern 10a ) May have fine concavities (P) on its surface. In particular, the concavo-convex pattern 10a on which the fine concavities and convexes P are formed may be divided into regions excluding the lower region of the unit light emitting elements UD, for example, a region for separating the unit light emitting elements UD, ). ≪ / RTI > In addition, as described in other embodiments, the area of the concavo-convex pattern 10a in which fine concavities and convexities are formed may also be located under the mesa etching region R of the unit light emitting devices UD. The fine irregularities P may be irregularly formed, but the present invention is not limited thereto and may be formed regularly.

The plurality of unit light emitting devices UD include unit light emitting devices 100 having a parallelogram shape having two acute angles and two obtuse angles and unit light emitting devices 200 having a triangular shape. As shown in Fig. 1, the unit light emitting elements 100 having parallel acute-angled shape with two acute angles and two obtuse angles can be arranged in two rows, and the same number of parallel-deformed shapes The unit light emitting devices 100 may be arranged.

In the case where the substrate 10 has a rectangular shape, two sides of each of the unit light emitting elements 100 in a parallelogram shape are parallel to two sides of the substrate 10, Is not parallel. As shown in FIG. 3, the unit light emitting device 100 includes a first side (401 in FIG. 3) facing each other and a second side (403 in FIG. 3) facing each other. The unit light emitting devices 100 are arranged on the substrate 10 so that the first sides 401 are parallel to the edge of the substrate 10 and the second sides 403 are not parallel to any edge of the substrate 10. [ ). ≪ / RTI >

3, the obtuse angle? Formed by the first side 401 and the second side 403 may be more than 90 degrees and less than 135 degrees. As the obtuse angle? Increases to 135 degrees, the light extraction efficiency of the light emitting diode is improved. By changing the shape of the unit light emitting device to a parallelogram shape, light loss in each unit light emitting device is reduced, and optical interference between the unit light emitting devices and light loss due to light absorption are reduced. However, when the obtuse angle? Exceeds 135 degrees, it is difficult to evenly distribute the current in the unit light emitting element region. The acute angles and the obtuse angles of the parallelepiped shape light emitting elements can be rounded, and in particular, the acute angles can be rounded to have a larger curvature (1 / radius) than the obtuse angles.

Referring again to FIG. 1, the unit light emitting elements 100 of the first row and the unit light emitting elements 100 of the second row are arranged to have a symmetrical structure with respect to the mirror surface passing through the dotted line L1 perpendicular to the substrate 10 . Here, the contours of the whole unit light-emitting devices having a parallelogram shape are mirror-symmetrical to each other, and it is not necessary that the wiring 46 and the electrodes 100a and 100b have a symmetrical structure. On the other hand, as shown in the figure, the opposing sides of the unit light emitting elements 100 of the first row and the unit light emitting elements 100 of the second row are parallel to each other.

On the other hand, the triangular unit light emitting device 200 may be positioned over the first and second rows. As the unit light emitting elements 100 are arranged in the first column and the second column, a convex contour is formed at one end of each row by the unit light emitting elements 100, and a concave contour is formed at the other end. The triangular unit light emitting device 100 may be disposed near one side edge of the substrate 10 to fill a concave contour.

For example, the triangular unit light emitting device 200 may have an isosceles triangle shape having long sides 201 and two sides 203 having the same length. In this case, the long side 201 may be disposed parallel to one side edge of the substrate 10. One of the sides 203 may be parallel to the second side 103 of the unit light emitting device 100 of the first row and the other may be parallel to the second side 103 of the unit light emitting device 100 of the second row. .

As shown in FIG. 1, the plurality of unit light emitting elements may be composed of six unit light emitting elements 100 in parallelogram shape and one unit light emitting element 200 in triangle shape. However, It is not. For example, it is possible to further increase the number of the unit light emitting elements 100 of the parallelogram shape disposed in each column so that more unit light emitting elements can be arranged in two columns. However, as shown in FIG. 1, a light emitting diode having seven unit light emitting elements is used, and a plurality of same light emitting diodes are electrically connected to each other, so that a light emitting module operating at a high voltage AC power source such as 110V or 220V can be easily Can be configured.

2, the unit light emitting devices UD include a first conductivity type semiconductor layer 23, an active layer 25, and a second conductivity type semiconductor layer 27 and include a buffer layer 21 Or the like. At least one side surface of the first conductivity type semiconductor layer 23, the active layer 25 and the second conductivity type semiconductor layer 27 of each unit light emitting device UD is set at 90 degrees Or less.

The active layer 25 may be a single quantum well structure or a multiple quantum well structure, and its material and composition are selected according to the required emission wavelength. For example, the active layer 25 may be formed of an AlInGaN-based compound semiconductor, such as InGaN. The first and second conductivity type semiconductor layers 23 and 27 are formed of a material having a larger bandgap than that of the active layer 25 and may be formed of an AlInGaN-based compound semiconductor, for example, GaN.

As shown in the figure, the second conductivity type semiconductor layer 27 is located above a partial region of the first conductivity type semiconductor layer 23, and the active layer 25 is located above the second conductivity type semiconductor layer 27 and the first Type semiconductor layer 23. The conductive-type semiconductor layer 23 is formed of a conductive material. Further, a current spreading conductive layer, for example, a transparent electrode layer 44, may be placed on the second conductivity type semiconductor layer 27. [ The transparent electrode layer 44 may be formed of a material such as indium tin oxide (ITO) or Ni / Au.

The first conductive semiconductor layer 23 and the second conductive semiconductor layer 27 may be an n-type semiconductor layer and a p-type semiconductor layer, respectively, but vice versa. The first electrodes 100a and 200a are positioned on the first conductivity type semiconductor layer 23 and the second electrodes 100b and 200b are located on the second conductivity type semiconductor layer 27 . The second electrodes 100b and 200b may be formed on the transparent electrode layer 44. [ As shown in FIG. 1, the first electrode 100a and the second electrode 100b are disposed to face each other.

The first electrode 100a may have a straight shape and the second electrodes 100b and 200b may have a curved shape. The second electrode 100b is disposed closer to the corner portion at one end and closer to the corner portion at the other end, and the other end disposed at the corner portion is relatively farther away from the corner than one end disposed at the corner portion . By forming the second electrodes 100b and 200b in a curved shape, the current dispersion characteristics in the unit light emitting device can be improved, thereby improving the luminous efficiency. On the other hand, the wiring 46 is connected to the second electrode 100b while shifting toward the obtuse angle side. As a result, the length of the wiring 46 can be relatively shortened, and the cutoff of the light by the wiring 46 can be reduced.

On the other hand, the first electrode pad 300a and the second electrode pad 300b are disposed on the substrate 10. The first and second electrode pads 300a and 300b may be disposed along the two rows. 1, the first and second electrode pads 300a and 300b are formed on the substrate 10 facing the one side edge of the substrate 10 on which the triangular unit light emitting device 100 is disposed In the present embodiment.

The first and second electrode pads 300a and 300b are formed on the substrate 10 and spaced apart from the unit light emitting devices 300 and 400 on the first conductivity type semiconductor layer 23, May be formed on the layer 27 or on the transparent electrode layer 44. Or the first and second electrode pads 300a and 300b may be disposed on the unit light emitting devices 100 or 200. [ However, by disposing the first and second electrode pads 300a and 300b apart from the unit light emitting devices 100 and 200, it is possible to prevent the light emitted from the unit light emitting devices from being cut off, Can be improved.

The first and second electrode pads 300a and 300b are pads for supplying electric power from an external power source, for example, pads through which a bonding wire can be bonded. The light emitting diode is driven by the electric power applied to the first and second electrode pads 300a and 300b.

The wires 46 electrically connect the adjacent unit light emitting elements 100 and 200 to each other. The wires 46 may connect the adjacent unit light emitting elements 100 and 200 in series. That is, the wires 46 connect the first electrode 100a of one unit light emitting device to the second electrode 100b of the adjacent unit light emitting device. The wiring 46 and the electrodes 100a, 100b, 200a, and 200b may be formed of the same material in the same process. On the other hand, the passivation film 43 covers the transparent electrode layer 44 and exposes the transparent electrode layer 44 in a part thereof. The passivation film 43 may cover the side surface of the unit light emitting device UD exposed in the mesa etching region R. [ The isolation insulating film 40 may cover the upper surface of the substrate 10 exposed in the separation groove G and the side surface of the light emitting elements UD. The isolation insulating film 40 prevents the second conductivity type semiconductor layer 27 and the first conductivity type semiconductor layer 23 from being short-circuited by the wiring 46. The passivation film 43 and the isolation insulating film 40 may be formed of the same material by the same process.

In the present embodiment, the mesa etching region R is formed as being separated from the separation groove G in FIG. 2, but the present invention is not limited thereto. That is, as shown in FIG. 2, protrusions of the semiconductor laminated structure may be interposed between the mesa etching region R and the separation groove G, but the present invention is not limited thereto, (G) may be formed immediately adjacent to the protruded portion of the semiconductor laminated structure. In this case, the length of the wiring 46 can be reduced, and the light absorption by the wiring 46 can be reduced.

Hereinafter, a method of manufacturing a light emitting diode according to embodiments of the present invention will be described.

4A to 4J are cross-sectional views illustrating a method of manufacturing a light emitting diode according to an embodiment of the present invention. 4A to 4E are cross-sectional views illustrating a method of forming a concavo-convex pattern in a substrate, and FIGS. 4F to 4J are cross-sectional views illustrating a method of manufacturing a light emitting diode using a substrate having a concavo-convex pattern.

Referring to FIG. 4A, a substrate 10 is provided. The substrate 10 may be formed of a material selected from the group consisting of Al 2 O 3, SiC, GaN, InGaN, AlGaN, AlN, Silicon substrate. As an example, the substrate 10 may be a sapphire substrate.

An etch mask layer 13 may be formed on the upper surface of the substrate 10. The etch mask layer 13 may be a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. However, the etch mask layer 13 is not limited thereto, but may be a material having an etch selectivity to the substrate 10. A photoresist pattern 17 may be formed on the etch mask layer 13.

Referring to FIG. 4B, the etch mask layer 13 may be wet or dry etched using the photoresist pattern 17 as a mask. As a result, the etching mask pattern 13a can be formed. When the etch mask layer 13 is a silicon oxide layer, the etch mask layer 13 may be etched using HF or BOE (Buffered Oxide Etch).

The etch mask pattern 13a may be formed to have various shapes. As an example, the etch mask pattern 13a may have a stripe shape (FIG. 5) or an island shape of a circle (FIG. 6) or a polygon (FIG. 7), as shown in FIGS. When the unit pattern of the etching mask pattern 13a has an island shape, the unit patterns of the etching mask pattern 13a are arranged such that six unit patterns are surrounded by a hexagon . However, the shape of the etching mask pattern 13a is not limited thereto.

Referring to FIG. 4C, the photoresist pattern 17 may be removed to expose the etch mask pattern 13a. The substrate 10 is first etched using the etching mask pattern 13a as a mask to form a concave and convex pattern 10a including concave 10ac and convex 10av in the upper surface of the substrate 10 10a can be formed. The substrate 10 may be etched using a wet etching method.

The etching solution used for the wet etching may exhibit a different etch rate depending on the crystal orientation of the substrate 10. In other words, the etching solution can preferentially etch the specific crystal orientation of the substrate 10. For example, the etching solution may be a mixed solution of sulfuric acid and phosphoric acid, a mixed solution of nitric acid and phosphoric acid, or a KOH solution when the substrate 10 is a sapphire substrate or a GaN substrate. In the case of a SiC substrate, Oxide Etch) or an HF solution, and in the case of a Si substrate, it may be a KOH solution. As an example, when the substrate 10 is a c-plane sapphire substrate and the etching solution is a mixed solution of sulfuric acid and phosphoric acid in a volume ratio of 3: 1, the c-plane is preferentially etched during the wet etching process . In this case, the bottom surface of the concave portion 10ac and the top surface of the convex portion 10av may be c-planes.

Referring to FIG. 4D, the etching mask pattern 13a is removed to expose the upper surface of the convex portion 10av. The top surface of the convex portion 10av may be planar and facets thereof may have a first inclination angle? 1 with respect to the substrate surface. These aspects may be the first crystal faces. In addition, the inclined angles, that is, the inclination angles of the side surfaces of the convex portion 10av with respect to the substrate surface may be the same or may differ from each other depending on the sides. Further, the bottom surfaces of the concave portions 10ac positioned between the convex portions 10av may be a plane substantially parallel to the substrate surface.

Referring to FIG. 4E, the substrate 10 having the uneven pattern 10a may be secondarily etched. As a result, the convex portion 10av has the lower side faces LF which are the first crystal faces and the upper side faces UF which are the second crystal faces different from the first crystal faces, and the second crystal faces meet, vertex, V).

The secondary etching may also be a wet etching. The etching solution used in the second etching process may be the same as or different from the etching solution used in the first etching process. In the case where the etching solution used in the second etching process is different from the solution used in the first etching process, the crystal surface preferentially etched in the first etching process may be preferentially etched. On the other hand, even when the etching solution used in the second etching process is the same as the solution used in the first etching process, as the bottom surface of the recess 10ac is continuously etched, 10) so that the lower side surfaces LF can be formed.

On the other hand, in the upper region of the convex portion 10av, the first crystal faces already formed in the first etching process are also gradually etched to expose other crystal faces, i.e., the second crystal faces, which form the upper side faces UF . This secondary etching can be performed until all the upper planes of the convex portions 10av are etched and the upper vertex V is formed where the second crystal planes meet (see the dotted line F in Fig. 4D).

The concavo-convex pattern will be described in more detail with reference to Figs. 8 and 9. Fig. Fig. 4E can correspond to the section taken along the section line I-I 'in Fig. 9 is a perspective view showing one convex portion.

Referring to Figs. 4E, 5 and 9, the uneven pattern 10a has a plurality of convex portions 10av and concavities 10ac defined therein. The bottom surface of the concave portions 10ac positioned between the convex portions 10av may be a plane substantially parallel to the substrate surface. The convex portions 10av may have one upper vertex V where a plurality of side faces UF and LF which are crystal faces and at least a part of the side faces UF and LF meet. Specifically, the side faces UF and LF may have lower side faces LF, which are first crystal faces, and upper side faces UF, which are second crystal faces. At this time, the upper vertex V may be formed by the upper side UF. The inclination angle 2 formed between the upper side UF and the substrate surface may be smaller than the inclination angle 1 formed between the lower side LF and the substrate surface.

The convex portion may have a stripe or island shape corresponding to the shape of the etching mask pattern 13a described with reference to FIGS. When the etching mask pattern 13a has a circular or polygonal island shape and particularly has a circular shape, as shown in FIGS. 8 and 9, the lower side faces LF of the convex portion 10av May have the shape of a pseudo triangle, in which each line segment is a curved surface protruding outward. Further, the upper side surfaces UF of the convex portion 10av may have a substantially hexagonal shape as viewed from above.

Referring to FIG. 4F, the buffer layer 21 may be formed on the substrate on which the concavo-convex pattern 10a is formed. In the case where the substrate 10 has a lattice constant different from that of the first conductivity type semiconductor layer, which will be described later, the buffer layer 21 is a layer formed to mitigate lattice mismatch between the substrate 10 and undoped GaN ) Layer.

At this time, since the upper end of the convex portions 10av is a pointed vertex V and the side surfaces UF and LF have a predetermined inclination angle with respect to the substrate surface, On the bottom surfaces, the buffer layer 21 may preferentially grow vertically. Thereafter, the buffer layer 21 grown first on the bottom surfaces of the adjacent recesses 10ac can meet with each other through horizontal growth at the upper portion of the convex portion 10av. Therefore, since the threading dislocation density is reduced at the upper portion of the convex portion 10av, the crystal quality can be improved. Further, there is an effect that the process step is reduced compared with the case of using the conventional ELO (epitaxial lateral overgrowth) method using an epitaxial mask pattern.

In addition, since the plurality of side surfaces UF and LF of the convex portions 10av are crystal planes formed by wet etching, the surface state of the crystal structure is stable, and the lattice of the buffer layer 21 formed thereon Defect generation can be suppressed.

The first conductive semiconductor layer 23 may be formed on the buffer layer 21. The first conductive semiconductor layer 23 may be a nitride-based semiconductor layer doped with an n-type dopant. For example, the first conductivity type semiconductor layer 23 may include a plurality of In _x Al _y Ga _1-xy N (0? X? 1, 0? _Y? 1, x + y? 1) . Thereafter, the active layer 25 may be formed on the first conductive semiconductor layer 23. The active layer 25 may be a layer of In _x Al _y Ga _1-xy N (0 x 1, 0 y 1, 0 x + y 1), and may be a single quantum well structure or a multiple quantum well structure multi-quantum well (MQW). As an example, the active layer 25 may have a single quantum well structure of an InGaN layer or an AlGaN layer, or a multiple quantum well structure of a multilayer structure of InGaN / GaN, AlGaN / (In) GaN, or InAlGaN / . The second conductive semiconductor layer 27 may be formed on the active layer 25. The second conductive semiconductor layer 27 may also be a nitride semiconductor layer or a layer doped with a p-type dopant. For example, the second conductive semiconductor layer 27 may be formed of In _x Al _y Ga _{1 -x- y} N (0? X? 1, 0? _Y? 1, 0? _X + Type may also be a layer doped with Mg or Zn as a fund. Alternatively, the second conductive semiconductor layer 27 may include a plurality of In _x Al _y Ga _{1 -xy} N (0? X? 1, 0? _Y? 1, 0? _X + Layers.

The buffer layer 21, the first conductivity type semiconductor layer 23, the active layer 25 and the second conductivity type semiconductor layer 27 may form a layered structure, (MOCVD), Chemical Vapor Deposition (CVD), Plasma-Enhanced Chemical Vapor Deposition (PECVD), Molecular Beam Epitaxy (MBE), Hydride Vapor Deposition (Hydride Vapor Phase Epitaxy (HVPE)), and the like.

Referring to FIG. 4G, a part of the stacked body is etched until the substrate 10 is exposed to form a separation groove G for separating a plurality of unit light emitting devices UD. The formation of the separation grooves G may be dry etching, for example, plasma etching. If the etch selectivity ratio of the etching gas used in the dry etching is good, the uneven pattern 10a exposed in the separation groove G may remain unetched. The semiconductor laminate is separated into the regions of the unit light emitting device 100 having the parallelogram shape and the region of the unit light emitting device 200 having the triangular shape by the separation groove G as described with reference to FIGS.

4H, a metal film (not shown) is laminated on the side surfaces and the upper surface of the unit light emitting devices UD and the uneven pattern 10a exposed in the separation groove G, So that the metal clusters 34 can be formed. The metal film may have a thickness of several nm to several tens of nm, and may have a thickness of, for example, about 3 nm to about 20 nm, specifically about 10 nm. In addition, the metal film and the metal cluster may be Ni, Al, or Pt. A protective film (not shown) may be optionally formed on the side surfaces and the upper surface of the unit light emitting devices UD before forming the metal film. The protective layer may be a silicon oxide layer or a silicon nitride layer and may prevent the metal layer or the metal clusters from reacting with a side surface or an upper surface of the unit light emitting devices UD.

A photoresist pattern 37 may be formed on the metal clusters 34 to cover the side surfaces and the upper surface of the unit light emitting devices UD. The surface of the relief patterns 10a in the separation groove G can be etched using the photoresist pattern 37 and the metal clusters 34 as a mask. As a result, fine irregularities (P in Fig. 4I) can be formed on the surface of the relief patterns 10a in the separation groove G, specifically, the surface of the convex portions 10av and the surface of the concave portions 10ac have. The etching of the surface of the concavo-convex patterns 10a in the separation groove G can be performed by plasma etching. At this time, the photoresist pattern 37 can prevent the unit light emitting devices UD from being damaged due to plasma.

Referring to FIG. 4I, the photoresist pattern 37 and the metal clusters 34 may be removed. As a result, the concavo-convex patterns 10a having the surface fine irregularities P can be exposed in the separation groove G. [

Referring to FIG. 4J, the second conductivity type semiconductor layer 27 and the active layer 25 are etched in the upper surface of each unit light emitting device UD to expose the first conductivity type semiconductor layer 23 To form a mesa etched region (R). The second conductivity type semiconductor layer 27 and the active layer 25 of each unit light emitting device UD may be exposed on the sidewall of the mesa etching region R. [ The width of the mesa etching region R may become narrower toward the substrate 10.

As shown in FIG. 4J, the mesa etching region R may be spaced apart from the isolation groove G by a predetermined distance. However, the present invention is not limited thereto, and the mesa etching region R may be formed to be immediately adjacent to the separation groove G. [

A current spreading conductive layer such as a transparent electrode layer 44 may be formed on the second conductivity type semiconductor layer 27 of each of the unit light emitting devices UD. The current spreading conductive film 44 may be a light transmitting conductive film. As an example, ITO (Indium Tin Oxide), Ni / Au, or Cu / Au may be used.

Thereafter, an insulation film is formed on the entire surface of the substrate, and the insulation film is patterned to separate the concave-convex patterns 10a exposed in the isolation groove G and the isolation insulation film 40 covering the side surfaces of the unit light-emitting devices UD. And the passivation film 43 disposed on the current spreading conductive film 44 can be formed. The isolation insulating film 40 may extend on one side wall in the mesa etching region R adjacent to the separation groove G. [ The passivation film 43 may extend on the other side wall in the mesa etching region R and may expose a part of the current spreading conductive film 44. The isolation insulating film 40 and the passivation film 43 may be formed of a polyimide film, a silicon oxide film, or a silicon nitride film.

The wiring 46 for electrically connecting a pair of the unit light emitting devices UD adjacent to the unit light emitting devices UD may be formed on the isolation insulating film 40. The wiring 46 is connected to one side of the pair of unit light emitting elements UD, that is, the second conductivity type semiconductor layer 27 (or the current spreading layer 44) of the first element, And can be electrically connected to the first conductivity type semiconductor layer 23 of the device. In this case, the unit light emitting elements UD can be connected in series by the wiring 46, which can exhibit a high operating voltage. Particularly, a first electrode (100a, 200a in FIG. 1) and a second electrode 100b, 200b are formed on the unit light emitting devices UD and these electrodes can be connected to each other by a wiring 46. The first and second electrodes and the wiring may be formed together with the same material by the same process. Further, a first electrode pad (300a in FIG. 1) and a second electrode pad (300b in FIG. 1) may also be formed together with the wiring (46).

The isolation insulating film 40 may be positioned between the wiring 46 and the second conductive semiconductor layer 27 of the second element. The width of the mesa etching region R may become narrower toward the substrate 10. In this case, disconnection of the wiring 46 may be prevented.

10A and 10B are schematic views schematically showing that the light emitted from the active layer is reflected in various directions by the concave-convex pattern in the lower part of the light emitting diode and the concave-convex pattern in the separation area.

Referring to FIG. 10A, when the light emitting diode described with reference to FIG. 4J operates, light traveling in the direction of the active layer (25 in FIG. 4J) toward the substrate (10 in FIG. 4J) do. At this time, since the convex portions 10av have side surfaces UF and LF having vertexes V which are not plane but sharp angles with respect to the substrate surface, light emitted from the active layer 25 It can be reflected in various directions. As a result, the light extraction efficiency can be improved.

Referring to FIG. 10B, the light traveling in the direction of the substrate in the separation groove G in the active layer (25 of FIG. 4J) meets the convex portions 10av and the concave portions 10ac between them. At this time, as described with reference to FIG. 10A, the light can be reflected in various directions by the shapes of the convex portions 10av, that is, the side surfaces UF and LF having the inclination angle and the sharp point. In addition, the light can be irregularly reflected not only by the surface of the convex portions 10av but also by the fine irregularities P in the surface of the concave portions 10ac. As a result, the light extraction efficiency can be further improved. In addition, some of the light entering the substrate 10 can be easily extracted through the concavo-convex pattern 10a having the fine irregularities P.

11A to 11E are cross-sectional views illustrating a method of manufacturing a light emitting diode according to another embodiment of the present invention. The manufacturing method of the light emitting diode according to the present embodiment can be similar to the manufacturing method described with reference to Figs. 4A to 4J, except as described below.

Referring to FIG. 11A, concavo-convex patterns 10a may be formed in the upper surface of the substrate 10. FIG. The concavo-convex patterns 10a may be formed using the method described with reference to Figs. 4A to 4E.

The metal clusters 34 may be formed by laminating a metal film (not shown) on the concavo-convex patterns 10a and then heat-treating the substrate on which the metal films are stacked. A photoresist pattern 37 may be formed on the metal clusters 34. The photoresist pattern 37 may expose some of the areas, specifically, the first area A1 and the second area A2. The first region A1 may correspond to an isolation groove to be described later, and the second region A2 may correspond to a mesa etching region described later. However, the present invention is not limited to this, and the photoresist pattern 37 may expose only the first region A1 corresponding to a separation groove to be described later.

Thereafter, using the photoresist pattern 37 and the metal clusters 34 as a mask, the surface of the concavo-convex patterns 10a of the first region A1 and the second region A2 is etched . As a result, fine irregularities (not shown) are formed in the surface of the irregular patterns 10a of the first area A1 and the second area A2, specifically, the surface of the convex portions 10av and the surface of the concave portions 10ac P in Fig. 11B) may be formed.

Referring to FIG. 11B, the photoresist pattern 37 and the metal clusters 34 may be removed. As a result, the concave-convex patterns 10a having the surface fine irregularities P can be exposed in the first area A1 and the second area A2.

Referring to FIG. 11C, a buffer layer 21 may be formed on a substrate on which the concavo-convex pattern 10a having the surface fine irregularities P is formed. As described above with reference to FIG. 4F, in the regions other than the first region A1 and the second region A2, the buffer layer 21 has morphological characteristics and crystallographically stable planes of the irregular patterns 10a The threading dislocation density can be reduced and the crystal quality can be improved. On the other hand, in the first region A1 and the second region A2, a threading dislocation may be generated due to the surface fine irregularities P.

Thereafter, the first conductive semiconductor layer 23, the active layer 25, and the second conductive semiconductor layer 27 are formed on the buffer layer 21 to form a semiconductor stacked body.

Referring to FIG. 11D, a region on the first region A1 of the stacked body is etched until the substrate 10 is exposed to form a separation groove G for separating the unit light emitting devices UD . The concavo-convex patterns 10a having surface fine irregularities can be exposed in the separation groove G. [ In addition, the light emitting device 100 regions and the triangular light emitting device 200 regions having a parallelogram shape as described with reference to Figs. 1 to 3 are defined by the separation grooves G.

Referring to FIG. 11E, a mesa etched region R may be formed in the upper surface of each of the unit light emitting devices UD to expose the first conductivity type semiconductor layer 13. The mesa etch region R corresponds to the second region A2. The mesa etching region R may be spaced apart from the separation groove G by a predetermined distance, but is not limited thereto and may be adjacent to the separation groove G. [ Thereafter, the current spreading conductive film 44, the isolation insulating film 40, the passivation film 43, and the wiring 46 can be formed as described with reference to FIG. 4J. The first electrodes 100a and 200b and the second electrodes 100b and 200b and the electrode pads 300a and 300b may be formed together with the wiring 46. [

When the light emitting diode is operated, the light traveling in the direction of the substrate 10 from the active layer 25 to the lower layer meets the convex portions 10av. Since the convex portions 10av have side surfaces UF and LF having vertexes V which are not planes but have a sharp vertex V and inclined angles with respect to the substrate surface, the light emitted from the active layer 25 is reflected in various directions Can be reflected. As a result, the light extraction efficiency can be improved. Light traveling in the direction of the substrate in the separation groove G from the active layer 25 meets the convex portions 10av and the concave portions 10ac between them. At this time, as described above, the light can be reflected in various directions by the shape of the convex portions 10av, and the light can be reflected by the surface of the convex portions 10av and the concave and convex portions formed in the surface of the concave portions 10ac (P). As a result, the light extraction efficiency can be further improved by the fine irregularities (P).

On the other hand, the threading dislocations generated by the surface fine irregularities (P) of the concavo-convex pattern (10a) on the first region (A1) Can be removed. Also, when forming the laminate, threading dislocations may be generated on the second region A2 due to the surface fine irregularities P of the concavo-convex pattern 10a and propagated into the active layer 25 of the region , The active layer 25 in this region is removed when the mesa etching region R is formed, so that crystal quality deterioration of the active layer 25 due to such threading dislocations may not occur. Therefore, the surface fine irregularities P of the concavo-convex pattern 10a can improve the light extraction efficiency without significantly deteriorating the epitaxial quality in the final device.

12A to 12D are cross-sectional views illustrating a method of manufacturing a light emitting diode according to another embodiment of the present invention. The manufacturing method of the light emitting diode according to the present embodiment can be similar to the manufacturing method described with reference to Figs. 4A to 4J, except as described below.

Referring to FIG. 12A, a substrate 10 is provided. An etch mask layer 13 may be formed on the upper surface of the substrate 10. A photoresist pattern 18 may be formed on the etch mask layer 13.

Referring to FIG. 12B, the etch mask layer 13 may be wet etched or etched using the photoresist pattern 18 as a mask. As a result, the etching mask pattern 13a can be formed. The etch mask pattern 13a may be formed to have a width of 0.2 to 1 um. For this, the width of the photoresist pattern 18 may be adjusted. The etch mask pattern 13a may be formed to have various shapes. As an example, the etch mask pattern 13a may have a stripe shape (FIG. 5) or an island shape of a circle (FIG. 6) or a polygon (FIG. 7), as shown in FIGS.

Referring to FIG. 12C, the photoresist pattern 18 may be removed to expose the etch mask pattern 13a. The substrate 10 is etched using the etch mask pattern 13a as a mask to form a concavo-convex pattern 10a including a concave 10ac and a convex 10av in the upper surface of the substrate 10, Can be formed. The substrate 10 may be etched using a wet etching method.

The convex portion 10av has lower side faces LF which are first crystal faces and upper side faces UF which are second crystal faces different from the first crystal face and the second crystal faces meet to form an upper vertex V ). Further, the bottom surfaces of the concave portions 10ac positioned between the convex portions 10av may be substantially parallel to the substrate surface.

The etch may be wet etch. The etching solution used in the etching process may exhibit a different etch rate depending on the crystal orientation of the substrate 10. In other words, the etching solution can preferentially etch the specific crystal orientation of the substrate 10. For example, the etching solution may be a mixed solution of sulfuric acid and phosphoric acid, a mixed solution of nitric acid and phosphoric acid, or a KOH solution when the substrate 10 is a sapphire substrate or a GaN substrate. In the case of a SiC substrate, Oxide Etch) or an HF solution, and in the case of a Si substrate, it may be a KOH solution. As an example, when the substrate 10 is a c-plane sapphire substrate and the etching solution is a mixed solution of sulfuric acid and phosphoric acid in a volume ratio of 3: 1, the c-plane is preferentially etched during the wet etching process .

In the wet etching process, the substrate 10 exposed between the etch mask patterns 13a is etched to form first crystal faces (dotted lines F) inclined at a first angle &thetas; ) May appear. Thereafter, the substrate 10 is further etched so that the first crystal faces extend downwardly of the substrate 10 to form the lower side faces LF of the convex portion 10av. On the other hand, the first crystal planes (dotted line F) near the surface of the substrate 10 formed at the initial stage of the etching are also gradually etched so that the second crystal planes are inclined with respect to the other crystal planes, Can be exposed, which can form the upper side surfaces UF. The second crystal faces may meet with each other to form a top vertex (V).

As described above, the etching mask pattern 13a is formed to have a width of 0.2 to 1 mu m with a small width, for example, so that even when the etching mask pattern 13a remains, So that the upper side faces UF and the upper side vertex V can be formed.

Thereafter, a process according to the method described with reference to FIGS. 4F and 4J is performed to fabricate a light emitting diode as shown in FIG. 4J.

13A to 13D are cross-sectional views illustrating a method of manufacturing a light emitting diode according to another embodiment of the present invention. The manufacturing method of the light emitting diode according to the present embodiment can be similar to the manufacturing method described with reference to Figs. 4A to 4J, except as described below.

Referring to FIG. 13A, an etch mask pattern 13a may be formed on the substrate 10. The etch mask pattern 13a may be formed by a method similar to that described with reference to FIGS. 4A and 4B. The etching mask pattern 13a may be a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. However, the etch mask pattern 13a is not limited thereto and may be a material having an etch selectivity to the substrate 10. [ The etch mask pattern 13a may be formed to have various shapes. As an example, the etch mask pattern 13a may have a stripe shape (FIG. 5) or an island shape of a circle (FIG. 6) or a polygon (FIG. 7), as shown in FIGS. When the unit pattern of the etching mask pattern 13a has an island shape, the unit patterns of the etching mask pattern 13a are arranged such that six unit patterns are surrounded by a hexagon . However, the shape of the etching mask pattern 13a is not limited thereto.

The substrate 10 is etched using the etch mask pattern 13a as a mask to form a concavo-convex pattern 10a including a concave 10ac and a convex 10av in the upper surface of the substrate 10, Can be formed. The substrate 10 may be etched using a wet etching method.

The etching solution used for the wet etching may exhibit a different etch rate depending on the crystal orientation of the substrate 10. In other words, the etching solution can preferentially etch the specific crystal orientation of the substrate 10. For example, the etching solution may be a mixed solution of sulfuric acid and phosphoric acid, a mixed solution of nitric acid and phosphoric acid, or a KOH solution when the substrate 10 is a sapphire substrate or a GaN substrate. In the case of a SiC substrate, Oxide Etch) or an HF solution, and in the case of a Si substrate, it may be a KOH solution. As an example, when the substrate 10 is a c-plane sapphire substrate and the etching solution is a mixed solution of sulfuric acid and phosphoric acid in a volume ratio of 3: 1, the c-plane is preferentially etched during the wet etching process .

Referring to FIG. 13B, the etching mask pattern 13a is removed to expose the upper surface of the convex portion 10av. The top surface T of the convex portion 10av may be planar and facets S thereof may have a first inclination angle? 1 with respect to the substrate surface. These aspects S may be the first crystal faces. In addition, the inclination angles, that is, the inclination angles of the side faces S of the convex portion 10av with respect to the substrate surface may be the same or may be different from each other depending on the side faces S. [ In addition, the bottom surfaces of the concave portions 10ac positioned between the convex portions 10av and the top surface of the convex portions 10av may be substantially parallel to the substrate surface.

The concave-convex pattern will be described in detail with reference to FIG. Fig. 13B can correspond to the section taken along the section line I-I 'in Fig.

13B and 14, the uneven pattern 10a has a plurality of convex portions 10av and concavities 10ac defined therein. The bottom surface of the concave portions 10ac positioned between the convex portions 10av and the top surface of the convex portions 10av may be a surface substantially parallel to the substrate surface, for example, c-plane. The convex portion may have a stripe or island shape corresponding to the shape of the etching mask pattern 13a described with reference to FIGS. 5 to 7. However, when the etching mask pattern 13a has an island shape having a circular or polygonal shape The bottom surface defined by the side surfaces of the convex portion 10av as shown in Fig. 14 may have the shape of a pseudo triangle, in which each line segment is a curved surface protruding outwardly. The upper surface of the convex portion 10av may have a circular shape depending on the shape of the etching mask pattern 13a.

Referring to FIG. 13C, the buffer layer 21 may be formed on the substrate on which the uneven pattern 10a is formed. At this time, the buffer layer 21 may be preferentially vertically grown on the bottom surface of the concave portion 10ac and the top surface of the convex portion 10av, which are substantially parallel to the substrate surface. In addition, the bottom surface of the concave portion 10ac and the side surfaces S of the formed convex portion 10av are formed through wet etching and are stable crystal planes, so that the probability of dislocation is low. Thus, the crystal quality can be improved.

Thereafter, a process according to the method described with reference to FIGS. 4F and 4J is performed to fabricate a light emitting diode as shown in FIG. 13D.

15A to 15D are cross-sectional views illustrating a method of manufacturing a light emitting diode according to another embodiment of the present invention. The manufacturing method of the light emitting diode according to the embodiment may be similar to the manufacturing method described with reference to Figs. 4A to 4J, except as described below.

Referring to FIG. 15A, an etch mask pattern 13a may be formed on the substrate 10. [ The etch mask pattern 13a may be formed by a method similar to that described with reference to FIGS. 4A and 4B.

The substrate 10 is etched using the etch mask pattern 13a as a mask to form a concavo-convex pattern 10a including a concave 10ac and a convex 10av in the upper surface of the substrate 10, Can be formed. The substrate 10 may be etched using a wet etching method.

The etching solution used for the wet etching may exhibit a different etch rate depending on the crystal orientation of the substrate 10. In other words, the etching solution can preferentially etch the specific crystal orientation of the substrate 10. For example, the etching solution may be a mixed solution of sulfuric acid and phosphoric acid, a mixed solution of nitric acid and phosphoric acid, or a KOH solution when the substrate 10 is a sapphire substrate or a GaN substrate. In the case of a SiC substrate, Oxide Etch) or an HF solution, and in the case of a Si substrate, it may be a KOH solution. As an example, when the substrate 10 is a c-plane sapphire substrate and the etching solution is a mixed solution of sulfuric acid and phosphoric acid in a volume ratio of 3: 1, the c-plane is preferentially etched during the wet etching process . The top surface of the convex portion 10av may be planar and facets thereof may have a first inclination angle? 1 with respect to the substrate surface. These aspects may be the first crystal faces. In addition, the inclined angles, that is, the inclination angles of the side surfaces of the convex portion 10av with respect to the substrate surface may be the same or may differ from each other depending on the sides. In addition, the bottom surfaces of the concave portions 10ac positioned between the convex portions 10av and the top surface of the convex portions 10av may be substantially parallel to the substrate surface.

Referring to FIG. 15B, the substrate 10 having the concave-convex pattern 10a may be second-etched using the etching mask pattern 13a as a mask. The secondary etching may be dry etching, specifically, anisotropic etching. In this process, the side surface of the convex portion 10av and the bottom surface of the concave portion 10ac may be etched by a predetermined depth.

Referring to FIG. 15C, the upper surface T of the convex portion 10av is exposed by removing the etching mask pattern 13a. The convex portion 10av has a first side surface S1 as an upper side and a second side surface S2 as a lower side having mutually different inclination angles. Specifically, the first side S1 adjacent to the top surface T of the convex portion 10av may be substantially perpendicular to the substrate surface, and the second side S2 adjacent to the recess 10ac may be substantially perpendicular to the substrate surface, The first inclination angle may be the same as or similar to the first inclination angle (&thetas; 1 in Fig. 15A).

Thereafter, a process according to the method described with reference to FIGS. 4F and 4J is followed to fabricate a light emitting diode as shown (see FIG. 15D).

16A to 16D are cross-sectional views illustrating a method of manufacturing a light emitting diode according to another embodiment of the present invention. The manufacturing method of the light emitting diode according to the present embodiment can be similar to the manufacturing method described with reference to Figs. 4A to 4J, except as described below.

Referring to FIG. 16A, an etch mask pattern 13a may be formed on the substrate 10. FIG. The etch mask pattern 13a may be formed by a method similar to that described with reference to FIGS. 4A and 4B.

The substrate 10 is etched using the etch mask pattern 13a as a mask to form a concavo-convex pattern 10a including a concave 10ac and a convex 10av in the upper surface of the substrate 10, Can be formed. The substrate 10 may be etched using a dry etching method, specifically, an anisotropic etching method. In this case, the side surface of the convex portion 10av may be substantially perpendicular to the substrate surface.

Referring to FIG. 16B, the substrate 10 having the uneven pattern 10a may be secondarily etched using the etch mask pattern 13a as a mask. The secondary etching may be wet etching. The etching solution used for the wet etching may exhibit a different etch rate depending on the crystal orientation of the substrate 10. In other words, the etching solution can preferentially etch the specific crystal orientation of the substrate 10. For example, the etching solution may be a mixed solution of sulfuric acid and phosphoric acid, a mixed solution of nitric acid and phosphoric acid, or a KOH solution when the substrate 10 is a sapphire substrate or a GaN substrate. In the case of a SiC substrate, Oxide Etch) or an HF solution, and in the case of a Si substrate, it may be a KOH solution. As an example, when the substrate 10 is a c-plane sapphire substrate and the etching solution is a mixed solution of sulfuric acid and phosphoric acid in a volume ratio of 3: 1, the c-plane is preferentially etched during the wet etching process .

Referring to FIG. 16C, the upper surface T of the convex portion 10av is exposed by removing the etching mask pattern 13a. The convex portion 10av may have a first side surface S1 and a second side surface S2 having different inclination angles. The second side surfaces S2 may be formed by first etching a specific crystal plane in the wet etching process and may have a predetermined inclination angle with respect to the substrate surface. The upper surface T of the convex portion 10av and the concave portion 10ac may be formed, And may be an upper side surface and a lower side surface formed adjacent to the bottom surface. Further, the first side surface S1, which is the intermediate side located between the second side surfaces S2, may be substantially perpendicular to the substrate surface.

The process according to the method described with reference to FIGS. 4F and 4J may be followed to fabricate a light emitting diode as shown (see FIG. 16D).

Hereinafter, a preferred example of forming a concavo-convex pattern is described in order to facilitate understanding of the present invention. It should be understood, however, that the following examples are for the purpose of promoting understanding of the present invention and are not intended to limit the scope of the present invention.

<Uneven Pattern Production Example 1>

A silicon oxide film was formed on a c-plane sapphire substrate, and then a photoresist pattern was formed on the silicon oxide film. The photoresist pattern was an array of unit-shaped unit patterns similar to those shown in Fig. Using the photoresist pattern as a mask, the silicon oxide film was etched with hydrofluoric acid to form a silicon oxide pattern. Thereafter, the photoresist pattern was removed. Using the silicon oxide pattern as a mask, the substrate was etched with a mixed solution of sulfuric acid and phosphoric acid in a volume ratio of 3: 1. Thereafter, the silicon oxide pattern was removed to form a concavo-convex pattern having a convex portion having a flat upper surface and a flat concave portion.

<Uneven Pattern Production Example 2>

A concavo-convex pattern was formed in the upper surface of the substrate using a method similar to that of Production Example 1 except that the substrate was dry-etched using the silicon oxide pattern as a mask.

<Uneven Pattern Production Example 3>

The resultant substrate of Production Example 1 was mixed with sulfuric acid and phosphoric acid in a volume ratio of 3: 1

And the second etching was performed with a mixed solution.

<Uneven Pattern Production Example 4>

A nickel layer having a thickness of 10 nm was formed on the concavo-convex pattern according to Production Example 2, and then heat-treated to form nickel clusters on the concave-convex pattern. Using the nickel clusters as a mask, the irregular pattern was subjected to plasma etching, and then the nickel clusters were removed.

<Light Emitting Diode Production Example 1>

An undoped GaN layer was formed on a substrate having a concavo-convex pattern formed according to the concavo-convex pattern production example 1 using the MOCVD method. An n-type GaN layer was formed on the undoped GaN layer, and then an active layer of InGaN / GaN multiple quantum well structure was formed on the n-type GaN layer. Thereafter, a p-type GaN layer was formed on the active layer, and then a mesa etching region was formed to expose the n-type GaN layer. Thereafter, an ITO layer was formed on the p-type GaN layer, and an n-type electrode and a p-type electrode were respectively formed on the n-type GaN layer and the ITO layer exposed in the mesa etching region.

<Light Emitting Diode Production Example 2>

A light emitting diode was manufactured using a method similar to that of Light Emitting Diode Production Example 1 except that the substrate according to Production Example 2 of irregularity pattern was used.

<Light Emitting Diode Production Example 3>

A light emitting diode was manufactured by a method similar to that of Light Emitting Diode Production Example 1 except that the substrate according to Production Example 3 of irregularity pattern was used.

FIGS. 17 and 18 are SEM cross-sectional photographs after the epitaxial layer is grown on the concavo-convex pattern according to the concavo-convex pattern production examples 1 and 2, respectively.

17 and 18, when a concavo-convex pattern is formed by dry etching, not only crystallographic mismatch such as minute voids VD occurs at the interface between the sloped surface of the concavo-convex pattern and the epi layer 121, (Dislocation pattern production example 2, Fig. 18). On the other hand, when the concavo-convex pattern 10a is formed by wet etching, fine voids are not observed at the interface between the sloped surface of the concavo-convex pattern 10a and the epi layer 21, (Uneven pattern production example 1, Fig. 17).

As a result of the ESD experiments on the light emitting diodes according to the light emitting diode manufacturing examples 1 and 2, the light emitting diode according to the production example 1 showed an ESD yield of 71.07% (a constant voltage of 1 kV was applied to a plurality of light emitting diodes three times And the ESD yield of the light emitting diode according to Production Example 2 was found to be 0.33%. This is because the light emitting diode having the concavo-convex pattern (concave-convex pattern production example 1) formed using the wet etching compared to the light emitting diode (production example 2) having the concavo-convex pattern (concavo-convex pattern production example 2) ) Is considered to have an epitaxial layer with improved crystal quality.

Figs. 19A to 19C are SEM photographs showing a substrate having a concavo-convex pattern manufactured according to the concavo-convex pattern production example 3. Fig.

19A to 19C, a concavo-convex pattern 10a having convex portions 10av and concavities 10ac defined therein is formed in the upper surface of the substrate. The convex portions 10av have lower side faces LF and upper side faces UF and the upper side faces UF meet to form the upper vertex V. [ The angle? 2 formed by the upper side surface UF with the substrate surface is smaller than the angle? 1 formed by the lower side surface LF with the substrate surface.

Further, the bottom surface defined by the lower side surfaces LF of the convex portion 10av has a pseudo-triangular shape in which each line segment is a curved surface protruding outward. Further, the upper side surfaces UF of the convex portion 10av have a substantially hexagonal shape as viewed from above.

20 is a graph showing outputs of currents of light emitting diodes manufactured according to Light Emitting Diode Production Example 2 and Light Emitting Diode Manufacturing Example 3, respectively.

Referring to FIG. 20, it can be seen that the light emitting diode according to Production Example 3 has an improved efficiency droop in the high current region as compared with the light emitting diode according to Production Example 2. This is because the light emitting diode according to Production Example 3, which is a light emitting diode having a concavo-convex pattern (concavo-convex pattern production example 3) formed through a secondary wet etching, is a light emitting diode having a concavo-convex pattern It means that the epitaxial quality is improved as compared with the light emitting diode according to Production Example 2.

Figs. 21A to 21B are SEM photographs showing a substrate having a concavo-convex pattern manufactured according to the concavo-convex pattern production example 4. Fig.

21A and 21B, it can be seen that a large number of fine irregularities P are formed on the surface of convex portion 10av and concave portion 10ac of concavo-convex pattern 10a. These fine irregularities P can diffuse light proceeding from the active layer irregularly, and the light extraction efficiency can be improved.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Therefore, it should be understood that the above-described embodiments are not intended to limit the scope of the present invention, but merely to facilitate a better understanding thereof. The scope of the present invention is not limited by these embodiments, but should be construed according to the following claims, and technical ideas within the scope of equivalents thereof should be construed as being included in the scope of the present invention.

Claims (30)

Board;
A plurality of unit light emitting elements positioned on the substrate; And
And wires connecting the plurality of unit light emitting elements,
Wherein the plurality of unit light emitting elements include unit light emitting elements of a parallelogram shape having two acute angles and two obtuse angles. The method according to claim 1,
Wherein the plurality of unit light emitting elements further comprise a triangle unit light emitting element. The method of claim 2,
Wherein the plurality of unit light emitting elements comprise six parallelogrammatic unit light emitting elements and one triangular unit light emitting element. The method of claim 3,
Wherein the unit light emitting elements of the six parallelogram shape are arranged in two rows, and the unit light emitting elements of the first column and the unit light emitting elements of the second column are arranged to have a mirror surface symmetry structure with each other. The method of claim 4,
And the triangular-shaped unit light-emitting element is disposed over the first column and the second column near one edge of the substrate. The method of claim 5,
A first electrode pad disposed in a first column; And
And a second electrode pad disposed in the second column. The method of claim 6,
Wherein the first and second electrode pads are disposed in the vicinity of the other edge opposite to one edge of the substrate on which the triangular unit light emitting device is disposed. The method of claim 4,
Wherein the unit light emitting elements of the first column and the unit light emitting elements of the second column are arranged in parallel on opposite sides. The method of claim 2,
The unit light emitting elements of the parallelogram-
First unit light emitting elements oriented in the same direction as each other; And
And unit light emitting elements of a second row oriented in the same direction as each other,
And the triangular unit light emitting element is disposed over the first and second rows. The method of claim 9,
Wherein the unit light emitting elements of the first row and the unit light emitting elements of the second column are arranged in a mirror plane symmetrical structure such that faces facing each other are parallel,
One side of the triangle-shaped unit light-emitting element is parallel to one side of the unit light-emitting element of the first column,
The other side of the triangle-shaped unit light-emitting element is parallel to one side of the unit light-emitting element of the second row,
And the other surface of the triangular unit light emitting device is parallel to one edge of the substrate. The method according to claim 1,
Wherein the substrate has a concavo-convex pattern having a convex portion on the upper surface and a concave portion defined by the convex portion, and the concavo-convex pattern in a part of the concavo-convex pattern has fine concavities and convexities on its surface. The method of claim 11,
And the concavo-convex pattern having fine concavities and convexities on its surface is disposed in a separation groove separating the unit light-emitting elements. The method according to claim 11 or 12,
The unit light emitting devices each include a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer,
Wherein the unit light emitting devices each include a mesa etching region for exposing the first conductivity type semiconductor layer by etching the second conductivity type semiconductor layer and the active layer,
Wherein the concavo-convex pattern located under the mesa etching region has fine irregularities on the surface thereof. The method of claim 11,
Wherein the convex pattern convex part has side faces including a plurality of crystal faces and one upper corner point where at least a part of the side faces meet. 15. The method of claim 14,
Wherein the side faces have lower side faces as first crystal faces and upper side faces as second crystal faces,
And the upper vertex corresponds to the second crystal planes. 16. The method of claim 15,
Wherein the inclined angle formed by the second crystal plane with the surface of the substrate is smaller than the inclined angle formed by the first crystal plane with the substrate surface. 15. The method of claim 14,
Wherein the convex portion is in the form of a stripe or an island. 18. The method of claim 17,
The convex portion has the shape of an island,
Wherein a bottom surface of the convex portion has a shape of a pseudo triangle, and each line segment is a curved surface protruding outward. The method of claim 11,
And the convex portion of the concave-convex pattern has side faces that are crystal faces and a flat upper face. The method of claim 11,
And the convex portion of the concavo-convex pattern has a lower side and an upper side with different inclination angles. The method of claim 11,
Wherein the convex portion of the concavo-convex pattern has a lower side, an intermediate side, and an upper side, and the adjacent sides have different inclination angles. The method according to claim 1,
And the plurality of unit light emitting elements are connected in series by wires. The method according to claim 1,
Further comprising a first electrode and a second electrode disposed on each of the unit light emitting elements,
Each unit light emitting device includes a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer,
The first electrode is electrically connected to the first conductivity type semiconductor layer,
The second electrode is electrically connected to the second conductive type semiconductor layer,
Wherein the wiring connects a first electrode of one unit light emitting element and a second electrode of another unit light emitting element adjacent to the first electrode. 24. The method of claim 23,
And the second electrode has a curved shape. 24. The method of claim 23,
Wherein at least one side of the first conductive semiconductor layer, the active layer, and the second conductive semiconductor layer is inclined at an angle of less than 90 degrees with respect to the substrate surface. Providing a substrate,
Forming a laminate including a first conductivity type semiconductor layer, an active layer and a second conductivity type semiconductor layer on the substrate,
And patterning the laminate to form a plurality of unit light emitting elements,
Wherein the unit light emitting devices include unit light emitting devices having a parallelogram shape having two acute angles and two obtuse angles. 27. The method of claim 26,
Providing the substrate comprises:
A concavo-convex pattern having convex portions and concave portions defined by the convex portions is formed on the upper surface of the substrate,
And forming micro concavities and convexities in the surface of the concavo-convex pattern disposed in a partial region of the upper surface of the substrate. 28. The method of claim 27,
Wherein the formation of the fine irregularities is performed after patterning the laminate. Board; And
A plurality of unit light emitting elements positioned on the substrate,
Wherein the plurality of unit light emitting elements include unit light emitting elements of a parallelogram shape having two acute angles and two obtuse angles,
Wherein the substrate has a convex-concave pattern having a convex portion on the upper surface and a concave portion defined by the convex portion,
Wherein the concavo-convex pattern in a part of the concavo-convex pattern has fine unevenness on the surface thereof. 29. The method of claim 29,
Further comprising an insulating film covering the plurality of light emitting devices and the concavo-convex pattern on the substrate,
And the concavo-convex pattern including the fine irregularities is located in a region of the substrate where the insulating film contacts.

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