KR20140063366A - Memory module and memory system - Google Patents

Abstract

The present invention relates to a memory module. The memory module of the present invention comprises a printed circuit board, first semiconductor packages provided on one side of the printed circuit board, and second semiconductor packages provided on the other side of the printed circuit board. The number of ranks formed by the first semiconductor packages and the number of ranks formed by the second semiconductor packages are different from each other.

Description

[0001] MEMORY MODULE AND MEMORY SYSTEM [0002]

The present invention relates to semiconductor memory, and more particularly, to a memory module and a memory system.

A semiconductor memory device is a memory device implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP) to be. Semiconductor memory devices are classified into a volatile memory device and a nonvolatile memory device.

The volatile memory device is a memory device in which data stored in the volatile memory device is lost when power supply is interrupted. Volatile memory devices include static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM). A nonvolatile memory device is a memory device that retains data that has been stored even when power is turned off. A nonvolatile memory device includes a ROM (Read Only Memory), a PROM (Programmable ROM), an EPROM (Electrically Programmable ROM), an EEPROM (Electrically Erasable and Programmable ROM), a flash memory device, a PRAM ), RRAM (Resistive RAM), and FRAM (Ferroelectric RAM).

It is an object of the present invention to provide a memory module and a memory system with improved operating performance.

A memory module according to an embodiment of the present invention includes: a printed circuit board; First semiconductor packages provided on one side of the printed circuit board; And second semiconductor packages provided on the other side of the printed circuit board, wherein the number of ranks formed by the first semiconductor packages and the number of ranks formed by the second semiconductor packages are different from each other, and one rank Semiconductor packages to be formed receive chip select signals in common, and semiconductor packages forming different ranks receive different chip select signals.

In an embodiment, the first semiconductor packages form two ranks, and the second semiconductor packages form one rank.

In an embodiment, the first semiconductor packages are dual die packages (DDP), and the second semiconductor packages are mono die packages.

In an embodiment, the semiconductor dies of the first layer of the first semiconductor packages form one rank and the semiconductor dies of the second layer form another rank.

In an embodiment, the first semiconductor packages and the second semiconductor packages have different structures.

In an embodiment, the number of semiconductor die provided in each of the first semiconductor packages is different from the number of semiconductor die provided in each of the second semiconductor packages.

A memory system according to an embodiment of the present invention includes a memory controller; And a plurality of semiconductor dice coupled to the memory controller via a common channel and configured to operate under the control of the memory controller, the plurality of semiconductor dies forming a number of ranks excluding a power of two, The semiconductor dies that form the ranks of the chip receive common chip select signals and the semiconductor dies that form the different ranks receive different chip select signals.

In an embodiment, the plurality of semiconductor dies form ranks corresponding to a number of one of 3, 5, 6,

As an embodiment, the apparatus further comprises a printed circuit board on one side of which the first semiconductor dies of the plurality of semiconductor dies are provided and on the other side of which the second of the plurality of semiconductor dies is provided, The number of ranks formed by the semiconductor dies and the number of ranks formed by the second semiconductor dies are different.

In an embodiment, the first semiconductor dies are provided on one side of the printed circuit board with dual die packages (DDP), and the second semiconductor dies are provided with mono die packages And is provided on the other side of the printed circuit board.

In an embodiment, the plurality of semiconductor dies are packaged with the memory controller to form a multi-chip package (MCP).

In an embodiment, the memory controller forms a first package, the plurality of semiconductor dies form at least one second package, and the first package and the at least one second package form a package-on-package PoP, Package-on-Package).

As an embodiment, it further comprises a plurality of second semiconductor dice connected to the memory controller via a second common channel and configured to operate in accordance with the control of the memory controller.

In an embodiment, the plurality of semiconductor dies and the plurality of second semiconductor dies are packaged with the memory controller to form a multi-chip package (MCP).

In an embodiment, the memory controller forms a first package, the plurality of semiconductor dies and the plurality of second semiconductor dies form at least one second package, and the first package and the at least one 2 package forms a package-on-package (PoP).

According to embodiments of the present invention, the number of ranks of semiconductor memories connected to one channel is adjusted. Accordingly, a memory module and a memory system having optimized operation speeds supported by semiconductor memories and having improved operation performance are provided.

1 is a block diagram illustrating a memory system in accordance with an embodiment of the present invention.
2 is a table showing the operating speeds of the memory units according to the number of ranks.
FIG. 3 is a table showing an example of configuring channels and ranks.
4 shows a memory module according to an embodiment of the present invention.
5 is a table showing memory modules according to embodiments of the present invention.
6 shows a memory system according to a second example of the present invention.
7 shows a memory system according to a third example of the present invention.
8 shows a memory system according to a fourth example of the present invention.
9 shows a memory system according to a fifth example of the present invention.
10 is a block diagram illustrating a computing device according to an embodiment of the present invention.
11 is a flowchart showing a method of manufacturing a semiconductor memory according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the technical idea of the present invention. .

1 is a block diagram illustrating a memory system 100 in accordance with an embodiment of the present invention. Referring to FIG. 1, a memory system 100 includes a memory controller 110, a first memory unit 120, and a third memory unit 130.

The memory controller 110 is configured to control the first memory unit 120 and the second memory unit 130.

The first memory unit 120 is configured to communicate with the memory controller 110 via a first channel CH1. The first memory unit 1200 can perform operations such as writing, reading and the like under the control of the memory controller 110.

The first memory unit 120 includes a plurality of ranks R1 to R3. Each rank includes one or more memory chips (or memory dies). For example, each rank may include one or more DRAM memory chips (or memory dies).

The ranks R1 to R3 may receive different chip select signals CS1, CS2, and CS3 from the memory controller 110 via the first channel CH1. For example, the first rank Rl may receive the first chip select signal CS1 through the first channel CH1. When the first chip select signal CS1 is activated, the memory chips (or memory dies) of the first rank Rl can be activated. The second rank R2 may receive the second chip select signal CS2 through the first channel CH1. The third rank R3 can receive the third chip select signal CS3 through the first channel CH1. That is, in the first channel CH1, the chip selection signals CS1 to CS3 associated with the first to third ranks R1 to R3 can be transmitted through electrically separated lines.

Data can be exchanged in common with the memory controller 110 via the ranks R1 to R3. For example, the first rank Rl receives data transmitted from the memory controller 110 via the first channel CH1 when the first chip select signal CS1 is activated, ). ≪ / RTI > The second rank R2 receives data transmitted from the memory controller 110 via the first channel CH1 when the second chip select signal CS2 is activated or receives data transmitted from the memory controller 110 via the first channel CH1 Lt; / RTI > The third rank R3 receives data transmitted from the memory controller 110 via the first channel CH1 when the third chip select signal CS3 is activated or receives data transmitted from the memory controller 110 via the first channel CH1 Lt; / RTI > That is, in the first channel CH1, data associated with the first through third ranks R1 through R3 can be transmitted through common data lines.

At each rank, memory chips (or memory dies) may share a chip select signal. For example, when the first chip select signal CS1 is activated, the memory chips (or memory dies) of the first rank R1 may be activated together.

At each rank, the memory chips (or memory dies) can independently exchange data over the first channel CH1. For example, the data lines of the first channel CH1 may be divided into groups corresponding to the number of memory chips (or memory dies) in each rank. Each group can be assigned to each memory chip (or memory die) in each rank. For example, the data line of the first channel CH1 is 64 bits, the number of memory chips (or memory dies) in each rank is 8, and each memory chip (or memory die) Lt; / RTI >

The second memory unit 130 communicates with the memory controller 110 via the second channel CH2 and receives the fourth to sixth chip select signals CS4 to CS6, (120). Therefore, detailed description of the second memory unit 130 is omitted.

According to an embodiment of the present invention, the memory unit 120 or 130 communicating with the memory controller 110 via one channel (CH1 or CH2) includes a plurality of ranks R1 to R3. Each rank includes a plurality of memory chips (or memory dies). The plurality of ranks R1 to R3 correspond to the plurality of chip select signals CS1 to CS3, respectively.

The number of ranks provided to one channel (CH1 or CH2) may be a number that is not a power of two. For example, the number of ranks provided in one channel (CH1 or CH2) may be one of a number not a power of 2, such as 3, 5, 6, 7, 9, 10,

Illustratively, the memory chips (or memory dies) may be random access memories such as DRAM, SRAM, PRAM, MRAM, FRAM, RRAM, and the like. Memory units 120 and 130 may be used as main memory in a computing device.

Illustratively, each of the memory units 120, 130 may be a memory module. For example, each of the memory units 120 and 130 may be one of memory modules such as a Dual In-line Memory Module (DIMM), a Registered DIMM (RDIMM), a Fully Buffered DIMM (FBDIMM)

2 is a table showing the operating speeds of the memory units according to the number of ranks. Referring to Figures 1 and 2, when one rank is provided to a memory unit (e.g., memory module), the memory unit may support both 1066 Mbps, 1333 Mbps, and 1600 Mbps.

When two ranks are provided to a memory unit (e.g., memory module), the memory unit may support both 1066 Mbps, 1333 Mbps, and 1600 Mbps.

When four ranks are provided to a memory unit (e. G., A memory module), the memory unit supports 1066 Mbps but can not support 1333 Mbps and 1600 Mbps.

The ranks connected to one channel (CH1 or CH2) act as a load. As the number of ranks connected to one channel (CH1 or CH2) increases, the load acting on one channel (CH1 or CH2) increases. As the load increases, the operating speed (e.g., clock frequency) supported by one channel (CH1 or CH2) is lowered.

A typical memory system provides one channel (CH1 or CH2) with a number of ranks corresponding to a power of two. For example, one memory module (DIMM, RDIMM, or FBDIMM) provides a number of ranks corresponding to a power of two. As shown in FIG. 2, when the number of ranks corresponding to a power of 2 is provided, the operating speed decreases exponentially as the number of ranks increases. Thus, when a number of ranks corresponding to a power of 2 is provided, optimization of the capacity and operating speed of the memory unit 110 or 120 connected to one channel is not normally performed.

For example, if the capacity of the memory unit 110 or 120 connected to one channel (CH1 or CH2) is to be increased, the number of ranks of the memory unit 110 or 120 may be increased. When the operation speed of the memory unit 110 or 120 is to be increased, the number of ranks of the memory unit 110 or 120 can be reduced. In accordance with the methods described above, the number of ranks can be adjusted to optimize the capacity and operating speed of the memory unit 110 or 120. Referring to the table shown in FIG. 2, if a number of ranks corresponding to a power of 2 is provided, a memory unit 110 or 120 having an operating speed of 1333 Mbps can not be provided. That is, even if the processor accessing the memory system 130 supports an operating speed of 1333 Mbps, the processor must access the memory system 130 at an operating speed of 1066 Mbps.

In order to solve such a problem, the memory unit (or memory module) according to the embodiment of the present invention may have a number of ranks such as 3, 5, 6, 7, 9, Lt; / RTI >

FIG. 3 is a table showing an example of configuring channels and ranks. In Fig. 3, examples of configurations of channels and ranks according to the first case and the second case are shown. Illustratively, the first case shows an example in which a number of ranks corresponding to a power of two is provided. The second case shows an example in which a number of ranks is provided that is not a power of two. Illustratively, it is assumed that the memory capacity to achieve through the configuration of channels and ranks is 48 GB. It is assumed that the capacity of the memory chips (or memory dies) provided in one rank is 8 GB.

Referring to Figures 1 to 3, in the first case, two ranks are provided in the first channel (CH1) and four ranks are provided in the second channel (CH2). In the first case, memory units (or memory modules) coupled to the first and second channels CH1, CH2 may support 1066 Mbps.

In the second case, three ranks are provided in the first channel (CH1) and three ranks are provided in the second channel (CH2). In the second case, memory units (or memory modules) coupled to the first and second channels CH1, CH2 may support 1033 Mbps.

According to an embodiment of the present invention, the number of ranks provided in one channel may be a number that is not a power of two. Thus, the operating speed and capacity of the memory units (or memory modules) are optimized.

4 shows a memory module 120 according to an embodiment of the present invention. Illustratively, memory module 120 may be a DIMM, an RDIMM, or an FBDIMM. The memory module 120 may provide three ranks (R1 to R3).

4, the memory module 120 includes a printed circuit board 121, a plurality of dual die packages (DDP), and a plurality of mono die packages (MDP) .

The dual die packages (DDP) may be provided on one side of the printed circuit board 121. The dual die packages (DDP) may provide two ranks (R1, R2). The mono die packages (MDP) may be provided on the other side of the printed circuit board 121. The mono die packages MDP may provide one rank R3.

Each of the dual die packages DDP includes a printed circuit board PCB1, memory dies D1 and D2, bonding wires BW1, a molding M1 and solder balls SB1. The memory dies D1 and D2 may be stacked on the printed circuit board PCB1. The memory dies D1 and D2 may be respectively connected to the printed circuit board PCB1 via bonding wires BW1. The molding M1 can enclose and protect the printed circuit board PCB1, the memory dies D1 and D2, and the bonding wires BW1. The solder balls SB1 may be electrically connected to the memory dies D1 and D2 via the printed circuit board PCB1 and the bonding wires BW1. The solder balls SB1 may be electrically connected to the printed circuit board 121.

The memory dies D1 located in one of the memory dies D1, D2 of the dual die packages DDP can form one rank R1. The memory dies D2 located in the other one of the memory dies D1 and D2 of the dual die packages DDP can form another rank R2.

Each of the mono die packages MDP includes a printed circuit board PCB2, a memory die D3, bonding wires BW2, a molding M2, and solder balls SB2. The memory die D3 may be provided on the printed circuit board PCB2. The memory die D3 may be connected to the printed circuit board PCB2 via bonding wires BW2. The molding M2 can wrap and protect the printed circuit board PCB2, the memory die D3, and the bonding wires BW2. Solder balls SB2 may be electrically connected to memory die D3 via printed circuit board PCB2 and bonding wires BW2. The solder balls SB2 may be electrically connected to the printed circuit board 121.

The memory dies D3 of the mono die packages MDP may form one rank R3.

By providing heterogeneous memory packages (e.g., DDP and MDP) to memory module 120, memory module 120 can form ranks that are not a power of two, as described above.

4, a specific example of dual die packages (DDP) and a mono die package (MDP) is shown, but the technical spirit of the present invention is not limited to the packages shown in Fig. It is sufficient that the dual die packages DDP include two memory dies D1 and D2, and the detailed structure such as location, connection method, etc., may be changed and applied to previously known packaging methods and later developed packaging methods . It is sufficient for the mono die packages (MDP) to include one memory die (D3), and the detailed structure such as position, connection method and the like can be changed and applied to previously known packaging methods and later developed packaging methods. This can be similarly applied to the following embodiments.

5 is a table showing memory modules according to embodiments of the present invention. Referring to FIG. 5, when the number of ranks is three, on one side of the memory module, a package including two stacked dies may be provided. One die of each package forms one rank, and the other die may form another rank. On the other side of the memory module, a package including one die may be provided. One die in each package can form one rank. This embodiment can form the memory module shown in Fig.

When the rank number is five, on one side of the memory module, a package including three stacked dies may be provided. The first die of each package forms a first rank, the second die forms a second rank, and the third die forms a third rank. On the other side of the memory module, a package including two stacked dies may be provided. One die of each package forms one rank, and the other die may form another rank.

When the number of ranks is six, on one side of the memory module, a package including three stacked dies may be provided. The first die of each package forms a first rank, the second die forms a second rank, and the third die forms a third rank. On the other side of the memory module, a package including three stacked dies may be provided. The first die of each package forms a first rank, the second die forms a second rank, and the third die forms a third rank.

When the number of ranks is seven, a package including four stacked dies may be provided on one side of the memory module. The first die of each package forms a first rank, the second die forms a second rank, the third die forms a third rank, and the fourth die forms a fourth rank. On the other side of the memory module, a package including three stacked dies may be provided. The first die of each package forms a first rank, the second die forms a second rank, and the third die forms a third rank.

Figure 6 shows a memory system 100a according to a second example of the present invention. Referring to FIG. 6, the memory system 100a includes first through seventh dies D1 through D7.

The first die D1 may be a memory controller.

The second through seventh dies D2 through D7 may be memory dies.

The first to seventh dies D1 to D2 are electrically connected to a printed circuit board (PCB) through a bonding wire BW. The solder balls SB are electrically connected to the first to seventh dies D1 to D7 through the printed circuit board (PCB) and the bonding wires BW. The first to seventh dies BW, the bonding wires BW and the printed circuit board PCB can be protected by the molding M. [

The first to seventh dies D1 to D7 may form a multi chip package (MCP) including different types of dies (or chips).

The second to seventh dies D2 to D7 can communicate with the first die D1 through one channel. The second through seventh dies D2 through D7 may form a number of ranks that is not a power of two. For example, the second and third dies D2 and D3 form the first rank R1, the fourth and fifth dies D4 and D5 form the second rank R2, The sixth and seventh ranks D6 and D7 may form the third rank R3.

Provided a number of ranks other than a power of two, the operating speed and capacity of the memory system 100a formed in the multichip package (MCP) is optimized.

FIG. 7 shows a memory system 100b according to a third example of the present invention. Referring to FIG. 7, the memory system 100b includes first to thirteenth dies D1 to D13.

The memory system 100b may have the same structure as the memory system 100a of FIG. 6, except that the number of memory dies increases and the memory dies communicate with the memory controller through a plurality of channels. Therefore, a detailed description of the redundant configuration is omitted.

The first die D1 may be a memory controller. The second to thirteenth dies D2 to D13 may be memory dies. The second through seventh dies D2 through D7 may communicate with the first die D1 through the first channel CH1. The eighth through thirteenth dies D8 through D13 may communicate with the first die D1 through a second channel CH2.

The memory dies connected to each channel may form a number of ranks, not a power of two. For example, in the first channel CH1, the second and third dies D2 and D3 form the first rank R1 and the fourth and fifth dies D4 and D5 form the second rank R1, And the sixth and seventh ranks D6 and D7 may form the third rank R3. In the second channel CH2 the eighth and ninth dies D8 and D9 form the first rank R1 and the tenth and eleventh dies D10 and D11 form the second rank R2, And the twelfth and thirteenth ranks D12 and D13 may form the third rank R3.

If a non-square number of ranks are provided, the operating speed and capacity of the memory system 100b formed in the multichip package (MCP) is optimized.

Fig. 8 shows a memory system 100c according to a fourth example of the present invention. Referring to FIG. 8, the memory system 100c includes a first package P1 and a second package P2.

The first package P1 may be a logic package. The first package P1 may be a memory controller. The first package P1 includes a printed circuit board PCB1, a die D1 provided on the printed circuit board PCB1, bonding wires BW1 connecting the printed circuit board PCB1 and the die D1, A mold M1 for protecting the die D1 and the bonding wires BW1, and solder balls SB1.

The second package P2 may be a memory package. The second package P2 includes a printed circuit board PCB2, a plurality of dies D2 to D7 stacked on the printed circuit board PCB2, a printed circuit board PCB2 and dies D2 to D7 A mold M2 for protecting bonding wires BW2, dies D2 to D7 and bonding wires BW2, and solder balls SB2. The solder balls SB2 may be combined with the printed circuit board PCB1 of the first package P1. The solder balls SB1 of the first package P1 may be electrically connected to the dies D1 of the first package P1 and the dies D2 to D7 of the second package P2.

The first and second packages P1 and P2 may form a package-on-package (PoP).

The dies D2 to D7 of the second package P2 may form a number of ranks other than a power of two. For example, the second and third dies D2 and D3 form the first rank R1, the fourth and fifth dies D4 and D5 form the second rank R2, The sixth and seventh ranks D6 and D7 may form the third rank R3.

If a non-square number of ranks is provided, the operating speed and capacity of the memory system 100c formed in the package-on-package (PoP) is optimized.

Fig. 9 shows a memory system 100d according to a fifth example of the present invention. Referring to Fig. 9, the memory system 100d includes a first package P1 and a second package P2.

Except that the number of memory dies in the second package P2 increases and the memory dies communicate with the memory controller of the first package P1 through a plurality of channels, 100c. Therefore, a detailed description of the redundant configuration is omitted.

The first package P1 includes a plurality of dies D2 to D13. The second through seventh dies D2 through D7 may communicate with the first package P1 via the first channel CH1. The eighth to thirteenth dies D8 to D13 can communicate with the first package P1 via the second channel CH2.

The memory dies connected to each channel may form a number of ranks, not a power of two. For example, in the first channel CH1, the second and third dies D2 and D3 form the first rank R1 and the fourth and fifth dies D4 and D5 form the second rank R1, And the sixth and seventh ranks D6 and D7 may form the third rank R3. In the second channel CH2 the eighth and ninth dies D8 and D9 form the first rank R1 and the tenth and eleventh dies D10 and D11 form the second rank R2, And the twelfth and thirteenth ranks D12 and D13 may form the third rank R3.

If a non-square number of ranks are provided, the operating speed and capacity of the memory system 100d formed with the package-on-package (PoP) is optimized.

10 is a block diagram illustrating a computing device 1000 in accordance with an embodiment of the present invention. 10, a computing device 1000 includes a processor 1110, a memory 1120, a storage 1130, a modem 1140, and a user interface 1150.

The processor 110 may control all operations of the computing device 1000 and may perform logical operations. The processor 1110 may be configured as a system-on-chip (SoC).

The memory 1120 may communicate with the processor 1110. The memory 1120 may be a processor 1110 or an operational memory (or main memory) of the computing device 1000. The memory 1120 may be a volatile memory such as a SRAM (Static RAM), a DRAM (Dynamic RAM), an SDRAM (Synchronous DRAM), or a flash memory, a phase-change RAM (PRAM), a magnetic RAM (MRAM) , FRAM (Ferroelectric RAM), and the like.

The memory 1120 may provide a number of ranks that are not a power of 2 squared per channel, as described with reference to Figures 1-9. Thus, the operating speed and capacity of the computing device 1000, including the processor 1110 and the memory 1120, in communication with the memory 1120 can be optimized.

The storage 1130 may store data to be stored on the computing device 1000 in the long term. The storage 1130 may be a nonvolatile memory such as a hard disk drive (HDD) or a flash memory, a PRAM (Phase-change RAM), an MRAM (Magnetic RAM), an RRAM (Resistive RAM) .

Illustratively, memory 1120 and storage 1130 may be constructed from the same kind of non-volatile memory. At this time, the memory 1120 and the storage 1130 may be constituted by one semiconductor integrated circuit.

The modem 1140 may communicate with an external device under the control of the processor 1110. For example, the modem 1140 can perform wired or wireless communication with an external device. The modem 1140 may be any one of a long term evolution (LTE), a WiMax, a GSM, a CDMA, a Bluetooth, a NFC, a WiFi, (Serial Attachment), SCSI (Small Computer Small Interface), Firewire, PCI (Peripheral Component Interconnection), and the like. And the like. [0035] [0033] The wireless communication system of the present invention may be configured to perform communication based on at least one of various wired communication methods.

The user interface 1150 may communicate with the user under the control of the processor 1110. For example, the user interface 1150 may include user input interfaces such as a keyboard, a keypad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyroscope sensor, The user interface 150 may include user output interfaces such as a Liquid Crystal Display (LCD), an Organic Light Emitting Diode (OLED) display, an AMOLED (Active Matrix OLED) display, an LED, a speaker,

The computing device 1000 may form various devices such as a computer, a notebook computer, a server, a smart television, and the like. The computing device 1000 may form various mobile devices such as a smart phone, a smart pad, a smart camera, and the like.

11 is a flowchart showing a method of manufacturing a semiconductor memory according to an embodiment of the present invention. Illustratively, the manufacturing method shown in Fig. 11 may be a method of manufacturing a memory module. However, the manufacturing method of Fig. 11 is not limited to the manufacturing method of the memory module.

Referring to Fig. 11, in step S110, a plurality of semiconductor dies are prepared.

In step S120, a plurality of semiconductor memory dies are grouped into a plurality of ranks. At this time, a plurality of semiconductor memory dies may be grouped into a number of ranks instead of a power of two.

In step S130, semiconductor memory dies belonging to the same rank are combined with a common chip selection signal line. Further, the same data lines can be commonly coupled to a plurality of ranks. The data lines connected to each rank can be distributed and coupled to the semiconductor memory dies belonging to the rank.

Illustratively, if packaging is performed prior to step S120, the memory module described with reference to FIG. 4 may be fabricated.

Illustratively, if packaging is performed after step S130, the multi-chip package (MCP) described with reference to FIG. 6 or 7, or the package-on-package (PoP) described with reference to FIG. 8 or 9, Can be prepared.

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the claims equivalent to the claims of the present invention as well as the claims of the following.

100, 100a to 100d; Memory system
110; Memory controllers 120, 130; Memory unit
R; Ranks D; Die
PCB; Printed circuit board BW; Bonding wires
M; Molding SB; Solder balls

Claims (10)

Printed circuit board;
First semiconductor packages provided on one side of the printed circuit board; And
And second semiconductor packages provided on the other side of the printed circuit board,
Wherein the number of ranks formed by the first semiconductor packages and the number of ranks formed by the second semiconductor packages are different from each other,
Wherein the semiconductor packages forming one rank receive chip select signals in common and the semiconductor packages forming different ranks receive different chip select signals, respectively. The method according to claim 1,
Wherein the first semiconductor packages form two ranks and the second semiconductor packages form one rank. 3. The method of claim 2,
Wherein the first semiconductor packages are dual die packages (DDP), and the second semiconductor packages are mono die packages. The method of claim 3,
Wherein the semiconductor die of the first layer of the first semiconductor packages forms one rank and the semiconductor die of the second layer forms another rank. The method according to claim 1,
Wherein the first semiconductor packages and the second semiconductor packages have different structures. The method according to claim 1,
Wherein the number of semiconductor die provided in each of the first semiconductor packages is different from the number of semiconductor die provided in each of the second semiconductor packages. Memory controller; And
A plurality of semiconductor dice coupled to the memory controller via a common channel and configured to operate in accordance with control of the memory controller,
The plurality of semiconductor dies forming a number of ranks excluding a power of two,
Wherein the semiconductor dies forming a rank collectively receive a chip select signal and the semiconductor dies forming different ranks receive different chip select signals. 8. The method of claim 7,
Wherein the plurality of semiconductor dies form ranks corresponding to a number of one of 3, 5, 6, 7. 8. The method of claim 7,
Wherein the plurality of semiconductor dies are packaged with the memory controller to form a multi chip package (MCP). 8. The method of claim 7,
Wherein the memory controller forms a first package,
The plurality of semiconductor dies forming at least one second package,
Wherein the first package and the at least one second package form a Package-on-Package (PoP).

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