JP2014116516A - Semiconductor memory device, method for manufacturing the same, and storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of being applied to information equipment such as a memory card and an SSD module and having excellent low power consumption, downsizing performance, and high-speed operation.SOLUTION: A semiconductor memory device comprises: a first substrate 1; a NAND flash unit formed on the first substrate 1 and including a NAND flash memory cell array (a memory cell 5 or the like) and a NAND flash peripheral circuit (a transistor 3 for a peripheral circuit or the like); and a ReRAM unit including a ReRAM memory cell array (a resistance change element 16, a memory cell transistor 11, or the like) and a ReRAM peripheral circuit (a transistor 2 for a peripheral circuit or the like). The ReRAM memory cell array is formed a higher layer than the NAND flash unit. The NAND flash peripheral circuit and the ReRAM peripheral circuit are regions on the first substrate, and formed in a region more peripheral than the NAND flash memory cell array.

Description

  The present invention relates to a semiconductor memory device in which a resistance change type nonvolatile memory device whose resistance value changes by application of a voltage pulse and a NAND flash memory type nonvolatile memory device capable of storing a large amount of data, and It relates to the manufacturing method.

  In recent years, with the advancement of digital technology, electronic devices such as portable information devices and information home appliances have become more sophisticated, and there is a great demand for high-speed operation and low power consumption for these devices. In addition, in storage devices such as SSD (Solid State Drive) modules and SD cards (trademark) such as memory cards that play a very important role in handling big data, there is a demand for large capacity, high speed operation, and low power consumption. In addition, it is also required to cope with space saving such as weight reduction, thickness reduction, and size reduction.

  The SSD module market is explosively expanding and is replacing existing hard disks. SSD modules consume less power than existing hard disks, generate less heat, have excellent impact resistance, and do not generate operational noise. They are suitable for mobile applications, and have been used in notebook computers before desktop computers. . Also, due to the advantages of high throughput and low power consumption, SSD modules are being adopted in server machines in place of hard disks in data centers.

  On the other hand, memory cards are also widely used in portable devices such as digital cameras and mobile phones, and home appliances such as televisions. Currently, low-priced versions with NAND flash memory (hereinafter simply referred to as “NAND flash”) and a controller are the mainstream, but in the future, the capacity will increase and the speed will increase, and the reliability of NAND flash will deteriorate. Therefore, there is a high possibility that a cache memory will be installed in the future. Of course, since it is a mobile application, there is a strong demand for low power consumption and miniaturization.

  In addition, along with the enhancement of functions of these electronic devices, miniaturization and speeding up of semiconductor elements used are rapidly progressing, and there is a great demand for miniaturization of chips. As an example of miniaturization of this chip, PCRAM (Phase-change Random Access Memory), which is a nonvolatile storage memory excellent in consistency with DRAM (Dynamic Random Access Memory), is used without complicating the circuit configuration. There has been proposed a semiconductor memory device that suppresses an increase in the exclusive area and has a high access speed (see, for example, Patent Document 1). In this configuration, a part of the bit line of the DRAM and a part of the bit line of the PCRAM are configured by a common conductive layer, a sense amplifier is connected between the two, the memory device is simplified, and a small area chip is embedded. Chips are realized with fewer process steps.

JP 2006-295130 A

  However, in the above-described conventional semiconductor memory device, PCRAM and DRAM are mixedly mounted. However, since only a part of the bit line is shared, the area reduction is insufficient. In addition, by sharing the bit line, the circuit operation is restricted, and it becomes difficult to operate each memory under the optimum operation condition. Further, the combination of PCRAM and DRAM is still insufficient in terms of reducing power consumption.

  The present invention solves the above-described problems, and provides a semiconductor memory device that can be applied to a storage device such as an SSD module or a memory card, has low power consumption, is excellent in size reduction and high-speed operation, and a manufacturing method thereof. The purpose is to do.

  In order to achieve the above object, one embodiment of a semiconductor memory device according to the present invention includes a first substrate, a NAND flash memory cell array formed on the first substrate, and having a plurality of NAND flash memory cells, and A NAND flash unit including a NAND flash peripheral circuit which is a peripheral circuit for the NAND flash memory cell array, a ReRAM memory cell array having a plurality of resistance change elements, and a ReRAM peripheral circuit which is a peripheral circuit for the ReRAM memory cell array. The ReRAM memory cell array is formed in an upper layer than the NAND flash unit, and the NAND flash peripheral circuit and the ReRAM peripheral circuit are regions on the first substrate, and the NAND Flash memory cell array Remote it is formed in a region of the periphery.

  In order to achieve the above object, one mode of a storage device according to the present invention is a memory card or a solid state drive mounted with the semiconductor storage device.

  In order to achieve the above object, a method for manufacturing a semiconductor memory device according to the present invention includes a step of forming a peripheral circuit transistor of a NAND flash portion in a first region on a substrate; Forming a NAND flash portion memory cell in the second region; forming a NAND flash portion selection transistor in the second region; and forming a ReRAM portion peripheral circuit transistor in the third region on the substrate. A step of forming a peripheral circuit wiring of the NAND flash unit above the first region, a step of forming a wiring of the NAND flash unit above the second region, Forming a memory cell and a wiring of the ReRAM unit above and on the wiring of the NAND flash unit; and a periphery of the ReRAM unit above the third region. And forming a circuit wiring.

  According to the present invention, a semiconductor memory device that can be applied to a storage device such as an SSD module or a memory card, has low power consumption, is excellent in size reduction and high-speed operation, and a manufacturing method thereof are realized.

(A) is an external view and internal configuration diagram of an SSD module, and (b) is a layout diagram showing a circuit configuration of a conventional SSD module. (A) is an external view and internal configuration diagram of a memory card, and (b) is a layout diagram showing a circuit configuration of a conventional memory card. (A) is a layout diagram showing the circuit configuration of the SSD module according to the first mounting example of the present invention, (b) is a layout diagram showing the circuit configuration of the SSD module according to the second mounting example of the present invention. (A) is a layout diagram showing the circuit configuration of the memory card according to the first mounting example of the present invention, (b) is a layout diagram showing the circuit configuration of the memory card according to the second mounting example of the present invention. Sectional drawing which shows the structural example of the semiconductor memory device in Embodiment 1 of this invention. Plan view showing a configuration example of the semiconductor memory device Sectional drawing which shows the manufacturing method of the principal part of the same semiconductor memory device Sectional drawing which shows the manufacturing method (continuation of FIG. 6A) of the principal part of the same semiconductor memory device Sectional drawing which shows the manufacturing method (continuation of FIG. 6B) of the principal part of the same semiconductor memory device Sectional drawing which shows the manufacturing method (continuation of FIG. 6C) of the principal part of the same semiconductor memory device Sectional drawing which shows the manufacturing method (continuation of FIG. 6D) of the principal part of the same semiconductor memory device Sectional drawing which shows the structural example of the semiconductor memory device in Embodiment 2 of this invention. Plan view showing a configuration example of the semiconductor memory device Sectional drawing which shows the manufacturing method of the principal part of the same semiconductor memory device Sectional drawing which shows the manufacturing method (continuation of FIG. 8A) of the principal part of the same semiconductor memory device Sectional drawing which shows the manufacturing method (continuation of FIG. 8B) of the principal part of the same semiconductor memory device Sectional drawing which shows the manufacturing method (continuation of FIG. 8C) of the principal part of the same semiconductor memory device Sectional drawing which shows the manufacturing method (continuation of FIG. 8D) of the principal part of the same semiconductor memory device The figure which shows the variation of the layout of the semiconductor memory device of this invention

(Knowledge that became the basis of the present invention)
1A is an external view and an internal configuration diagram of the SSD module 30, and FIG. 1B is a layout diagram illustrating a circuit configuration of the SSD module 30 recently proposed. As shown in this figure, the semiconductor integrated circuit in such an application includes a NAND flash memory 31, a controller 33, and a cache memory 32 (ReRAM: Resistance Random Access Memory in this example). The NAND flash 31 uses a plurality of memory chips and stores a large amount of data. By arranging the NAND flash 31 in parallel so that they can be accessed at the same time, it is possible to increase the writing speed in large-capacity data communication. Next, the controller 33 is a circuit that controls reading and writing between the NAND flash 31 and the external interface, and is an important integrated circuit that affects the performance and life of the SSD module 30. In particular, wear leveling (write distribution processing) and defective block processing are unique to the SSD module, and contribute to improving the performance of reading, rewriting speed, and number of rewritings. Finally, cache memories 32 are often mounted on high-end products. It is used to temporarily hold the entire target block during partial writing. In addition, a plurality of fine write requests for one block are stored in the cache memory 32 without being written to the NAND flash 31, and are written together at a certain time, thereby substantially improving the number of possible writes. Also used for. Usually, a DRAM of about 128 MB is often used as the cache memory, which contributes to speeding up reading and writing. In addition, recently, ReRAM has been proposed for low power consumption and data retention during power outages.

  2A is an external view and an internal configuration diagram of the memory card 35, and FIG. 2B is a layout diagram illustrating a circuit configuration of the memory card 35 that has been recently proposed. As shown in this figure, like the SSD module 30, the semiconductor integrated circuit in such an application includes a NAND flash memory 36, a controller 38, and a cache memory 37 (ReRAM in this example). The basic function of each chip is as described above. The difference from the SSD module 30 is that the capacity of the mounted NAND flash 36 is small.

  When the above-described semiconductor integrated circuit is mounted as a chip, it is packaged by POP (Package on Package) or SIP (System in Package) in view of the necessity for high-speed operation and yield loss. For example, as shown in FIG. 1B, by stacking the NAND flash 31 with a POP package, a larger mounting area can be secured when the device is mounted. Also, since each package can be tested individually, yield loss can be reduced. The wiring between the memories can be shortened, and the influence of reflection and noise can be minimized. On the other hand, even when the SIP packages are stacked, the entire system can be contained in one package, so that the mounting area when mounting the device can be drastically reduced.

  However, these conventional packages have the following problems common to both (POP and SIP). That is, although the area can be reduced by stacking chips, it is inevitable that the thickness increases. Moreover, although the wiring delay is suppressed by the connection on the wiring board, the wiring delay in the wire wiring due to the mounting still remains. Even in the storage devices such as the SSD module 30 and the memory card 35 described above, the wiring delay due to the thinning and miniaturization and the increase in the amount of data communication is becoming a problem.

  Therefore, the inventors have devised a semiconductor memory device suitable for these storage devices. FIG. 3A shows a layout showing a circuit configuration of an SSD module 40 which is an example of a storage device in which the semiconductor storage device 42 according to the first mounting example of the present invention is mounted. In this example, the semiconductor memory device 42 illustrated in the upper left forms NAND flash and ReRAM together as a single chip in the manufacturing process of the previous process. Specifically, a variable resistance nonvolatile memory device that is capable of high-speed operation with low power consumption as a device and can be integrated in a wiring process while suppressing a thermal budget in the upper part of a NAND flash. ReRAM is used.

  FIG. 3B shows a layout showing a circuit configuration of the SSD module 45 in which the semiconductor memory device 47 according to the second mounting example of the present invention is mounted. Specifically, the semiconductor storage device 47 illustrated in the upper left is mounted together with the NAND flash as a single chip by using a mixed ReRAM process in which the integrated circuit of the controller is embedded in the ReRAM.

  FIG. 4A shows a layout showing a circuit configuration of the memory card 50 on which the semiconductor memory device 51 according to the first mounting example of the present invention is mounted. In this example, as in FIG. 3A, in the semiconductor memory device 51 illustrated on the right, NAND flash and ReRAM are formed together as a single chip in the manufacturing process of the previous process.

  FIG. 4B shows a layout showing a circuit configuration of the memory card 55 on which the semiconductor memory device 56 according to the second mounting example of the present invention is mounted. Similar to FIG. 3B, specifically, the semiconductor memory device 56 is mounted together with the NAND flash as a single chip by using a mixed ReRAM process in which the integrated circuit of the controller is mounted in the ReRAM.

  With the above configuration, the conventional stack technology such as POP and SIP becomes unnecessary, and a thin package with a small area can be realized.

  The external appearance and internal configuration of the SSD modules 40 and 45 and the memory cards 50 and 55 on which the semiconductor memory devices according to the first and second mounting examples of the present invention are mounted are shown in FIG. It may be in the form as shown.

  As described above, the semiconductor memory device and the manufacturing method thereof according to the present invention are a NAND flash that is a nonvolatile memory device capable of holding a large amount of data, and a nonvolatile memory device that has low power consumption and excellent high-speed operation. The present invention relates to a structure in which ReRAM is integrated on a substrate to form one chip. By disposing the main memory cell array of ReRAM above the NAND flash, the chip area can be greatly reduced. This is because three-dimensional integration of NAND flash and ReRAM is possible without affecting the characteristics of the NAND flash because a high heat treatment temperature is not required when forming the variable resistance layer of the variable resistance element that is the core of the ReRAM. Because it can be done. In addition, by forming the NAND flash peripheral circuit and the ReRAM peripheral circuit independently on the substrate, each can be operated in an optimum state as in the case of a single chip. In particular, these can greatly contribute to the reduction in size, weight and thickness of storage devices such as SSD modules and memory cards.

  In other words, in order to achieve the above object, an embodiment of a semiconductor memory device according to the present invention includes a first substrate and a NAND flash memory cell array formed on the first substrate and having a plurality of NAND flash memory cells. A NAND flash unit including a NAND flash peripheral circuit which is a peripheral circuit for the NAND flash memory cell array, a ReRAM memory cell array having a plurality of resistance change elements, and a ReRAM peripheral which is a peripheral circuit for the ReRAM memory cell array A ReRAM unit including a circuit, the ReRAM memory cell array is formed in an upper layer than the NAND flash unit, and the NAND flash peripheral circuit and the ReRAM peripheral circuit are regions on the first substrate, The NAND flash memory cell It is formed in a region of the peripheral edge than the array.

  As a result, the ReRAM memory cell array, which is the main area in the ReRAM unit, is formed in an upper layer than the NAND flash unit, and the NAND flash unit and the ReRAM unit are integrated into one chip. Compared to a conventional package arranged side by side on a wiring board, a non-volatile memory device having a package that is significantly reduced in size is realized.

  In other words, in the same way as when ReRAM and NAND flash are formed separately, a one-chip nonvolatile semiconductor memory device that takes advantage of the low power consumption and high-speed operation of ReRAM and the large storage capacity of NAND flash is realized. can do. Further, by arranging the ReRAM memory cell array, which is the main area, above the NAND flash part (upper layer), the area can be significantly reduced.

  Therefore, a variable resistance nonvolatile memory device and a NAND flash memory nonvolatile memory device that can be applied to a storage device such as an SSD module or a memory card, and have low power consumption, excellent miniaturization, and high-speed operation are combined. A chip is realized.

  Here, the ReRAM memory cell array may be formed at least above the NAND flash memory cell array. For example, the ReRAM memory cell array may be formed above the NAND flash memory cell array and above the NAND flash peripheral circuit. As a result, the package size of the nonvolatile memory device is reduced by the area of the ReRAM memory cell array.

  Further, the ReRAM peripheral circuit may be formed in a region on the first substrate and in a peripheral region with respect to the NAND flash peripheral circuit. As a result, the ReRAM peripheral circuit is formed on the first substrate 1 with few crystal defects, so that a reliable ReRAM peripheral circuit that operates stably is formed.

  The ReRAM memory cell array further includes a plurality of memory cells formed on the second substrate in addition to the plurality of resistance change elements. The second substrate is formed above the NAND flash unit. A transistor may be included. As a result, a plurality of memory cell transistors constituting the ReRAM memory cell array are formed on the second substrate formed above the NAND flash portion, so that a 1T1R (one transistor and one resistance change element) type ReRAM memory cell is formed. Is realized.

  The ReRAM memory cell array may be a cross-point type memory cell array having a plurality of current control elements in addition to the plurality of resistance change elements. Thereby, since the ReRAM memory cell array has a plurality of current control elements in addition to a plurality of resistance change elements, a semiconductor memory device including a cross-point type memory cell array is realized.

  Furthermore, a first wiring layer, a second wiring layer, and a third wiring layer are provided above the first substrate in order from the side closer to the first substrate. The wiring layer and the second wiring layer may be formed in the NAND flash unit, and the third wiring layer may be a lowermost wiring layer of the ReRAM memory cell array. Thereby, a semiconductor memory device having a multilayer wiring layer is realized.

  In order to achieve the above object, one mode of the storage device according to the present invention may be a memory card or a solid state drive equipped with the semiconductor storage device. As a result, an SSD module or memory card having a mixed chip of a resistance change type nonvolatile memory device and a NAND flash memory type nonvolatile memory device, which is low power consumption, excellent in miniaturization and high speed operation, is realized.

  In order to achieve the above object, a method of manufacturing a semiconductor memory device according to the present invention includes a step of forming a peripheral circuit transistor of a NAND flash portion in a first region on a substrate, and a second region on the substrate. Forming a NAND flash portion memory cell, forming a NAND flash portion selection transistor in the second region, forming a ReRAM portion peripheral circuit transistor in the third region on the substrate, and Forming a peripheral circuit wiring of the NAND flash portion above the first region, forming a NAND flash portion wiring above the second region, above the second region, and Forming a memory cell and a wiring of the ReRAM unit on the wiring of the NAND flash unit, and for a peripheral circuit of the ReRAM unit above the third region And forming a line. As a result, a variable resistance nonvolatile memory device and a NAND flash memory nonvolatile memory device, which have low power consumption, can be applied to a storage device such as an SSD module or a memory card, and are excellent in miniaturization and high-speed operation, are combined. A method of manufacturing a semiconductor memory device that is a chip is realized.

  Here, the step of forming the memory cell and the wiring of the ReRAM portion includes a step of forming a second substrate, a step of forming a memory cell transistor of the ReRAM portion on the second substrate, Forming a variable resistance element of the ReRAM portion. As a result, a plurality of memory cell transistors constituting the ReRAM memory cell array are formed on the second substrate formed above the NAND flash unit, so that a semiconductor memory device including 1T1R type ReRAM memory cells is manufactured.

  In the step of forming the memory cell and the wiring in the ReRAM portion, a memory cell including a resistance change element and a current control element may be formed. Thus, since the ReRAM memory cell array has a plurality of current control elements in addition to a plurality of resistance change elements, a semiconductor memory device including a cross-point type memory cell array is manufactured.

  Embodiments of a semiconductor memory device and a manufacturing method thereof according to the present invention will be described below with reference to the drawings. Note that each of the embodiments described below shows a specific example of the present invention. The numerical values, shapes, materials, constituent elements, arrangement positions and connecting forms of the constituent elements, steps, order of steps, and the like shown in the following embodiments are merely examples, and are not intended to limit the present invention. In addition, among the constituent elements in the following embodiments, constituent elements that are not described in the independent claims indicating the highest concept are described as optional constituent elements.

(Embodiment 1)
A semiconductor memory device according to a first embodiment of the present invention includes a first substrate, a NAND flash memory cell array formed on the first substrate and having a plurality of NAND flash memory cells, and a NAND flash memory cell array A NAND flash unit including a NAND flash peripheral circuit as a peripheral circuit, a ReRAM memory cell array having a plurality of resistance change elements, a ReRAM unit including a ReRAM peripheral circuit as a peripheral circuit for the ReRAM memory cell array, and a NAND flash unit A second substrate formed above. Here, the ReRAM memory cell array is formed in an upper layer than the NAND flash unit. The NAND flash peripheral circuit and the ReRAM peripheral circuit are formed in a region on the first substrate and in a peripheral region with respect to the NAND flash memory cell array. Further, the ReRAM memory cell array has a plurality of memory cell transistors formed on the second substrate in addition to the plurality of resistance change elements. That is, in this embodiment, the ReRAM memory cell is a so-called 1T1R type.

  With the above configuration, a single-chip non-volatile semiconductor memory that takes advantage of the low power consumption and high speed of ReRAM, the large storage capacity of NAND flash, etc., as in the case where ReRAM and NAND flash are formed independently. An apparatus can be realized. Further, by arranging the ReRAM memory cell array, which is the main area, above the NAND flash part (upper layer), the area can be significantly reduced.

  A specific example of the structure of the semiconductor memory device in this embodiment will be described below with reference to FIGS. 5A and 5B. FIG. 5A is a cross-sectional view showing a configuration example of the semiconductor memory device 1000 according to the first embodiment of the present invention. FIG. 5B is a plan view thereof.

  The semiconductor memory device 1000 has three areas on the first substrate 1, a NAND flash memory cell array area 101, a NAND flash peripheral circuit area 102, and a ReRAM peripheral circuit area 202. Further, the ReRAM memory cell array region 201 is arranged in a layer above the NAND flash portion (in the present embodiment, above the NAND flash memory cell array region 101 and the NAND flash peripheral circuit region 102). That is, in this embodiment, the ReRAM memory cell array region 201 is located above the NAND flash memory cell array region 101 and above the NAND flash peripheral circuit region 102. In addition, the ReRAM peripheral circuit region 202 is located on the first substrate 1 and at the periphery of the NAND flash peripheral circuit region 102.

  In FIG. 5B, when the semiconductor memory device 1000 is viewed from above, the NAND flash memory cell array region 101 is inside the smaller dotted frame. The NAND flash peripheral circuit region 102 is outside the smaller dotted frame and inside the larger dotted frame. The ReRAM memory cell array region 201 is inside the smaller solid line frame (that is, a region where the NAND flash memory cell array region 101 and the NAND flash peripheral circuit region 102 are combined). The ReRAM peripheral circuit area 202 is outside the smaller solid line frame and inside the larger solid line frame.

  Here, the NAND flash memory cell array region 101 forms a NAND flash memory cell array having a plurality of NAND flash memory cells (for example, floating gate type or MONOS (Metal Oxide Silicon Silicon type) memory cells) and a selection transistor. It is an area. The NAND flash peripheral circuit area 102 is an area for forming a NAND flash peripheral circuit which is a peripheral circuit for the NAND flash memory cell array. The ReRAM memory cell array region 201 is a region for forming a ReRAM memory cell array having a plurality of resistance change elements. The ReRAM peripheral circuit area 202 is an area for forming a ReRAM peripheral circuit that is a peripheral circuit for the ReRAM memory cell array. Note that the NAND flash memory cell array region 101 and the NAND flash peripheral circuit region 102 mean a space above the first substrate 1 and below the second substrate 10 in the stacking direction. In addition, the ReRAM memory cell array region 201 means a space above the second substrate 10 in the stacking direction. A circuit including the NAND flash memory cell array and the NAND flash peripheral circuit is referred to as a NAND flash unit, and a circuit including the ReRAM memory cell array and the ReRAM peripheral circuit is referred to as a ReRAM unit.

  Here, the NAND flash memory cell array is a collection of NAND flash memory cells. The ReRAM memory cell array is a group of non-volatile memory elements (resistance change elements) whose resistance value changes with application of a voltage pulse. The peripheral circuit for the NAND flash memory cell array is a circuit related to the NAND flash memory cell array, a selection circuit that selects a NAND flash memory cell from the NAND flash memory cell array, and a drive that drives the selected NAND flash memory cell. The circuit includes at least one of a circuit, a writing circuit to the NAND flash memory cell array, a reading circuit from the NAND flash memory cell array, a control circuit for controlling writing and reading, and a power supply circuit for supplying power for writing and reading. The peripheral circuit for the ReRAM memory cell array is a circuit related to the ReRAM memory cell array, a selection circuit (address / decode circuit) for selecting a ReRAM memory cell from the ReRAM memory cell array, and driving the selected ReRAM memory cell. At least one of a drive circuit, a write circuit to the ReRAM memory cell array, a read circuit from the ReRAM memory cell array, a control circuit that controls writing and reading, and a power supply circuit that supplies power for writing and reading is included.

  As shown in FIG. 5A, a NAND flash memory cell (NAND flash memory cell) 5 and a bit line selection transistor 4 are provided on a first substrate 1 in a NAND flash memory cell array region 101. A peripheral circuit transistor 3 for NAND flash is formed on the first substrate 1, and a peripheral circuit transistor 2 for ReRAM is formed on the first substrate 1 in the ReRAM peripheral circuit region 202. In this figure, a portion in the semiconductor memory device 1000 where no circuit components and wiring are formed above the first substrate 1 (white portion in the figure) is an interlayer insulating layer. The same applies to other sectional views.

  In an interlayer insulating layer covering the various transistors (memory cell 5, selection transistor 4, peripheral circuit transistor 3, peripheral circuit transistor 2), a first electrode connected to the main electrode of each transistor on the first substrate 1 is provided. One contact plug 6 is formed, and a first wiring (first wiring layer) 7 connected to the first contact plug 6 is formed on the first contact plug 6. A second contact plug 8 connected to the first wiring 7 is formed in the interlayer insulating layer covering the first wiring 7. Furthermore, a second wiring (second wiring layer) 9 connected to the second contact plug 8 is formed on the second contact plug 8. With the components described above, the NAND flash unit is completed as a device.

  A second substrate 10 made of, for example, silicon is formed at least partly above the NAND flash memory cell array region 101 and the NAND flash peripheral circuit region 102 (that is, above the NAND flash unit). Yes. A ReRAM memory cell transistor 11 is formed on the second substrate 10. In the interlayer insulating layer covering the ReRAM memory cell transistor 11, a 3A contact plug 12 connected to the main electrode of the ReRAM memory cell transistor 11 on the second substrate 10 is formed. In a region where the substrate 10 is not formed, a 3B contact plug 13 connected to the second wiring 9 is formed. A third wiring (third wiring layer) 14 is formed on the 3A contact plug 12 and the 3B contact plug 13. In the ReRAM memory cell array region 201, a 4A contact plug 15 is formed on the 3A contact plug 12 in addition to the 3rd wiring 14 functioning as a bit line, and a resistance change element 16 is formed thereon. Is formed.

  The resistance change element 16 includes a lower electrode, a resistance change layer, and an upper electrode. In addition, although the planar structure was illustrated here as a structure of the resistance change element 16, it may be a hole type. A 4B contact plug 17 is formed on the variable resistance element 16.

  On the other hand, in the ReRAM peripheral circuit region 202, a 4C contact plug 18 connected to the third wiring 14 is formed in an interlayer insulating layer covering the third wiring 14. Further, a fourth wiring (fourth wiring layer) 19 connected to the 4B contact plug 17 and the 4C contact plug 18 is formed on the 4B contact plug 17 and the 4C contact plug 18.

  As described above, in the semiconductor memory device 1000 according to the present embodiment, the first wiring 7, the second wiring 9, and the first wiring 1 are arranged above the first substrate 1 in order from the first substrate 1. Four wiring layers of the third wiring 14 and the fourth wiring 19 are provided. Here, two wiring layers are used for the NAND flash, and two wiring layers are used for the ReRAM. As a result, the semiconductor memory device of the present invention can be realized with a minimum number of wiring layers, that is, with a reduced number of process steps and reduced costs. However, the present invention is not limited to this, and the number of wiring layers may be increased in response to requests for encryption and higher functionality, and the number of wiring layers may be decreased in response to requests for downsizing. It doesn't matter. For example, one wiring layer may be used for ReRAM.

  The boundary between the NAND flash memory cell array region 101 and the NAND flash peripheral circuit region 102 and the boundary between the ReRAM memory cell array region 201 and the ReRAM peripheral circuit region 202 are boundaries for functionally dividing the blocks. In this specification, for convenience of understanding, the former boundary is defined by connecting the outer edges of the outermost peripheral elements of the NAND flash memory cells 5 and the NAND flash selection transistor 4 with a line. Of the plurality of variable resistance elements 16, the outer edges of the outermost variable resistance elements are connected by lines. Therefore, the NAND flash peripheral circuit area 102 and the ReRAM peripheral circuit area 202 may overlap each other (that is, if there is no actual influence on the operation of each memory, there is a shared circuit). Good). Here, at least a part of the NAND flash memory cell array region 101 may be covered and the ReRAM memory cell array region 201 may be disposed, and a semiconductor memory device effective for a storage device such as an SSD module or a memory card can be realized. it can.

  As described above, the semiconductor memory device 1000 according to the present embodiment is formed on the first substrate 1 and has a NAND flash memory cell array (memory cell 5, selection transistor 4, etc.) having a plurality of NAND flash memory cells 5. And a NAND flash peripheral circuit (peripheral circuit transistor 3 or the like) that is a peripheral circuit for the NAND flash memory cell array, and a ReRAM memory cell array (memory cell transistor 11, resistor) including a plurality of resistance change elements 16. And a ReRAM unit including a ReRAM peripheral circuit (peripheral circuit transistor 2 or the like) which is a peripheral circuit for the ReRAM memory cell array. The ReRAM memory cell array is formed in an upper layer than the NAND flash unit, and the NAND flash peripheral circuit and the ReRAM peripheral circuit are formed in a region on the first substrate 1 and in a peripheral region from the NAND flash memory cell array. Has been. As a result, the ReRAM memory cell array, which is the main area, is arranged above (above) the NAND flash unit, so that a semiconductor memory device with a significantly reduced area is realized, such as an SSD module, memory card, etc. Thus, a mixed chip of a resistance change type nonvolatile memory device and a NAND flash memory type nonvolatile memory device, which can be applied to a storage device, has low power consumption and is excellent in miniaturization and high speed operation.

  In this embodiment, the ReRAM memory cell is a so-called 1T1R type. For this purpose, the second substrate 10 is provided above the NAND flash unit, and the ReRAM memory cell array has a plurality of memory cell transistors 11 formed on the second substrate 10 in addition to the plurality of resistance change elements 16. .

  Next, a method for manufacturing the semiconductor memory device 1000 according to the present embodiment configured as described above will be described. FIG. 6A (a) to FIG. 6E (i) are cross-sectional views of semiconductor memory device 1000 showing the method of manufacturing semiconductor memory device 1000 in the first embodiment of the present invention.

  First, as shown in FIG. 6A, NAND flash memory cells 5 are formed in the NAND flash memory cell array region 101 of the first substrate 1.

  Next, as shown in FIG. 6A (b), a NAND flash selection transistor 4 is formed in the NAND flash memory cell array region 101 of the first substrate 1.

  Next, as shown in FIG. 6C, the NAND flash peripheral circuit transistor 3 is formed in the NAND flash peripheral circuit region 102 of the first substrate 1.

  Next, as shown in FIG. 6D, a ReRAM peripheral circuit transistor 2 is formed in the ReRAM peripheral circuit region 202 of the first substrate 1.

  Next, as shown in FIG. 6A (e), an interlayer insulating layer that covers the above-described various transistors is formed, and a first contact plug 6 that passes through the interlayer insulating layer and is connected to the main electrodes of the various transistors is formed. To do. Further, a first wiring 7 connected to the first contact plug 6 is formed on the interlayer insulating layer.

  Next, as shown in FIG. 6B (f), after an interlayer insulating layer covering the first wiring 7 is formed, a second contact plug 8 connected to the first wiring 7 is formed. Further, a second wiring 9 connected to the second contact plug 8 is formed on the interlayer insulating layer.

  Next, as shown in FIG. 6B (g), after forming an interlayer insulating layer covering the whole, a second substrate 10 is formed above the NAND flash memory cell array region 101. About the 2nd board | substrate 10, the Si semiconductor is formed by patterning using the method of selectively forming Si semiconductor with a laser, or a desired mask. Subsequently, the ReRAM memory cell transistor 11 is formed in the ReRAM memory cell array region 201 of the second substrate 10. It is inevitable that the second substrate 10 produced here has more crystal defects than the first substrate 1 formed by the ingot method, but the ReRAM memory cell transistor 11 has an OFF characteristic. Since the driving current with high ON characteristics is more important than the low leakage performance, desired characteristics can be realized. Since the circuit for controlling the driving of the ReRAM is formed on the first substrate 1, there is no problem in device operation. Here, as will be described in the next step, in the ReRAM peripheral circuit region 202, a part of the contact plug 13 for connecting the second wiring 9 and the third wiring 14 can be formed. In this case, the second substrate 10 may not be formed, or the second substrate 10 may be removed.

  Next, as shown in (h) of FIG. 6C, an interlayer insulating layer that covers the memory cell transistor 11 of ReRAM is formed, and the third insulating layer is formed through the third insulating layer A connected to the main electrode of the memory cell transistor 11 of ReRAM. The contact plug 12 and the 3B contact plug 13 connected to the second wiring 9 are formed. Further, a third wiring 14 connected to the 3A contact plug 12 and the 3B contact plug 13 is formed on the interlayer insulating layer.

  Next, as shown in FIG. 6D (i), after forming an interlayer insulating layer covering the third wiring 14, the interlayer insulating layer is formed on the 3A contact plug 12 in the ReRAM memory cell array region 201. A 4A contact plug 15 penetrating the layer is formed. Further, a resistance change element 16 including a lower electrode, a resistance change layer, and an upper electrode is formed on the 4A contact plug 15.

  Finally, as shown in FIG. 6E (j), an interlayer insulating layer covering the resistance change element 16 is formed, and in the interlayer insulation layer, a 4B contact plug 17 connected to the resistance change element 16 is formed. Then, a 4C contact plug 18 connected to the third wiring 14 is formed. Further, the fourth wiring 19 connected to these contact plugs is formed on the interlayer insulating layer, and the semiconductor memory device 1000 is completed.

  As described above, the manufacturing method of the semiconductor memory device 1000 according to the present embodiment includes (1) the NAND flash unit in the first region (NAND flash peripheral circuit region 102) on the first substrate 1 as main steps. Forming a peripheral circuit transistor; (2) forming a memory cell transistor of a NAND flash portion in a second region (NAND flash memory cell array region 101) on the first substrate 1; Forming a selection transistor of the NAND flash unit in a second region (NAND flash memory cell array region 101) on one substrate 1, and (4) a third region (ReRAM peripheral circuit region 202) on the first substrate 1. Forming a peripheral circuit transistor of the ReRAM portion in the first region (5) first region (NAND flash peripheral circuit region) 02) forming a peripheral circuit wiring (first wiring 7) in the NAND flash section above (02), and (6) wiring in the NAND flash section above the second area (NAND flash memory cell array area 101). A step of forming (second wiring 9); and (7) a memory cell in the ReRAM section (memory cell transistor 11, resistance change element 16, etc.) above the second region and on the memory cell 5 and wiring in the NAND flash section. ) And a wiring (third wiring 14), and (8) a peripheral circuit wiring (first wiring 7, second wiring 9, third wiring) in the ReRAM section above the third region. 14).

  In this embodiment, since the ReRAM memory cell is composed of 1T1R, the process of forming the memory cell and the wiring of the ReRAM portion includes (1) a process of forming the second substrate 10 and (2) a second process. A step of forming a memory cell transistor (memory cell transistor 11) of the ReRAM portion on the second substrate 10 and a step of (3) forming a resistance change element (resistance change element 16) of the ReRAM portion.

  With such a manufacturing method, the resistance change type that is low power consumption and excellent in miniaturization and high-speed operation that can be applied to the semiconductor storage device 1000 in this embodiment, that is, a storage device such as an SSD module or a memory card. A mixed chip of a nonvolatile memory device and a NAND flash memory type nonvolatile memory device is manufactured.

  Although not shown in the semiconductor memory device 1000 of the present embodiment, a system that is an SOC (System-on-a-chip) in an area other than the above NAND flash and ReRAM as in the embedded ReRAM process and the like. An LSI (SSD module or memory card, controller) may be formed. That is, the present invention may be realized as a storage device such as an SSD module or a memory card provided with the semiconductor storage device in the present embodiment. At that time, circuits such as various processors may be incorporated in the semiconductor memory device in this embodiment.

  As in the case where ReRAM and NAND flash are independently formed by the above manufacturing method, a one-chip non-volatile semiconductor that takes advantage of ReRAM's low power consumption and high speed, NAND flash's large storage capacity, etc. A storage device can be realized. The reason is that the peripheral circuit transistors necessary for controlling the operation and the NAND flash memory cell transistors sensitive to crystal defects are formed on the first substrate 1 which is stable and has few crystal defects. This is because the memory cell transistor for ReRAM that only needs the driving current and the switching characteristics is formed on the second substrate 10. Further, by utilizing the fact that the thermal budget is small for the formation of the variable resistance element of ReRAM, the ReRAM memory cell array, which is the main area, is arranged above the NAND flash part (upper layer), so that a large area can be obtained. Reduction is possible. As a result, a thin and small-sized semiconductor memory device that does not require stack packaging technology can be realized.

(Embodiment 2)
A semiconductor memory device according to a second embodiment of the present invention includes a first substrate, a NAND flash memory cell array formed on the first substrate and having a plurality of NAND flash memory cells, and a NAND flash memory cell array A NAND flash unit including a NAND flash peripheral circuit as a peripheral circuit, a ReRAM memory cell array having a plurality of resistance change elements, and a ReRAM unit including a ReRAM peripheral circuit as a peripheral circuit for the ReRAM memory cell array. Here, the ReRAM memory cell array is formed in an upper layer than the NAND flash unit. The NAND flash peripheral circuit and the ReRAM peripheral circuit are formed in a region on the first substrate and in a peripheral region with respect to the NAND flash memory cell array. Furthermore, the ReRAM memory cell array is a cross-point type memory cell array having a plurality of current control elements in addition to a plurality of resistance change elements. That is, in this embodiment, the ReRAM memory cell is a cross-point type configured by connecting one current control element (for example, a bidirectional diode) and one resistance change element in series.

  With the above configuration, a single-chip non-volatile semiconductor memory that takes advantage of the low power consumption and high speed of ReRAM, the large storage capacity of NAND flash, etc., as in the case where ReRAM and NAND flash are formed independently. An apparatus can be realized. In addition, since the cross-point type ReRAM memory cell array, which is the main area, can be multilayered above the NAND flash part (upper layer), the capacity can be increased and the chip area can be greatly increased. The area can be reduced.

  Hereinafter, a specific example of the structure of the semiconductor memory device in this embodiment will be described with reference to FIGS. 7A and 7B. FIG. 7A is a cross-sectional view showing a configuration example of the semiconductor memory device 2000 according to the second embodiment of the present invention. FIG. 7B is a plan view thereof.

  The configuration of the semiconductor memory device 2000 according to the second embodiment of the present invention is different from the semiconductor memory device 1000 according to the first embodiment of the present invention in that the switching element of the ReRAM memory cell array is not a memory cell transistor but a current control element. (For example, a bidirectional diode). That is, in the present embodiment, the memory cell composed of the memory cell transistor and the resistance change element in the first embodiment is replaced with a cross-point type memory cell composed of the resistance change element and the current control element. Yes. For this reason, since the memory cell transistor is not required, the second substrate 10 required in the first embodiment is not required. In this respect, the semiconductor memory device 2000 in the present embodiment has a simpler structure. The structure of the NAND flash unit and the plan view of the NAND flash region and the ReRAM region are the same as in the first embodiment.

  The semiconductor memory device 2000 has three areas on the first substrate 1, a NAND flash memory cell array area 101, a NAND flash peripheral circuit area 102, and a ReRAM peripheral circuit area 202. Further, the ReRAM memory cell array region 201 is arranged in a layer above the NAND flash portion (in the present embodiment, above the NAND flash memory cell array region 101 and the NAND flash peripheral circuit region 102). That is, in this embodiment, as in the first embodiment, the ReRAM memory cell array region 201 is located above the NAND flash memory cell array region 101 and above the NAND flash peripheral circuit region 102. In addition, the ReRAM peripheral circuit region 202 is located on the first substrate 1 and at the periphery of the NAND flash peripheral circuit region 102. 7B, the positions of the NAND flash memory cell array region 101, the NAND flash peripheral circuit region 102, the ReRAM memory cell array region 201, and the ReRAM peripheral circuit region 202 when the semiconductor memory device 2000 is viewed from above are as follows. This is the same as Embodiment 1 shown in FIG. 5B.

  As shown in FIG. 7A, a NAND flash memory cell 5 and a selection transistor 4 are formed on the first substrate 1 in the NAND flash memory cell array region 101, and a first substrate 1 in the NAND flash peripheral circuit region 102 is formed on the first substrate 1. The peripheral circuit transistor 3 of the NAND flash is formed on the first substrate 1 in the ReRAM peripheral circuit area 202, and the peripheral circuit transistor 2 of the ReRAM is formed.

  In an interlayer insulating layer covering the various transistors (memory cell 5, selection transistor 4, peripheral circuit transistor 3, peripheral circuit transistor 2), a first electrode connected to the main electrode of each transistor on the first substrate 1 is provided. One contact plug 6 is formed, and a first wiring (first wiring layer) 7 connected to the first contact plug 6 is formed on the first contact plug 6. In the NAND flash memory cell array region 101, a first wiring 7 connected to a word line or a bit line is formed on the first contact plug 6.

  On the other hand, in the NAND flash peripheral circuit region 102 and the ReRAM peripheral circuit region 202, a second contact plug 8 connected to the first wiring 7 is formed in an interlayer insulating layer covering the first wiring 7. Further, a second wiring (second wiring layer) 9 connected to these is formed on the second contact plug 8. With the components described above, the NAND flash unit is completed as a device.

  Above the NAND flash memory cell array region 101 and the NAND flash peripheral circuit region 102, a ReRAM memory cell array region 201 in which a cross-point type ReRAM memory cell array is formed is disposed. In the ReRAM memory cell array region 201, a second wiring 9 and a third wiring (third wiring layer) 14 are formed via an interlayer insulating layer, and a 4A contact plug 15 and a first wiring are formed thereon. A variable resistance element 16 of a layer is formed.

  The first-layer cross-point type memory cell 20 includes a lower electrode, a current control layer, a resistance change layer, and an upper electrode that constitute a resistance change element and a current control element, and has a non-linear current-voltage characteristic, that is, a diode characteristic function. Have On these cross-point type memory cells 20, a third wiring 14 and a fourth wiring (fourth wiring layer) 19 orthogonal to the third wiring 14 connected to the third wiring 14 are formed. Yes. On the fourth wiring 19, a 5A contact plug 21 and a second-layer cross-point type memory cell 22 are formed.

  The cross-point type memory cell 22 in the second layer is also composed of a lower electrode, a current control layer, a resistance change layer, and an upper electrode that constitute the resistance change element and the current control element. Characteristic, that is, a diode characteristic function. On these second-layer cross-point type memory cells 22, there are connected a fourth wiring 19 and a fifth wiring (fifth wiring layer) 24 orthogonal to the fourth wiring 19. Is formed. Here, a planar structure is illustrated as a cross-point type memory cell (a memory cell in which a resistance change element and a current control element are connected to an intersection of upper and lower wirings), but a hole type may also be used. . In the ReRAM memory cell array region 201, the third wiring 14 and the fourth wiring 19 are orthogonal to each other, and the fourth wiring 19 and the fifth wiring 24 are orthogonal to each other. This is why it is called a cross-point type.

  On the other hand, in the ReRAM peripheral circuit region 202, the 3B contact plug 13 connected to the second wiring 9 is formed in the interlayer insulating layer covering the second wiring 9. A third wiring 14 is formed on the third-B contact plug 13. A 4C contact plug 18 connected to the third wiring 14 is formed in the interlayer insulating layer covering the third wiring 14, and further connected to the fourth C contact plug 18. A fourth wiring 19 is formed. Similarly, a fifth C contact plug 23 connected to the fourth wiring 19 is formed in the interlayer insulating layer covering the fourth wiring 19, and the fifth C contact plug 23 is further formed on the fifth C contact plug 23. A wiring 24 is formed. In the ReRAM peripheral circuit region 202, the third wiring 14, the fourth wiring 19, and the fifth wiring 24 are arranged in a desired layout. Therefore, it is not necessary for all of these wirings to be orthogonal to each other, and a part of the wiring may be arranged in parallel with other wirings.

  As described above, the semiconductor memory device 2000 according to the present embodiment is formed on the first substrate 1 and has a NAND flash memory cell array (a memory cell 5, a selection transistor 4, etc.) having a plurality of NAND flash memory cells 5. And a NAND flash peripheral circuit (peripheral circuit transistor 3 or the like) that is a peripheral circuit for the NAND flash memory cell array, and a ReRAM memory cell array (first-layer cross-point type) having a plurality of resistance change elements And a ReRAM unit including a ReRAM peripheral circuit (peripheral circuit transistor 2 and the like) which is a peripheral circuit for the ReRAM memory cell array. The ReRAM memory cell array is formed in an upper layer than the NAND flash unit, and the NAND flash peripheral circuit and the ReRAM peripheral circuit are formed in a region on the first substrate 1 and in a peripheral region from the NAND flash memory cell array. Has been. As a result, the ReRAM memory cell array, which is the main area, is arranged above (above) the NAND flash unit, so that a semiconductor memory device with a significantly reduced area is realized, such as an SSD module, memory card, etc. Therefore, it is possible to realize a mixed chip of a variable resistance nonvolatile memory device and a NAND flash memory nonvolatile memory device, which can be applied to a storage device, has low power consumption, and is excellent in miniaturization and high-speed operation.

  In the present embodiment, the ReRAM memory cell array is a cross-point type memory cell array having a plurality of current control elements in addition to a plurality of resistance change elements.

  Next, a method for manufacturing the semiconductor memory device 2000 according to the present embodiment configured as described above will be described. 8A to 8E are cross-sectional views of semiconductor memory device 2000 showing the method for manufacturing semiconductor memory device 2000 in the second embodiment of the present invention. The processes before the process shown in FIG. 8A are the same as (a) to (f) in FIG.

  First, as shown in FIG. 8A, NAND flash is formed in the NAND flash memory cell array region 101 and the NAND flash peripheral circuit region 102 on the first substrate 1. A ReRAM peripheral circuit transistor 2 is formed in the outer (peripheral) ReRAM peripheral circuit region 202. An interlayer insulating layer covering the whole is formed thereon, and a 3B contact plug 13 connected to the second wiring 9 is formed in the ReRAM peripheral circuit region 202. In addition to the ReRAM peripheral circuit region 202, the third wiring 14 connected to the third wiring 14 is also formed in the ReRAM memory cell array region 201.

  Next, as illustrated in FIG. 8B, in the ReRAM memory cell array region 201, a 4A contact plug 15 that penetrates the interlayer insulating layer is formed on the third wiring 14. Further, on the 4A contact plug 15, a first-layer cross-point type memory cell 20 including a lower electrode, a current control layer, a resistance change layer, and an upper electrode is formed.

  Next, as shown in FIG. 8C, first, a 4C contact plug 18 is formed on the third wiring 14 in the ReRAM peripheral circuit region 202. Further, a fourth wiring 19 connected to the fourth C contact plug 18 and the first-layer cross-point type memory cell 20 is formed.

  Next, as illustrated in FIG. 8D, in the ReRAM memory cell array region 201, a 5A contact plug 21 that penetrates the interlayer insulating layer is formed on the fourth wiring 19. Further, a second-layer cross-point type memory cell 22 including a lower electrode, a current control layer, a resistance change layer, and an upper electrode is formed on the 5A contact plug 21.

  Finally, as shown in FIG. 8E, first, a 5C contact plug 23 is formed on the fourth wiring 19 in the ReRAM peripheral circuit region 202. Further, the fifth wiring 24 connected to the 5C contact plug 23 and the second-layer cross-point type memory cell 22 is formed, and the semiconductor memory device 2000 is completed.

  As described above, the manufacturing method of the semiconductor memory device 2000 according to the present embodiment includes (1) the NAND flash unit in the first region (NAND flash peripheral circuit region 102) on the first substrate 1 as main steps. Forming a peripheral circuit transistor; (2) forming a memory cell transistor of a NAND flash portion in a second region (NAND flash memory cell array region 101) on the first substrate 1; Forming a selection transistor of the NAND flash unit in a second region (NAND flash memory cell array region 101) on one substrate 1, and (4) a third region (ReRAM peripheral circuit region 202) on the first substrate 1. Forming a peripheral circuit transistor of the ReRAM portion in the first region (5) first region (NAND flash peripheral circuit region) 02) forming a peripheral circuit wiring (first wiring 7) in the NAND flash section above (02), and (6) wiring in the NAND flash section above the second area (NAND flash memory cell array area 101). A step of forming (second wiring 9); and (7) a memory cell in the ReRAM section (one-layer cross-point type memory cell 20,. Forming a second-layer cross-point type memory cell 22) and wiring (third wiring 14, fourth wiring 19, and fifth wiring 24); and (8) ReRAM portion above the third region. Forming a peripheral circuit wiring (first wiring 7, second wiring 9, third wiring 14, fourth wiring 19, and fifth wiring 24).

  In this embodiment, since the ReRAM memory cell is a cross-point type, in the step of forming the memory cell and wiring of the ReRAM portion, a cross-point type memory cell composed of a resistance change element and a current control element is used. Form.

  By such a manufacturing method, resistance change that is applicable to the semiconductor storage device 2000 in this embodiment, that is, a storage device such as an SSD module or a memory card, is low in power consumption, excellent in downsizing and high-speed operation. A mixed chip of a type nonvolatile memory device and a NAND flash memory type nonvolatile memory device is manufactured.

  Although not shown in the semiconductor memory device 2000 of the present embodiment, a system LSI (SSD module or memory card) that is an SOC in an area other than the above NAND flash and ReRAM, as in the embedded ReRAM process. For example, a controller) may be formed. That is, the present invention may be realized as a storage device such as an SSD module or a memory card provided with the semiconductor storage device in the present embodiment. At that time, circuits such as various processors may be incorporated in the semiconductor memory device in this embodiment.

  In this device, the number of ReRAM memory cells is two, but it may be one or three or more as required.

  As in the case where ReRAM and NAND flash are independently formed by the above manufacturing method, a one-chip non-volatile semiconductor that takes advantage of ReRAM's low power consumption and high speed, NAND flash's large storage capacity, etc. A storage device can be realized. The reason is that the transistor for the peripheral circuit of the memory necessary for controlling the operation is formed on the first substrate 1 which is stable and has few crystal defects, and the switching of the ReRAM which only requires high driving current and switching characteristics. This is because a current control element having a diode characteristic connected to the variable resistance element is incorporated as the element. In addition, by utilizing the fact that the thermal budget is small for the formation of the variable resistance element of ReRAM, the ReRAM memory cell array, which is the main area, is arranged above the NAND flash part (upper layer). Reduction is possible. As a result, it is possible to form a thin and small area that does not require a stack packaging technique. Furthermore, in a ReRAM memory cell that does not require a memory cell transistor, the capacity of the memory in the ReRAM portion can be increased by increasing the number of layers.

  As described above, the semiconductor memory device, the manufacturing method, and the memory device according to the plurality of aspects of the present invention have been described based on the first mounting example, the second mounting example, and the first and second embodiments. These are not limited to the first mounting example, the second mounting example, and the first and second embodiments. Unless departing from the gist of the present invention, various modifications conceivable by those skilled in the art are applied to these first implementation example, second implementation example, and first and second embodiments, and different implementation examples and embodiments. Forms constructed by combining components may also be included within the scope of one or more aspects of the present invention.

  For example, in the first and second embodiments, the ReRAM memory cell array region 201 coincides with the combined region of the NAND flash memory cell array region 101 and the NAND flash peripheral circuit region 102 when the semiconductor memory device is viewed from above. However, the width and position of such a region are not limited.

  FIG. 9 is a diagram showing a variation of the layout of the semiconductor memory device of the present invention. When the semiconductor memory device is viewed from above, the ReRAM memory cell array region 201 may coincide with the NAND flash memory cell array region 101, as shown in FIG. As shown in FIG. 7, a part of the NAND flash memory cell array region 101 may be used. Further, the ReRAM memory cell array region 201 may be a region including a part of the NAND flash memory cell array region 101 and a part of the NAND flash peripheral circuit region 102, as shown in FIG. 9C. As shown in FIG. 9D, the NAND flash memory cell array region 101 and a part of the NAND flash peripheral circuit region 102 may be included. Further, as shown in FIG. 9E, the ReRAM memory cell array region 201 includes all of the NAND flash memory cell array region 101, a part of the NAND flash peripheral circuit region 102, and a part of the ReRAM peripheral circuit region 202. As shown in FIG. 9F, it includes all of the NAND flash memory cell array region 101, all of the NAND flash peripheral circuit region 102, and part of the ReRAM peripheral circuit region 202. It may be a region. Which of these positional relationships (the size and position of the ReRAM memory cell array region 201) is selected may be determined according to the storage capacity required for the ReRAM memory cell array region 201 and the connection relationship with peripheral circuits.

  Further, the ReRAM peripheral circuit region 202 may be on the first substrate 1 as long as it is peripheral to the NAND flash memory cell array region 101, and not all locations are necessarily peripheral to the NAND flash peripheral circuit region 102. Good. For example, a part of the ReRAM peripheral circuit area 202 may be formed inside the NAND flash peripheral circuit area 102.

  The present invention is a one-chip semiconductor memory device in which NAND flash and ReRAM are mixedly mounted, a method for manufacturing the same, and a memory device, which operates stably at high speed, has excellent low power consumption, and can store large amounts of data. Since it is a simple memory, it is particularly useful as a semiconductor storage device used in storage devices such as SSD modules and memory cards.

DESCRIPTION OF SYMBOLS 1 1st board | substrate 2 ReRAM peripheral circuit transistor 3 NAND flash peripheral circuit transistor 4 NAND flash selection transistor 5 NAND flash memory cell (NAND flash memory cell)
6 First contact plug 7 First wiring (first wiring layer)
8 Second contact plug 9 Second wiring (second wiring layer)
10 Second substrate 11 ReRAM memory cell transistor 12 3A contact plug 13 3B contact plug 14 Third wiring (third wiring layer)
15 4A Contact plug 16 Resistance change element 17 4B contact plug 18 4C contact plug 19 4th wiring (4th wiring layer)
20 First-layer cross-point type memory cell (resistance change element + current control element)
21 5A Contact plug 22 Second layer cross-point type memory cell (resistance change element + current control element)
23 5C contact plug 24 Fifth wiring (fifth wiring layer)
30, 40, 45 SSD module 31, 36 NAND flash (NAND flash memory)
32, 37 Cache memory 33, 38 Controller 35, 50, 55 Memory card 42, 47, 51, 56 Semiconductor memory device 101 NAND flash memory cell array region 102 NAND flash peripheral circuit region 201 ReRAM memory cell array region 202 ReRAM peripheral circuit region 1000 Semiconductor memory device 2000 according to the first embodiment of the invention Semiconductor memory device according to the second embodiment of the present invention

Claims (11)

A first substrate;
A NAND flash memory cell array formed on the first substrate and having a plurality of NAND flash memory cells, and a NAND flash unit including a NAND flash peripheral circuit which is a peripheral circuit for the NAND flash memory cell array;
A ReRAM memory cell array having a plurality of resistance change elements, and a ReRAM unit including a ReRAM peripheral circuit that is a peripheral circuit for the ReRAM memory cell array,
The ReRAM memory cell array is formed above the NAND flash unit,
The NAND flash peripheral circuit and the ReRAM peripheral circuit are formed in a region on the first substrate and in a peripheral region with respect to the NAND flash memory cell array. The semiconductor memory device according to claim 1, wherein the ReRAM memory cell array is formed at least above the NAND flash memory cell array. The semiconductor memory device according to claim 2, wherein the ReRAM memory cell array is formed above the NAND flash memory cell array and above the NAND flash peripheral circuit. 4. The semiconductor memory device according to claim 1, wherein the ReRAM peripheral circuit is an area on the first substrate and is formed in a peripheral area of the NAND flash peripheral circuit. 5. And a second substrate formed above the NAND flash unit,
The semiconductor memory device according to claim 1, wherein the ReRAM memory cell array includes a plurality of memory cell transistors formed on the second substrate in addition to the plurality of resistance change elements. The semiconductor memory device according to claim 1, wherein the ReRAM memory cell array is a cross-point type memory cell array having a plurality of current control elements in addition to the plurality of resistance change elements. Furthermore, a first wiring layer, a second wiring layer, and a third wiring layer are provided above the first substrate in order from the one closer to the first substrate.
The first wiring layer and the second wiring layer are formed in the NAND flash unit,
The semiconductor memory device according to claim 1, wherein the third wiring layer is a lowermost wiring layer of the ReRAM memory cell array.   A storage device that is a memory card or a solid-state drive on which the semiconductor storage device according to claim 1 is mounted. Forming a peripheral circuit transistor of the NAND flash portion in a first region on the substrate;
Forming a NAND flash memory cell in a second region on the substrate;
Forming a selection transistor of a NAND flash part in the second region;
Forming a peripheral circuit transistor of the ReRAM portion in a third region on the substrate;
Forming a peripheral circuit wiring of the NAND flash portion above the first region;
Forming a NAND flash wiring above the second region;
Forming a memory cell and a wiring of the ReRAM unit above the second region and on the wiring of the NAND flash unit;
Forming a peripheral circuit wiring of a ReRAM portion above the third region. A method of manufacturing a semiconductor memory device. Forming the memory cell and the wiring of the ReRAM portion;
Forming a second substrate;
Forming a memory cell transistor of the ReRAM portion on the second substrate;
The method of manufacturing a semiconductor memory device according to claim 9, further comprising: forming a resistance change element of the ReRAM portion. The method of manufacturing a semiconductor memory device according to claim 9, wherein in the step of forming the memory cell and the wiring in the ReRAM portion, a memory cell including a resistance change element and a current control element is formed.

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